[BNX2]: Add firmware decompression
[linux-2.6.git] / drivers / net / bnx2.c
index 3a9d6a8..c6510e1 100644 (file)
@@ -1,6 +1,6 @@
 /* bnx2.c: Broadcom NX2 network driver.
  *
- * Copyright (c) 2004, 2005 Broadcom Corporation
+ * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,24 +9,66 @@
  * Written by: Michael Chan  (mchan@broadcom.com)
  */
 
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#define BCM_VLAN 1
+#endif
+#ifdef NETIF_F_TSO
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/checksum.h>
+#define BCM_TSO 1
+#endif
+#include <linux/workqueue.h>
+#include <linux/crc32.h>
+#include <linux/prefetch.h>
+#include <linux/cache.h>
+#include <linux/zlib.h>
+
 #include "bnx2.h"
 #include "bnx2_fw.h"
 
 #define DRV_MODULE_NAME                "bnx2"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "1.2.19"
-#define DRV_MODULE_RELDATE     "May 23, 2005"
+#define DRV_MODULE_VERSION     "1.4.40"
+#define DRV_MODULE_RELDATE     "May 22, 2006"
 
 #define RUN_AT(x) (jiffies + (x))
 
 /* Time in jiffies before concluding the transmitter is hung. */
 #define TX_TIMEOUT  (5*HZ)
 
-static char version[] __devinitdata =
+static const char version[] __devinitdata =
        "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
-MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
+MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_MODULE_VERSION);
 
@@ -41,10 +83,12 @@ typedef enum {
        NC370I,
        BCM5706S,
        NC370F,
+       BCM5708,
+       BCM5708S,
 } board_t;
 
 /* indexed by board_t, above */
-static struct {
+static const struct {
        char *name;
 } board_info[] __devinitdata = {
        { "Broadcom NetXtreme II BCM5706 1000Base-T" },
@@ -52,6 +96,8 @@ static struct {
        { "HP NC370i Multifunction Gigabit Server Adapter" },
        { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
        { "HP NC370F Multifunction Gigabit Server Adapter" },
+       { "Broadcom NetXtreme II BCM5708 1000Base-T" },
+       { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
        };
 
 static struct pci_device_id bnx2_pci_tbl[] = {
@@ -61,52 +107,115 @@ static struct pci_device_id bnx2_pci_tbl[] = {
          PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
          PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
+       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
+         PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
        { 0, }
 };
 
 static struct flash_spec flash_table[] =
 {
        /* Slow EEPROM */
-       {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
+       {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
         1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
         SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
         "EEPROM - slow"},
-       /* Fast EEPROM */
-       {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
-        1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
-        SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
-        "EEPROM - fast"},
-       /* ATMEL AT45DB011B (buffered flash) */
-       {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
-        1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
-        BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
-        "Buffered flash"},
-       /* Saifun SA25F005 (non-buffered flash) */
-               /* strap, cfg1, & write1 need updates */
-       {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
+       /* Expansion entry 0001 */
+       {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
         0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
-        SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
-        "Non-buffered flash (64kB)"},
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 0001"},
        /* Saifun SA25F010 (non-buffered flash) */
        /* strap, cfg1, & write1 need updates */
-       {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
+       {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
         0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
         SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
         "Non-buffered flash (128kB)"},
        /* Saifun SA25F020 (non-buffered flash) */
        /* strap, cfg1, & write1 need updates */
-       {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
+       {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
         0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
         SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
         "Non-buffered flash (256kB)"},
+       /* Expansion entry 0100 */
+       {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 0100"},
+       /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
+       {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,        
+        0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
+        ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
+        "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
+       /* Entry 0110: ST M45PE20 (non-buffered flash)*/
+       {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
+        0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
+        ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
+        "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
+       /* Saifun SA25F005 (non-buffered flash) */
+       /* strap, cfg1, & write1 need updates */
+       {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
+        "Non-buffered flash (64kB)"},
+       /* Fast EEPROM */
+       {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
+        1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
+        SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
+        "EEPROM - fast"},
+       /* Expansion entry 1001 */
+       {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 1001"},
+       /* Expansion entry 1010 */
+       {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 1010"},
+       /* ATMEL AT45DB011B (buffered flash) */
+       {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
+        1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
+        BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
+        "Buffered flash (128kB)"},
+       /* Expansion entry 1100 */
+       {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 1100"},
+       /* Expansion entry 1101 */
+       {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
+        0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
+        SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 1101"},
+       /* Ateml Expansion entry 1110 */
+       {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
+        1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
+        BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
+        "Entry 1110 (Atmel)"},
+       /* ATMEL AT45DB021B (buffered flash) */
+       {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
+        1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
+        BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
+        "Buffered flash (256kB)"},
 };
 
 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 
+static inline u32 bnx2_tx_avail(struct bnx2 *bp)
+{
+       u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
+
+       if (diff > MAX_TX_DESC_CNT)
+               diff = (diff & MAX_TX_DESC_CNT) - 1;
+       return (bp->tx_ring_size - diff);
+}
+
 static u32
 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 {
@@ -246,13 +355,14 @@ bnx2_disable_int(struct bnx2 *bp)
 static void
 bnx2_enable_int(struct bnx2 *bp)
 {
-       u32 val;
+       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+              BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
+              BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 
        REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
               BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 
-       val = REG_RD(bp, BNX2_HC_COMMAND);
-       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+       REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 }
 
 static void
@@ -289,15 +399,13 @@ bnx2_netif_start(struct bnx2 *bp)
 static void
 bnx2_free_mem(struct bnx2 *bp)
 {
-       if (bp->stats_blk) {
-               pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
-                                   bp->stats_blk, bp->stats_blk_mapping);
-               bp->stats_blk = NULL;
-       }
+       int i;
+
        if (bp->status_blk) {
-               pci_free_consistent(bp->pdev, sizeof(struct status_block),
+               pci_free_consistent(bp->pdev, bp->status_stats_size,
                                    bp->status_blk, bp->status_blk_mapping);
                bp->status_blk = NULL;
+               bp->stats_blk = NULL;
        }
        if (bp->tx_desc_ring) {
                pci_free_consistent(bp->pdev,
@@ -305,31 +413,30 @@ bnx2_free_mem(struct bnx2 *bp)
                                    bp->tx_desc_ring, bp->tx_desc_mapping);
                bp->tx_desc_ring = NULL;
        }
-       if (bp->tx_buf_ring) {
-               kfree(bp->tx_buf_ring);
-               bp->tx_buf_ring = NULL;
-       }
-       if (bp->rx_desc_ring) {
-               pci_free_consistent(bp->pdev,
-                                   sizeof(struct rx_bd) * RX_DESC_CNT,
-                                   bp->rx_desc_ring, bp->rx_desc_mapping);
-               bp->rx_desc_ring = NULL;
-       }
-       if (bp->rx_buf_ring) {
-               kfree(bp->rx_buf_ring);
-               bp->rx_buf_ring = NULL;
-       }
+       kfree(bp->tx_buf_ring);
+       bp->tx_buf_ring = NULL;
+       for (i = 0; i < bp->rx_max_ring; i++) {
+               if (bp->rx_desc_ring[i])
+                       pci_free_consistent(bp->pdev,
+                                           sizeof(struct rx_bd) * RX_DESC_CNT,
+                                           bp->rx_desc_ring[i],
+                                           bp->rx_desc_mapping[i]);
+               bp->rx_desc_ring[i] = NULL;
+       }
+       vfree(bp->rx_buf_ring);
+       bp->rx_buf_ring = NULL;
 }
 
 static int
 bnx2_alloc_mem(struct bnx2 *bp)
 {
-       bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
-                                    GFP_KERNEL);
+       int i, status_blk_size;
+
+       bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
+                                 GFP_KERNEL);
        if (bp->tx_buf_ring == NULL)
                return -ENOMEM;
 
-       memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
        bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
                                                sizeof(struct tx_bd) *
                                                TX_DESC_CNT,
@@ -337,34 +444,40 @@ bnx2_alloc_mem(struct bnx2 *bp)
        if (bp->tx_desc_ring == NULL)
                goto alloc_mem_err;
 
-       bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
-                                    GFP_KERNEL);
+       bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
+                                 bp->rx_max_ring);
        if (bp->rx_buf_ring == NULL)
                goto alloc_mem_err;
 
-       memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
-       bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
-                                               sizeof(struct rx_bd) *
-                                               RX_DESC_CNT,
-                                               &bp->rx_desc_mapping);
-       if (bp->rx_desc_ring == NULL)
-               goto alloc_mem_err;
+       memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
+                                  bp->rx_max_ring);
+
+       for (i = 0; i < bp->rx_max_ring; i++) {
+               bp->rx_desc_ring[i] =
+                       pci_alloc_consistent(bp->pdev,
+                                            sizeof(struct rx_bd) * RX_DESC_CNT,
+                                            &bp->rx_desc_mapping[i]);
+               if (bp->rx_desc_ring[i] == NULL)
+                       goto alloc_mem_err;
+
+       }
+
+       /* Combine status and statistics blocks into one allocation. */
+       status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
+       bp->status_stats_size = status_blk_size +
+                               sizeof(struct statistics_block);
 
-       bp->status_blk = pci_alloc_consistent(bp->pdev,
-                                             sizeof(struct status_block),
+       bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
                                              &bp->status_blk_mapping);
        if (bp->status_blk == NULL)
                goto alloc_mem_err;
 
-       memset(bp->status_blk, 0, sizeof(struct status_block));
+       memset(bp->status_blk, 0, bp->status_stats_size);
 
-       bp->stats_blk = pci_alloc_consistent(bp->pdev,
-                                            sizeof(struct statistics_block),
-                                            &bp->stats_blk_mapping);
-       if (bp->stats_blk == NULL)
-               goto alloc_mem_err;
+       bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
+                                 status_blk_size);
 
-       memset(bp->stats_blk, 0, sizeof(struct statistics_block));
+       bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 
        return 0;
 
@@ -374,6 +487,62 @@ alloc_mem_err:
 }
 
 static void
+bnx2_report_fw_link(struct bnx2 *bp)
+{
+       u32 fw_link_status = 0;
+
+       if (bp->link_up) {
+               u32 bmsr;
+
+               switch (bp->line_speed) {
+               case SPEED_10:
+                       if (bp->duplex == DUPLEX_HALF)
+                               fw_link_status = BNX2_LINK_STATUS_10HALF;
+                       else
+                               fw_link_status = BNX2_LINK_STATUS_10FULL;
+                       break;
+               case SPEED_100:
+                       if (bp->duplex == DUPLEX_HALF)
+                               fw_link_status = BNX2_LINK_STATUS_100HALF;
+                       else
+                               fw_link_status = BNX2_LINK_STATUS_100FULL;
+                       break;
+               case SPEED_1000:
+                       if (bp->duplex == DUPLEX_HALF)
+                               fw_link_status = BNX2_LINK_STATUS_1000HALF;
+                       else
+                               fw_link_status = BNX2_LINK_STATUS_1000FULL;
+                       break;
+               case SPEED_2500:
+                       if (bp->duplex == DUPLEX_HALF)
+                               fw_link_status = BNX2_LINK_STATUS_2500HALF;
+                       else
+                               fw_link_status = BNX2_LINK_STATUS_2500FULL;
+                       break;
+               }
+
+               fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
+
+               if (bp->autoneg) {
+                       fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
+
+                       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+                       bnx2_read_phy(bp, MII_BMSR, &bmsr);
+
+                       if (!(bmsr & BMSR_ANEGCOMPLETE) ||
+                           bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
+                               fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
+                       else
+                               fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
+               }
+       }
+       else
+               fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
+
+       REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
+}
+
+static void
 bnx2_report_link(struct bnx2 *bp)
 {
        if (bp->link_up) {
@@ -404,6 +573,8 @@ bnx2_report_link(struct bnx2 *bp)
                netif_carrier_off(bp->dev);
                printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
        }
+
+       bnx2_report_fw_link(bp);
 }
 
 static void
@@ -425,6 +596,18 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
                return;
        }
 
+       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+           (CHIP_NUM(bp) == CHIP_NUM_5708)) {
+               u32 val;
+
+               bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
+               if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
+                       bp->flow_ctrl |= FLOW_CTRL_TX;
+               if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
+                       bp->flow_ctrl |= FLOW_CTRL_RX;
+               return;
+       }
+
        bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
        bnx2_read_phy(bp, MII_LPA, &remote_adv);
 
@@ -471,7 +654,36 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 }
 
 static int
-bnx2_serdes_linkup(struct bnx2 *bp)
+bnx2_5708s_linkup(struct bnx2 *bp)
+{
+       u32 val;
+
+       bp->link_up = 1;
+       bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
+       switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
+               case BCM5708S_1000X_STAT1_SPEED_10:
+                       bp->line_speed = SPEED_10;
+                       break;
+               case BCM5708S_1000X_STAT1_SPEED_100:
+                       bp->line_speed = SPEED_100;
+                       break;
+               case BCM5708S_1000X_STAT1_SPEED_1G:
+                       bp->line_speed = SPEED_1000;
+                       break;
+               case BCM5708S_1000X_STAT1_SPEED_2G5:
+                       bp->line_speed = SPEED_2500;
+                       break;
+       }
+       if (val & BCM5708S_1000X_STAT1_FD)
+               bp->duplex = DUPLEX_FULL;
+       else
+               bp->duplex = DUPLEX_HALF;
+
+       return 0;
+}
+
+static int
+bnx2_5706s_linkup(struct bnx2 *bp)
 {
        u32 bmcr, local_adv, remote_adv, common;
 
@@ -588,13 +800,27 @@ bnx2_set_mac_link(struct bnx2 *bp)
        val = REG_RD(bp, BNX2_EMAC_MODE);
 
        val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
-               BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
+               BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
+               BNX2_EMAC_MODE_25G);
 
        if (bp->link_up) {
-               if (bp->line_speed != SPEED_1000)
-                       val |= BNX2_EMAC_MODE_PORT_MII;
-               else
-                       val |= BNX2_EMAC_MODE_PORT_GMII;
+               switch (bp->line_speed) {
+                       case SPEED_10:
+                               if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+                                       val |= BNX2_EMAC_MODE_PORT_MII_10;
+                                       break;
+                               }
+                               /* fall through */
+                       case SPEED_100:
+                               val |= BNX2_EMAC_MODE_PORT_MII;
+                               break;
+                       case SPEED_2500:
+                               val |= BNX2_EMAC_MODE_25G;
+                               /* fall through */
+                       case SPEED_1000:
+                               val |= BNX2_EMAC_MODE_PORT_GMII;
+                               break;
+               }
        }
        else {
                val |= BNX2_EMAC_MODE_PORT_GMII;
@@ -657,7 +883,10 @@ bnx2_set_link(struct bnx2 *bp)
                bp->link_up = 1;
 
                if (bp->phy_flags & PHY_SERDES_FLAG) {
-                       bnx2_serdes_linkup(bp);
+                       if (CHIP_NUM(bp) == CHIP_NUM_5706)
+                               bnx2_5706s_linkup(bp);
+                       else if (CHIP_NUM(bp) == CHIP_NUM_5708)
+                               bnx2_5708s_linkup(bp);
                }
                else {
                        bnx2_copper_linkup(bp);
@@ -750,39 +979,61 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
 static int
 bnx2_setup_serdes_phy(struct bnx2 *bp)
 {
-       u32 adv, bmcr;
+       u32 adv, bmcr, up1;
        u32 new_adv = 0;
 
        if (!(bp->autoneg & AUTONEG_SPEED)) {
                u32 new_bmcr;
+               int force_link_down = 0;
+
+               if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+                       bnx2_read_phy(bp, BCM5708S_UP1, &up1);
+                       if (up1 & BCM5708S_UP1_2G5) {
+                               up1 &= ~BCM5708S_UP1_2G5;
+                               bnx2_write_phy(bp, BCM5708S_UP1, up1);
+                               force_link_down = 1;
+                       }
+               }
+
+               bnx2_read_phy(bp, MII_ADVERTISE, &adv);
+               adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
 
                bnx2_read_phy(bp, MII_BMCR, &bmcr);
                new_bmcr = bmcr & ~BMCR_ANENABLE;
                new_bmcr |= BMCR_SPEED1000;
                if (bp->req_duplex == DUPLEX_FULL) {
+                       adv |= ADVERTISE_1000XFULL;
                        new_bmcr |= BMCR_FULLDPLX;
                }
                else {
+                       adv |= ADVERTISE_1000XHALF;
                        new_bmcr &= ~BMCR_FULLDPLX;
                }
-               if (new_bmcr != bmcr) {
+               if ((new_bmcr != bmcr) || (force_link_down)) {
                        /* Force a link down visible on the other side */
                        if (bp->link_up) {
-                               bnx2_read_phy(bp, MII_ADVERTISE, &adv);
-                               adv &= ~(ADVERTISE_1000XFULL |
-                                       ADVERTISE_1000XHALF);
-                               bnx2_write_phy(bp, MII_ADVERTISE, adv);
+                               bnx2_write_phy(bp, MII_ADVERTISE, adv &
+                                              ~(ADVERTISE_1000XFULL |
+                                                ADVERTISE_1000XHALF));
                                bnx2_write_phy(bp, MII_BMCR, bmcr |
                                        BMCR_ANRESTART | BMCR_ANENABLE);
 
                                bp->link_up = 0;
                                netif_carrier_off(bp->dev);
+                               bnx2_write_phy(bp, MII_BMCR, new_bmcr);
                        }
+                       bnx2_write_phy(bp, MII_ADVERTISE, adv);
                        bnx2_write_phy(bp, MII_BMCR, new_bmcr);
                }
                return 0;
        }
 
+       if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
+               bnx2_read_phy(bp, BCM5708S_UP1, &up1);
+               up1 |= BCM5708S_UP1_2G5;
+               bnx2_write_phy(bp, BCM5708S_UP1, up1);
+       }
+
        if (bp->advertising & ADVERTISED_1000baseT_Full)
                new_adv |= ADVERTISE_1000XFULL;
 
@@ -806,7 +1057,19 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
                bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
                bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
                        BMCR_ANENABLE);
-               bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval;
+               if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+                       /* Speed up link-up time when the link partner
+                        * does not autonegotiate which is very common
+                        * in blade servers. Some blade servers use
+                        * IPMI for kerboard input and it's important
+                        * to minimize link disruptions. Autoneg. involves
+                        * exchanging base pages plus 3 next pages and
+                        * normally completes in about 120 msec.
+                        */
+                       bp->current_interval = SERDES_AN_TIMEOUT;
+                       bp->serdes_an_pending = 1;
+                       mod_timer(&bp->timer, jiffies + bp->current_interval);
+               }
        }
 
        return 0;
@@ -935,7 +1198,61 @@ bnx2_setup_phy(struct bnx2 *bp)
 }
 
 static int
-bnx2_init_serdes_phy(struct bnx2 *bp)
+bnx2_init_5708s_phy(struct bnx2 *bp)
+{
+       u32 val;
+
+       bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
+       bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
+       bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
+
+       bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
+       val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
+       bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
+
+       bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
+       val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
+       bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
+
+       if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
+               bnx2_read_phy(bp, BCM5708S_UP1, &val);
+               val |= BCM5708S_UP1_2G5;
+               bnx2_write_phy(bp, BCM5708S_UP1, val);
+       }
+
+       if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
+               /* increase tx signal amplitude */
+               bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
+                              BCM5708S_BLK_ADDR_TX_MISC);
+               bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
+               val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
+               bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
+               bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
+       }
+
+       val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
+             BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
+
+       if (val) {
+               u32 is_backplane;
+
+               is_backplane = REG_RD_IND(bp, bp->shmem_base +
+                                         BNX2_SHARED_HW_CFG_CONFIG);
+               if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
+                       bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
+                                      BCM5708S_BLK_ADDR_TX_MISC);
+                       bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
+                       bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
+                                      BCM5708S_BLK_ADDR_DIG);
+               }
+       }
+       return 0;
+}
+
+static int
+bnx2_init_5706s_phy(struct bnx2 *bp)
 {
        bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 
@@ -973,6 +1290,8 @@ bnx2_init_serdes_phy(struct bnx2 *bp)
 static int
 bnx2_init_copper_phy(struct bnx2 *bp)
 {
+       u32 val;
+
        bp->phy_flags |= PHY_CRC_FIX_FLAG;
 
        if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
@@ -987,8 +1306,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
        }
 
        if (bp->dev->mtu > 1500) {
-               u32 val;
-
                /* Set extended packet length bit */
                bnx2_write_phy(bp, 0x18, 0x7);
                bnx2_read_phy(bp, 0x18, &val);
@@ -998,8 +1315,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
                bnx2_write_phy(bp, 0x10, val | 0x1);
        }
        else {
-               u32 val;
-
                bnx2_write_phy(bp, 0x18, 0x7);
                bnx2_read_phy(bp, 0x18, &val);
                bnx2_write_phy(bp, 0x18, val & ~0x4007);
@@ -1008,6 +1323,10 @@ bnx2_init_copper_phy(struct bnx2 *bp)
                bnx2_write_phy(bp, 0x10, val & ~0x1);
        }
 
+       /* ethernet@wirespeed */
+       bnx2_write_phy(bp, 0x18, 0x7007);
+       bnx2_read_phy(bp, 0x18, &val);
+       bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
        return 0;
 }
 
@@ -1031,7 +1350,10 @@ bnx2_init_phy(struct bnx2 *bp)
        bp->phy_id |= val & 0xffff;
 
        if (bp->phy_flags & PHY_SERDES_FLAG) {
-               rc = bnx2_init_serdes_phy(bp);
+               if (CHIP_NUM(bp) == CHIP_NUM_5706)
+                       rc = bnx2_init_5706s_phy(bp);
+               else if (CHIP_NUM(bp) == CHIP_NUM_5708)
+                       rc = bnx2_init_5708s_phy(bp);
        }
        else {
                rc = bnx2_init_copper_phy(bp);
@@ -1055,44 +1377,78 @@ bnx2_set_mac_loopback(struct bnx2 *bp)
        return 0;
 }
 
+static int bnx2_test_link(struct bnx2 *);
+
+static int
+bnx2_set_phy_loopback(struct bnx2 *bp)
+{
+       u32 mac_mode;
+       int rc, i;
+
+       spin_lock_bh(&bp->phy_lock);
+       rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
+                           BMCR_SPEED1000);
+       spin_unlock_bh(&bp->phy_lock);
+       if (rc)
+               return rc;
+
+       for (i = 0; i < 10; i++) {
+               if (bnx2_test_link(bp) == 0)
+                       break;
+               udelay(10);
+       }
+
+       mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
+       mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
+                     BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
+                     BNX2_EMAC_MODE_25G);
+
+       mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
+       REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
+       bp->link_up = 1;
+       return 0;
+}
+
 static int
-bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
+bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
 {
        int i;
        u32 val;
 
-       if (bp->fw_timed_out)
-               return -EBUSY;
-
        bp->fw_wr_seq++;
        msg_data |= bp->fw_wr_seq;
 
-       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
+       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
 
        /* wait for an acknowledgement. */
-       for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
-               udelay(5);
+       for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
+               msleep(10);
 
-               val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
+               val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
 
                if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
                        break;
        }
+       if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
+               return 0;
 
        /* If we timed out, inform the firmware that this is the case. */
-       if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
-               ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
+       if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
+               if (!silent)
+                       printk(KERN_ERR PFX "fw sync timeout, reset code = "
+                                           "%x\n", msg_data);
 
                msg_data &= ~BNX2_DRV_MSG_CODE;
                msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
 
-               REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
-
-               bp->fw_timed_out = 1;
+               REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
 
                return -EBUSY;
        }
 
+       if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
+               return -EIO;
+
        return 0;
 }
 
@@ -1210,7 +1566,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
        struct sk_buff *skb;
        struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
        dma_addr_t mapping;
-       struct rx_bd *rxbd = &bp->rx_desc_ring[index];
+       struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
        unsigned long align;
 
        skb = dev_alloc_skb(bp->rx_buf_size);
@@ -1262,10 +1618,11 @@ bnx2_phy_int(struct bnx2 *bp)
 static void
 bnx2_tx_int(struct bnx2 *bp)
 {
+       struct status_block *sblk = bp->status_blk;
        u16 hw_cons, sw_cons, sw_ring_cons;
        int tx_free_bd = 0;
 
-       hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
+       hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
        if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
                hw_cons++;
        }
@@ -1320,61 +1677,66 @@ bnx2_tx_int(struct bnx2 *bp)
 
                dev_kfree_skb_irq(skb);
 
-               hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
+               hw_cons = bp->hw_tx_cons =
+                       sblk->status_tx_quick_consumer_index0;
+
                if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
                        hw_cons++;
                }
        }
 
-       atomic_add(tx_free_bd, &bp->tx_avail_bd);
+       bp->tx_cons = sw_cons;
 
        if (unlikely(netif_queue_stopped(bp->dev))) {
-               unsigned long flags;
-
-               spin_lock_irqsave(&bp->tx_lock, flags);
+               spin_lock(&bp->tx_lock);
                if ((netif_queue_stopped(bp->dev)) &&
-                       (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) {
+                   (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
 
                        netif_wake_queue(bp->dev);
                }
-               spin_unlock_irqrestore(&bp->tx_lock, flags);
+               spin_unlock(&bp->tx_lock);
        }
-
-       bp->tx_cons = sw_cons;
-
 }
 
 static inline void
 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
        u16 cons, u16 prod)
 {
-       struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
-       struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
-       struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
-       struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
+       struct sw_bd *cons_rx_buf, *prod_rx_buf;
+       struct rx_bd *cons_bd, *prod_bd;
+
+       cons_rx_buf = &bp->rx_buf_ring[cons];
+       prod_rx_buf = &bp->rx_buf_ring[prod];
 
        pci_dma_sync_single_for_device(bp->pdev,
                pci_unmap_addr(cons_rx_buf, mapping),
                bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
 
-       prod_rx_buf->skb = cons_rx_buf->skb;
-       pci_unmap_addr_set(prod_rx_buf, mapping,
-                       pci_unmap_addr(cons_rx_buf, mapping));
+       bp->rx_prod_bseq += bp->rx_buf_use_size;
 
-       memcpy(prod_bd, cons_bd, 8);
+       prod_rx_buf->skb = skb;
 
-       bp->rx_prod_bseq += bp->rx_buf_use_size;
+       if (cons == prod)
+               return;
 
+       pci_unmap_addr_set(prod_rx_buf, mapping,
+                       pci_unmap_addr(cons_rx_buf, mapping));
+
+       cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
+       prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
+       prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
+       prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
 }
 
 static int
 bnx2_rx_int(struct bnx2 *bp, int budget)
 {
+       struct status_block *sblk = bp->status_blk;
        u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
        struct l2_fhdr *rx_hdr;
        int rx_pkt = 0;
 
-       hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
+       hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
        if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
                hw_cons++;
        }
@@ -1387,23 +1749,28 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
        rmb();
        while (sw_cons != hw_cons) {
                unsigned int len;
-               u16 status;
+               u32 status;
                struct sw_bd *rx_buf;
                struct sk_buff *skb;
+               dma_addr_t dma_addr;
 
                sw_ring_cons = RX_RING_IDX(sw_cons);
                sw_ring_prod = RX_RING_IDX(sw_prod);
 
                rx_buf = &bp->rx_buf_ring[sw_ring_cons];
                skb = rx_buf->skb;
-               pci_dma_sync_single_for_cpu(bp->pdev,
-                       pci_unmap_addr(rx_buf, mapping),
+
+               rx_buf->skb = NULL;
+
+               dma_addr = pci_unmap_addr(rx_buf, mapping);
+
+               pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
                        bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
 
                rx_hdr = (struct l2_fhdr *) skb->data;
                len = rx_hdr->l2_fhdr_pkt_len - 4;
 
-               if (rx_hdr->l2_fhdr_errors &
+               if ((status = rx_hdr->l2_fhdr_status) &
                        (L2_FHDR_ERRORS_BAD_CRC |
                        L2_FHDR_ERRORS_PHY_DECODE |
                        L2_FHDR_ERRORS_ALIGNMENT |
@@ -1438,8 +1805,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
                        skb = new_skb;
                }
                else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
-                       pci_unmap_single(bp->pdev,
-                               pci_unmap_addr(rx_buf, mapping),
+                       pci_unmap_single(bp->pdev, dma_addr,
                                bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 
                        skb_reserve(skb, bp->rx_offset);
@@ -1455,22 +1821,20 @@ reuse_rx:
                skb->protocol = eth_type_trans(skb, bp->dev);
 
                if ((len > (bp->dev->mtu + ETH_HLEN)) &&
-                       (htons(skb->protocol) != 0x8100)) {
+                       (ntohs(skb->protocol) != 0x8100)) {
 
                        dev_kfree_skb_irq(skb);
                        goto next_rx;
 
                }
 
-               status = rx_hdr->l2_fhdr_status;
                skb->ip_summed = CHECKSUM_NONE;
                if (bp->rx_csum &&
                        (status & (L2_FHDR_STATUS_TCP_SEGMENT |
                        L2_FHDR_STATUS_UDP_DATAGRAM))) {
 
-                       u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
-
-                       if (cksum == 0xffff)
+                       if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
+                                             L2_FHDR_ERRORS_UDP_XSUM)) == 0))
                                skb->ip_summed = CHECKSUM_UNNECESSARY;
                }
 
@@ -1487,13 +1851,20 @@ reuse_rx:
                rx_pkt++;
 
 next_rx:
-               rx_buf->skb = NULL;
-
                sw_cons = NEXT_RX_BD(sw_cons);
                sw_prod = NEXT_RX_BD(sw_prod);
 
                if ((rx_pkt == budget))
                        break;
+
+               /* Refresh hw_cons to see if there is new work */
+               if (sw_cons == hw_cons) {
+                       hw_cons = bp->hw_rx_cons =
+                               sblk->status_rx_quick_consumer_index0;
+                       if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
+                               hw_cons++;
+                       rmb();
+               }
        }
        bp->rx_cons = sw_cons;
        bp->rx_prod = sw_prod;
@@ -1515,29 +1886,27 @@ static irqreturn_t
 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
 {
        struct net_device *dev = dev_instance;
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
+       prefetch(bp->status_blk);
        REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
                BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 
        /* Return here if interrupt is disabled. */
-       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
-               return IRQ_RETVAL(1);
-       }
+       if (unlikely(atomic_read(&bp->intr_sem) != 0))
+               return IRQ_HANDLED;
 
-       if (netif_rx_schedule_prep(dev)) {
-               __netif_rx_schedule(dev);
-       }
+       netif_rx_schedule(dev);
 
-       return IRQ_RETVAL(1);
+       return IRQ_HANDLED;
 }
 
 static irqreturn_t
 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
 {
        struct net_device *dev = dev_instance;
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        /* When using INTx, it is possible for the interrupt to arrive
         * at the CPU before the status block posted prior to the
@@ -1545,53 +1914,66 @@ bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
         * When using MSI, the MSI message will always complete after
         * the status block write.
         */
-       if ((bp->status_blk->status_idx == bp->last_status_idx) ||
+       if ((bp->status_blk->status_idx == bp->last_status_idx) &&
            (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
             BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
-               return IRQ_RETVAL(0);
+               return IRQ_NONE;
 
        REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
                BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 
        /* Return here if interrupt is shared and is disabled. */
-       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
-               return IRQ_RETVAL(1);
-       }
+       if (unlikely(atomic_read(&bp->intr_sem) != 0))
+               return IRQ_HANDLED;
 
-       if (netif_rx_schedule_prep(dev)) {
-               __netif_rx_schedule(dev);
-       }
+       netif_rx_schedule(dev);
+
+       return IRQ_HANDLED;
+}
+
+static inline int
+bnx2_has_work(struct bnx2 *bp)
+{
+       struct status_block *sblk = bp->status_blk;
+
+       if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
+           (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
+               return 1;
 
-       return IRQ_RETVAL(1);
+       if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
+           bp->link_up)
+               return 1;
+
+       return 0;
 }
 
 static int
 bnx2_poll(struct net_device *dev, int *budget)
 {
-       struct bnx2 *bp = dev->priv;
-       int rx_done = 1;
+       struct bnx2 *bp = netdev_priv(dev);
 
-       bp->last_status_idx = bp->status_blk->status_idx;
-
-       rmb();
        if ((bp->status_blk->status_attn_bits &
                STATUS_ATTN_BITS_LINK_STATE) !=
                (bp->status_blk->status_attn_bits_ack &
                STATUS_ATTN_BITS_LINK_STATE)) {
 
-               unsigned long flags;
-
-               spin_lock_irqsave(&bp->phy_lock, flags);
+               spin_lock(&bp->phy_lock);
                bnx2_phy_int(bp);
-               spin_unlock_irqrestore(&bp->phy_lock, flags);
+               spin_unlock(&bp->phy_lock);
+
+               /* This is needed to take care of transient status
+                * during link changes.
+                */
+               REG_WR(bp, BNX2_HC_COMMAND,
+                      bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+               REG_RD(bp, BNX2_HC_COMMAND);
        }
 
-       if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
+       if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
                bnx2_tx_int(bp);
-       }
 
-       if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
+       if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
                int orig_budget = *budget;
                int work_done;
 
@@ -1601,45 +1983,54 @@ bnx2_poll(struct net_device *dev, int *budget)
                work_done = bnx2_rx_int(bp, orig_budget);
                *budget -= work_done;
                dev->quota -= work_done;
-               
-               if (work_done >= orig_budget) {
-                       rx_done = 0;
-               }
        }
        
-       if (rx_done) {
+       bp->last_status_idx = bp->status_blk->status_idx;
+       rmb();
+
+       if (!bnx2_has_work(bp)) {
                netif_rx_complete(dev);
+               if (likely(bp->flags & USING_MSI_FLAG)) {
+                       REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+                              BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
+                              bp->last_status_idx);
+                       return 0;
+               }
                REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
-                       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
-                       bp->last_status_idx);
+                      BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
+                      BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
+                      bp->last_status_idx);
+
+               REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
+                      BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
+                      bp->last_status_idx);
                return 0;
        }
 
        return 1;
 }
 
-/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
+/* Called with rtnl_lock from vlan functions and also netif_tx_lock
  * from set_multicast.
  */
 static void
 bnx2_set_rx_mode(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        u32 rx_mode, sort_mode;
        int i;
-       unsigned long flags;
 
-       spin_lock_irqsave(&bp->phy_lock, flags);
+       spin_lock_bh(&bp->phy_lock);
 
        rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
                                  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
        sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
 #ifdef BCM_VLAN
-       if (!bp->vlgrp) {
+       if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
                rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
-       }
 #else
-       rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
+       if (!(bp->flags & ASF_ENABLE_FLAG))
+               rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
 #endif
        if (dev->flags & IFF_PROMISC) {
                /* Promiscuous mode. */
@@ -1690,7 +2081,93 @@ bnx2_set_rx_mode(struct net_device *dev)
        REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
        REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
 
-       spin_unlock_irqrestore(&bp->phy_lock, flags);
+       spin_unlock_bh(&bp->phy_lock);
+}
+
+#define FW_BUF_SIZE    0x8000
+
+static int
+bnx2_gunzip_init(struct bnx2 *bp)
+{
+       if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
+               goto gunzip_nomem1;
+
+       if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
+               goto gunzip_nomem2;
+
+       bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
+       if (bp->strm->workspace == NULL)
+               goto gunzip_nomem3;
+
+       return 0;
+
+gunzip_nomem3:
+       kfree(bp->strm);
+       bp->strm = NULL;
+
+gunzip_nomem2:
+       vfree(bp->gunzip_buf);
+       bp->gunzip_buf = NULL;
+
+gunzip_nomem1:
+       printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
+                           "uncompression.\n", bp->dev->name);
+       return -ENOMEM;
+}
+
+static void
+bnx2_gunzip_end(struct bnx2 *bp)
+{
+       kfree(bp->strm->workspace);
+
+       kfree(bp->strm);
+       bp->strm = NULL;
+
+       if (bp->gunzip_buf) {
+               vfree(bp->gunzip_buf);
+               bp->gunzip_buf = NULL;
+       }
+}
+
+static int
+bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
+{
+       int n, rc;
+
+       /* check gzip header */
+       if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
+               return -EINVAL;
+
+       n = 10;
+
+#define FNAME  0x8
+       if (zbuf[3] & FNAME)
+               while ((zbuf[n++] != 0) && (n < len));
+
+       bp->strm->next_in = zbuf + n;
+       bp->strm->avail_in = len - n;
+       bp->strm->next_out = bp->gunzip_buf;
+       bp->strm->avail_out = FW_BUF_SIZE;
+
+       rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
+       if (rc != Z_OK)
+               return rc;
+
+       rc = zlib_inflate(bp->strm, Z_FINISH);
+
+       *outlen = FW_BUF_SIZE - bp->strm->avail_out;
+       *outbuf = bp->gunzip_buf;
+
+       if ((rc != Z_OK) && (rc != Z_STREAM_END))
+               printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
+                      bp->dev->name, bp->strm->msg);
+
+       zlib_inflateEnd(bp->strm);
+
+       if (rc == Z_STREAM_END)
+               return 0;
+
+       return rc;
 }
 
 static void
@@ -1702,9 +2179,9 @@ load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
 
 
        for (i = 0; i < rv2p_code_len; i += 8) {
-               REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
+               REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
                rv2p_code++;
-               REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
+               REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
                rv2p_code++;
 
                if (rv2p_proc == RV2P_PROC1) {
@@ -1744,7 +2221,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                int j;
 
                for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, fw->text[j]);
+                       REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
                }
        }
 
@@ -1800,15 +2277,32 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
        REG_WR_IND(bp, cpu_reg->mode, val);
 }
 
-static void
+static int
 bnx2_init_cpus(struct bnx2 *bp)
 {
        struct cpu_reg cpu_reg;
        struct fw_info fw;
+       int rc = 0;
+       void *text;
+       u32 text_len;
+
+       if ((rc = bnx2_gunzip_init(bp)) != 0)
+               return rc;
 
        /* Initialize the RV2P processor. */
-       load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
-       load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
+       rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
+                        &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
+
+       rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
+                        &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
 
        /* Initialize the RX Processor. */
        cpu_reg.mode = BNX2_RXP_CPU_MODE;
@@ -1832,7 +2326,13 @@ bnx2_init_cpus(struct bnx2 *bp)
        fw.text_addr = bnx2_RXP_b06FwTextAddr;
        fw.text_len = bnx2_RXP_b06FwTextLen;
        fw.text_index = 0;
-       fw.text = bnx2_RXP_b06FwText;
+
+       rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
+                        &text, &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       fw.text = text;
 
        fw.data_addr = bnx2_RXP_b06FwDataAddr;
        fw.data_len = bnx2_RXP_b06FwDataLen;
@@ -1878,7 +2378,13 @@ bnx2_init_cpus(struct bnx2 *bp)
        fw.text_addr = bnx2_TXP_b06FwTextAddr;
        fw.text_len = bnx2_TXP_b06FwTextLen;
        fw.text_index = 0;
-       fw.text = bnx2_TXP_b06FwText;
+
+       rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
+                        &text, &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       fw.text = text;
 
        fw.data_addr = bnx2_TXP_b06FwDataAddr;
        fw.data_len = bnx2_TXP_b06FwDataLen;
@@ -1924,7 +2430,13 @@ bnx2_init_cpus(struct bnx2 *bp)
        fw.text_addr = bnx2_TPAT_b06FwTextAddr;
        fw.text_len = bnx2_TPAT_b06FwTextLen;
        fw.text_index = 0;
-       fw.text = bnx2_TPAT_b06FwText;
+
+       rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
+                        &text, &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       fw.text = text;
 
        fw.data_addr = bnx2_TPAT_b06FwDataAddr;
        fw.data_len = bnx2_TPAT_b06FwDataLen;
@@ -1970,7 +2482,13 @@ bnx2_init_cpus(struct bnx2 *bp)
        fw.text_addr = bnx2_COM_b06FwTextAddr;
        fw.text_len = bnx2_COM_b06FwTextLen;
        fw.text_index = 0;
-       fw.text = bnx2_COM_b06FwText;
+
+       rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
+                        &text, &text_len);
+       if (rc)
+               goto init_cpu_err;
+
+       fw.text = text;
 
        fw.data_addr = bnx2_COM_b06FwDataAddr;
        fw.data_len = bnx2_COM_b06FwDataLen;
@@ -1994,17 +2512,20 @@ bnx2_init_cpus(struct bnx2 *bp)
 
        load_cpu_fw(bp, &cpu_reg, &fw);
 
+init_cpu_err:
+       bnx2_gunzip_end(bp);
+       return rc;
 }
 
 static int
-bnx2_set_power_state(struct bnx2 *bp, int state)
+bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
 {
        u16 pmcsr;
 
        pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
 
        switch (state) {
-       case 0: {
+       case PCI_D0: {
                u32 val;
 
                pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
@@ -2025,7 +2546,7 @@ bnx2_set_power_state(struct bnx2 *bp, int state)
                REG_WR(bp, BNX2_RPM_CONFIG, val);
                break;
        }
-       case 3: {
+       case PCI_D3hot: {
                int i;
                u32 val, wol_msg;
 
@@ -2057,7 +2578,6 @@ bnx2_set_power_state(struct bnx2 *bp, int state)
                        val |= BNX2_EMAC_MODE_PORT_MII |
                               BNX2_EMAC_MODE_MPKT_RCVD |
                               BNX2_EMAC_MODE_ACPI_RCVD |
-                              BNX2_EMAC_MODE_FORCE_LINK |
                               BNX2_EMAC_MODE_MPKT;
 
                        REG_WR(bp, BNX2_EMAC_MODE, val);
@@ -2093,7 +2613,8 @@ bnx2_set_power_state(struct bnx2 *bp, int state)
                        wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
                }
 
-               bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
+               if (!(bp->flags & NO_WOL_FLAG))
+                       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
 
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
@@ -2379,21 +2900,27 @@ bnx2_init_nvram(struct bnx2 *bp)
 
                /* Flash interface has been reconfigured */
                for (j = 0, flash = &flash_table[0]; j < entry_count;
-                       j++, flash++) {
-
-                       if (val == flash->config1) {
+                    j++, flash++) {
+                       if ((val & FLASH_BACKUP_STRAP_MASK) ==
+                           (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
                                bp->flash_info = flash;
                                break;
                        }
                }
        }
        else {
+               u32 mask;
                /* Not yet been reconfigured */
 
+               if (val & (1 << 23))
+                       mask = FLASH_BACKUP_STRAP_MASK;
+               else
+                       mask = FLASH_STRAP_MASK;
+
                for (j = 0, flash = &flash_table[0]; j < entry_count;
                        j++, flash++) {
 
-                       if ((val & FLASH_STRAP_MASK) == flash->strapping) {
+                       if ((val & mask) == (flash->strapping & mask)) {
                                bp->flash_info = flash;
 
                                /* Request access to the flash interface. */
@@ -2420,10 +2947,17 @@ bnx2_init_nvram(struct bnx2 *bp)
 
        if (j == entry_count) {
                bp->flash_info = NULL;
-               printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
-               rc = -ENODEV;
+               printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
+               return -ENODEV;
        }
 
+       val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
+       val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
+       if (val)
+               bp->flash_size = val;
+       else
+               bp->flash_size = bp->flash_info->total_size;
+
        return rc;
 }
 
@@ -2542,7 +3076,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
                int buf_size)
 {
        u32 written, offset32, len32;
-       u8 *buf, start[4], end[4];
+       u8 *buf, start[4], end[4], *flash_buffer = NULL;
        int rc = 0;
        int align_start, align_end;
 
@@ -2582,12 +3116,19 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
                memcpy(buf + align_start, data_buf, buf_size);
        }
 
+       if (bp->flash_info->buffered == 0) {
+               flash_buffer = kmalloc(264, GFP_KERNEL);
+               if (flash_buffer == NULL) {
+                       rc = -ENOMEM;
+                       goto nvram_write_end;
+               }
+       }
+
        written = 0;
        while ((written < len32) && (rc == 0)) {
                u32 page_start, page_end, data_start, data_end;
                u32 addr, cmd_flags;
                int i;
-               u8 flash_buffer[264];
 
                /* Find the page_start addr */
                page_start = offset32 + written;
@@ -2658,7 +3199,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
                }
 
                /* Loop to write the new data from data_start to data_end */
-               for (addr = data_start; addr < data_end; addr += 4, i++) {
+               for (addr = data_start; addr < data_end; addr += 4, i += 4) {
                        if ((addr == page_end - 4) ||
                                ((bp->flash_info->buffered) &&
                                 (addr == data_end - 4))) {
@@ -2706,6 +3247,9 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
        }
 
 nvram_write_end:
+       if (bp->flash_info->buffered == 0)
+               kfree(flash_buffer);
+
        if (align_start || align_end)
                kfree(buf);
        return rc;
@@ -2727,16 +3271,14 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
        val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
        udelay(5);
 
+       /* Wait for the firmware to tell us it is ok to issue a reset. */
+       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
+
        /* Deposit a driver reset signature so the firmware knows that
         * this is a soft reset. */
-       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
+       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
                   BNX2_DRV_RESET_SIGNATURE_MAGIC);
 
-       bp->fw_timed_out = 0;
-
-       /* Wait for the firmware to tell us it is ok to issue a reset. */
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
-
        /* Do a dummy read to force the chip to complete all current transaction
         * before we issue a reset. */
        val = REG_RD(bp, BNX2_MISC_ID);
@@ -2775,10 +3317,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
                return -ENODEV;
        }
 
-       bp->fw_timed_out = 0;
-
        /* Wait for the firmware to finish its initialization. */
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
+       rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
+       if (rc)
+               return rc;
 
        if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
                /* Adjust the voltage regular to two steps lower.  The default
@@ -2796,6 +3338,7 @@ static int
 bnx2_init_chip(struct bnx2 *bp)
 {
        u32 val;
+       int rc;
 
        /* Make sure the interrupt is not active. */
        REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
@@ -2811,7 +3354,7 @@ bnx2_init_chip(struct bnx2 *bp)
 
        val |= (0x2 << 20) | (1 << 11);
 
-       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
+       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
                val |= (1 << 23);
 
        if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
@@ -2844,7 +3387,9 @@ bnx2_init_chip(struct bnx2 *bp)
         * context block must have already been enabled. */
        bnx2_init_context(bp);
 
-       bnx2_init_cpus(bp);
+       if ((rc = bnx2_init_cpus(bp)) != 0)
+               return rc;
+
        bnx2_init_nvram(bp);
 
        bnx2_set_mac_addr(bp);
@@ -2931,17 +3476,24 @@ bnx2_init_chip(struct bnx2 *bp)
 
        REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
 
+       if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
+           BNX2_PORT_FEATURE_ASF_ENABLED)
+               bp->flags |= ASF_ENABLE_FLAG;
+
        /* Initialize the receive filter. */
        bnx2_set_rx_mode(bp->dev);
 
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
+       rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
+                         0);
 
        REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
        REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
 
        udelay(20);
 
-       return 0;
+       bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
+
+       return rc;
 }
 
 
@@ -2958,8 +3510,8 @@ bnx2_init_tx_ring(struct bnx2 *bp)
 
        bp->tx_prod = 0;
        bp->tx_cons = 0;
+       bp->hw_tx_cons = 0;
        bp->tx_prod_bseq = 0;
-       atomic_set(&bp->tx_avail_bd, bp->tx_ring_size);
        
        val = BNX2_L2CTX_TYPE_TYPE_L2;
        val |= BNX2_L2CTX_TYPE_SIZE_L2;
@@ -2991,29 +3543,38 @@ bnx2_init_rx_ring(struct bnx2 *bp)
 
        ring_prod = prod = bp->rx_prod = 0;
        bp->rx_cons = 0;
+       bp->hw_rx_cons = 0;
        bp->rx_prod_bseq = 0;
                
-       rxbd = &bp->rx_desc_ring[0];
-       for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
-               rxbd->rx_bd_len = bp->rx_buf_use_size;
-               rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
-       }
+       for (i = 0; i < bp->rx_max_ring; i++) {
+               int j;
 
-       rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
-       rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
+               rxbd = &bp->rx_desc_ring[i][0];
+               for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
+                       rxbd->rx_bd_len = bp->rx_buf_use_size;
+                       rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
+               }
+               if (i == (bp->rx_max_ring - 1))
+                       j = 0;
+               else
+                       j = i + 1;
+               rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
+               rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
+                                      0xffffffff;
+       }
 
        val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
        val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
        val |= 0x02 << 8;
        CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
 
-       val = (u64) bp->rx_desc_mapping >> 32;
+       val = (u64) bp->rx_desc_mapping[0] >> 32;
        CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
 
-       val = (u64) bp->rx_desc_mapping & 0xffffffff;
+       val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
        CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
 
-       for ( ;ring_prod < bp->rx_ring_size; ) {
+       for (i = 0; i < bp->rx_ring_size; i++) {
                if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
                        break;
                }
@@ -3028,6 +3589,29 @@ bnx2_init_rx_ring(struct bnx2 *bp)
 }
 
 static void
+bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
+{
+       u32 num_rings, max;
+
+       bp->rx_ring_size = size;
+       num_rings = 1;
+       while (size > MAX_RX_DESC_CNT) {
+               size -= MAX_RX_DESC_CNT;
+               num_rings++;
+       }
+       /* round to next power of 2 */
+       max = MAX_RX_RINGS;
+       while ((max & num_rings) == 0)
+               max >>= 1;
+
+       if (num_rings != max)
+               max <<= 1;
+
+       bp->rx_max_ring = max;
+       bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
+}
+
+static void
 bnx2_free_tx_skbs(struct bnx2 *bp)
 {
        int i;
@@ -3072,11 +3656,11 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
        if (bp->rx_buf_ring == NULL)
                return;
 
-       for (i = 0; i < RX_DESC_CNT; i++) {
+       for (i = 0; i < bp->rx_max_ring_idx; i++) {
                struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
                struct sk_buff *skb = rx_buf->skb;
 
-               if (skb == 0)
+               if (skb == NULL)
                        continue;
 
                pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
@@ -3105,7 +3689,9 @@ bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
        if (rc)
                return rc;
 
-       bnx2_init_chip(bp);
+       if ((rc = bnx2_init_chip(bp)) != 0)
+               return rc;
+
        bnx2_init_tx_ring(bp);
        bnx2_init_rx_ring(bp);
        return 0;
@@ -3129,7 +3715,7 @@ bnx2_test_registers(struct bnx2 *bp)
 {
        int ret;
        int i;
-       static struct {
+       static const struct {
                u16   offset;
                u16   flags;
                u32   rw_mask;
@@ -3159,190 +3745,23 @@ bnx2_test_registers(struct bnx2 *bp)
                { 0x0c00, 0, 0x00000000, 0x00000001 },
                { 0x0c04, 0, 0x00000000, 0x03ff0001 },
                { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
-               { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
-               { 0x0c30, 0, 0x00000000, 0xffffffff },
-               { 0x0c34, 0, 0x00000000, 0xffffffff },
-               { 0x0c38, 0, 0x00000000, 0xffffffff },
-               { 0x0c3c, 0, 0x00000000, 0xffffffff },
-               { 0x0c40, 0, 0x00000000, 0xffffffff },
-               { 0x0c44, 0, 0x00000000, 0xffffffff },
-               { 0x0c48, 0, 0x00000000, 0x0007ffff },
-               { 0x0c4c, 0, 0x00000000, 0xffffffff },
-               { 0x0c50, 0, 0x00000000, 0xffffffff },
-               { 0x0c54, 0, 0x00000000, 0xffffffff },
-               { 0x0c58, 0, 0x00000000, 0xffffffff },
-               { 0x0c5c, 0, 0x00000000, 0xffffffff },
-               { 0x0c60, 0, 0x00000000, 0xffffffff },
-               { 0x0c64, 0, 0x00000000, 0xffffffff },
-               { 0x0c68, 0, 0x00000000, 0xffffffff },
-               { 0x0c6c, 0, 0x00000000, 0xffffffff },
-               { 0x0c70, 0, 0x00000000, 0xffffffff },
-               { 0x0c74, 0, 0x00000000, 0xffffffff },
-               { 0x0c78, 0, 0x00000000, 0xffffffff },
-               { 0x0c7c, 0, 0x00000000, 0xffffffff },
-               { 0x0c80, 0, 0x00000000, 0xffffffff },
-               { 0x0c84, 0, 0x00000000, 0xffffffff },
-               { 0x0c88, 0, 0x00000000, 0xffffffff },
-               { 0x0c8c, 0, 0x00000000, 0xffffffff },
-               { 0x0c90, 0, 0x00000000, 0xffffffff },
-               { 0x0c94, 0, 0x00000000, 0xffffffff },
-               { 0x0c98, 0, 0x00000000, 0xffffffff },
-               { 0x0c9c, 0, 0x00000000, 0xffffffff },
-               { 0x0ca0, 0, 0x00000000, 0xffffffff },
-               { 0x0ca4, 0, 0x00000000, 0xffffffff },
-               { 0x0ca8, 0, 0x00000000, 0x0007ffff },
-               { 0x0cac, 0, 0x00000000, 0xffffffff },
-               { 0x0cb0, 0, 0x00000000, 0xffffffff },
-               { 0x0cb4, 0, 0x00000000, 0xffffffff },
-               { 0x0cb8, 0, 0x00000000, 0xffffffff },
-               { 0x0cbc, 0, 0x00000000, 0xffffffff },
-               { 0x0cc0, 0, 0x00000000, 0xffffffff },
-               { 0x0cc4, 0, 0x00000000, 0xffffffff },
-               { 0x0cc8, 0, 0x00000000, 0xffffffff },
-               { 0x0ccc, 0, 0x00000000, 0xffffffff },
-               { 0x0cd0, 0, 0x00000000, 0xffffffff },
-               { 0x0cd4, 0, 0x00000000, 0xffffffff },
-               { 0x0cd8, 0, 0x00000000, 0xffffffff },
-               { 0x0cdc, 0, 0x00000000, 0xffffffff },
-               { 0x0ce0, 0, 0x00000000, 0xffffffff },
-               { 0x0ce4, 0, 0x00000000, 0xffffffff },
-               { 0x0ce8, 0, 0x00000000, 0xffffffff },
-               { 0x0cec, 0, 0x00000000, 0xffffffff },
-               { 0x0cf0, 0, 0x00000000, 0xffffffff },
-               { 0x0cf4, 0, 0x00000000, 0xffffffff },
-               { 0x0cf8, 0, 0x00000000, 0xffffffff },
-               { 0x0cfc, 0, 0x00000000, 0xffffffff },
-               { 0x0d00, 0, 0x00000000, 0xffffffff },
-               { 0x0d04, 0, 0x00000000, 0xffffffff },
 
                { 0x1000, 0, 0x00000000, 0x00000001 },
                { 0x1004, 0, 0x00000000, 0x000f0001 },
-               { 0x1044, 0, 0x00000000, 0xffc003ff },
-               { 0x1080, 0, 0x00000000, 0x0001ffff },
-               { 0x1084, 0, 0x00000000, 0xffffffff },
-               { 0x1088, 0, 0x00000000, 0xffffffff },
-               { 0x108c, 0, 0x00000000, 0xffffffff },
-               { 0x1090, 0, 0x00000000, 0xffffffff },
-               { 0x1094, 0, 0x00000000, 0xffffffff },
-               { 0x1098, 0, 0x00000000, 0xffffffff },
-               { 0x109c, 0, 0x00000000, 0xffffffff },
-               { 0x10a0, 0, 0x00000000, 0xffffffff },
 
                { 0x1408, 0, 0x01c00800, 0x00000000 },
                { 0x149c, 0, 0x8000ffff, 0x00000000 },
                { 0x14a8, 0, 0x00000000, 0x000001ff },
-               { 0x14ac, 0, 0x4fffffff, 0x10000000 },
+               { 0x14ac, 0, 0x0fffffff, 0x10000000 },
                { 0x14b0, 0, 0x00000002, 0x00000001 },
                { 0x14b8, 0, 0x00000000, 0x00000000 },
                { 0x14c0, 0, 0x00000000, 0x00000009 },
                { 0x14c4, 0, 0x00003fff, 0x00000000 },
                { 0x14cc, 0, 0x00000000, 0x00000001 },
                { 0x14d0, 0, 0xffffffff, 0x00000000 },
-               { 0x1500, 0, 0x00000000, 0xffffffff },
-               { 0x1504, 0, 0x00000000, 0xffffffff },
-               { 0x1508, 0, 0x00000000, 0xffffffff },
-               { 0x150c, 0, 0x00000000, 0xffffffff },
-               { 0x1510, 0, 0x00000000, 0xffffffff },
-               { 0x1514, 0, 0x00000000, 0xffffffff },
-               { 0x1518, 0, 0x00000000, 0xffffffff },
-               { 0x151c, 0, 0x00000000, 0xffffffff },
-               { 0x1520, 0, 0x00000000, 0xffffffff },
-               { 0x1524, 0, 0x00000000, 0xffffffff },
-               { 0x1528, 0, 0x00000000, 0xffffffff },
-               { 0x152c, 0, 0x00000000, 0xffffffff },
-               { 0x1530, 0, 0x00000000, 0xffffffff },
-               { 0x1534, 0, 0x00000000, 0xffffffff },
-               { 0x1538, 0, 0x00000000, 0xffffffff },
-               { 0x153c, 0, 0x00000000, 0xffffffff },
-               { 0x1540, 0, 0x00000000, 0xffffffff },
-               { 0x1544, 0, 0x00000000, 0xffffffff },
-               { 0x1548, 0, 0x00000000, 0xffffffff },
-               { 0x154c, 0, 0x00000000, 0xffffffff },
-               { 0x1550, 0, 0x00000000, 0xffffffff },
-               { 0x1554, 0, 0x00000000, 0xffffffff },
-               { 0x1558, 0, 0x00000000, 0xffffffff },
-               { 0x1600, 0, 0x00000000, 0xffffffff },
-               { 0x1604, 0, 0x00000000, 0xffffffff },
-               { 0x1608, 0, 0x00000000, 0xffffffff },
-               { 0x160c, 0, 0x00000000, 0xffffffff },
-               { 0x1610, 0, 0x00000000, 0xffffffff },
-               { 0x1614, 0, 0x00000000, 0xffffffff },
-               { 0x1618, 0, 0x00000000, 0xffffffff },
-               { 0x161c, 0, 0x00000000, 0xffffffff },
-               { 0x1620, 0, 0x00000000, 0xffffffff },
-               { 0x1624, 0, 0x00000000, 0xffffffff },
-               { 0x1628, 0, 0x00000000, 0xffffffff },
-               { 0x162c, 0, 0x00000000, 0xffffffff },
-               { 0x1630, 0, 0x00000000, 0xffffffff },
-               { 0x1634, 0, 0x00000000, 0xffffffff },
-               { 0x1638, 0, 0x00000000, 0xffffffff },
-               { 0x163c, 0, 0x00000000, 0xffffffff },
-               { 0x1640, 0, 0x00000000, 0xffffffff },
-               { 0x1644, 0, 0x00000000, 0xffffffff },
-               { 0x1648, 0, 0x00000000, 0xffffffff },
-               { 0x164c, 0, 0x00000000, 0xffffffff },
-               { 0x1650, 0, 0x00000000, 0xffffffff },
-               { 0x1654, 0, 0x00000000, 0xffffffff },
 
                { 0x1800, 0, 0x00000000, 0x00000001 },
                { 0x1804, 0, 0x00000000, 0x00000003 },
-               { 0x1840, 0, 0x00000000, 0xffffffff },
-               { 0x1844, 0, 0x00000000, 0xffffffff },
-               { 0x1848, 0, 0x00000000, 0xffffffff },
-               { 0x184c, 0, 0x00000000, 0xffffffff },
-               { 0x1850, 0, 0x00000000, 0xffffffff },
-               { 0x1900, 0, 0x7ffbffff, 0x00000000 },
-               { 0x1904, 0, 0xffffffff, 0x00000000 },
-               { 0x190c, 0, 0xffffffff, 0x00000000 },
-               { 0x1914, 0, 0xffffffff, 0x00000000 },
-               { 0x191c, 0, 0xffffffff, 0x00000000 },
-               { 0x1924, 0, 0xffffffff, 0x00000000 },
-               { 0x192c, 0, 0xffffffff, 0x00000000 },
-               { 0x1934, 0, 0xffffffff, 0x00000000 },
-               { 0x193c, 0, 0xffffffff, 0x00000000 },
-               { 0x1944, 0, 0xffffffff, 0x00000000 },
-               { 0x194c, 0, 0xffffffff, 0x00000000 },
-               { 0x1954, 0, 0xffffffff, 0x00000000 },
-               { 0x195c, 0, 0xffffffff, 0x00000000 },
-               { 0x1964, 0, 0xffffffff, 0x00000000 },
-               { 0x196c, 0, 0xffffffff, 0x00000000 },
-               { 0x1974, 0, 0xffffffff, 0x00000000 },
-               { 0x197c, 0, 0xffffffff, 0x00000000 },
-               { 0x1980, 0, 0x0700ffff, 0x00000000 },
-
-               { 0x1c00, 0, 0x00000000, 0x00000001 },
-               { 0x1c04, 0, 0x00000000, 0x00000003 },
-               { 0x1c08, 0, 0x0000000f, 0x00000000 },
-               { 0x1c40, 0, 0x00000000, 0xffffffff },
-               { 0x1c44, 0, 0x00000000, 0xffffffff },
-               { 0x1c48, 0, 0x00000000, 0xffffffff },
-               { 0x1c4c, 0, 0x00000000, 0xffffffff },
-               { 0x1c50, 0, 0x00000000, 0xffffffff },
-               { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
-               { 0x1d04, 0, 0xffffffff, 0x00000000 },
-               { 0x1d0c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d14, 0, 0xffffffff, 0x00000000 },
-               { 0x1d1c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d24, 0, 0xffffffff, 0x00000000 },
-               { 0x1d2c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d34, 0, 0xffffffff, 0x00000000 },
-               { 0x1d3c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d44, 0, 0xffffffff, 0x00000000 },
-               { 0x1d4c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d54, 0, 0xffffffff, 0x00000000 },
-               { 0x1d5c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d64, 0, 0xffffffff, 0x00000000 },
-               { 0x1d6c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d74, 0, 0xffffffff, 0x00000000 },
-               { 0x1d7c, 0, 0xffffffff, 0x00000000 },
-               { 0x1d80, 0, 0x0700ffff, 0x00000000 },
-
-               { 0x2004, 0, 0x00000000, 0x0337000f },
-               { 0x2008, 0, 0xffffffff, 0x00000000 },
-               { 0x200c, 0, 0xffffffff, 0x00000000 },
-               { 0x2010, 0, 0xffffffff, 0x00000000 },
-               { 0x2014, 0, 0x801fff80, 0x00000000 },
-               { 0x2018, 0, 0x000003ff, 0x00000000 },
 
                { 0x2800, 0, 0x00000000, 0x00000001 },
                { 0x2804, 0, 0x00000000, 0x00003f01 },
@@ -3360,16 +3779,6 @@ bnx2_test_registers(struct bnx2 *bp)
                { 0x2c00, 0, 0x00000000, 0x00000011 },
                { 0x2c04, 0, 0x00000000, 0x00030007 },
 
-               { 0x3000, 0, 0x00000000, 0x00000001 },
-               { 0x3004, 0, 0x00000000, 0x007007ff },
-               { 0x3008, 0, 0x00000003, 0x00000000 },
-               { 0x300c, 0, 0xffffffff, 0x00000000 },
-               { 0x3010, 0, 0xffffffff, 0x00000000 },
-               { 0x3014, 0, 0xffffffff, 0x00000000 },
-               { 0x3034, 0, 0xffffffff, 0x00000000 },
-               { 0x3038, 0, 0xffffffff, 0x00000000 },
-               { 0x3050, 0, 0x00000001, 0x00000000 },
-
                { 0x3c00, 0, 0x00000000, 0x00000001 },
                { 0x3c04, 0, 0x00000000, 0x00070000 },
                { 0x3c08, 0, 0x00007f71, 0x07f00000 },
@@ -3379,88 +3788,11 @@ bnx2_test_registers(struct bnx2 *bp)
                { 0x3c18, 0, 0x00000000, 0xffffffff },
                { 0x3c1c, 0, 0xfffff000, 0x00000000 },
                { 0x3c20, 0, 0xffffff00, 0x00000000 },
-               { 0x3c24, 0, 0xffffffff, 0x00000000 },
-               { 0x3c28, 0, 0xffffffff, 0x00000000 },
-               { 0x3c2c, 0, 0xffffffff, 0x00000000 },
-               { 0x3c30, 0, 0xffffffff, 0x00000000 },
-               { 0x3c34, 0, 0xffffffff, 0x00000000 },
-               { 0x3c38, 0, 0xffffffff, 0x00000000 },
-               { 0x3c3c, 0, 0xffffffff, 0x00000000 },
-               { 0x3c40, 0, 0xffffffff, 0x00000000 },
-               { 0x3c44, 0, 0xffffffff, 0x00000000 },
-               { 0x3c48, 0, 0xffffffff, 0x00000000 },
-               { 0x3c4c, 0, 0xffffffff, 0x00000000 },
-               { 0x3c50, 0, 0xffffffff, 0x00000000 },
-               { 0x3c54, 0, 0xffffffff, 0x00000000 },
-               { 0x3c58, 0, 0xffffffff, 0x00000000 },
-               { 0x3c5c, 0, 0xffffffff, 0x00000000 },
-               { 0x3c60, 0, 0xffffffff, 0x00000000 },
-               { 0x3c64, 0, 0xffffffff, 0x00000000 },
-               { 0x3c68, 0, 0xffffffff, 0x00000000 },
-               { 0x3c6c, 0, 0xffffffff, 0x00000000 },
-               { 0x3c70, 0, 0xffffffff, 0x00000000 },
-               { 0x3c74, 0, 0x0000003f, 0x00000000 },
-               { 0x3c78, 0, 0x00000000, 0x00000000 },
-               { 0x3c7c, 0, 0x00000000, 0x00000000 },
-               { 0x3c80, 0, 0x3fffffff, 0x00000000 },
-               { 0x3c84, 0, 0x0000003f, 0x00000000 },
-               { 0x3c88, 0, 0x00000000, 0xffffffff },
-               { 0x3c8c, 0, 0x00000000, 0xffffffff },
-
-               { 0x4000, 0, 0x00000000, 0x00000001 },
-               { 0x4004, 0, 0x00000000, 0x00030000 },
-               { 0x4008, 0, 0x00000ff0, 0x00000000 },
-               { 0x400c, 0, 0xffffffff, 0x00000000 },
-               { 0x4088, 0, 0x00000000, 0x00070303 },
-
-               { 0x4400, 0, 0x00000000, 0x00000001 },
-               { 0x4404, 0, 0x00000000, 0x00003f01 },
-               { 0x4408, 0, 0x7fff00ff, 0x00000000 },
-               { 0x440c, 0, 0xffffffff, 0x00000000 },
-               { 0x4410, 0, 0xffff,     0x0000 },
-               { 0x4414, 0, 0xffff,     0x0000 },
-               { 0x4418, 0, 0xffff,     0x0000 },
-               { 0x441c, 0, 0xffff,     0x0000 },
-               { 0x4428, 0, 0xffffffff, 0x00000000 },
-               { 0x442c, 0, 0xffffffff, 0x00000000 },
-               { 0x4430, 0, 0xffffffff, 0x00000000 },
-               { 0x4434, 0, 0xffffffff, 0x00000000 },
-               { 0x4438, 0, 0xffffffff, 0x00000000 },
-               { 0x443c, 0, 0xffffffff, 0x00000000 },
-               { 0x4440, 0, 0xffffffff, 0x00000000 },
-               { 0x4444, 0, 0xffffffff, 0x00000000 },
-
-               { 0x4c00, 0, 0x00000000, 0x00000001 },
-               { 0x4c04, 0, 0x00000000, 0x0000003f },
-               { 0x4c08, 0, 0xffffffff, 0x00000000 },
-               { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
-               { 0x4c10, 0, 0x80003fe0, 0x00000000 },
-               { 0x4c14, 0, 0xffffffff, 0x00000000 },
-               { 0x4c44, 0, 0x00000000, 0x9fff9fff },
-               { 0x4c48, 0, 0x00000000, 0xb3009fff },
-               { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
-               { 0x4c50, 0, 0x00000000, 0xffffffff },
 
                { 0x5004, 0, 0x00000000, 0x0000007f },
                { 0x5008, 0, 0x0f0007ff, 0x00000000 },
                { 0x500c, 0, 0xf800f800, 0x07ff07ff },
 
-               { 0x5400, 0, 0x00000008, 0x00000001 },
-               { 0x5404, 0, 0x00000000, 0x0000003f },
-               { 0x5408, 0, 0x0000001f, 0x00000000 },
-               { 0x540c, 0, 0xffffffff, 0x00000000 },
-               { 0x5410, 0, 0xffffffff, 0x00000000 },
-               { 0x5414, 0, 0x0000ffff, 0x00000000 },
-               { 0x5418, 0, 0x0000ffff, 0x00000000 },
-               { 0x541c, 0, 0x0000ffff, 0x00000000 },
-               { 0x5420, 0, 0x0000ffff, 0x00000000 },
-               { 0x5428, 0, 0x000000ff, 0x00000000 },
-               { 0x542c, 0, 0xff00ffff, 0x00000000 },
-               { 0x5430, 0, 0x001fff80, 0x00000000 },
-               { 0x5438, 0, 0xffffffff, 0x00000000 },
-               { 0x543c, 0, 0xffffffff, 0x00000000 },
-               { 0x5440, 0, 0xf800f800, 0x07ff07ff },
-
                { 0x5c00, 0, 0x00000000, 0x00000001 },
                { 0x5c04, 0, 0x00000000, 0x0003000f },
                { 0x5c08, 0, 0x00000003, 0x00000000 },
@@ -3544,7 +3876,7 @@ reg_test_err:
 static int
 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
 {
-       static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
+       static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
                0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
        int i;
 
@@ -3569,12 +3901,12 @@ bnx2_test_memory(struct bnx2 *bp)
 {
        int ret = 0;
        int i;
-       static struct {
+       static const struct {
                u32   offset;
                u32   len;
        } mem_tbl[] = {
                { 0x60000,  0x4000 },
-               { 0xa0000,  0x4000 },
+               { 0xa0000,  0x3000 },
                { 0xe0000,  0x4000 },
                { 0x120000, 0x4000 },
                { 0x1a0000, 0x4000 },
@@ -3592,29 +3924,37 @@ bnx2_test_memory(struct bnx2 *bp)
        return ret;
 }
 
+#define BNX2_MAC_LOOPBACK      0
+#define BNX2_PHY_LOOPBACK      1
+
 static int
-bnx2_test_loopback(struct bnx2 *bp)
+bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
 {
        unsigned int pkt_size, num_pkts, i;
        struct sk_buff *skb, *rx_skb;
        unsigned char *packet;
-       u16 rx_start_idx, rx_idx, send_idx;
-       u32 send_bseq, val;
+       u16 rx_start_idx, rx_idx;
        dma_addr_t map;
        struct tx_bd *txbd;
        struct sw_bd *rx_buf;
        struct l2_fhdr *rx_hdr;
        int ret = -ENODEV;
 
-       if (!netif_running(bp->dev))
-               return -ENODEV;
-
-       bp->loopback = MAC_LOOPBACK;
-       bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
-       bnx2_set_mac_loopback(bp);
+       if (loopback_mode == BNX2_MAC_LOOPBACK) {
+               bp->loopback = MAC_LOOPBACK;
+               bnx2_set_mac_loopback(bp);
+       }
+       else if (loopback_mode == BNX2_PHY_LOOPBACK) {
+               bp->loopback = 0;
+               bnx2_set_phy_loopback(bp);
+       }
+       else
+               return -EINVAL;
 
        pkt_size = 1514;
        skb = dev_alloc_skb(pkt_size);
+       if (!skb)
+               return -ENOMEM;
        packet = skb_put(skb, pkt_size);
        memcpy(packet, bp->mac_addr, 6);
        memset(packet + 6, 0x0, 8);
@@ -3624,18 +3964,17 @@ bnx2_test_loopback(struct bnx2 *bp)
        map = pci_map_single(bp->pdev, skb->data, pkt_size,
                PCI_DMA_TODEVICE);
 
-       val = REG_RD(bp, BNX2_HC_COMMAND);
-       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+       REG_WR(bp, BNX2_HC_COMMAND,
+              bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
        REG_RD(bp, BNX2_HC_COMMAND);
 
        udelay(5);
        rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
 
-       send_idx = 0;
-       send_bseq = 0;
        num_pkts = 0;
 
-       txbd = &bp->tx_desc_ring[send_idx];
+       txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
 
        txbd->tx_bd_haddr_hi = (u64) map >> 32;
        txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
@@ -3643,18 +3982,17 @@ bnx2_test_loopback(struct bnx2 *bp)
        txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
 
        num_pkts++;
-       send_idx = NEXT_TX_BD(send_idx);
-
-       send_bseq += pkt_size;
-
-       REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
-       REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
+       bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
+       bp->tx_prod_bseq += pkt_size;
 
+       REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
+       REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
 
        udelay(100);
 
-       val = REG_RD(bp, BNX2_HC_COMMAND);
-       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+       REG_WR(bp, BNX2_HC_COMMAND,
+              bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
        REG_RD(bp, BNX2_HC_COMMAND);
 
        udelay(5);
@@ -3662,7 +4000,7 @@ bnx2_test_loopback(struct bnx2 *bp)
        pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
        dev_kfree_skb_irq(skb);
 
-       if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
+       if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
                goto loopback_test_done;
        }
 
@@ -3681,7 +4019,7 @@ bnx2_test_loopback(struct bnx2 *bp)
                pci_unmap_addr(rx_buf, mapping),
                bp->rx_buf_size, PCI_DMA_FROMDEVICE);
 
-       if (rx_hdr->l2_fhdr_errors &
+       if (rx_hdr->l2_fhdr_status &
                (L2_FHDR_ERRORS_BAD_CRC |
                L2_FHDR_ERRORS_PHY_DECODE |
                L2_FHDR_ERRORS_ALIGNMENT |
@@ -3708,6 +4046,30 @@ loopback_test_done:
        return ret;
 }
 
+#define BNX2_MAC_LOOPBACK_FAILED       1
+#define BNX2_PHY_LOOPBACK_FAILED       2
+#define BNX2_LOOPBACK_FAILED           (BNX2_MAC_LOOPBACK_FAILED |     \
+                                        BNX2_PHY_LOOPBACK_FAILED)
+
+static int
+bnx2_test_loopback(struct bnx2 *bp)
+{
+       int rc = 0;
+
+       if (!netif_running(bp->dev))
+               return BNX2_LOOPBACK_FAILED;
+
+       bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
+       spin_lock_bh(&bp->phy_lock);
+       bnx2_init_phy(bp);
+       spin_unlock_bh(&bp->phy_lock);
+       if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
+               rc |= BNX2_MAC_LOOPBACK_FAILED;
+       if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
+               rc |= BNX2_PHY_LOOPBACK_FAILED;
+       return rc;
+}
+
 #define NVRAM_SIZE 0x200
 #define CRC32_RESIDUAL 0xdebb20e3
 
@@ -3751,10 +4113,10 @@ bnx2_test_link(struct bnx2 *bp)
 {
        u32 bmsr;
 
-       spin_lock_irq(&bp->phy_lock);
+       spin_lock_bh(&bp->phy_lock);
        bnx2_read_phy(bp, MII_BMSR, &bmsr);
        bnx2_read_phy(bp, MII_BMSR, &bmsr);
-       spin_unlock_irq(&bp->phy_lock);
+       spin_unlock_bh(&bp->phy_lock);
                
        if (bmsr & BMSR_LSTATUS) {
                return 0;
@@ -3766,7 +4128,6 @@ static int
 bnx2_test_intr(struct bnx2 *bp)
 {
        int i;
-       u32 val;
        u16 status_idx;
 
        if (!netif_running(bp->dev))
@@ -3775,8 +4136,7 @@ bnx2_test_intr(struct bnx2 *bp)
        status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
 
        /* This register is not touched during run-time. */
-       val = REG_RD(bp, BNX2_HC_COMMAND);
-       REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+       REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
        REG_RD(bp, BNX2_HC_COMMAND);
 
        for (i = 0; i < 10; i++) {
@@ -3800,23 +4160,29 @@ bnx2_timer(unsigned long data)
        struct bnx2 *bp = (struct bnx2 *) data;
        u32 msg;
 
+       if (!netif_running(bp->dev))
+               return;
+
        if (atomic_read(&bp->intr_sem) != 0)
                goto bnx2_restart_timer;
 
        msg = (u32) ++bp->fw_drv_pulse_wr_seq;
-       REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
+       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
+
+       bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
 
        if ((bp->phy_flags & PHY_SERDES_FLAG) &&
            (CHIP_NUM(bp) == CHIP_NUM_5706)) {
-               unsigned long flags;
 
-               spin_lock_irqsave(&bp->phy_lock, flags);
+               spin_lock(&bp->phy_lock);
                if (bp->serdes_an_pending) {
                        bp->serdes_an_pending--;
                }
                else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
                        u32 bmcr;
 
+                       bp->current_interval = bp->timer_interval;
+
                        bnx2_read_phy(bp, MII_BMCR, &bmcr);
 
                        if (bmcr & BMCR_ANENABLE) {
@@ -3859,24 +4225,24 @@ bnx2_timer(unsigned long data)
 
                        }
                }
+               else
+                       bp->current_interval = bp->timer_interval;
 
-               spin_unlock_irqrestore(&bp->phy_lock, flags);
+               spin_unlock(&bp->phy_lock);
        }
 
 bnx2_restart_timer:
-       bp->timer.expires = RUN_AT(bp->timer_interval);
-
-       add_timer(&bp->timer);
+       mod_timer(&bp->timer, jiffies + bp->current_interval);
 }
 
 /* Called with rtnl_lock */
 static int
 bnx2_open(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int rc;
 
-       bnx2_set_power_state(bp, 0);
+       bnx2_set_power_state(bp, PCI_D0);
        bnx2_disable_int(bp);
 
        rc = bnx2_alloc_mem(bp);
@@ -3919,12 +4285,7 @@ bnx2_open(struct net_device *dev)
                return rc;
        }
        
-       init_timer(&bp->timer);
-
-       bp->timer.expires = RUN_AT(bp->timer_interval);
-       bp->timer.data = (unsigned long) bp;
-       bp->timer.function = bnx2_timer;
-       add_timer(&bp->timer);
+       mod_timer(&bp->timer, jiffies + bp->current_interval);
 
        atomic_set(&bp->intr_sem, 0);
 
@@ -3975,18 +4336,23 @@ bnx2_reset_task(void *data)
 {
        struct bnx2 *bp = data;
 
+       if (!netif_running(bp->dev))
+               return;
+
+       bp->in_reset_task = 1;
        bnx2_netif_stop(bp);
 
        bnx2_init_nic(bp);
 
        atomic_set(&bp->intr_sem, 1);
        bnx2_netif_start(bp);
+       bp->in_reset_task = 0;
 }
 
 static void
 bnx2_tx_timeout(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        /* This allows the netif to be shutdown gracefully before resetting */
        schedule_work(&bp->reset_task);
@@ -3997,7 +4363,7 @@ bnx2_tx_timeout(struct net_device *dev)
 static void
 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        bnx2_netif_stop(bp);
 
@@ -4011,7 +4377,7 @@ bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
 static void
 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        bnx2_netif_stop(bp);
 
@@ -4023,7 +4389,7 @@ bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
 }
 #endif
 
-/* Called with dev->xmit_lock.
+/* Called with netif_tx_lock.
  * hard_start_xmit is pseudo-lockless - a lock is only required when
  * the tx queue is full. This way, we get the benefit of lockless
  * operations most of the time without the complexities to handle
@@ -4032,7 +4398,7 @@ bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
 static int
 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        dma_addr_t mapping;
        struct tx_bd *txbd;
        struct sw_bd *tx_buf;
@@ -4040,9 +4406,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
        u16 prod, ring_prod;
        int i;
 
-       if (unlikely(atomic_read(&bp->tx_avail_bd) <
-               (skb_shinfo(skb)->nr_frags + 1))) {
-
+       if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
                netif_stop_queue(dev);
                printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
                        dev->name);
@@ -4083,7 +4447,7 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
                ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
 
                skb->nh.iph->check = 0;
-               skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
+               skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
                skb->h.th->check =
                        ~csum_tcpudp_magic(skb->nh.iph->saddr,
                                            skb->nh.iph->daddr,
@@ -4139,8 +4503,6 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
        prod = NEXT_TX_BD(prod);
        bp->tx_prod_bseq += skb->len;
 
-       atomic_sub(last_frag + 1, &bp->tx_avail_bd);
-
        REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
        REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
 
@@ -4149,17 +4511,13 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
        bp->tx_prod = prod;
        dev->trans_start = jiffies;
 
-       if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) {
-               unsigned long flags;
-
-               spin_lock_irqsave(&bp->tx_lock, flags);
-               if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) {
-                       netif_stop_queue(dev);
-
-                       if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)
-                               netif_wake_queue(dev);
-               }
-               spin_unlock_irqrestore(&bp->tx_lock, flags);
+       if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
+               spin_lock(&bp->tx_lock);
+               netif_stop_queue(dev);
+               
+               if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
+                       netif_wake_queue(dev);
+               spin_unlock(&bp->tx_lock);
        }
 
        return NETDEV_TX_OK;
@@ -4169,13 +4527,21 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
 static int
 bnx2_close(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        u32 reset_code;
 
-       flush_scheduled_work();
+       /* Calling flush_scheduled_work() may deadlock because
+        * linkwatch_event() may be on the workqueue and it will try to get
+        * the rtnl_lock which we are holding.
+        */
+       while (bp->in_reset_task)
+               msleep(1);
+
        bnx2_netif_stop(bp);
        del_timer_sync(&bp->timer);
-       if (bp->wol)
+       if (bp->flags & NO_WOL_FLAG)
+               reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
+       else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
        else
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
@@ -4189,7 +4555,7 @@ bnx2_close(struct net_device *dev)
        bnx2_free_mem(bp);
        bp->link_up = 0;
        netif_carrier_off(bp->dev);
-       bnx2_set_power_state(bp, 3);
+       bnx2_set_power_state(bp, PCI_D3hot);
        return 0;
 }
 
@@ -4209,7 +4575,7 @@ bnx2_close(struct net_device *dev)
 static struct net_device_stats *
 bnx2_get_stats(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        struct statistics_block *stats_blk = bp->stats_blk;
        struct net_device_stats *net_stats = &bp->net_stats;
 
@@ -4259,7 +4625,8 @@ bnx2_get_stats(struct net_device *dev)
                (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
                stats_blk->stat_Dot3StatsLateCollisions);
 
-       if (CHIP_NUM(bp) == CHIP_NUM_5706)
+       if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_A0))
                net_stats->tx_carrier_errors = 0;
        else {
                net_stats->tx_carrier_errors =
@@ -4274,6 +4641,10 @@ bnx2_get_stats(struct net_device *dev)
                net_stats->tx_aborted_errors +
                net_stats->tx_carrier_errors;
 
+       net_stats->rx_missed_errors =
+               (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
+               stats_blk->stat_FwRxDrop);
+
        return net_stats;
 }
 
@@ -4282,7 +4653,7 @@ bnx2_get_stats(struct net_device *dev)
 static int
 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        cmd->supported = SUPPORTED_Autoneg;
        if (bp->phy_flags & PHY_SERDES_FLAG) {
@@ -4329,7 +4700,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 static int
 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        u8 autoneg = bp->autoneg;
        u8 req_duplex = bp->req_duplex;
        u16 req_line_speed = bp->req_line_speed;
@@ -4389,11 +4760,11 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        bp->req_line_speed = req_line_speed;
        bp->req_duplex = req_duplex;
 
-       spin_lock_irq(&bp->phy_lock);
+       spin_lock_bh(&bp->phy_lock);
 
        bnx2_setup_phy(bp);
 
-       spin_unlock_irq(&bp->phy_lock);
+       spin_unlock_bh(&bp->phy_lock);
 
        return 0;
 }
@@ -4401,7 +4772,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 static void
 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        strcpy(info->driver, DRV_MODULE_NAME);
        strcpy(info->version, DRV_MODULE_VERSION);
@@ -4409,15 +4780,72 @@ bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
        info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
        info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
        info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
-       info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
-       info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
-       info->fw_version[7] = 0;
+       info->fw_version[1] = info->fw_version[3] = '.';
+       info->fw_version[5] = 0;
+}
+
+#define BNX2_REGDUMP_LEN               (32 * 1024)
+
+static int
+bnx2_get_regs_len(struct net_device *dev)
+{
+       return BNX2_REGDUMP_LEN;
+}
+
+static void
+bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
+{
+       u32 *p = _p, i, offset;
+       u8 *orig_p = _p;
+       struct bnx2 *bp = netdev_priv(dev);
+       u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
+                                0x0800, 0x0880, 0x0c00, 0x0c10,
+                                0x0c30, 0x0d08, 0x1000, 0x101c,
+                                0x1040, 0x1048, 0x1080, 0x10a4,
+                                0x1400, 0x1490, 0x1498, 0x14f0,
+                                0x1500, 0x155c, 0x1580, 0x15dc,
+                                0x1600, 0x1658, 0x1680, 0x16d8,
+                                0x1800, 0x1820, 0x1840, 0x1854,
+                                0x1880, 0x1894, 0x1900, 0x1984,
+                                0x1c00, 0x1c0c, 0x1c40, 0x1c54,
+                                0x1c80, 0x1c94, 0x1d00, 0x1d84,
+                                0x2000, 0x2030, 0x23c0, 0x2400,
+                                0x2800, 0x2820, 0x2830, 0x2850,
+                                0x2b40, 0x2c10, 0x2fc0, 0x3058,
+                                0x3c00, 0x3c94, 0x4000, 0x4010,
+                                0x4080, 0x4090, 0x43c0, 0x4458,
+                                0x4c00, 0x4c18, 0x4c40, 0x4c54,
+                                0x4fc0, 0x5010, 0x53c0, 0x5444,
+                                0x5c00, 0x5c18, 0x5c80, 0x5c90,
+                                0x5fc0, 0x6000, 0x6400, 0x6428,
+                                0x6800, 0x6848, 0x684c, 0x6860,
+                                0x6888, 0x6910, 0x8000 };
+
+       regs->version = 0;
+
+       memset(p, 0, BNX2_REGDUMP_LEN);
+
+       if (!netif_running(bp->dev))
+               return;
+
+       i = 0;
+       offset = reg_boundaries[0];
+       p += offset;
+       while (offset < BNX2_REGDUMP_LEN) {
+               *p++ = REG_RD(bp, offset);
+               offset += 4;
+               if (offset == reg_boundaries[i + 1]) {
+                       offset = reg_boundaries[i + 2];
+                       p = (u32 *) (orig_p + offset);
+                       i += 2;
+               }
+       }
 }
 
 static void
 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        if (bp->flags & NO_WOL_FLAG) {
                wol->supported = 0;
@@ -4436,7 +4864,7 @@ bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 static int
 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        if (wol->wolopts & ~WAKE_MAGIC)
                return -EINVAL;
@@ -4456,26 +4884,27 @@ bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 static int
 bnx2_nway_reset(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        u32 bmcr;
 
        if (!(bp->autoneg & AUTONEG_SPEED)) {
                return -EINVAL;
        }
 
-       spin_lock_irq(&bp->phy_lock);
+       spin_lock_bh(&bp->phy_lock);
 
        /* Force a link down visible on the other side */
        if (bp->phy_flags & PHY_SERDES_FLAG) {
                bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
-               spin_unlock_irq(&bp->phy_lock);
+               spin_unlock_bh(&bp->phy_lock);
 
                msleep(20);
 
-               spin_lock_irq(&bp->phy_lock);
+               spin_lock_bh(&bp->phy_lock);
                if (CHIP_NUM(bp) == CHIP_NUM_5706) {
-                       bp->serdes_an_pending = SERDES_AN_TIMEOUT /
-                               bp->timer_interval;
+                       bp->current_interval = SERDES_AN_TIMEOUT;
+                       bp->serdes_an_pending = 1;
+                       mod_timer(&bp->timer, jiffies + bp->current_interval);
                }
        }
 
@@ -4483,7 +4912,7 @@ bnx2_nway_reset(struct net_device *dev)
        bmcr &= ~BMCR_LOOPBACK;
        bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
 
-       spin_unlock_irq(&bp->phy_lock);
+       spin_unlock_bh(&bp->phy_lock);
 
        return 0;
 }
@@ -4491,26 +4920,22 @@ bnx2_nway_reset(struct net_device *dev)
 static int
 bnx2_get_eeprom_len(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
-       if (bp->flash_info == 0)
+       if (bp->flash_info == NULL)
                return 0;
 
-       return (int) bp->flash_info->total_size;
+       return (int) bp->flash_size;
 }
 
 static int
 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
                u8 *eebuf)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int rc;
 
-       if (eeprom->offset > bp->flash_info->total_size)
-               return -EINVAL;
-
-       if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
-               eeprom->len = bp->flash_info->total_size - eeprom->offset;
+       /* parameters already validated in ethtool_get_eeprom */
 
        rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 
@@ -4521,14 +4946,10 @@ static int
 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
                u8 *eebuf)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int rc;
 
-       if (eeprom->offset > bp->flash_info->total_size)
-               return -EINVAL;
-
-       if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
-               eeprom->len = bp->flash_info->total_size - eeprom->offset;
+       /* parameters already validated in ethtool_set_eeprom */
 
        rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
 
@@ -4538,7 +4959,7 @@ bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
 static int
 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        memset(coal, 0, sizeof(struct ethtool_coalesce));
 
@@ -4560,7 +4981,7 @@ bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
 static int
 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
        if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
@@ -4604,9 +5025,9 @@ bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
 static void
 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
-       ering->rx_max_pending = MAX_RX_DESC_CNT;
+       ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
        ering->rx_mini_max_pending = 0;
        ering->rx_jumbo_max_pending = 0;
 
@@ -4621,19 +5042,30 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
 static int
 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
-       if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
+       if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
                (ering->tx_pending > MAX_TX_DESC_CNT) ||
                (ering->tx_pending <= MAX_SKB_FRAGS)) {
 
                return -EINVAL;
        }
-       bp->rx_ring_size = ering->rx_pending;
+       if (netif_running(bp->dev)) {
+               bnx2_netif_stop(bp);
+               bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
+               bnx2_free_skbs(bp);
+               bnx2_free_mem(bp);
+       }
+
+       bnx2_set_rx_ring_size(bp, ering->rx_pending);
        bp->tx_ring_size = ering->tx_pending;
 
        if (netif_running(bp->dev)) {
-               bnx2_netif_stop(bp);
+               int rc;
+
+               rc = bnx2_alloc_mem(bp);
+               if (rc)
+                       return rc;
                bnx2_init_nic(bp);
                bnx2_netif_start(bp);
        }
@@ -4644,7 +5076,7 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
 static void
 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
        epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
@@ -4654,7 +5086,7 @@ bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
 static int
 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        bp->req_flow_ctrl = 0;
        if (epause->rx_pause)
@@ -4669,11 +5101,11 @@ bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
                bp->autoneg &= ~AUTONEG_FLOW_CTRL;
        }
 
-       spin_lock_irq(&bp->phy_lock);
+       spin_lock_bh(&bp->phy_lock);
 
        bnx2_setup_phy(bp);
 
-       spin_unlock_irq(&bp->phy_lock);
+       spin_unlock_bh(&bp->phy_lock);
 
        return 0;
 }
@@ -4681,7 +5113,7 @@ bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
 static u32
 bnx2_get_rx_csum(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        return bp->rx_csum;
 }
@@ -4689,13 +5121,13 @@ bnx2_get_rx_csum(struct net_device *dev)
 static int
 bnx2_set_rx_csum(struct net_device *dev, u32 data)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        bp->rx_csum = data;
        return 0;
 }
 
-#define BNX2_NUM_STATS 45
+#define BNX2_NUM_STATS 46
 
 static struct {
        char string[ETH_GSTRING_LEN];
@@ -4745,11 +5177,12 @@ static struct {
        { "rx_mac_ctrl_frames" },
        { "rx_filtered_packets" },
        { "rx_discards" },
+       { "rx_fw_discards" },
 };
 
 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
 
-static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
+static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
     STATS_OFFSET32(stat_IfHCInOctets_hi),
     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
     STATS_OFFSET32(stat_IfHCOutOctets_hi),
@@ -4795,6 +5228,7 @@ static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
     STATS_OFFSET32(stat_MacControlFramesReceived),                    
     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),                  
     STATS_OFFSET32(stat_IfInMBUFDiscards),                            
+    STATS_OFFSET32(stat_FwRxDrop),
 };
 
 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
@@ -4805,7 +5239,15 @@ static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
        4,0,4,4,4,4,4,4,4,4,
        4,4,4,4,4,4,4,4,4,4,
        4,4,4,4,4,4,4,4,4,4,
-       4,4,4,4,4,
+       4,4,4,4,4,4,
+};
+
+static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
+       8,0,8,8,8,8,8,8,8,8,
+       4,4,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,4,4,4,4,4,
+       4,4,4,4,4,4,
 };
 
 #define BNX2_NUM_TESTS 6
@@ -4830,7 +5272,7 @@ bnx2_self_test_count(struct net_device *dev)
 static void
 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
        if (etest->flags & ETH_TEST_FL_OFFLINE) {
@@ -4846,10 +5288,8 @@ bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
                        buf[1] = 1;
                        etest->flags |= ETH_TEST_FL_FAILED;
                }
-               if (bnx2_test_loopback(bp) != 0) {
-                       buf[2] = 1;
+               if ((buf[2] = bnx2_test_loopback(bp)) != 0)
                        etest->flags |= ETH_TEST_FL_FAILED;
-               }
 
                if (!netif_running(bp->dev)) {
                        bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
@@ -4906,7 +5346,7 @@ static void
 bnx2_get_ethtool_stats(struct net_device *dev,
                struct ethtool_stats *stats, u64 *buf)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int i;
        u32 *hw_stats = (u32 *) bp->stats_blk;
        u8 *stats_len_arr = NULL;
@@ -4916,8 +5356,13 @@ bnx2_get_ethtool_stats(struct net_device *dev,
                return;
        }
 
-       if (CHIP_NUM(bp) == CHIP_NUM_5706)
+       if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
+           (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
+           (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_A0))
                stats_len_arr = bnx2_5706_stats_len_arr;
+       else
+               stats_len_arr = bnx2_5708_stats_len_arr;
 
        for (i = 0; i < BNX2_NUM_STATS; i++) {
                if (stats_len_arr[i] == 0) {
@@ -4941,7 +5386,7 @@ bnx2_get_ethtool_stats(struct net_device *dev,
 static int
 bnx2_phys_id(struct net_device *dev, u32 data)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int i;
        u32 save;
 
@@ -4976,6 +5421,8 @@ static struct ethtool_ops bnx2_ethtool_ops = {
        .get_settings           = bnx2_get_settings,
        .set_settings           = bnx2_set_settings,
        .get_drvinfo            = bnx2_get_drvinfo,
+       .get_regs_len           = bnx2_get_regs_len,
+       .get_regs               = bnx2_get_regs,
        .get_wol                = bnx2_get_wol,
        .set_wol                = bnx2_set_wol,
        .nway_reset             = bnx2_nway_reset,
@@ -5005,6 +5452,7 @@ static struct ethtool_ops bnx2_ethtool_ops = {
        .phys_id                = bnx2_phys_id,
        .get_stats_count        = bnx2_get_stats_count,
        .get_ethtool_stats      = bnx2_get_ethtool_stats,
+       .get_perm_addr          = ethtool_op_get_perm_addr,
 };
 
 /* Called with rtnl_lock */
@@ -5012,7 +5460,7 @@ static int
 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
        struct mii_ioctl_data *data = if_mii(ifr);
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        int err;
 
        switch(cmd) {
@@ -5023,9 +5471,9 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        case SIOCGMIIREG: {
                u32 mii_regval;
 
-               spin_lock_irq(&bp->phy_lock);
+               spin_lock_bh(&bp->phy_lock);
                err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
-               spin_unlock_irq(&bp->phy_lock);
+               spin_unlock_bh(&bp->phy_lock);
 
                data->val_out = mii_regval;
 
@@ -5036,9 +5484,9 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (!capable(CAP_NET_ADMIN))
                        return -EPERM;
 
-               spin_lock_irq(&bp->phy_lock);
+               spin_lock_bh(&bp->phy_lock);
                err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
-               spin_unlock_irq(&bp->phy_lock);
+               spin_unlock_bh(&bp->phy_lock);
 
                return err;
 
@@ -5054,7 +5502,10 @@ static int
 bnx2_change_mac_addr(struct net_device *dev, void *p)
 {
        struct sockaddr *addr = p;
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
+
+       if (!is_valid_ether_addr(addr->sa_data))
+               return -EINVAL;
 
        memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
        if (netif_running(dev))
@@ -5067,7 +5518,7 @@ bnx2_change_mac_addr(struct net_device *dev, void *p)
 static int
 bnx2_change_mtu(struct net_device *dev, int new_mtu)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
                ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
@@ -5088,7 +5539,7 @@ bnx2_change_mtu(struct net_device *dev, int new_mtu)
 static void
 poll_bnx2(struct net_device *dev)
 {
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        disable_irq(bp->pdev->irq);
        bnx2_interrupt(bp->pdev->irq, dev, NULL);
@@ -5106,7 +5557,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
        SET_MODULE_OWNER(dev);
        SET_NETDEV_DEV(dev, &pdev->dev);
-       bp = dev->priv;
+       bp = netdev_priv(dev);
 
        bp->flags = 0;
        bp->phy_flags = 0;
@@ -5191,12 +5642,10 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
                               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
 
-       bnx2_set_power_state(bp, 0);
+       bnx2_set_power_state(bp, PCI_D0);
 
        bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
 
-       bp->phy_addr = 1;
-
        /* Get bus information. */
        reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
        if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
@@ -5259,10 +5708,18 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
        bnx2_init_nvram(bp);
 
+       reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
+
+       if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
+           BNX2_SHM_HDR_SIGNATURE_SIG)
+               bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
+       else
+               bp->shmem_base = HOST_VIEW_SHMEM_BASE;
+
        /* Get the permanent MAC address.  First we need to make sure the
         * firmware is actually running.
         */
-       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
+       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
 
        if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
            BNX2_DEV_INFO_SIGNATURE_MAGIC) {
@@ -5271,21 +5728,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                goto err_out_unmap;
        }
 
-       bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
-                               BNX2_DEV_INFO_BC_REV);
+       bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
 
-       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
+       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
        bp->mac_addr[0] = (u8) (reg >> 8);
        bp->mac_addr[1] = (u8) reg;
 
-       reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
+       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
        bp->mac_addr[2] = (u8) (reg >> 24);
        bp->mac_addr[3] = (u8) (reg >> 16);
        bp->mac_addr[4] = (u8) (reg >> 8);
        bp->mac_addr[5] = (u8) reg;
 
        bp->tx_ring_size = MAX_TX_DESC_CNT;
-       bp->rx_ring_size = 100;
+       bnx2_set_rx_ring_size(bp, 100);
 
        bp->rx_csum = 1;
 
@@ -5304,13 +5760,28 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
        bp->stats_ticks = 1000000 & 0xffff00;
 
        bp->timer_interval =  HZ;
+       bp->current_interval =  HZ;
+
+       bp->phy_addr = 1;
 
        /* Disable WOL support if we are running on a SERDES chip. */
        if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
                bp->phy_flags |= PHY_SERDES_FLAG;
                bp->flags |= NO_WOL_FLAG;
+               if (CHIP_NUM(bp) == CHIP_NUM_5708) {
+                       bp->phy_addr = 2;
+                       reg = REG_RD_IND(bp, bp->shmem_base +
+                                        BNX2_SHARED_HW_CFG_CONFIG);
+                       if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
+                               bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
+               }
        }
 
+       if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_B1))
+               bp->flags |= NO_WOL_FLAG;
+
        if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
                bp->tx_quick_cons_trip_int =
                        bp->tx_quick_cons_trip;
@@ -5327,6 +5798,14 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
        bp->req_line_speed = 0;
        if (bp->phy_flags & PHY_SERDES_FLAG) {
                bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
+
+               reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
+               reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
+               if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
+                       bp->autoneg = 0;
+                       bp->req_line_speed = bp->line_speed = SPEED_1000;
+                       bp->req_duplex = DUPLEX_FULL;
+               }
        }
        else {
                bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
@@ -5334,11 +5813,17 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
        bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
 
+       init_timer(&bp->timer);
+       bp->timer.expires = RUN_AT(bp->timer_interval);
+       bp->timer.data = (unsigned long) bp;
+       bp->timer.function = bnx2_timer;
+
        return 0;
 
 err_out_unmap:
        if (bp->regview) {
                iounmap(bp->regview);
+               bp->regview = NULL;
        }
 
 err_out_release:
@@ -5393,7 +5878,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
        dev->ethtool_ops = &bnx2_ethtool_ops;
        dev->weight = 64;
 
-       bp = dev->priv;
+       bp = netdev_priv(dev);
 
 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
        dev->poll_controller = poll_bnx2;
@@ -5413,6 +5898,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
        pci_set_drvdata(pdev, dev);
 
        memcpy(dev->dev_addr, bp->mac_addr, 6);
+       memcpy(dev->perm_addr, bp->mac_addr, 6);
        bp->name = board_info[ent->driver_data].name,
        printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
                "IRQ %d, ",
@@ -5451,7 +5937,9 @@ static void __devexit
 bnx2_remove_one(struct pci_dev *pdev)
 {
        struct net_device *dev = pci_get_drvdata(pdev);
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
+
+       flush_scheduled_work();
 
        unregister_netdev(dev);
 
@@ -5465,25 +5953,28 @@ bnx2_remove_one(struct pci_dev *pdev)
 }
 
 static int
-bnx2_suspend(struct pci_dev *pdev, u32 state)
+bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
 {
        struct net_device *dev = pci_get_drvdata(pdev);
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
        u32 reset_code;
 
        if (!netif_running(dev))
                return 0;
 
+       flush_scheduled_work();
        bnx2_netif_stop(bp);
        netif_device_detach(dev);
        del_timer_sync(&bp->timer);
-       if (bp->wol)
+       if (bp->flags & NO_WOL_FLAG)
+               reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
+       else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
        else
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
        bnx2_reset_chip(bp, reset_code);
        bnx2_free_skbs(bp);
-       bnx2_set_power_state(bp, state);
+       bnx2_set_power_state(bp, pci_choose_state(pdev, state));
        return 0;
 }
 
@@ -5491,12 +5982,12 @@ static int
 bnx2_resume(struct pci_dev *pdev)
 {
        struct net_device *dev = pci_get_drvdata(pdev);
-       struct bnx2 *bp = dev->priv;
+       struct bnx2 *bp = netdev_priv(dev);
 
        if (!netif_running(dev))
                return 0;
 
-       bnx2_set_power_state(bp, 0);
+       bnx2_set_power_state(bp, PCI_D0);
        netif_device_attach(dev);
        bnx2_init_nic(bp);
        bnx2_netif_start(bp);