Merge branch 'gpu-switcher' of /ssd/git//linux-2.6 into drm-next-stage
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_drv.h
index cb0cfe4..4fe1646 100644 (file)
@@ -34,6 +34,8 @@
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
 
+#include "radeon_family.h"
+
 /* General customization:
  */
 
  * 1.29- R500 3D cmd buffer support
  * 1.30- Add support for occlusion queries
  * 1.31- Add support for num Z pipes from GET_PARAM
+ * 1.32- fixes for rv740 setup
  */
 #define DRIVER_MAJOR           1
-#define DRIVER_MINOR           31
+#define DRIVER_MINOR           32
 #define DRIVER_PATCHLEVEL      0
 
-/*
- * Radeon chip families
- */
-enum radeon_family {
-       CHIP_R100,
-       CHIP_RV100,
-       CHIP_RS100,
-       CHIP_RV200,
-       CHIP_RS200,
-       CHIP_R200,
-       CHIP_RV250,
-       CHIP_RS300,
-       CHIP_RV280,
-       CHIP_R300,
-       CHIP_R350,
-       CHIP_RV350,
-       CHIP_RV380,
-       CHIP_R420,
-       CHIP_R423,
-       CHIP_RV410,
-       CHIP_RS400,
-       CHIP_RS480,
-       CHIP_RS600,
-       CHIP_RS690,
-       CHIP_RS740,
-       CHIP_RV515,
-       CHIP_R520,
-       CHIP_RV530,
-       CHIP_RV560,
-       CHIP_RV570,
-       CHIP_R580,
-       CHIP_R600,
-       CHIP_RV610,
-       CHIP_RV630,
-       CHIP_RV620,
-       CHIP_RV635,
-       CHIP_RV670,
-       CHIP_RS780,
-       CHIP_RS880,
-       CHIP_RV770,
-       CHIP_RV730,
-       CHIP_RV710,
-       CHIP_RV740,
-       CHIP_LAST,
-};
-
 enum radeon_cp_microcode_version {
        UCODE_R100,
        UCODE_R200,
        UCODE_R300,
 };
 
-/*
- * Chip flags
- */
-enum radeon_chip_flags {
-       RADEON_FAMILY_MASK = 0x0000ffffUL,
-       RADEON_FLAGS_MASK = 0xffff0000UL,
-       RADEON_IS_MOBILITY = 0x00010000UL,
-       RADEON_IS_IGP = 0x00020000UL,
-       RADEON_SINGLE_CRTC = 0x00040000UL,
-       RADEON_IS_AGP = 0x00080000UL,
-       RADEON_HAS_HIERZ = 0x00100000UL,
-       RADEON_IS_PCIE = 0x00200000UL,
-       RADEON_NEW_MEMMAP = 0x00400000UL,
-       RADEON_IS_PCI = 0x00800000UL,
-       RADEON_IS_IGPGART = 0x01000000UL,
-};
-
 typedef struct drm_radeon_freelist {
        unsigned int age;
        struct drm_buf *buf;
@@ -328,6 +268,8 @@ typedef struct drm_radeon_private {
 
        u32 scratch_ages[5];
 
+       int have_z_offset;
+
        /* starting from here on, data is preserved accross an open */
        uint32_t flags;         /* see radeon_chip_flags */
        resource_size_t fb_aper_offset;
@@ -355,6 +297,9 @@ typedef struct drm_radeon_private {
        int r700_sc_prim_fifo_size;
        int r700_sc_hiz_tile_fifo_size;
        int r700_sc_earlyz_tile_fifo_fize;
+       int r600_group_size;
+       int r600_npipes;
+       int r600_nbanks;
 
        struct mutex cs_mutex;
        u32 cs_id_scnt;
@@ -370,9 +315,11 @@ typedef struct drm_radeon_buf_priv {
        u32 age;
 } drm_radeon_buf_priv_t;
 
+struct drm_buffer;
+
 typedef struct drm_radeon_kcmd_buffer {
        int bufsz;
-       char *buf;
+       struct drm_buffer *buffer;
        int nbox;
        struct drm_clip_rect __user *boxes;
 } drm_radeon_kcmd_buffer_t;
@@ -515,6 +462,9 @@ extern void r600_blit_swap(struct drm_device *dev,
                           int sx, int sy, int dx, int dy,
                           int w, int h, int src_pitch, int dst_pitch, int cpp);
 
+/* atpx handler */
+void radeon_register_atpx_handler(void);
+void radeon_unregister_atpx_handler(void);
 /* Flags for stats.boxes
  */
 #define RADEON_BOX_DMA_IDLE      0x1
@@ -1165,7 +1115,6 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
 #       define R600_IT_WAIT_REG_MEM             0x00003C00
 #       define R600_IT_MEM_WRITE                0x00003D00
 #       define R600_IT_INDIRECT_BUFFER          0x00003200
-#       define R600_IT_CP_INTERRUPT             0x00004000
 #       define R600_IT_SURFACE_SYNC             0x00004300
 #              define R600_CB0_DEST_BASE_ENA    (1 << 6)
 #              define R600_TC_ACTION_ENA        (1 << 23)
@@ -2183,4 +2132,32 @@ extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
        write &= mask;                                          \
 } while (0)
 
+/**
+ * Copy given number of dwords from drm buffer to the ring buffer.
+ */
+#define OUT_RING_DRM_BUFFER(buf, sz) do {                              \
+       int _size = (sz) * 4;                                           \
+       struct drm_buffer *_buf = (buf);                                \
+       int _part_size;                                                 \
+       while (_size > 0) {                                             \
+               _part_size = _size;                                     \
+                                                                       \
+               if (write + _part_size/4 > mask)                        \
+                       _part_size = ((mask + 1) - write)*4;            \
+                                                                       \
+               if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE)    \
+                       _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
+                                                                       \
+                                                                       \
+                                                                       \
+               memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
+                       [drm_buffer_index(_buf)], _part_size);          \
+                                                                       \
+               _size -= _part_size;                                    \
+               write = (write + _part_size/4) & mask;                  \
+               drm_buffer_advance(_buf, _part_size);                   \
+       }                                                               \
+} while (0)
+
+
 #endif                         /* __RADEON_DRV_H__ */