radeon: Use request_firmware()
[linux-2.6.git] / drivers / gpu / drm / radeon / r100.c
index 0e00fef..639d5b2 100644 (file)
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_drm.h"
-#include "radeon_microcode.h"
 #include "radeon_reg.h"
 #include "radeon.h"
+#include <linux/firmware.h>
+#include <linux/platform_device.h>
+
+/* Firmware Names */
+#define FIRMWARE_R100          "radeon/R100_cp.bin"
+#define FIRMWARE_R200          "radeon/R200_cp.bin"
+#define FIRMWARE_R300          "radeon/R300_cp.bin"
+#define FIRMWARE_R420          "radeon/R420_cp.bin"
+#define FIRMWARE_RS690         "radeon/RS690_cp.bin"
+#define FIRMWARE_RS600         "radeon/RS600_cp.bin"
+#define FIRMWARE_R520          "radeon/R520_cp.bin"
+
+MODULE_FIRMWARE(FIRMWARE_R100);
+MODULE_FIRMWARE(FIRMWARE_R200);
+MODULE_FIRMWARE(FIRMWARE_R300);
+MODULE_FIRMWARE(FIRMWARE_R420);
+MODULE_FIRMWARE(FIRMWARE_RS690);
+MODULE_FIRMWARE(FIRMWARE_RS600);
+MODULE_FIRMWARE(FIRMWARE_R520);
 
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
@@ -173,8 +191,12 @@ void r100_mc_setup(struct radeon_device *rdev)
                DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
        }
        /* Write VRAM size in case we are limiting it */
-       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+       /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
+        * if the aperture is 64MB but we have 32MB VRAM
+        * we report only 32MB VRAM but we have to set MC_FB_LOCATION
+        * to 64MB, otherwise the gpu accidentially dies */
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32(RADEON_MC_FB_LOCATION, tmp);
@@ -250,6 +272,72 @@ void r100_mc_fini(struct radeon_device *rdev)
 
 
 /*
+ * Interrupts
+ */
+int r100_irq_set(struct radeon_device *rdev)
+{
+       uint32_t tmp = 0;
+
+       if (rdev->irq.sw_int) {
+               tmp |= RADEON_SW_INT_ENABLE;
+       }
+       if (rdev->irq.crtc_vblank_int[0]) {
+               tmp |= RADEON_CRTC_VBLANK_MASK;
+       }
+       if (rdev->irq.crtc_vblank_int[1]) {
+               tmp |= RADEON_CRTC2_VBLANK_MASK;
+       }
+       WREG32(RADEON_GEN_INT_CNTL, tmp);
+       return 0;
+}
+
+static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
+{
+       uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
+       uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
+               RADEON_CRTC2_VBLANK_STAT;
+
+       if (irqs) {
+               WREG32(RADEON_GEN_INT_STATUS, irqs);
+       }
+       return irqs & irq_mask;
+}
+
+int r100_irq_process(struct radeon_device *rdev)
+{
+       uint32_t status;
+
+       status = r100_irq_ack(rdev);
+       if (!status) {
+               return IRQ_NONE;
+       }
+       while (status) {
+               /* SW interrupt */
+               if (status & RADEON_SW_INT_TEST) {
+                       radeon_fence_process(rdev);
+               }
+               /* Vertical blank interrupts */
+               if (status & RADEON_CRTC_VBLANK_STAT) {
+                       drm_handle_vblank(rdev->ddev, 0);
+               }
+               if (status & RADEON_CRTC2_VBLANK_STAT) {
+                       drm_handle_vblank(rdev->ddev, 1);
+               }
+               status = r100_irq_ack(rdev);
+       }
+       return IRQ_HANDLED;
+}
+
+u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
+{
+       if (crtc == 0)
+               return RREG32(RADEON_CRTC_CRNT_FRAME);
+       else
+               return RREG32(RADEON_CRTC2_CRNT_FRAME);
+}
+
+
+/*
  * Fence emission
  */
 void r100_fence_ring_emit(struct radeon_device *rdev,
@@ -408,33 +496,33 @@ void r100_ring_start(struct radeon_device *rdev)
        radeon_ring_unlock_commit(rdev);
 }
 
-static void r100_cp_load_microcode(struct radeon_device *rdev)
+
+/* Load the microcode for the CP */
+static int r100_cp_init_microcode(struct radeon_device *rdev)
 {
-       int i;
+       struct platform_device *pdev;
+       const char *fw_name = NULL;
+       int err;
 
-       if (r100_gui_wait_for_idle(rdev)) {
-               printk(KERN_WARNING "Failed to wait GUI idle while "
-                      "programming pipes. Bad things might happen.\n");
-       }
+       DRM_DEBUG("\n");
 
-       WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+       pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+       err = IS_ERR(pdev);
+       if (err) {
+               printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+               return -EINVAL;
+       }
        if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
            (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
            (rdev->family == CHIP_RS200)) {
                DRM_INFO("Loading R100 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_R100;
        } else if ((rdev->family == CHIP_R200) ||
                   (rdev->family == CHIP_RV250) ||
                   (rdev->family == CHIP_RV280) ||
                   (rdev->family == CHIP_RS300)) {
                DRM_INFO("Loading R200 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_R200;
        } else if ((rdev->family == CHIP_R300) ||
                   (rdev->family == CHIP_R350) ||
                   (rdev->family == CHIP_RV350) ||
@@ -442,31 +530,19 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
                   (rdev->family == CHIP_RS400) ||
                   (rdev->family == CHIP_RS480)) {
                DRM_INFO("Loading R300 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_R300;
        } else if ((rdev->family == CHIP_R420) ||
                   (rdev->family == CHIP_R423) ||
                   (rdev->family == CHIP_RV410)) {
                DRM_INFO("Loading R400 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_R420;
        } else if ((rdev->family == CHIP_RS690) ||
                   (rdev->family == CHIP_RS740)) {
                DRM_INFO("Loading RS690/RS740 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_RS690;
        } else if (rdev->family == CHIP_RS600) {
                DRM_INFO("Loading RS600 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
-               }
+               fw_name = FIRMWARE_RS600;
        } else if ((rdev->family == CHIP_RV515) ||
                   (rdev->family == CHIP_R520) ||
                   (rdev->family == CHIP_RV530) ||
@@ -474,9 +550,43 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
                   (rdev->family == CHIP_RV560) ||
                   (rdev->family == CHIP_RV570)) {
                DRM_INFO("Loading R500 Microcode\n");
-               for (i = 0; i < 256; i++) {
-                       WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
-                       WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
+               fw_name = FIRMWARE_R520;
+       }
+
+       err = request_firmware(&rdev->fw, fw_name, &pdev->dev);
+       platform_device_unregister(pdev);
+       if (err) {
+               printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
+                      fw_name);
+       } else if (rdev->fw->size % 8) {
+               printk(KERN_ERR
+                      "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
+                      rdev->fw->size, fw_name);
+               err = -EINVAL;
+               release_firmware(rdev->fw);
+               rdev->fw = NULL;
+       }
+       return err;
+}
+static void r100_cp_load_microcode(struct radeon_device *rdev)
+{
+       const __be32 *fw_data;
+       int i, size;
+
+       if (r100_gui_wait_for_idle(rdev)) {
+               printk(KERN_WARNING "Failed to wait GUI idle while "
+                      "programming pipes. Bad things might happen.\n");
+       }
+
+       if (rdev->fw) {
+               size = rdev->fw->size / 4;
+               fw_data = (const __be32 *)&rdev->fw->data[0];
+               WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+               for (i = 0; i < size; i += 2) {
+                       WREG32(RADEON_CP_ME_RAM_DATAH,
+                              be32_to_cpup(&fw_data[i]));
+                       WREG32(RADEON_CP_ME_RAM_DATAL,
+                              be32_to_cpup(&fw_data[i + 1]));
                }
        }
 }
@@ -515,6 +625,15 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        } else {
                DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
        }
+
+       if (!rdev->fw) {
+               r = r100_cp_init_microcode(rdev);
+               if (r) {
+                       DRM_ERROR("Failed to load firmware!\n");
+                       return r;
+               }
+       }
+
        /* Align ring size */
        rb_bufsz = drm_order(ring_size / 8);
        ring_size = (1 << (rb_bufsz + 1)) * 4;
@@ -718,13 +837,14 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p,
                         unsigned idx)
 {
        struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
-       uint32_t header = ib_chunk->kdata[idx];
+       uint32_t header;
 
        if (idx >= ib_chunk->length_dw) {
                DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
                          idx, ib_chunk->length_dw);
                return -EINVAL;
        }
+       header = ib_chunk->kdata[idx];
        pkt->idx = idx;
        pkt->type = CP_PACKET_GET_TYPE(header);
        pkt->count = CP_PACKET_GET_COUNT(header);
@@ -1447,25 +1567,28 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
                uint32_t tom;
                /* read NB_TOM to get the amount of ram stolen for the GPU */
                tom = RREG32(RADEON_NB_TOM);
-               rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
+               rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
                /* for IGPs we need to keep VRAM where it was put by the BIOS */
                rdev->mc.vram_location = (tom & 0xffff) << 16;
-               WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+               WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+               rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
        } else {
-               rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+               rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
                /* Some production boards of m6 will report 0
                 * if it's 8 MB
                 */
-               if (rdev->mc.vram_size == 0) {
-                       rdev->mc.vram_size = 8192 * 1024;
-                       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+               if (rdev->mc.real_vram_size == 0) {
+                       rdev->mc.real_vram_size = 8192 * 1024;
+                       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
                }
                /* let driver place VRAM */
                rdev->mc.vram_location = 0xFFFFFFFFUL;
                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
                  * Novell bug 204882 + along with lots of ubuntu ones */
-               if (config_aper_size > rdev->mc.vram_size)
-                       rdev->mc.vram_size = config_aper_size;
+               if (config_aper_size > rdev->mc.real_vram_size)
+                       rdev->mc.mc_vram_size = config_aper_size;
+               else
+                       rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
        }
 
        /* work out accessible VRAM */
@@ -1477,8 +1600,11 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
        if (accessible > rdev->mc.aper_size)
                accessible = rdev->mc.aper_size;
 
-       if (rdev->mc.vram_size > rdev->mc.aper_size)
-               rdev->mc.vram_size = rdev->mc.aper_size;
+       if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
+               rdev->mc.mc_vram_size = rdev->mc.aper_size;
+
+       if (rdev->mc.real_vram_size > rdev->mc.aper_size)
+               rdev->mc.real_vram_size = rdev->mc.aper_size;
 }
 
 void r100_vram_info(struct radeon_device *rdev)
@@ -1545,26 +1671,6 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
        r100_pll_errata_after_data(rdev);
 }
 
-uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
-{
-       if (reg < 0x10000)
-               return readl(((void __iomem *)rdev->rmmio) + reg);
-       else {
-               writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
-               return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
-       }
-}
-
-void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
-{
-       if (reg < 0x10000)
-               writel(v, ((void __iomem *)rdev->rmmio) + reg);
-       else {
-               writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
-               writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
-       }
-}
-
 int r100_init(struct radeon_device *rdev)
 {
        return 0;