Fix common misspellings
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreen_cs.c
index 64516b9..23d3641 100644 (file)
@@ -29,6 +29,7 @@
 #include "radeon.h"
 #include "evergreend.h"
 #include "evergreen_reg_safe.h"
+#include "cayman_reg_safe.h"
 
 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
                                          struct radeon_cs_reloc **cs_reloc);
@@ -292,33 +293,28 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
        if (wait_reg_mem.type != PACKET_TYPE3 ||
            wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
                DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
-               r = -EINVAL;
-               return r;
+               return -EINVAL;
        }
 
        wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
        /* bit 4 is reg (0) or mem (1) */
        if (wait_reg_mem_info & 0x10) {
                DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
-               r = -EINVAL;
-               return r;
+               return -EINVAL;
        }
        /* waiting for value to be equal */
        if ((wait_reg_mem_info & 0x7) != 0x3) {
                DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
-               r = -EINVAL;
-               return r;
+               return -EINVAL;
        }
        if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
                DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
-               r = -EINVAL;
-               return r;
+               return -EINVAL;
        }
 
        if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
                DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
-               r = -EINVAL;
-               return r;
+               return -EINVAL;
        }
 
        /* jump over the NOP */
@@ -333,12 +329,10 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
        header = radeon_get_ib_value(p, h_idx);
        crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
        reg = CP_PACKET0_GET_REG(header);
-       mutex_lock(&p->rdev->ddev->mode_config.mutex);
        obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
        if (!obj) {
                DRM_ERROR("cannot find crtc %d\n", crtc_id);
-               r = -EINVAL;
-               goto out;
+               return -EINVAL;
        }
        crtc = obj_to_crtc(obj);
        radeon_crtc = to_radeon_crtc(crtc);
@@ -363,13 +357,10 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
                        break;
                default:
                        DRM_ERROR("unknown crtc reloc\n");
-                       r = -EINVAL;
-                       goto out;
+                       return -EINVAL;
                }
        }
-out:
-       mutex_unlock(&p->rdev->ddev->mode_config.mutex);
-       return r;
+       return 0;
 }
 
 static int evergreen_packet0_check(struct radeon_cs_parser *p,
@@ -427,21 +418,31 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
 {
        struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
        struct radeon_cs_reloc *reloc;
-       u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
+       u32 last_reg;
        u32 m, i, tmp, *ib;
        int r;
 
+       if (p->rdev->family >= CHIP_CAYMAN)
+               last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
+       else
+               last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
+
        i = (reg >> 7);
        if (i > last_reg) {
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return -EINVAL;
        }
        m = 1 << ((reg >> 2) & 31);
-       if (!(evergreen_reg_safe_bm[i] & m))
-               return 0;
+       if (p->rdev->family >= CHIP_CAYMAN) {
+               if (!(cayman_reg_safe_bm[i] & m))
+                       return 0;
+       } else {
+               if (!(evergreen_reg_safe_bm[i] & m))
+                       return 0;
+       }
        ib = p->ib->ptr;
        switch (reg) {
-       /* force following reg to 0 in an attemp to disable out buffer
+       /* force following reg to 0 in an attempt to disable out buffer
         * which will need us to better understand how it works to perform
         * security check on it (Jerome)
         */
@@ -470,12 +471,42 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
        case SQ_VSTMP_RING_ITEMSIZE:
        case VGT_TF_RING_SIZE:
                /* get value to populate the IB don't remove */
-               tmp =radeon_get_ib_value(p, idx);
-               ib[idx] = 0;
+               /*tmp =radeon_get_ib_value(p, idx);
+                 ib[idx] = 0;*/
+               break;
+       case SQ_ESGS_RING_BASE:
+       case SQ_GSVS_RING_BASE:
+       case SQ_ESTMP_RING_BASE:
+       case SQ_GSTMP_RING_BASE:
+       case SQ_HSTMP_RING_BASE:
+       case SQ_LSTMP_RING_BASE:
+       case SQ_PSTMP_RING_BASE:
+       case SQ_VSTMP_RING_BASE:
+               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               if (r) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                       "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                break;
        case DB_DEPTH_CONTROL:
                track->db_depth_control = radeon_get_ib_value(p, idx);
                break;
+       case CAYMAN_DB_EQAA:
+               if (p->rdev->family < CHIP_CAYMAN) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               break;
+       case CAYMAN_DB_DEPTH_INFO:
+               if (p->rdev->family < CHIP_CAYMAN) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               break;
        case DB_Z_INFO:
                r = evergreen_cs_packet_next_reloc(p, &reloc);
                if (r) {
@@ -561,9 +592,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
                track->cb_shader_mask = radeon_get_ib_value(p, idx);
                break;
        case PA_SC_AA_CONFIG:
+               if (p->rdev->family >= CHIP_CAYMAN) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                "0x%04X\n", reg);
+                       return -EINVAL;
+               }
                tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
                track->nsamples = 1 << tmp;
                break;
+       case CAYMAN_PA_SC_AA_CONFIG:
+               if (p->rdev->family < CHIP_CAYMAN) {
+                       dev_warn(p->dev, "bad SET_CONTEXT_REG "
+                                "0x%04X\n", reg);
+                       return -EINVAL;
+               }
+               tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
+               track->nsamples = 1 << tmp;
+               break;
        case CB_COLOR0_VIEW:
        case CB_COLOR1_VIEW:
        case CB_COLOR2_VIEW:
@@ -944,6 +989,37 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
        idx_value = radeon_get_ib_value(p, idx);
 
        switch (pkt->opcode) {
+       case PACKET3_SET_PREDICATION:
+       {
+               int pred_op;
+               int tmp;
+               if (pkt->count != 1) {
+                       DRM_ERROR("bad SET PREDICATION\n");
+                       return -EINVAL;
+               }
+
+               tmp = radeon_get_ib_value(p, idx + 1);
+               pred_op = (tmp >> 16) & 0x7;
+
+               /* for the clear predicate operation */
+               if (pred_op == 0)
+                       return 0;
+
+               if (pred_op > 2) {
+                       DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
+                       return -EINVAL;
+               }
+
+               r = evergreen_cs_packet_next_reloc(p, &reloc);
+               if (r) {
+                       DRM_ERROR("bad SET PREDICATION\n");
+                       return -EINVAL;
+               }
+
+               ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
+               ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
+       }
+       break;
        case PACKET3_CONTEXT_CONTROL:
                if (pkt->count != 1) {
                        DRM_ERROR("bad CONTEXT_CONTROL\n");
@@ -958,6 +1034,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                        return -EINVAL;
                }
                break;
+       case CAYMAN_PACKET3_DEALLOC_STATE:
+               if (p->rdev->family < CHIP_CAYMAN) {
+                       DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
+                       return -EINVAL;
+               }
+               if (pkt->count) {
+                       DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
+                       return -EINVAL;
+               }
+               break;
        case PACKET3_INDEX_BASE:
                if (pkt->count != 1) {
                        DRM_ERROR("bad INDEX_BASE\n");
@@ -1197,7 +1283,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                        DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                        return -EINVAL;
                                }
-                               ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                               ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                                if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
                                        ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
                                else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
@@ -1209,7 +1295,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                        DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                        return -EINVAL;
                                }
-                               ib[idx+1+(i*8)+4] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                               ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                                mipmap = reloc->robj;
                                r = evergreen_check_texture_resource(p,  idx+1+(i*8),
                                                texture, mipmap);