drm/radeon: don't allow audio on DCE6
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios_encoders.c
index e0285c4..ced9370 100644 (file)
@@ -57,22 +57,6 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
        }
 }
 
-static struct drm_connector *
-radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
-{
-       struct drm_device *dev = encoder->dev;
-       struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-       struct drm_connector *connector;
-       struct radeon_connector *radeon_connector;
-
-       list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-               radeon_connector = to_radeon_connector(connector);
-               if (radeon_encoder->devices & radeon_connector->devices)
-                       return connector;
-       }
-       return NULL;
-}
-
 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
                                   struct drm_display_mode *mode,
                                   struct drm_display_mode *adjusted_mode)
@@ -111,7 +95,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
            ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-               radeon_dp_set_link_config(connector, mode);
+               radeon_dp_set_link_config(connector, adjusted_mode);
        }
 
        return true;
@@ -246,6 +230,10 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
                return;
 
+       /* some R4xx chips have the wrong frev */
+       if (rdev->family <= CHIP_RV410)
+               frev = 1;
+
        switch (frev) {
        case 1:
                switch (crev) {
@@ -253,7 +241,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
                        /* R4xx, R5xx */
                        args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 
-                       if (radeon_encoder->pixel_clock > 165000)
+                       if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 
                        args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
@@ -265,7 +253,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
                        /* DFP1, CRT1, TV1 depending on the type of port */
                        args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 
-                       if (radeon_encoder->pixel_clock > 165000)
+                       if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
                        break;
                case 3:
@@ -349,7 +337,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                        } else {
                                if (dig->linkb)
                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
-                               if (radeon_encoder->pixel_clock > 165000)
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
                                /*if (pScrn->rgbBits == 8) */
                                args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
@@ -388,7 +376,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
                        } else {
                                if (dig->linkb)
                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
-                               if (radeon_encoder->pixel_clock > 165000)
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
                        }
                        break;
@@ -408,9 +396,9 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
 int
 atombios_get_encoder_mode(struct drm_encoder *encoder)
 {
-       struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
+       struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_connector *connector;
        struct radeon_connector *radeon_connector;
        struct radeon_connector_atom_dig *dig_connector;
@@ -434,13 +422,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
        switch (connector->connector_type) {
        case DRM_MODE_CONNECTOR_DVII:
        case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
-               if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
-                       /* fix me */
-                       if (ASIC_IS_DCE4(rdev))
-                               return ATOM_ENCODER_MODE_DVI;
-                       else
-                               return ATOM_ENCODER_MODE_HDMI;
-               } else if (radeon_connector->use_digital)
+               if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+                   radeon_audio &&
+                   !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
+                       return ATOM_ENCODER_MODE_HDMI;
+               else if (radeon_connector->use_digital)
                        return ATOM_ENCODER_MODE_DVI;
                else
                        return ATOM_ENCODER_MODE_CRT;
@@ -448,13 +434,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
        case DRM_MODE_CONNECTOR_DVID:
        case DRM_MODE_CONNECTOR_HDMIA:
        default:
-               if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
-                       /* fix me */
-                       if (ASIC_IS_DCE4(rdev))
-                               return ATOM_ENCODER_MODE_DVI;
-                       else
-                               return ATOM_ENCODER_MODE_HDMI;
-               } else
+               if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+                   radeon_audio &&
+                   !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
+                       return ATOM_ENCODER_MODE_HDMI;
+               else
                        return ATOM_ENCODER_MODE_DVI;
                break;
        case DRM_MODE_CONNECTOR_LVDS:
@@ -465,13 +449,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
                    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                        return ATOM_ENCODER_MODE_DP;
-               else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
-                       /* fix me */
-                       if (ASIC_IS_DCE4(rdev))
-                               return ATOM_ENCODER_MODE_DVI;
-                       else
-                               return ATOM_ENCODER_MODE_HDMI;
-               } else
+               else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
+                        radeon_audio &&
+                        !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
+                       return ATOM_ENCODER_MODE_HDMI;
+               else
                        return ATOM_ENCODER_MODE_DVI;
                break;
        case DRM_MODE_CONNECTOR_eDP:
@@ -506,7 +488,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
  * - 2 DIG encoder blocks.
  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
  *
- * DCE 4.0/5.0
+ * DCE 4.0/5.0/6.0
  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
  * Supports up to 6 digital outputs
  * - 6 DIG encoder blocks.
@@ -522,7 +504,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
  * Supports up to 6 digital outputs
  * - 2 DIG encoder blocks.
+ * llano
  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
+ * ontario
+ * DIG1 drives UNIPHY0/1/2 link A
+ * DIG2 drives UNIPHY0/1/2 link B
  *
  * Routing
  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
@@ -564,7 +550,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
                dp_clock = dig_connector->dp_clock;
                dp_lane_count = dig_connector->dp_lane_count;
                hpd_id = radeon_connector->hpd.hpd;
-               bpc = connector->display_info.bpc;
+               /* bpc = connector->display_info.bpc; */
        }
 
        /* no dig encoder assigned */
@@ -598,7 +584,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
 
                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
                                args.v1.ucLaneNum = dp_lane_count;
-                       else if (radeon_encoder->pixel_clock > 165000)
+                       else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.v1.ucLaneNum = 8;
                        else
                                args.v1.ucLaneNum = 4;
@@ -633,7 +619,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
 
                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
                                args.v3.ucLaneNum = dp_lane_count;
-                       else if (radeon_encoder->pixel_clock > 165000)
+                       else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.v3.ucLaneNum = 8;
                        else
                                args.v3.ucLaneNum = 4;
@@ -673,7 +659,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
 
                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
                                args.v4.ucLaneNum = dp_lane_count;
-                       else if (radeon_encoder->pixel_clock > 165000)
+                       else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.v4.ucLaneNum = 8;
                        else
                                args.v4.ucLaneNum = 4;
@@ -730,6 +716,7 @@ union dig_transmitter_control {
        DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
        DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
        DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
+       DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 };
 
 void
@@ -750,6 +737,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
        int connector_object_id = 0;
        int igp_lane_info = 0;
        int dig_encoder = dig->dig_encoder;
+       int hpd_id = RADEON_HPD_NONE;
 
        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
                connector = radeon_get_connector_for_encoder_init(encoder);
@@ -765,6 +753,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                struct radeon_connector_atom_dig *dig_connector =
                        radeon_connector->con_priv;
 
+               hpd_id = radeon_connector->hpd.hpd;
                dp_clock = dig_connector->dp_clock;
                dp_lane_count = dig_connector->dp_lane_count;
                connector_object_id =
@@ -772,6 +761,11 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
                igp_lane_info = dig_connector->igp_lane_info;
        }
 
+       if (encoder->crtc) {
+               struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+               pll_id = radeon_crtc->pll_id;
+       }
+
        /* no dig encoder assigned */
        if (dig_encoder == -1)
                return;
@@ -798,146 +792,295 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
                return;
 
-       args.v1.ucAction = action;
-       if (action == ATOM_TRANSMITTER_ACTION_INIT) {
-               args.v1.usInitInfo = cpu_to_le16(connector_object_id);
-       } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
-               args.v1.asMode.ucLaneSel = lane_num;
-               args.v1.asMode.ucLaneSet = lane_set;
-       } else {
-               if (is_dp)
-                       args.v1.usPixelClock =
-                               cpu_to_le16(dp_clock / 10);
-               else if (radeon_encoder->pixel_clock > 165000)
-                       args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
-               else
-                       args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
-       }
-       if (ASIC_IS_DCE4(rdev)) {
-               if (is_dp)
-                       args.v3.ucLaneNum = dp_lane_count;
-               else if (radeon_encoder->pixel_clock > 165000)
-                       args.v3.ucLaneNum = 8;
-               else
-                       args.v3.ucLaneNum = 4;
+       switch (frev) {
+       case 1:
+               switch (crev) {
+               case 1:
+                       args.v1.ucAction = action;
+                       if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+                               args.v1.usInitInfo = cpu_to_le16(connector_object_id);
+                       } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+                               args.v1.asMode.ucLaneSel = lane_num;
+                               args.v1.asMode.ucLaneSet = lane_set;
+                       } else {
+                               if (is_dp)
+                                       args.v1.usPixelClock =
+                                               cpu_to_le16(dp_clock / 10);
+                               else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
+                               else
+                                       args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                       }
 
-               if (dig->linkb)
-                       args.v3.acConfig.ucLinkSel = 1;
-               if (dig_encoder & 1)
-                       args.v3.acConfig.ucEncoderSel = 1;
+                       args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 
-               /* Select the PLL for the PHY
-                * DP PHY should be clocked from external src if there is
-                * one.
-                */
-               if (encoder->crtc) {
-                       struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
-                       pll_id = radeon_crtc->pll_id;
-               }
+                       if (dig_encoder)
+                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
+                       else
+                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
+
+                       if ((rdev->flags & RADEON_IS_IGP) &&
+                           (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
+                               if (is_dp ||
+                                   !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
+                                       if (igp_lane_info & 0x1)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                       else if (igp_lane_info & 0x2)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
+                                       else if (igp_lane_info & 0x4)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
+                                       else if (igp_lane_info & 0x8)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
+                               } else {
+                                       if (igp_lane_info & 0x3)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
+                                       else if (igp_lane_info & 0xc)
+                                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+                               }
+                       }
+
+                       if (dig->linkb)
+                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
+                       else
+                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
+
+                       if (is_dp)
+                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+                       else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                               if (dig->coherent_mode)
+                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
+                       }
+                       break;
+               case 2:
+                       args.v2.ucAction = action;
+                       if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+                               args.v2.usInitInfo = cpu_to_le16(connector_object_id);
+                       } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+                               args.v2.asMode.ucLaneSel = lane_num;
+                               args.v2.asMode.ucLaneSet = lane_set;
+                       } else {
+                               if (is_dp)
+                                       args.v2.usPixelClock =
+                                               cpu_to_le16(dp_clock / 10);
+                               else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
+                               else
+                                       args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                       }
+
+                       args.v2.acConfig.ucEncoderSel = dig_encoder;
+                       if (dig->linkb)
+                               args.v2.acConfig.ucLinkSel = 1;
+
+                       switch (radeon_encoder->encoder_id) {
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                               args.v2.acConfig.ucTransmitterSel = 0;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                               args.v2.acConfig.ucTransmitterSel = 1;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                               args.v2.acConfig.ucTransmitterSel = 2;
+                               break;
+                       }
 
-               if (ASIC_IS_DCE5(rdev)) {
-                       /* On DCE5 DCPLL usually generates the DP ref clock */
                        if (is_dp) {
-                               if (rdev->clock.dp_extclk)
-                                       args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
+                               args.v2.acConfig.fCoherentMode = 1;
+                               args.v2.acConfig.fDPConnector = 1;
+                       } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                               if (dig->coherent_mode)
+                                       args.v2.acConfig.fCoherentMode = 1;
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v2.acConfig.fDualLinkConnector = 1;
+                       }
+                       break;
+               case 3:
+                       args.v3.ucAction = action;
+                       if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+                               args.v3.usInitInfo = cpu_to_le16(connector_object_id);
+                       } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+                               args.v3.asMode.ucLaneSel = lane_num;
+                               args.v3.asMode.ucLaneSet = lane_set;
+                       } else {
+                               if (is_dp)
+                                       args.v3.usPixelClock =
+                                               cpu_to_le16(dp_clock / 10);
+                               else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
                                else
-                                       args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
-                       } else
-                               args.v4.acConfig.ucRefClkSource = pll_id;
-               } else {
+                                       args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                       }
+
+                       if (is_dp)
+                               args.v3.ucLaneNum = dp_lane_count;
+                       else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                               args.v3.ucLaneNum = 8;
+                       else
+                               args.v3.ucLaneNum = 4;
+
+                       if (dig->linkb)
+                               args.v3.acConfig.ucLinkSel = 1;
+                       if (dig_encoder & 1)
+                               args.v3.acConfig.ucEncoderSel = 1;
+
+                       /* Select the PLL for the PHY
+                        * DP PHY should be clocked from external src if there is
+                        * one.
+                        */
                        /* On DCE4, if there is an external clock, it generates the DP ref clock */
                        if (is_dp && rdev->clock.dp_extclk)
                                args.v3.acConfig.ucRefClkSource = 2; /* external src */
                        else
                                args.v3.acConfig.ucRefClkSource = pll_id;
-               }
 
-               switch (radeon_encoder->encoder_id) {
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                       args.v3.acConfig.ucTransmitterSel = 0;
-                       break;
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-                       args.v3.acConfig.ucTransmitterSel = 1;
-                       break;
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-                       args.v3.acConfig.ucTransmitterSel = 2;
+                       switch (radeon_encoder->encoder_id) {
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                               args.v3.acConfig.ucTransmitterSel = 0;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                               args.v3.acConfig.ucTransmitterSel = 1;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                               args.v3.acConfig.ucTransmitterSel = 2;
+                               break;
+                       }
+
+                       if (is_dp)
+                               args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
+                       else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                               if (dig->coherent_mode)
+                                       args.v3.acConfig.fCoherentMode = 1;
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v3.acConfig.fDualLinkConnector = 1;
+                       }
                        break;
-               }
+               case 4:
+                       args.v4.ucAction = action;
+                       if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+                               args.v4.usInitInfo = cpu_to_le16(connector_object_id);
+                       } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+                               args.v4.asMode.ucLaneSel = lane_num;
+                               args.v4.asMode.ucLaneSet = lane_set;
+                       } else {
+                               if (is_dp)
+                                       args.v4.usPixelClock =
+                                               cpu_to_le16(dp_clock / 10);
+                               else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
+                               else
+                                       args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                       }
 
-               if (is_dp)
-                       args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
-               else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
-                       if (dig->coherent_mode)
-                               args.v3.acConfig.fCoherentMode = 1;
-                       if (radeon_encoder->pixel_clock > 165000)
-                               args.v3.acConfig.fDualLinkConnector = 1;
-               }
-       } else if (ASIC_IS_DCE32(rdev)) {
-               args.v2.acConfig.ucEncoderSel = dig_encoder;
-               if (dig->linkb)
-                       args.v2.acConfig.ucLinkSel = 1;
+                       if (is_dp)
+                               args.v4.ucLaneNum = dp_lane_count;
+                       else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                               args.v4.ucLaneNum = 8;
+                       else
+                               args.v4.ucLaneNum = 4;
 
-               switch (radeon_encoder->encoder_id) {
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
-                       args.v2.acConfig.ucTransmitterSel = 0;
-                       break;
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
-                       args.v2.acConfig.ucTransmitterSel = 1;
-                       break;
-               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
-                       args.v2.acConfig.ucTransmitterSel = 2;
-                       break;
-               }
+                       if (dig->linkb)
+                               args.v4.acConfig.ucLinkSel = 1;
+                       if (dig_encoder & 1)
+                               args.v4.acConfig.ucEncoderSel = 1;
+
+                       /* Select the PLL for the PHY
+                        * DP PHY should be clocked from external src if there is
+                        * one.
+                        */
+                       /* On DCE5 DCPLL usually generates the DP ref clock */
+                       if (is_dp) {
+                               if (rdev->clock.dp_extclk)
+                                       args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
+                               else
+                                       args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
+                       } else
+                               args.v4.acConfig.ucRefClkSource = pll_id;
 
-               if (is_dp) {
-                       args.v2.acConfig.fCoherentMode = 1;
-                       args.v2.acConfig.fDPConnector = 1;
-               } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
-                       if (dig->coherent_mode)
-                               args.v2.acConfig.fCoherentMode = 1;
-                       if (radeon_encoder->pixel_clock > 165000)
-                               args.v2.acConfig.fDualLinkConnector = 1;
-               }
-       } else {
-               args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
+                       switch (radeon_encoder->encoder_id) {
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                               args.v4.acConfig.ucTransmitterSel = 0;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                               args.v4.acConfig.ucTransmitterSel = 1;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                               args.v4.acConfig.ucTransmitterSel = 2;
+                               break;
+                       }
 
-               if (dig_encoder)
-                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
-               else
-                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
-
-               if ((rdev->flags & RADEON_IS_IGP) &&
-                   (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
-                       if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
-                               if (igp_lane_info & 0x1)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
-                               else if (igp_lane_info & 0x2)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
-                               else if (igp_lane_info & 0x4)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
-                               else if (igp_lane_info & 0x8)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
-                       } else {
-                               if (igp_lane_info & 0x3)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
-                               else if (igp_lane_info & 0xc)
-                                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+                       if (is_dp)
+                               args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
+                       else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                               if (dig->coherent_mode)
+                                       args.v4.acConfig.fCoherentMode = 1;
+                               if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
+                                       args.v4.acConfig.fDualLinkConnector = 1;
                        }
-               }
+                       break;
+               case 5:
+                       args.v5.ucAction = action;
+                       if (is_dp)
+                               args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
+                       else
+                               args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 
-               if (dig->linkb)
-                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
-               else
-                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
+                       switch (radeon_encoder->encoder_id) {
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                               if (dig->linkb)
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
+                               else
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                               if (dig->linkb)
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
+                               else
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
+                               break;
+                       case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                               if (dig->linkb)
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
+                               else
+                                       args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
+                               break;
+                       }
+                       if (is_dp)
+                               args.v5.ucLaneNum = dp_lane_count;
+                       else if (radeon_encoder->pixel_clock > 165000)
+                               args.v5.ucLaneNum = 8;
+                       else
+                               args.v5.ucLaneNum = 4;
+                       args.v5.ucConnObjId = connector_object_id;
+                       args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
 
-               if (is_dp)
-                       args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
-               else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
-                       if (dig->coherent_mode)
-                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
-                       if (radeon_encoder->pixel_clock > 165000)
-                               args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
+                       if (is_dp && rdev->clock.dp_extclk)
+                               args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
+                       else
+                               args.v5.asConfig.ucPhyClkSrcId = pll_id;
+
+                       if (is_dp)
+                               args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
+                       else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                               if (dig->coherent_mode)
+                                       args.v5.asConfig.ucCoherentMode = 1;
+                       }
+                       if (hpd_id == RADEON_HPD_NONE)
+                               args.v5.asConfig.ucHPDSel = 0;
+                       else
+                               args.v5.asConfig.ucHPDSel = hpd_id + 1;
+                       args.v5.ucDigEncoderSel = 1 << dig_encoder;
+                       args.v5.ucDPLaneSet = lane_set;
+                       break;
+               default:
+                       DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+                       break;
                }
+               break;
+       default:
+               DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+               break;
        }
 
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
@@ -1025,7 +1168,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
                dp_lane_count = dig_connector->dp_lane_count;
                connector_object_id =
                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
-               bpc = connector->display_info.bpc;
+               /* bpc = connector->display_info.bpc; */
        }
 
        memset(&args, 0, sizeof(args));
@@ -1049,7 +1192,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
                                if (dp_clock == 270000)
                                        args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
                                args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
-                       } else if (radeon_encoder->pixel_clock > 165000)
+                       } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.v1.sDigEncoder.ucLaneNum = 8;
                        else
                                args.v1.sDigEncoder.ucLaneNum = 4;
@@ -1068,7 +1211,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
                                else if (dp_clock == 540000)
                                        args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
                                args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
-                       } else if (radeon_encoder->pixel_clock > 165000)
+                       } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
                                args.v3.sExtEncoder.ucLaneNum = 8;
                        else
                                args.v3.sExtEncoder.ucLaneNum = 4;
@@ -1241,6 +1384,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+       struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
+       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
        struct radeon_connector *radeon_connector = NULL;
        struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
@@ -1252,19 +1397,44 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
 
        switch (mode) {
        case DRM_MODE_DPMS_ON:
-               /* some early dce3.2 boards have a bug in their transmitter control table */
-               if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
+               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
+                       if (!connector)
+                               dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+                       else
+                               dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
+
+                       /* setup and enable the encoder */
+                       atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                       atombios_dig_encoder_setup(encoder,
+                                                  ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
+                                                  dig->panel_mode);
+                       if (ext_encoder) {
+                               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
+                                       atombios_external_encoder_setup(encoder, ext_encoder,
+                                                                       EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
+                       }
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+               } else if (ASIC_IS_DCE4(rdev)) {
+                       /* setup and enable the encoder */
+                       atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                       /* enable the transmitter */
                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-               else
                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
+               } else {
+                       /* setup and enable the encoder and transmitter */
+                       atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+                       /* some early dce3.2 boards have a bug in their transmitter control table */
+                       if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
+                               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
+               }
                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
                        if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
                                atombios_set_edp_panel_power(connector,
                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
                                radeon_dig_connector->edp_on = true;
                        }
-                       if (ASIC_IS_DCE4(rdev))
-                               atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
                        radeon_dp_link_train(encoder, connector);
                        if (ASIC_IS_DCE4(rdev))
                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
@@ -1275,7 +1445,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
        case DRM_MODE_DPMS_OFF:
-               atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
+                       /* disable the transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+               } else if (ASIC_IS_DCE4(rdev)) {
+                       /* disable the transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+               } else {
+                       /* disable the encoder and transmitter */
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+                       atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
+               }
                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
                        if (ASIC_IS_DCE4(rdev))
                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1302,7 +1484,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
        switch (mode) {
        case DRM_MODE_DPMS_ON:
        default:
-               if (ASIC_IS_DCE41(rdev)) {
+               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
                        atombios_external_encoder_setup(encoder, ext_encoder,
                                                        EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
                        atombios_external_encoder_setup(encoder, ext_encoder,
@@ -1313,7 +1495,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
        case DRM_MODE_DPMS_OFF:
-               if (ASIC_IS_DCE41(rdev)) {
+               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
                        atombios_external_encoder_setup(encoder, ext_encoder,
                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
                        atombios_external_encoder_setup(encoder, ext_encoder,
@@ -1592,13 +1774,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        struct drm_encoder *test_encoder;
-       struct radeon_encoder_atom_dig *dig;
+       struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        uint32_t dig_enc_in_use = 0;
 
-       /* DCE4/5 */
-       if (ASIC_IS_DCE4(rdev)) {
-               dig = radeon_encoder->enc_priv;
-               if (ASIC_IS_DCE41(rdev)) {
+       if (ASIC_IS_DCE6(rdev)) {
+               /* DCE6 */
+               switch (radeon_encoder->encoder_id) {
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                       if (dig->linkb)
+                               return 1;
+                       else
+                               return 0;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                       if (dig->linkb)
+                               return 3;
+                       else
+                               return 2;
+                       break;
+               case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                       if (dig->linkb)
+                               return 5;
+                       else
+                               return 4;
+                       break;
+               }
+       } else if (ASIC_IS_DCE4(rdev)) {
+               /* DCE4/5 */
+               if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
                        /* ontario follows DCE4 */
                        if (rdev->family == CHIP_PALM) {
                                if (dig->linkb)
@@ -1686,7 +1889,7 @@ radeon_atom_encoder_init(struct radeon_device *rdev)
                        break;
                }
 
-               if (ext_encoder && ASIC_IS_DCE41(rdev))
+               if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
                        atombios_external_encoder_setup(encoder, ext_encoder,
                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
        }
@@ -1700,10 +1903,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        struct drm_device *dev = encoder->dev;
        struct radeon_device *rdev = dev->dev_private;
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-       struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
 
        radeon_encoder->pixel_clock = adjusted_mode->clock;
 
+       /* need to call this here rather than in prepare() since we need some crtc info */
+       radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+
        if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
                if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
                        atombios_yuv_setup(encoder, true);
@@ -1722,24 +1927,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-               if (ASIC_IS_DCE4(rdev)) {
-                       /* disable the transmitter */
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                       /* setup and enable the encoder */
-                       atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
-
-                       /* enable the transmitter */
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-               } else {
-                       /* disable the encoder and transmitter */
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                       atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
-
-                       /* setup and enable the encoder and transmitter */
-                       atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-               }
+               /* handled in dpms */
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DDI:
        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1760,14 +1948,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
                break;
        }
 
-       if (ext_encoder) {
-               if (ASIC_IS_DCE41(rdev))
-                       atombios_external_encoder_setup(encoder, ext_encoder,
-                                                       EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
-               else
-                       atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
-       }
-
        atombios_apply_encoder_quirks(encoder, adjusted_mode);
 
        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -1940,7 +2120,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
        }
 
        radeon_atom_output_lock(encoder, true);
-       radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 
        if (connector) {
                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1961,6 +2140,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
 {
+       /* need to call this here as we need the crtc set up */
        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
        radeon_atom_output_lock(encoder, false);
 }
@@ -2001,14 +2181,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-               if (ASIC_IS_DCE4(rdev))
-                       /* disable the transmitter */
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-               else {
-                       /* disable the encoder and transmitter */
-                       atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                       atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
-               }
+               /* handled in dpms */
                break;
        case ENCODER_OBJECT_ID_INTERNAL_DDI:
        case ENCODER_OBJECT_ID_INTERNAL_DVO1: