-/* Intel 7 core Memory Controller kernel module (Nehalem)
+/* Intel i7 core/Nehalem Memory Controller kernel module
+ *
+ * This driver supports yhe memory controllers found on the Intel
+ * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
+ * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
+ * and Westmere-EP.
*
* This file may be distributed under the terms of the
* GNU General Public License version 2 only.
*
- * Copyright (c) 2009 by:
+ * Copyright (c) 2009-2010 by:
* Mauro Carvalho Chehab <mchehab@redhat.com>
*
* Red Hat Inc. http://www.redhat.com
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
#include <linux/edac_mce.h>
-#include <linux/spinlock.h>
+#include <linux/smp.h>
+#include <asm/processor.h>
#include "edac_core.h"
+/* Static vars */
+static LIST_HEAD(i7core_edac_list);
+static DEFINE_MUTEX(i7core_edac_lock);
+static int probed;
+
+static int use_pci_fixup;
+module_param(use_pci_fixup, int, 0444);
+MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
+/*
+ * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
+ * registers start at bus 255, and are not reported by BIOS.
+ * We currently find devices with only 2 sockets. In order to support more QPI
+ * Quick Path Interconnect, just increment this number.
+ */
+#define MAX_SOCKET_BUSES 2
+
+
/*
* Alter this version for the module when modifications are made
*/
#define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
#define EDAC_MOD_STR "i7core_edac"
-/* HACK: temporary, just to enable all logs, for now */
-#undef debugf0
-#define debugf0(fmt, arg...) edac_printk(KERN_INFO, "i7core", fmt, ##arg)
-
/*
* Debug macros
*/
#define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
#define DIMM0_COR_ERR(r) ((r) & 0x7fff)
+/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
+#define MC_COR_ECC_CNT_0 0x80
+#define MC_COR_ECC_CNT_1 0x84
+#define MC_COR_ECC_CNT_2 0x88
+#define MC_COR_ECC_CNT_3 0x8c
+#define MC_COR_ECC_CNT_4 0x90
+#define MC_COR_ECC_CNT_5 0x94
+
+#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
+#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
+
+
/* OFFSETS for Devices 4,5 and 6 Function 0 */
#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
#define REPEAT_EN 0x01
/* OFFSETS for Devices 4,5 and 6 Function 1 */
+
#define MC_DOD_CH_DIMM0 0x48
#define MC_DOD_CH_DIMM1 0x4c
#define MC_DOD_CH_DIMM2 0x50
#define NUM_CHANS 3
#define MAX_DIMMS 3 /* Max DIMMS per channel */
-#define NUM_SOCKETS 2 /* Max number of MC sockets */
#define MAX_MCR_FUNC 4
#define MAX_CHAN_FUNC 3
struct i7core_inject {
int enable;
- u8 socket;
u32 section;
u32 type;
u32 eccmask;
};
struct pci_id_descr {
- int dev;
- int func;
- int dev_id;
- struct pci_dev *pdev[NUM_SOCKETS];
+ int dev;
+ int func;
+ int dev_id;
+ int optional;
+};
+
+struct pci_id_table {
+ const struct pci_id_descr *descr;
+ int n_devs;
+};
+
+struct i7core_dev {
+ struct list_head list;
+ u8 socket;
+ struct pci_dev **pdev;
+ int n_devs;
+ struct mem_ctl_info *mci;
};
struct i7core_pvt {
- struct pci_dev *pci_noncore[NUM_SOCKETS];
- struct pci_dev *pci_mcr[NUM_SOCKETS][MAX_MCR_FUNC + 1];
- struct pci_dev *pci_ch[NUM_SOCKETS][NUM_CHANS][MAX_CHAN_FUNC + 1];
+ struct pci_dev *pci_noncore;
+ struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
+ struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
+
+ struct i7core_dev *i7core_dev;
struct i7core_info info;
struct i7core_inject inject;
- struct i7core_channel channel[NUM_SOCKETS][NUM_CHANS];
+ struct i7core_channel channel[NUM_CHANS];
+
+ int ce_count_available;
+ int csrow_map[NUM_CHANS][MAX_DIMMS];
- int sockets; /* Number of sockets */
- int channels; /* Number of active channels */
+ /* ECC corrected errors counts per udimm */
+ unsigned long udimm_ce_count[MAX_DIMMS];
+ int udimm_last_ce_count[MAX_DIMMS];
+ /* ECC corrected errors counts per rdimm */
+ unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
+ int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
- int ce_count_available[NUM_SOCKETS];
- /* ECC corrected errors counts per dimm */
- unsigned long ce_count[NUM_SOCKETS][MAX_DIMMS];
- int last_ce_count[NUM_SOCKETS][MAX_DIMMS];
+ unsigned int is_registered;
/* mcelog glue */
struct edac_mce edac_mce;
+
+ /* Fifo double buffers */
struct mce mce_entry[MCE_LOG_LEN];
- unsigned mce_count;
- spinlock_t mce_lock;
-};
+ struct mce mce_outentry[MCE_LOG_LEN];
+
+ /* Fifo in/out counters */
+ unsigned mce_in, mce_out;
-/* Device name and register DID (Device ID) */
-struct i7core_dev_info {
- const char *ctl_name; /* name for this device */
- u16 fsb_mapping_errors; /* DID for the branchmap,control */
+ /* Count indicator to show errors not got */
+ unsigned mce_overrun;
+
+ /* Struct to control EDAC polling */
+ struct edac_pci_ctl_info *i7core_pci;
};
#define PCI_DESCR(device, function, device_id) \
.func = (function), \
.dev_id = (device_id)
-struct pci_id_descr pci_devs[] = {
+static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
/* Memory controller */
{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
- { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM is supported */
+
+ /* Exists only for RDIMM */
+ { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
/* Channel 0 */
{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
+};
- /* Generic Non-core registers */
- /*
- * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
- * On Xeon 55xx, however, it has a different id (8086:2c40). So,
- * the probing code needs to test for the other address in case of
- * failure of this one
- */
- { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
+static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
+ { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
+ { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
+ { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
+
+ { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
+ { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
+ { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
+ { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
+ { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
+ { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
+ { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
+ { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
+};
+
+static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
+ /* Memory controller */
+ { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
+ { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
+ /* Exists only for RDIMM */
+ { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
+ { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
+
+ /* Channel 0 */
+ { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
+ { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
+ { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
+ { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
+
+ /* Channel 1 */
+ { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
+ { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
+ { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
+ { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
+
+ /* Channel 2 */
+ { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
+ { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
+ { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
+ { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
+};
+
+#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
+static const struct pci_id_table pci_dev_table[] = {
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
+ PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
+ {0,} /* 0 terminated list. */
};
-#define N_DEVS ARRAY_SIZE(pci_devs)
/*
* pci_device_id table for which devices we are looking for
- * This should match the first device at pci_devs table
*/
static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
{0,} /* 0 terminated list. */
};
-
-/* Table of devices attributes supported by this driver */
-static const struct i7core_dev_info i7core_devs[] = {
- {
- .ctl_name = "i7 Core",
- .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
- },
-};
-
-static struct edac_pci_ctl_info *i7core_pci;
-
/****************************************************************************
Anciliary status routines
****************************************************************************/
#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
/* MC_STATUS bits */
-#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 3))
+#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
/* MC_MAX_DOD read functions */
return cols[col & 0x3];
}
+static struct i7core_dev *get_i7core_dev(u8 socket)
+{
+ struct i7core_dev *i7core_dev;
+
+ list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
+ if (i7core_dev->socket == socket)
+ return i7core_dev;
+ }
+
+ return NULL;
+}
+
+static struct i7core_dev *alloc_i7core_dev(u8 socket,
+ const struct pci_id_table *table)
+{
+ struct i7core_dev *i7core_dev;
+
+ i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
+ if (!i7core_dev)
+ return NULL;
+
+ i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
+ GFP_KERNEL);
+ if (!i7core_dev->pdev) {
+ kfree(i7core_dev);
+ return NULL;
+ }
+
+ i7core_dev->socket = socket;
+ i7core_dev->n_devs = table->n_devs;
+ list_add_tail(&i7core_dev->list, &i7core_edac_list);
+
+ return i7core_dev;
+}
+
+static void free_i7core_dev(struct i7core_dev *i7core_dev)
+{
+ list_del(&i7core_dev->list);
+ kfree(i7core_dev->pdev);
+ kfree(i7core_dev);
+}
+
/****************************************************************************
Memory check routines
****************************************************************************/
static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
unsigned func)
{
+ struct i7core_dev *i7core_dev = get_i7core_dev(socket);
int i;
- for (i = 0; i < N_DEVS; i++) {
- if (!pci_devs[i].pdev[socket])
+ if (!i7core_dev)
+ return NULL;
+
+ for (i = 0; i < i7core_dev->n_devs; i++) {
+ if (!i7core_dev->pdev[i])
continue;
- if (PCI_SLOT(pci_devs[i].pdev[socket]->devfn) == slot &&
- PCI_FUNC(pci_devs[i].pdev[socket]->devfn) == func) {
- return pci_devs[i].pdev[socket];
+ if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
+ PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
+ return i7core_dev->pdev[i];
}
}
* to add a fake description for csrows.
* So, this driver is attributing one DIMM memory for one csrow.
*/
-static int i7core_get_active_channels(u8 socket, unsigned *channels,
+static int i7core_get_active_channels(const u8 socket, unsigned *channels,
unsigned *csrows)
{
struct pci_dev *pdev = NULL;
return 0;
}
-static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
+static int get_dimm_config(const struct mem_ctl_info *mci)
{
struct i7core_pvt *pvt = mci->pvt_info;
struct csrow_info *csr;
struct pci_dev *pdev;
int i, j;
+ int csrow = 0;
unsigned long last_page = 0;
enum edac_type mode;
enum mem_type mtype;
/* Get data from the MC register, function 0 */
- pdev = pvt->pci_mcr[socket][0];
+ pdev = pvt->pci_mcr[0];
if (!pdev)
return -ENODEV;
pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
- socket, pvt->info.mc_control, pvt->info.mc_status,
+ pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
pvt->info.max_dod, pvt->info.ch_map);
if (ECC_ENABLED(pvt)) {
for (i = 0; i < NUM_CHANS; i++) {
u32 data, dimm_dod[3], value[8];
+ if (!pvt->pci_ch[i][0])
+ continue;
+
if (!CH_ACTIVE(pvt, i)) {
debugf0("Channel %i is not active\n", i);
continue;
}
/* Devices 4-6 function 0 */
- pci_read_config_dword(pvt->pci_ch[socket][i][0],
+ pci_read_config_dword(pvt->pci_ch[i][0],
MC_CHANNEL_DIMM_INIT_PARAMS, &data);
- pvt->channel[socket][i].ranks = (data & QUAD_RANK_PRESENT) ?
+ pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
4 : 2;
if (data & REGISTERED_DIMM)
#endif
/* Devices 4-6 function 1 */
- pci_read_config_dword(pvt->pci_ch[socket][i][1],
+ pci_read_config_dword(pvt->pci_ch[i][1],
MC_DOD_CH_DIMM0, &dimm_dod[0]);
- pci_read_config_dword(pvt->pci_ch[socket][i][1],
+ pci_read_config_dword(pvt->pci_ch[i][1],
MC_DOD_CH_DIMM1, &dimm_dod[1]);
- pci_read_config_dword(pvt->pci_ch[socket][i][1],
+ pci_read_config_dword(pvt->pci_ch[i][1],
MC_DOD_CH_DIMM2, &dimm_dod[2]);
debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
i,
RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
data,
- pvt->channel[socket][i].ranks,
+ pvt->channel[i].ranks,
(data & REGISTERED_DIMM) ? 'R' : 'U');
for (j = 0; j < 3; j++) {
/* DDR3 has 8 I/O banks */
size = (rows * cols * banks * ranks) >> (20 - 3);
- pvt->channel[socket][i].dimms++;
+ pvt->channel[i].dimms++;
debugf0("\tdimm %d %d Mb offset: %x, "
"bank: %d, rank: %d, row: %#x, col: %#x\n",
RANKOFFSET(dimm_dod[j]),
banks, ranks, rows, cols);
-#if PAGE_SHIFT > 20
- npages = size >> (PAGE_SHIFT - 20);
-#else
- npages = size << (20 - PAGE_SHIFT);
-#endif
+ npages = MiB_TO_PAGES(size);
- csr = &mci->csrows[*csrow];
+ csr = &mci->csrows[csrow];
csr->first_page = last_page + 1;
last_page += npages;
csr->last_page = last_page;
csr->page_mask = 0;
csr->grain = 8;
- csr->csrow_idx = *csrow;
+ csr->csrow_idx = csrow;
csr->nr_channels = 1;
csr->channels[0].chan_idx = i;
csr->channels[0].ce_count = 0;
+ pvt->csrow_map[i][j] = csrow;
+
switch (banks) {
case 4:
csr->dtype = DEV_X4;
csr->edac_mode = mode;
csr->mtype = mtype;
- (*csrow)++;
+ csrow++;
}
pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
we're disabling error injection on all write calls to the sysfs nodes that
controls the error code injection.
*/
-static int disable_inject(struct mem_ctl_info *mci)
+static int disable_inject(const struct mem_ctl_info *mci)
{
struct i7core_pvt *pvt = mci->pvt_info;
pvt->inject.enable = 0;
- if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
+ if (!pvt->pci_ch[pvt->inject.channel][0])
return -ENODEV;
- pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
- MC_CHANNEL_ERROR_MASK, 0);
+ pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
+ MC_CHANNEL_ERROR_INJECT, 0);
return 0;
}
-/*
- * i7core inject inject.socket
- *
- * accept and store error injection inject.socket value
- */
-static ssize_t i7core_inject_socket_store(struct mem_ctl_info *mci,
- const char *data, size_t count)
-{
- struct i7core_pvt *pvt = mci->pvt_info;
- unsigned long value;
- int rc;
-
- rc = strict_strtoul(data, 10, &value);
- if ((rc < 0) || (value >= pvt->sockets))
- return -EIO;
-
- pvt->inject.section = (u32) value;
- return count;
-}
-
-static ssize_t i7core_inject_socket_show(struct mem_ctl_info *mci,
- char *data)
-{
- struct i7core_pvt *pvt = mci->pvt_info;
- return sprintf(data, "%d\n", pvt->inject.socket);
-}
-
/*
* i7core inject inject.section
*
* 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
* uncorrectable error to be injected.
*/
-static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
- const char *data, size_t count)
-{
- struct i7core_pvt *pvt = mci->pvt_info;
- char *cmd, *val;
- long value;
- int rc;
-
- if (pvt->inject.enable)
- disable_inject(mci);
-
- do {
- cmd = strsep((char **) &data, ":");
- if (!cmd)
- break;
- val = strsep((char **) &data, " \n\t");
- if (!val)
- return cmd - data;
-
- if (!strcasecmp(val, "any"))
- value = -1;
- else {
- rc = strict_strtol(val, 10, &value);
- if ((rc < 0) || (value < 0))
- return cmd - data;
- }
- if (!strcasecmp(cmd, "channel")) {
- if (value < 3)
- pvt->inject.channel = value;
- else
- return cmd - data;
- } else if (!strcasecmp(cmd, "dimm")) {
- if (value < 3)
- pvt->inject.dimm = value;
- else
- return cmd - data;
- } else if (!strcasecmp(cmd, "rank")) {
- if (value < 4)
- pvt->inject.rank = value;
- else
- return cmd - data;
- } else if (!strcasecmp(cmd, "bank")) {
- if (value < 32)
- pvt->inject.bank = value;
- else
- return cmd - data;
- } else if (!strcasecmp(cmd, "page")) {
- if (value <= 0xffff)
- pvt->inject.page = value;
- else
- return cmd - data;
- } else if (!strcasecmp(cmd, "col") ||
- !strcasecmp(cmd, "column")) {
- if (value <= 0x3fff)
- pvt->inject.col = value;
- else
- return cmd - data;
- }
- } while (1);
-
- return count;
+#define DECLARE_ADDR_MATCH(param, limit) \
+static ssize_t i7core_inject_store_##param( \
+ struct mem_ctl_info *mci, \
+ const char *data, size_t count) \
+{ \
+ struct i7core_pvt *pvt; \
+ long value; \
+ int rc; \
+ \
+ debugf1("%s()\n", __func__); \
+ pvt = mci->pvt_info; \
+ \
+ if (pvt->inject.enable) \
+ disable_inject(mci); \
+ \
+ if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
+ value = -1; \
+ else { \
+ rc = strict_strtoul(data, 10, &value); \
+ if ((rc < 0) || (value >= limit)) \
+ return -EIO; \
+ } \
+ \
+ pvt->inject.param = value; \
+ \
+ return count; \
+} \
+ \
+static ssize_t i7core_inject_show_##param( \
+ struct mem_ctl_info *mci, \
+ char *data) \
+{ \
+ struct i7core_pvt *pvt; \
+ \
+ pvt = mci->pvt_info; \
+ debugf1("%s() pvt=%p\n", __func__, pvt); \
+ if (pvt->inject.param < 0) \
+ return sprintf(data, "any\n"); \
+ else \
+ return sprintf(data, "%d\n", pvt->inject.param);\
}
-static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
- char *data)
-{
- struct i7core_pvt *pvt = mci->pvt_info;
- char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];
-
- if (pvt->inject.channel < 0)
- sprintf(channel, "any");
- else
- sprintf(channel, "%d", pvt->inject.channel);
- if (pvt->inject.dimm < 0)
- sprintf(dimm, "any");
- else
- sprintf(dimm, "%d", pvt->inject.dimm);
- if (pvt->inject.bank < 0)
- sprintf(bank, "any");
- else
- sprintf(bank, "%d", pvt->inject.bank);
- if (pvt->inject.rank < 0)
- sprintf(rank, "any");
- else
- sprintf(rank, "%d", pvt->inject.rank);
- if (pvt->inject.page < 0)
- sprintf(page, "any");
- else
- sprintf(page, "0x%04x", pvt->inject.page);
- if (pvt->inject.col < 0)
- sprintf(col, "any");
- else
- sprintf(col, "0x%04x", pvt->inject.col);
+#define ATTR_ADDR_MATCH(param) \
+ { \
+ .attr = { \
+ .name = #param, \
+ .mode = (S_IRUGO | S_IWUSR) \
+ }, \
+ .show = i7core_inject_show_##param, \
+ .store = i7core_inject_store_##param, \
+ }
- return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
- "rank: %s\npage: %s\ncolumn: %s\n",
- channel, dimm, bank, rank, page, col);
-}
+DECLARE_ADDR_MATCH(channel, 3);
+DECLARE_ADDR_MATCH(dimm, 3);
+DECLARE_ADDR_MATCH(rank, 4);
+DECLARE_ADDR_MATCH(bank, 32);
+DECLARE_ADDR_MATCH(page, 0x10000);
+DECLARE_ADDR_MATCH(col, 0x4000);
-static int write_and_test(struct pci_dev *dev, int where, u32 val)
+static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
{
u32 read;
int count;
+ debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
+ dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
+ where, val);
+
for (count = 0; count < 10; count++) {
if (count)
- msleep (100);
+ msleep(100);
pci_write_config_dword(dev, where, val);
pci_read_config_dword(dev, where, &read);
return 0;
}
- debugf0("Error Injection Register 0x%02x: Tried to write 0x%08x, "
- "but read: 0x%08x\n", where, val, read);
+ i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
+ "write=%08x. Read=%08x\n",
+ dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
+ where, val, read);
return -EINVAL;
}
-
/*
* This routine prepares the Memory Controller for error injection.
* The error will be injected when some process tries to write to the
int rc;
long enable;
- if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
+ if (!pvt->pci_ch[pvt->inject.channel][0])
return 0;
rc = strict_strtoul(data, 10, &enable);
/* Sets pvt->inject.dimm mask */
if (pvt->inject.dimm < 0)
- mask |= 1L << 41;
+ mask |= 1LL << 41;
else {
- if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
- mask |= (pvt->inject.dimm & 0x3L) << 35;
+ if (pvt->channel[pvt->inject.channel].dimms > 2)
+ mask |= (pvt->inject.dimm & 0x3LL) << 35;
else
- mask |= (pvt->inject.dimm & 0x1L) << 36;
+ mask |= (pvt->inject.dimm & 0x1LL) << 36;
}
/* Sets pvt->inject.rank mask */
if (pvt->inject.rank < 0)
- mask |= 1L << 40;
+ mask |= 1LL << 40;
else {
- if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
- mask |= (pvt->inject.rank & 0x1L) << 34;
+ if (pvt->channel[pvt->inject.channel].dimms > 2)
+ mask |= (pvt->inject.rank & 0x1LL) << 34;
else
- mask |= (pvt->inject.rank & 0x3L) << 34;
+ mask |= (pvt->inject.rank & 0x3LL) << 34;
}
/* Sets pvt->inject.bank mask */
if (pvt->inject.bank < 0)
- mask |= 1L << 39;
+ mask |= 1LL << 39;
else
- mask |= (pvt->inject.bank & 0x15L) << 30;
+ mask |= (pvt->inject.bank & 0x15LL) << 30;
/* Sets pvt->inject.page mask */
if (pvt->inject.page < 0)
- mask |= 1L << 38;
+ mask |= 1LL << 38;
else
- mask |= (pvt->inject.page & 0xffffL) << 14;
+ mask |= (pvt->inject.page & 0xffff) << 14;
/* Sets pvt->inject.column mask */
if (pvt->inject.col < 0)
- mask |= 1L << 37;
+ mask |= 1LL << 37;
else
- mask |= (pvt->inject.col & 0x3fffL);
+ mask |= (pvt->inject.col & 0x3fff);
/*
* bit 0: REPEAT_EN
(pvt->inject.type & 0x6) << (3 - 1);
/* Unlock writes to registers - this register is write only */
- pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
+ pci_write_config_dword(pvt->pci_noncore,
MC_CFG_CONTROL, 0x2);
-#if 0
- /* Zeroes error count registers */
- pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
- MC_TEST_ERR_RCV1, 0);
- pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
- MC_TEST_ERR_RCV0, 0);
- pvt->ce_count_available[pvt->inject.socket] = 0;
-#endif
-
- write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+ write_and_test(pvt->pci_ch[pvt->inject.channel][0],
MC_CHANNEL_ADDR_MATCH, mask);
- write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+ write_and_test(pvt->pci_ch[pvt->inject.channel][0],
MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
- write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
+ write_and_test(pvt->pci_ch[pvt->inject.channel][0],
MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
- write_and_test(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
- MC_CHANNEL_ERROR_MASK, injectmask);
+ write_and_test(pvt->pci_ch[pvt->inject.channel][0],
+ MC_CHANNEL_ERROR_INJECT, injectmask);
/*
* This is something undocumented, based on my tests
* Without writing 8 to this register, errors aren't injected. Not sure
* why.
*/
- pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
+ pci_write_config_dword(pvt->pci_noncore,
MC_CFG_CONTROL, 8);
debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
struct i7core_pvt *pvt = mci->pvt_info;
u32 injectmask;
- pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
- MC_CHANNEL_ERROR_MASK, &injectmask);
+ if (!pvt->pci_ch[pvt->inject.channel][0])
+ return 0;
+
+ pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
+ MC_CHANNEL_ERROR_INJECT, &injectmask);
debugf0("Inject error read: 0x%018x\n", injectmask);
return sprintf(data, "%d\n", pvt->inject.enable);
}
-static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
-{
- unsigned i, count, total = 0;
- struct i7core_pvt *pvt = mci->pvt_info;
+#define DECLARE_COUNTER(param) \
+static ssize_t i7core_show_counter_##param( \
+ struct mem_ctl_info *mci, \
+ char *data) \
+{ \
+ struct i7core_pvt *pvt = mci->pvt_info; \
+ \
+ debugf1("%s() \n", __func__); \
+ if (!pvt->ce_count_available || (pvt->is_registered)) \
+ return sprintf(data, "data unavailable\n"); \
+ return sprintf(data, "%lu\n", \
+ pvt->udimm_ce_count[param]); \
+}
- for (i = 0; i < pvt->sockets; i++) {
- if (!pvt->ce_count_available[i])
- count = sprintf(data, "socket 0 data unavailable\n");
- else
- count = sprintf(data, "socket %d, dimm0: %lu\n"
- "dimm1: %lu\ndimm2: %lu\n",
- i,
- pvt->ce_count[i][0],
- pvt->ce_count[i][1],
- pvt->ce_count[i][2]);
- data += count;
- total += count;
+#define ATTR_COUNTER(param) \
+ { \
+ .attr = { \
+ .name = __stringify(udimm##param), \
+ .mode = (S_IRUGO | S_IWUSR) \
+ }, \
+ .show = i7core_show_counter_##param \
}
- return total;
-}
+DECLARE_COUNTER(0);
+DECLARE_COUNTER(1);
+DECLARE_COUNTER(2);
/*
* Sysfs struct
*/
-static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
+
+static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
+ ATTR_ADDR_MATCH(channel),
+ ATTR_ADDR_MATCH(dimm),
+ ATTR_ADDR_MATCH(rank),
+ ATTR_ADDR_MATCH(bank),
+ ATTR_ADDR_MATCH(page),
+ ATTR_ADDR_MATCH(col),
+ { } /* End of list */
+};
+
+static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
+ .name = "inject_addrmatch",
+ .mcidev_attr = i7core_addrmatch_attrs,
+};
+
+static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
+ ATTR_COUNTER(0),
+ ATTR_COUNTER(1),
+ ATTR_COUNTER(2),
+ { .attr = { .name = NULL } }
+};
+
+static const struct mcidev_sysfs_group i7core_udimm_counters = {
+ .name = "all_channel_counts",
+ .mcidev_attr = i7core_udimm_counters_attrs,
+};
+
+static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
{
.attr = {
- .name = "inject_socket",
+ .name = "inject_section",
+ .mode = (S_IRUGO | S_IWUSR)
+ },
+ .show = i7core_inject_section_show,
+ .store = i7core_inject_section_store,
+ }, {
+ .attr = {
+ .name = "inject_type",
.mode = (S_IRUGO | S_IWUSR)
},
- .show = i7core_inject_socket_show,
- .store = i7core_inject_socket_store,
+ .show = i7core_inject_type_show,
+ .store = i7core_inject_type_store,
}, {
+ .attr = {
+ .name = "inject_eccmask",
+ .mode = (S_IRUGO | S_IWUSR)
+ },
+ .show = i7core_inject_eccmask_show,
+ .store = i7core_inject_eccmask_store,
+ }, {
+ .grp = &i7core_inject_addrmatch,
+ }, {
+ .attr = {
+ .name = "inject_enable",
+ .mode = (S_IRUGO | S_IWUSR)
+ },
+ .show = i7core_inject_enable_show,
+ .store = i7core_inject_enable_store,
+ },
+ { } /* End of list */
+};
+
+static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
+ {
.attr = {
.name = "inject_section",
.mode = (S_IRUGO | S_IWUSR)
.show = i7core_inject_eccmask_show,
.store = i7core_inject_eccmask_store,
}, {
- .attr = {
- .name = "inject_addrmatch",
- .mode = (S_IRUGO | S_IWUSR)
- },
- .show = i7core_inject_addrmatch_show,
- .store = i7core_inject_addrmatch_store,
+ .grp = &i7core_inject_addrmatch,
}, {
.attr = {
.name = "inject_enable",
.show = i7core_inject_enable_show,
.store = i7core_inject_enable_store,
}, {
- .attr = {
- .name = "corrected_error_counts",
- .mode = (S_IRUGO | S_IWUSR)
- },
- .show = i7core_ce_regs_show,
- .store = NULL,
+ .grp = &i7core_udimm_counters,
},
+ { } /* End of list */
};
/****************************************************************************
****************************************************************************/
/*
- * i7core_put_devices 'put' all the devices that we have
+ * i7core_put_all_devices 'put' all the devices that we have
* reserved via 'get'
*/
-static void i7core_put_devices(void)
+static void i7core_put_devices(struct i7core_dev *i7core_dev)
{
- int i, j;
+ int i;
- for (i = 0; i < NUM_SOCKETS; i++)
- for (j = 0; j < N_DEVS; j++)
- pci_dev_put(pci_devs[j].pdev[i]);
+ debugf0(__FILE__ ": %s()\n", __func__);
+ for (i = 0; i < i7core_dev->n_devs; i++) {
+ struct pci_dev *pdev = i7core_dev->pdev[i];
+ if (!pdev)
+ continue;
+ debugf0("Removing dev %02x:%02x.%d\n",
+ pdev->bus->number,
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+ pci_dev_put(pdev);
+ }
}
-/*
- * i7core_get_devices Find and perform 'get' operation on the MCH's
- * device/functions we want to reference for this driver
- *
- * Need to 'get' device 16 func 1 and func 2
- */
-int i7core_get_onedevice(struct pci_dev **prev, int devno)
+static void i7core_put_all_devices(void)
{
- struct pci_dev *pdev = NULL;
- u8 bus = 0;
- u8 socket = 0;
+ struct i7core_dev *i7core_dev, *tmp;
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- pci_devs[devno].dev_id, *prev);
+ list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
+ i7core_put_devices(i7core_dev);
+ free_i7core_dev(i7core_dev);
+ }
+}
+
+static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
+{
+ struct pci_dev *pdev = NULL;
+ int i;
/*
* On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
* aren't announced by acpi. So, we need to use a legacy scan probing
* to detect them
*/
- if (unlikely(!pdev && !devno && !prev)) {
- pcibios_scan_specific_bus(254);
- pcibios_scan_specific_bus(255);
+ while (table && table->descr) {
+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
+ if (unlikely(!pdev)) {
+ for (i = 0; i < MAX_SOCKET_BUSES; i++)
+ pcibios_scan_specific_bus(255-i);
+ }
+ pci_dev_put(pdev);
+ table++;
+ }
+}
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- pci_devs[devno].dev_id, *prev);
+static unsigned i7core_pci_lastbus(void)
+{
+ int last_bus = 0, bus;
+ struct pci_bus *b = NULL;
+
+ while ((b = pci_find_next_bus(b)) != NULL) {
+ bus = b->number;
+ debugf0("Found bus %d\n", bus);
+ if (bus > last_bus)
+ last_bus = bus;
}
- /*
- * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
- * is at addr 8086:2c40, instead of 8086:2c41. So, we need
- * to probe for the alternate address in case of failure
- */
- if (pci_devs[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
- pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
+ debugf0("Last bus %d\n", last_bus);
+
+ return last_bus;
+}
+
+/*
+ * i7core_get_all_devices Find and perform 'get' operation on the MCH's
+ * device/functions we want to reference for this driver
+ *
+ * Need to 'get' device 16 func 1 and func 2
+ */
+static int i7core_get_onedevice(struct pci_dev **prev,
+ const struct pci_id_table *table,
+ const unsigned devno,
+ const unsigned last_bus)
+{
+ struct i7core_dev *i7core_dev;
+ const struct pci_id_descr *dev_descr = &table->descr[devno];
+
+ struct pci_dev *pdev = NULL;
+ u8 bus = 0;
+ u8 socket = 0;
+
+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
+ dev_descr->dev_id, *prev);
if (!pdev) {
if (*prev) {
return 0;
}
- /*
- * Dev 3 function 2 only exists on chips with RDIMMs
- * so, it is ok to not found it
- */
- if ((pci_devs[devno].dev == 3) && (pci_devs[devno].func == 2)) {
- *prev = pdev;
+ if (dev_descr->optional)
return 0;
- }
- i7core_printk(KERN_ERR,
+ if (devno == 0)
+ return -ENODEV;
+
+ i7core_printk(KERN_INFO,
"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
- pci_devs[devno].dev, pci_devs[devno].func,
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+ dev_descr->dev, dev_descr->func,
+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
/* End of list, leave */
return -ENODEV;
}
bus = pdev->bus->number;
- if (bus == 0x3f)
- socket = 0;
- else
- socket = 255 - bus;
+ socket = last_bus - bus;
- if (socket >= NUM_SOCKETS) {
- i7core_printk(KERN_ERR,
- "Unexpected socket for "
- "dev %02x:%02x.%d PCI ID %04x:%04x\n",
- bus, pci_devs[devno].dev, pci_devs[devno].func,
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
- pci_dev_put(pdev);
- return -ENODEV;
+ i7core_dev = get_i7core_dev(socket);
+ if (!i7core_dev) {
+ i7core_dev = alloc_i7core_dev(socket, table);
+ if (!i7core_dev) {
+ pci_dev_put(pdev);
+ return -ENOMEM;
+ }
}
- if (pci_devs[devno].pdev[socket]) {
+ if (i7core_dev->pdev[devno]) {
i7core_printk(KERN_ERR,
"Duplicated device for "
"dev %02x:%02x.%d PCI ID %04x:%04x\n",
- bus, pci_devs[devno].dev, pci_devs[devno].func,
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+ bus, dev_descr->dev, dev_descr->func,
+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
pci_dev_put(pdev);
return -ENODEV;
}
- pci_devs[devno].pdev[socket] = pdev;
+ i7core_dev->pdev[devno] = pdev;
/* Sanity check */
- if (unlikely(PCI_SLOT(pdev->devfn) != pci_devs[devno].dev ||
- PCI_FUNC(pdev->devfn) != pci_devs[devno].func)) {
+ if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
+ PCI_FUNC(pdev->devfn) != dev_descr->func)) {
i7core_printk(KERN_ERR,
"Device PCI ID %04x:%04x "
"has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id,
+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
- bus, pci_devs[devno].dev, pci_devs[devno].func);
+ bus, dev_descr->dev, dev_descr->func);
return -ENODEV;
}
i7core_printk(KERN_ERR,
"Couldn't enable "
"dev %02x:%02x.%d PCI ID %04x:%04x\n",
- bus, pci_devs[devno].dev, pci_devs[devno].func,
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+ bus, dev_descr->dev, dev_descr->func,
+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
return -ENODEV;
}
- i7core_printk(KERN_INFO,
- "Registered socket %d "
- "dev %02x:%02x.%d PCI ID %04x:%04x\n",
- socket, bus, pci_devs[devno].dev, pci_devs[devno].func,
- PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
+ debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
+ socket, bus, dev_descr->dev,
+ dev_descr->func,
+ PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
+
+ /*
+ * As stated on drivers/pci/search.c, the reference count for
+ * @from is always decremented if it is not %NULL. So, as we need
+ * to get all devices up to null, we need to do a get for the device
+ */
+ pci_dev_get(pdev);
*prev = pdev;
return 0;
}
-static int i7core_get_devices(void)
+static int i7core_get_all_devices(void)
{
- int i;
+ int i, rc, last_bus;
struct pci_dev *pdev = NULL;
-
- for (i = 0; i < N_DEVS; i++) {
- pdev = NULL;
- do {
- if (i7core_get_onedevice(&pdev, i) < 0) {
- i7core_put_devices();
- return -ENODEV;
- }
- } while (pdev);
+ const struct pci_id_table *table = pci_dev_table;
+
+ last_bus = i7core_pci_lastbus();
+
+ while (table && table->descr) {
+ for (i = 0; i < table->n_devs; i++) {
+ pdev = NULL;
+ do {
+ rc = i7core_get_onedevice(&pdev, table, i,
+ last_bus);
+ if (rc < 0) {
+ if (i == 0) {
+ i = table->n_devs;
+ break;
+ }
+ i7core_put_all_devices();
+ return -ENODEV;
+ }
+ } while (pdev);
+ }
+ table++;
}
+
return 0;
}
-static int mci_bind_devs(struct mem_ctl_info *mci)
+static int mci_bind_devs(struct mem_ctl_info *mci,
+ struct i7core_dev *i7core_dev)
{
struct i7core_pvt *pvt = mci->pvt_info;
struct pci_dev *pdev;
- int i, j, func, slot;
+ int i, func, slot;
- for (i = 0; i < pvt->sockets; i++) {
- for (j = 0; j < N_DEVS; j++) {
- pdev = pci_devs[j].pdev[i];
- if (!pdev)
- continue;
+ pvt->is_registered = 0;
+ for (i = 0; i < i7core_dev->n_devs; i++) {
+ pdev = i7core_dev->pdev[i];
+ if (!pdev)
+ continue;
- func = PCI_FUNC(pdev->devfn);
- slot = PCI_SLOT(pdev->devfn);
- if (slot == 3) {
- if (unlikely(func > MAX_MCR_FUNC))
- goto error;
- pvt->pci_mcr[i][func] = pdev;
- } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
- if (unlikely(func > MAX_CHAN_FUNC))
- goto error;
- pvt->pci_ch[i][slot - 4][func] = pdev;
- } else if (!slot && !func)
- pvt->pci_noncore[i] = pdev;
- else
+ func = PCI_FUNC(pdev->devfn);
+ slot = PCI_SLOT(pdev->devfn);
+ if (slot == 3) {
+ if (unlikely(func > MAX_MCR_FUNC))
+ goto error;
+ pvt->pci_mcr[func] = pdev;
+ } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
+ if (unlikely(func > MAX_CHAN_FUNC))
goto error;
+ pvt->pci_ch[slot - 4][func] = pdev;
+ } else if (!slot && !func)
+ pvt->pci_noncore = pdev;
+ else
+ goto error;
- debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
- PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
- pdev, i);
- }
+ debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
+ PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
+ pdev, i7core_dev->socket);
+
+ if (PCI_SLOT(pdev->devfn) == 3 &&
+ PCI_FUNC(pdev->devfn) == 2)
+ pvt->is_registered = 1;
}
return 0;
/****************************************************************************
Error check routines
****************************************************************************/
+static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
+ const int chan,
+ const int dimm,
+ const int add)
+{
+ char *msg;
+ struct i7core_pvt *pvt = mci->pvt_info;
+ int row = pvt->csrow_map[chan][dimm], i;
+
+ for (i = 0; i < add; i++) {
+ msg = kasprintf(GFP_KERNEL, "Corrected error "
+ "(Socket=%d channel=%d dimm=%d)",
+ pvt->i7core_dev->socket, chan, dimm);
+
+ edac_mc_handle_fbd_ce(mci, row, 0, msg);
+ kfree (msg);
+ }
+}
+
+static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
+ const int chan,
+ const int new0,
+ const int new1,
+ const int new2)
+{
+ struct i7core_pvt *pvt = mci->pvt_info;
+ int add0 = 0, add1 = 0, add2 = 0;
+ /* Updates CE counters if it is not the first time here */
+ if (pvt->ce_count_available) {
+ /* Updates CE counters */
+
+ add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
+ add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
+ add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
+
+ if (add2 < 0)
+ add2 += 0x7fff;
+ pvt->rdimm_ce_count[chan][2] += add2;
+
+ if (add1 < 0)
+ add1 += 0x7fff;
+ pvt->rdimm_ce_count[chan][1] += add1;
+
+ if (add0 < 0)
+ add0 += 0x7fff;
+ pvt->rdimm_ce_count[chan][0] += add0;
+ } else
+ pvt->ce_count_available = 1;
+
+ /* Store the new values */
+ pvt->rdimm_last_ce_count[chan][2] = new2;
+ pvt->rdimm_last_ce_count[chan][1] = new1;
+ pvt->rdimm_last_ce_count[chan][0] = new0;
+
+ /*updated the edac core */
+ if (add0 != 0)
+ i7core_rdimm_update_csrow(mci, chan, 0, add0);
+ if (add1 != 0)
+ i7core_rdimm_update_csrow(mci, chan, 1, add1);
+ if (add2 != 0)
+ i7core_rdimm_update_csrow(mci, chan, 2, add2);
+
+}
+
+static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
+{
+ struct i7core_pvt *pvt = mci->pvt_info;
+ u32 rcv[3][2];
+ int i, new0, new1, new2;
+
+ /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
+ &rcv[0][0]);
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
+ &rcv[0][1]);
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
+ &rcv[1][0]);
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
+ &rcv[1][1]);
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
+ &rcv[2][0]);
+ pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
+ &rcv[2][1]);
+ for (i = 0 ; i < 3; i++) {
+ debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
+ (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
+ /*if the channel has 3 dimms*/
+ if (pvt->channel[i].dimms > 2) {
+ new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
+ new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
+ new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
+ } else {
+ new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
+ DIMM_BOT_COR_ERR(rcv[i][0]);
+ new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
+ DIMM_BOT_COR_ERR(rcv[i][1]);
+ new2 = 0;
+ }
+
+ i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
+ }
+}
/* This function is based on the device 3 function 4 registers as described on:
* Intel Xeon Processor 5500 Series Datasheet Volume 2
* also available at:
* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
*/
-static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
+static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
{
struct i7core_pvt *pvt = mci->pvt_info;
u32 rcv1, rcv0;
int new0, new1, new2;
- if (!pvt->pci_mcr[socket][4]) {
- debugf0("%s MCR registers not found\n",__func__);
+ if (!pvt->pci_mcr[4]) {
+ debugf0("%s MCR registers not found\n", __func__);
return;
}
- /* Corrected error reads */
- pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
- pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
+ /* Corrected test errors */
+ pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
+ pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
/* Store the new values */
new2 = DIMM2_COR_ERR(rcv1);
new1 = DIMM1_COR_ERR(rcv0);
new0 = DIMM0_COR_ERR(rcv0);
-#if 0
- debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
- (pvt->ce_count_available ? "UPDATE" : "READ"),
- rcv1, rcv0, new0, new1, new2);
-#endif
-
/* Updates CE counters if it is not the first time here */
- if (pvt->ce_count_available[socket]) {
+ if (pvt->ce_count_available) {
/* Updates CE counters */
int add0, add1, add2;
- add2 = new2 - pvt->last_ce_count[socket][2];
- add1 = new1 - pvt->last_ce_count[socket][1];
- add0 = new0 - pvt->last_ce_count[socket][0];
+ add2 = new2 - pvt->udimm_last_ce_count[2];
+ add1 = new1 - pvt->udimm_last_ce_count[1];
+ add0 = new0 - pvt->udimm_last_ce_count[0];
if (add2 < 0)
add2 += 0x7fff;
- pvt->ce_count[socket][2] += add2;
+ pvt->udimm_ce_count[2] += add2;
if (add1 < 0)
add1 += 0x7fff;
- pvt->ce_count[socket][1] += add1;
+ pvt->udimm_ce_count[1] += add1;
if (add0 < 0)
add0 += 0x7fff;
- pvt->ce_count[socket][0] += add0;
+ pvt->udimm_ce_count[0] += add0;
+
+ if (add0 | add1 | add2)
+ i7core_printk(KERN_ERR, "New Corrected error(s): "
+ "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
+ add0, add1, add2);
} else
- pvt->ce_count_available[socket] = 1;
+ pvt->ce_count_available = 1;
/* Store the new values */
- pvt->last_ce_count[socket][2] = new2;
- pvt->last_ce_count[socket][1] = new1;
- pvt->last_ce_count[socket][0] = new0;
+ pvt->udimm_last_ce_count[2] = new2;
+ pvt->udimm_last_ce_count[1] = new1;
+ pvt->udimm_last_ce_count[0] = new0;
}
/*
* fields
*/
static void i7core_mce_output_error(struct mem_ctl_info *mci,
- struct mce *m)
+ const struct mce *m)
{
+ struct i7core_pvt *pvt = mci->pvt_info;
char *type, *optype, *err, *msg;
unsigned long error = m->status & 0x1ff0000l;
u32 optypenum = (m->status >> 4) & 0x07;
u32 channel = (m->misc >> 18) & 0x3;
u32 syndrome = m->misc >> 32;
u32 errnum = find_first_bit(&error, 32);
+ int csrow;
if (m->mcgstatus & 1)
type = "FATAL";
type = "NON_FATAL";
switch (optypenum) {
- case 0:
- optype = "generic undef request";
- break;
- case 1:
- optype = "read error";
- break;
- case 2:
- optype = "write error";
- break;
- case 3:
- optype = "addr/cmd error";
- break;
- case 4:
- optype = "scrubbing error";
- break;
- default:
- optype = "reserved";
- break;
+ case 0:
+ optype = "generic undef request";
+ break;
+ case 1:
+ optype = "read error";
+ break;
+ case 2:
+ optype = "write error";
+ break;
+ case 3:
+ optype = "addr/cmd error";
+ break;
+ case 4:
+ optype = "scrubbing error";
+ break;
+ default:
+ optype = "reserved";
+ break;
}
switch (errnum) {
/* FIXME: should convert addr into bank and rank information */
msg = kasprintf(GFP_ATOMIC,
- "%s (addr = 0x%08llx, socket=%d, Dimm=%d, Channel=%d, "
+ "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
"syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
type, (long long) m->addr, m->cpu, dimm, channel,
syndrome, core_err_cnt, (long long)m->status,
debugf0("%s", msg);
+ csrow = pvt->csrow_map[channel][dimm];
+
/* Call the helper to output message */
- edac_mc_handle_fbd_ue(mci, 0 /* FIXME: should be rank here */,
- 0, 0 /* FIXME: should be channel here */, msg);
+ if (m->mcgstatus & 1)
+ edac_mc_handle_fbd_ue(mci, csrow, 0,
+ 0 /* FIXME: should be channel here */, msg);
+ else if (!pvt->is_registered)
+ edac_mc_handle_fbd_ce(mci, csrow,
+ 0 /* FIXME: should be channel here */, msg);
kfree(msg);
}
struct i7core_pvt *pvt = mci->pvt_info;
int i;
unsigned count = 0;
- struct mce *m = NULL;
- unsigned long flags;
-
- /* Copy all mce errors into a temporary buffer */
- spin_lock_irqsave(&pvt->mce_lock, flags);
- if (pvt->mce_count) {
- m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC);
- if (m) {
- count = pvt->mce_count;
- memcpy(m, &pvt->mce_entry, sizeof(*m) * count);
- }
- pvt->mce_count = 0;
+ struct mce *m;
+
+ /*
+ * MCE first step: Copy all mce errors into a temporary buffer
+ * We use a double buffering here, to reduce the risk of
+ * loosing an error.
+ */
+ smp_rmb();
+ count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
+ % MCE_LOG_LEN;
+ if (!count)
+ goto check_ce_error;
+
+ m = pvt->mce_outentry;
+ if (pvt->mce_in + count > MCE_LOG_LEN) {
+ unsigned l = MCE_LOG_LEN - pvt->mce_in;
+
+ memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
+ smp_wmb();
+ pvt->mce_in = 0;
+ count -= l;
+ m += l;
+ }
+ memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
+ smp_wmb();
+ pvt->mce_in += count;
+
+ smp_rmb();
+ if (pvt->mce_overrun) {
+ i7core_printk(KERN_ERR, "Lost %d memory errors\n",
+ pvt->mce_overrun);
+ smp_wmb();
+ pvt->mce_overrun = 0;
}
- spin_unlock_irqrestore(&pvt->mce_lock, flags);
- /* proccess mcelog errors */
+ /*
+ * MCE second step: parse errors and display
+ */
for (i = 0; i < count; i++)
- i7core_mce_output_error(mci, &m[i]);
-
- kfree(m);
+ i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
- /* check memory count errors */
- for (i = 0; i < pvt->sockets; i++)
- check_mc_test_err(mci, i);
+ /*
+ * Now, let's increment CE error counts
+ */
+check_ce_error:
+ if (!pvt->is_registered)
+ i7core_udimm_check_mc_ecc_err(mci);
+ else
+ i7core_rdimm_check_mc_ecc_err(mci);
}
/*
* This routine simply queues mcelog errors, and
* return. The error itself should be handled later
* by i7core_check_error.
+ * WARNING: As this routine should be called at NMI time, extra care should
+ * be taken to avoid deadlocks, and to be as fast as possible.
*/
static int i7core_mce_check_error(void *priv, struct mce *mce)
{
struct mem_ctl_info *mci = priv;
struct i7core_pvt *pvt = mci->pvt_info;
- unsigned long flags;
/*
* Just let mcelog handle it if the error is
if (mce->bank != 8)
return 0;
- spin_lock_irqsave(&pvt->mce_lock, flags);
- if (pvt->mce_count < MCE_LOG_LEN) {
- memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
- pvt->mce_count++;
+#ifdef CONFIG_SMP
+ /* Only handle if it is the right mc controller */
+ if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
+ return 0;
+#endif
+
+ smp_rmb();
+ if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
+ smp_wmb();
+ pvt->mce_overrun++;
+ return 0;
}
- spin_unlock_irqrestore(&pvt->mce_lock, flags);
+
+ /* Copy memory error at the ringbuffer */
+ memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
+ smp_wmb();
+ pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
/* Handle fatal errors immediately */
if (mce->mcgstatus & 1)
return 1;
}
-/*
- * i7core_probe Probe for ONE instance of device to see if it is
- * present.
- * return:
- * 0 for FOUND a device
- * < 0 for error code
- */
-static int __devinit i7core_probe(struct pci_dev *pdev,
- const struct pci_device_id *id)
+static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
{
- struct mem_ctl_info *mci;
+ pvt->i7core_pci = edac_pci_create_generic_ctl(
+ &pvt->i7core_dev->pdev[0]->dev,
+ EDAC_MOD_STR);
+ if (unlikely(!pvt->i7core_pci))
+ pr_warn("Unable to setup PCI error report via EDAC\n");
+}
+
+static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
+{
+ if (likely(pvt->i7core_pci))
+ edac_pci_release_generic_ctl(pvt->i7core_pci);
+ else
+ i7core_printk(KERN_ERR,
+ "Couldn't find mem_ctl_info for socket %d\n",
+ pvt->i7core_dev->socket);
+ pvt->i7core_pci = NULL;
+}
+
+static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
+{
+ struct mem_ctl_info *mci = i7core_dev->mci;
struct i7core_pvt *pvt;
- int num_channels = 0;
- int num_csrows = 0;
- int csrow = 0;
- int dev_idx = id->driver_data;
- int rc, i;
- u8 sockets;
- if (unlikely(dev_idx >= ARRAY_SIZE(i7core_devs)))
- return -EINVAL;
+ if (unlikely(!mci || !mci->pvt_info)) {
+ debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
+ __func__, &i7core_dev->pdev[0]->dev);
- /* get the pci devices we want to reserve for our use */
- rc = i7core_get_devices();
- if (unlikely(rc < 0))
- return rc;
+ i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
+ return;
+ }
- sockets = 1;
- for (i = NUM_SOCKETS - 1; i > 0; i--)
- if (pci_devs[0].pdev[i]) {
- sockets = i + 1;
- break;
- }
+ pvt = mci->pvt_info;
- for (i = 0; i < sockets; i++) {
- int channels;
- int csrows;
+ debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
+ __func__, mci, &i7core_dev->pdev[0]->dev);
- /* Check the number of active and not disabled channels */
- rc = i7core_get_active_channels(i, &channels, &csrows);
- if (unlikely(rc < 0))
- goto fail0;
+ /* Disable MCE NMI handler */
+ edac_mce_unregister(&pvt->edac_mce);
- num_channels += channels;
- num_csrows += csrows;
- }
+ /* Disable EDAC polling */
+ i7core_pci_ctl_release(pvt);
+
+ /* Remove MC sysfs nodes */
+ edac_mc_del_mc(mci->dev);
+
+ debugf1("%s: free mci struct\n", mci->ctl_name);
+ kfree(mci->ctl_name);
+ edac_mc_free(mci);
+ i7core_dev->mci = NULL;
+}
+
+static int i7core_register_mci(struct i7core_dev *i7core_dev)
+{
+ struct mem_ctl_info *mci;
+ struct i7core_pvt *pvt;
+ int rc, channels, csrows;
+
+ /* Check the number of active and not disabled channels */
+ rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
+ if (unlikely(rc < 0))
+ return rc;
/* allocate a new MC control structure */
- mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
- if (unlikely(!mci)) {
- rc = -ENOMEM;
- goto fail0;
- }
+ mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
+ if (unlikely(!mci))
+ return -ENOMEM;
- debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
+ debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
+ __func__, mci, &i7core_dev->pdev[0]->dev);
- mci->dev = &pdev->dev; /* record ptr to the generic device */
pvt = mci->pvt_info;
memset(pvt, 0, sizeof(*pvt));
- pvt->sockets = sockets;
- mci->mc_idx = 0;
+
+ /* Associates i7core_dev and mci for future usage */
+ pvt->i7core_dev = i7core_dev;
+ i7core_dev->mci = mci;
/*
* FIXME: how to handle RDDR3 at MCI level? It is possible to have
mci->edac_cap = EDAC_FLAG_NONE;
mci->mod_name = "i7core_edac.c";
mci->mod_ver = I7CORE_REVISION;
- mci->ctl_name = i7core_devs[dev_idx].ctl_name;
- mci->dev_name = pci_name(pdev);
+ mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
+ i7core_dev->socket);
+ mci->dev_name = pci_name(i7core_dev->pdev[0]);
mci->ctl_page_to_phys = NULL;
- mci->mc_driver_sysfs_attributes = i7core_inj_attrs;
- /* Set the function pointer to an actual operation function */
- mci->edac_check = i7core_check_error;
/* Store pci devices at mci for faster access */
- rc = mci_bind_devs(mci);
+ rc = mci_bind_devs(mci, i7core_dev);
if (unlikely(rc < 0))
- goto fail1;
+ goto fail0;
+
+ if (pvt->is_registered)
+ mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
+ else
+ mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
/* Get dimm basic config */
- for (i = 0; i < sockets; i++)
- get_dimm_config(mci, &csrow, i);
+ get_dimm_config(mci);
+ /* record ptr to the generic device */
+ mci->dev = &i7core_dev->pdev[0]->dev;
+ /* Set the function pointer to an actual operation function */
+ mci->edac_check = i7core_check_error;
/* add this new MC control structure to EDAC's list of MCs */
if (unlikely(edac_mc_add_mc(mci))) {
*/
rc = -EINVAL;
- goto fail1;
- }
-
- /* allocating generic PCI control info */
- i7core_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
- if (unlikely(!i7core_pci)) {
- printk(KERN_WARNING
- "%s(): Unable to create PCI control\n",
- __func__);
- printk(KERN_WARNING
- "%s(): PCI error report via EDAC not setup\n",
- __func__);
+ goto fail0;
}
/* Default error mask is any memory */
pvt->inject.page = -1;
pvt->inject.col = -1;
+ /* allocating generic PCI control info */
+ i7core_pci_ctl_create(pvt);
+
/* Registers on edac_mce in order to receive memory errors */
pvt->edac_mce.priv = mci;
pvt->edac_mce.check_error = i7core_mce_check_error;
- spin_lock_init(&pvt->mce_lock);
-
rc = edac_mce_register(&pvt->edac_mce);
- if (unlikely (rc < 0)) {
+ if (unlikely(rc < 0)) {
debugf0("MC: " __FILE__
": %s(): failed edac_mce_register()\n", __func__);
goto fail1;
}
+ return 0;
+
+fail1:
+ i7core_pci_ctl_release(pvt);
+ edac_mc_del_mc(mci->dev);
+fail0:
+ kfree(mci->ctl_name);
+ edac_mc_free(mci);
+ i7core_dev->mci = NULL;
+ return rc;
+}
+
+/*
+ * i7core_probe Probe for ONE instance of device to see if it is
+ * present.
+ * return:
+ * 0 for FOUND a device
+ * < 0 for error code
+ */
+
+static int __devinit i7core_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int rc;
+ struct i7core_dev *i7core_dev;
+
+ /* get the pci devices we want to reserve for our use */
+ mutex_lock(&i7core_edac_lock);
+
+ /*
+ * All memory controllers are allocated at the first pass.
+ */
+ if (unlikely(probed >= 1)) {
+ mutex_unlock(&i7core_edac_lock);
+ return -ENODEV;
+ }
+ probed++;
+
+ rc = i7core_get_all_devices();
+ if (unlikely(rc < 0))
+ goto fail0;
+
+ list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
+ rc = i7core_register_mci(i7core_dev);
+ if (unlikely(rc < 0))
+ goto fail1;
+ }
+
i7core_printk(KERN_INFO, "Driver loaded.\n");
+ mutex_unlock(&i7core_edac_lock);
return 0;
fail1:
- edac_mc_free(mci);
+ list_for_each_entry(i7core_dev, &i7core_edac_list, list)
+ i7core_unregister_mci(i7core_dev);
+ i7core_put_all_devices();
fail0:
- i7core_put_devices();
+ mutex_unlock(&i7core_edac_lock);
return rc;
}
*/
static void __devexit i7core_remove(struct pci_dev *pdev)
{
- struct mem_ctl_info *mci;
- struct i7core_pvt *pvt;
+ struct i7core_dev *i7core_dev;
debugf0(__FILE__ ": %s()\n", __func__);
- if (i7core_pci)
- edac_pci_release_generic_ctl(i7core_pci);
+ /*
+ * we have a trouble here: pdev value for removal will be wrong, since
+ * it will point to the X58 register used to detect that the machine
+ * is a Nehalem or upper design. However, due to the way several PCI
+ * devices are grouped together to provide MC functionality, we need
+ * to use a different method for releasing the devices
+ */
+ mutex_lock(&i7core_edac_lock);
- mci = edac_mc_del_mc(&pdev->dev);
- if (!mci)
+ if (unlikely(!probed)) {
+ mutex_unlock(&i7core_edac_lock);
return;
+ }
- /* Unregisters on edac_mce in order to receive memory errors */
- pvt = mci->pvt_info;
- edac_mce_unregister(&pvt->edac_mce);
+ list_for_each_entry(i7core_dev, &i7core_edac_list, list)
+ i7core_unregister_mci(i7core_dev);
- /* retrieve references to resources, and free those resources */
- i7core_put_devices();
+ /* Release PCI resources */
+ i7core_put_all_devices();
- edac_mc_free(mci);
+ probed--;
+
+ mutex_unlock(&i7core_edac_lock);
}
MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
opstate_init();
+ if (use_pci_fixup)
+ i7core_xeon_pci_fixup(pci_dev_table);
+
pci_rc = pci_register_driver(&i7core_driver);
- return (pci_rc < 0) ? pci_rc : 0;
+ if (pci_rc >= 0)
+ return 0;
+
+ i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
+ pci_rc);
+
+ return pci_rc;
}
/*
Code Review / linux-2.6.git / blobdiff