Merge branch 'mfd/wm8994' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[linux-2.6.git] / drivers / dma / ste_dma40_ll.c
index 772636b..cad9e1d 100644 (file)
@@ -1,10 +1,8 @@
 /*
- * driver/dma/ste_dma40_ll.c
- *
- * Copyright (C) ST-Ericsson 2007-2010
+ * Copyright (C) ST-Ericsson SA 2007-2010
+ * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
- * Author: Per Friden <per.friden@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
  */
 
 #include <linux/kernel.h>
@@ -39,16 +37,13 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
            cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
                l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
 
-       l3 |= 1 << D40_MEM_LCSP3_DCFG_TIM_POS;
        l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
        l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
        l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
-       l3 |= 1 << D40_MEM_LCSP3_DTCP_POS;
 
        l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
        l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
        l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
-       l1 |= 1 << D40_MEM_LCSP1_STCP_POS;
 
        *lcsp1 = l1;
        *lcsp3 = l3;
@@ -113,28 +108,32 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
                src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
        }
 
-       if (cfg->channel_type & STEDMA40_HIGH_PRIORITY_CHANNEL) {
+       if (cfg->high_priority) {
                src |= 1 << D40_SREG_CFG_PRI_POS;
                dst |= 1 << D40_SREG_CFG_PRI_POS;
        }
 
-       src |= cfg->src_info.endianess << D40_SREG_CFG_LBE_POS;
-       dst |= cfg->dst_info.endianess << D40_SREG_CFG_LBE_POS;
+       if (cfg->src_info.big_endian)
+               src |= 1 << D40_SREG_CFG_LBE_POS;
+       if (cfg->dst_info.big_endian)
+               dst |= 1 << D40_SREG_CFG_LBE_POS;
 
        *src_cfg = src;
        *dst_cfg = dst;
 }
 
-int d40_phy_fill_lli(struct d40_phy_lli *lli,
-                    dma_addr_t data,
-                    u32 data_size,
-                    int psize,
-                    dma_addr_t next_lli,
-                    u32 reg_cfg,
-                    bool term_int,
-                    u32 data_width,
-                    bool is_device)
+static int d40_phy_fill_lli(struct d40_phy_lli *lli,
+                           dma_addr_t data,
+                           u32 data_size,
+                           dma_addr_t next_lli,
+                           u32 reg_cfg,
+                           struct stedma40_half_channel_info *info,
+                           unsigned int flags)
 {
+       bool addr_inc = flags & LLI_ADDR_INC;
+       bool term_int = flags & LLI_TERM_INT;
+       unsigned int data_width = info->data_width;
+       int psize = info->psize;
        int num_elems;
 
        if (psize == STEDMA40_PSIZE_PHY_1)
@@ -142,13 +141,6 @@ int d40_phy_fill_lli(struct d40_phy_lli *lli,
        else
                num_elems = 2 << psize;
 
-       /*
-        * Size is 16bit. data_width is 8, 16, 32 or 64 bit
-        * Block large than 64 KiB must be split.
-        */
-       if (data_size > (0xffff << data_width))
-               return -EINVAL;
-
        /* Must be aligned */
        if (!IS_ALIGNED(data, 0x1 << data_width))
                return -EINVAL;
@@ -164,7 +156,7 @@ int d40_phy_fill_lli(struct d40_phy_lli *lli,
         * Distance to next element sized entry.
         * Usually the size of the element unless you want gaps.
         */
-       if (!is_device)
+       if (addr_inc)
                lli->reg_elt |= (0x1 << data_width) <<
                        D40_SREG_ELEM_PHY_EIDX_POS;
 
@@ -190,98 +182,190 @@ int d40_phy_fill_lli(struct d40_phy_lli *lli,
        return 0;
 }
 
+static int d40_seg_size(int size, int data_width1, int data_width2)
+{
+       u32 max_w = max(data_width1, data_width2);
+       u32 min_w = min(data_width1, data_width2);
+       u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+
+       if (seg_max > STEDMA40_MAX_SEG_SIZE)
+               seg_max -= (1 << max_w);
+
+       if (size <= seg_max)
+               return size;
+
+       if (size <= 2 * seg_max)
+               return ALIGN(size / 2, 1 << max_w);
+
+       return seg_max;
+}
+
+static struct d40_phy_lli *
+d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
+                  dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
+                  struct stedma40_half_channel_info *info,
+                  struct stedma40_half_channel_info *otherinfo,
+                  unsigned long flags)
+{
+       bool lastlink = flags & LLI_LAST_LINK;
+       bool addr_inc = flags & LLI_ADDR_INC;
+       bool term_int = flags & LLI_TERM_INT;
+       bool cyclic = flags & LLI_CYCLIC;
+       int err;
+       dma_addr_t next = lli_phys;
+       int size_rest = size;
+       int size_seg = 0;
+
+       /*
+        * This piece may be split up based on d40_seg_size(); we only want the
+        * term int on the last part.
+        */
+       if (term_int)
+               flags &= ~LLI_TERM_INT;
+
+       do {
+               size_seg = d40_seg_size(size_rest, info->data_width,
+                                       otherinfo->data_width);
+               size_rest -= size_seg;
+
+               if (size_rest == 0 && term_int)
+                       flags |= LLI_TERM_INT;
+
+               if (size_rest == 0 && lastlink)
+                       next = cyclic ? first_phys : 0;
+               else
+                       next = ALIGN(next + sizeof(struct d40_phy_lli),
+                                    D40_LLI_ALIGN);
+
+               err = d40_phy_fill_lli(lli, addr, size_seg, next,
+                                      reg_cfg, info, flags);
+
+               if (err)
+                       goto err;
+
+               lli++;
+               if (addr_inc)
+                       addr += size_seg;
+       } while (size_rest);
+
+       return lli;
+
+ err:
+       return NULL;
+}
+
 int d40_phy_sg_to_lli(struct scatterlist *sg,
                      int sg_len,
                      dma_addr_t target,
-                     struct d40_phy_lli *lli,
+                     struct d40_phy_lli *lli_sg,
                      dma_addr_t lli_phys,
                      u32 reg_cfg,
-                     u32 data_width,
-                     int psize,
-                     bool term_int)
+                     struct stedma40_half_channel_info *info,
+                     struct stedma40_half_channel_info *otherinfo,
+                     unsigned long flags)
 {
        int total_size = 0;
        int i;
        struct scatterlist *current_sg = sg;
-       dma_addr_t next_lli_phys;
-       dma_addr_t dst;
-       int err = 0;
+       struct d40_phy_lli *lli = lli_sg;
+       dma_addr_t l_phys = lli_phys;
+
+       if (!target)
+               flags |= LLI_ADDR_INC;
 
        for_each_sg(sg, current_sg, sg_len, i) {
+               dma_addr_t sg_addr = sg_dma_address(current_sg);
+               unsigned int len = sg_dma_len(current_sg);
+               dma_addr_t dst = target ?: sg_addr;
 
                total_size += sg_dma_len(current_sg);
 
-               /* If this scatter list entry is the last one, no next link */
-               if (sg_len - 1 == i)
-                       next_lli_phys = 0;
-               else
-                       next_lli_phys = ALIGN(lli_phys + (i + 1) *
-                                             sizeof(struct d40_phy_lli),
-                                             D40_LLI_ALIGN);
+               if (i == sg_len - 1)
+                       flags |= LLI_TERM_INT | LLI_LAST_LINK;
 
-               if (target)
-                       dst = target;
-               else
-                       dst = sg_phys(current_sg);
-
-               err = d40_phy_fill_lli(&lli[i],
-                                      dst,
-                                      sg_dma_len(current_sg),
-                                      psize,
-                                      next_lli_phys,
-                                      reg_cfg,
-                                      !next_lli_phys,
-                                      data_width,
-                                      target == dst);
-               if (err)
-                       goto err;
+               l_phys = ALIGN(lli_phys + (lli - lli_sg) *
+                              sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
+
+               lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
+                                        reg_cfg, info, otherinfo, flags);
+
+               if (lli == NULL)
+                       return -EINVAL;
        }
 
        return total_size;
- err:
-       return err;
 }
 
 
-void d40_phy_lli_write(void __iomem *virtbase,
-                      u32 phy_chan_num,
-                      struct d40_phy_lli *lli_dst,
-                      struct d40_phy_lli *lli_src)
+/* DMA logical lli operations */
+
+static void d40_log_lli_link(struct d40_log_lli *lli_dst,
+                            struct d40_log_lli *lli_src,
+                            int next, unsigned int flags)
 {
+       bool interrupt = flags & LLI_TERM_INT;
+       u32 slos = 0;
+       u32 dlos = 0;
+
+       if (next != -EINVAL) {
+               slos = next * 2;
+               dlos = next * 2 + 1;
+       }
+
+       if (interrupt) {
+               lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
+               lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
+       }
 
-       writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
-       writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
-       writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
-       writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
-
-       writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
-       writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
-       writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
-       writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
-              phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
+       lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
+               (slos << D40_MEM_LCSP1_SLOS_POS);
 
+       lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
+               (dlos << D40_MEM_LCSP1_SLOS_POS);
 }
 
-/* DMA logical lli operations */
+void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
+                          struct d40_log_lli *lli_dst,
+                          struct d40_log_lli *lli_src,
+                          int next, unsigned int flags)
+{
+       d40_log_lli_link(lli_dst, lli_src, next, flags);
 
-void d40_log_fill_lli(struct d40_log_lli *lli,
-                     dma_addr_t data, u32 data_size,
-                     u32 lli_next_off, u32 reg_cfg,
-                     u32 data_width,
-                     bool term_int, bool addr_inc)
+       writel(lli_src->lcsp02, &lcpa[0].lcsp0);
+       writel(lli_src->lcsp13, &lcpa[0].lcsp1);
+       writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
+       writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
+}
+
+void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
+                          struct d40_log_lli *lli_dst,
+                          struct d40_log_lli *lli_src,
+                          int next, unsigned int flags)
 {
+       d40_log_lli_link(lli_dst, lli_src, next, flags);
+
+       writel(lli_src->lcsp02, &lcla[0].lcsp02);
+       writel(lli_src->lcsp13, &lcla[0].lcsp13);
+       writel(lli_dst->lcsp02, &lcla[1].lcsp02);
+       writel(lli_dst->lcsp13, &lcla[1].lcsp13);
+}
+
+static void d40_log_fill_lli(struct d40_log_lli *lli,
+                            dma_addr_t data, u32 data_size,
+                            u32 reg_cfg,
+                            u32 data_width,
+                            unsigned int flags)
+{
+       bool addr_inc = flags & LLI_ADDR_INC;
+
        lli->lcsp13 = reg_cfg;
 
        /* The number of elements to transfer */
        lli->lcsp02 = ((data_size >> data_width) <<
                       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
+
+       BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
+
        /* 16 LSBs address of the current element */
        lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
        /* 16 MSBs address of the current element */
@@ -290,162 +374,67 @@ void d40_log_fill_lli(struct d40_log_lli *lli,
        if (addr_inc)
                lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;
 
-       lli->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
-       /* If this scatter list entry is the last one, no next link */
-       lli->lcsp13 |= (lli_next_off << D40_MEM_LCSP1_SLOS_POS) &
-               D40_MEM_LCSP1_SLOS_MASK;
-
-       if (term_int)
-               lli->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
-       else
-               lli->lcsp13 &= ~D40_MEM_LCSP1_SCFG_TIM_MASK;
 }
 
-int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
-                     struct scatterlist *sg,
-                     int sg_len,
-                     struct d40_log_lli_bidir *lli,
-                     struct d40_def_lcsp *lcsp,
-                     u32 src_data_width,
-                     u32 dst_data_width,
-                     enum dma_data_direction direction,
-                     bool term_int, dma_addr_t dev_addr, int max_len,
-                     int llis_per_log)
+static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
+                                      dma_addr_t addr,
+                                      int size,
+                                      u32 lcsp13, /* src or dst*/
+                                      u32 data_width1,
+                                      u32 data_width2,
+                                      unsigned int flags)
 {
-       int total_size = 0;
-       struct scatterlist *current_sg = sg;
-       int i;
-       u32 next_lli_off_dst = 0;
-       u32 next_lli_off_src = 0;
-
-       for_each_sg(sg, current_sg, sg_len, i) {
-               total_size += sg_dma_len(current_sg);
-
-               /*
-                * If this scatter list entry is the last one or
-                * max length, terminate link.
-                */
-               if (sg_len - 1 == i || ((i+1) % max_len == 0)) {
-                       next_lli_off_src = 0;
-                       next_lli_off_dst = 0;
-               } else {
-                       if (next_lli_off_dst == 0 &&
-                           next_lli_off_src == 0) {
-                               /* The first lli will be at next_lli_off */
-                               next_lli_off_dst = (lcla->dst_id *
-                                                   llis_per_log + 1);
-                               next_lli_off_src = (lcla->src_id *
-                                                   llis_per_log + 1);
-                       } else {
-                               next_lli_off_dst++;
-                               next_lli_off_src++;
-                       }
-               }
-
-               if (direction == DMA_TO_DEVICE) {
-                       d40_log_fill_lli(&lli->src[i],
-                                        sg_phys(current_sg),
-                                        sg_dma_len(current_sg),
-                                        next_lli_off_src,
-                                        lcsp->lcsp1, src_data_width,
-                                        false,
-                                        true);
-                       d40_log_fill_lli(&lli->dst[i],
-                                        dev_addr,
-                                        sg_dma_len(current_sg),
-                                        next_lli_off_dst,
-                                        lcsp->lcsp3, dst_data_width,
-                                        /* No next == terminal interrupt */
-                                        term_int && !next_lli_off_dst,
-                                        false);
-               } else {
-                       d40_log_fill_lli(&lli->dst[i],
-                                        sg_phys(current_sg),
-                                        sg_dma_len(current_sg),
-                                        next_lli_off_dst,
-                                        lcsp->lcsp3, dst_data_width,
-                                        /* No next == terminal interrupt */
-                                        term_int && !next_lli_off_dst,
-                                        true);
-                       d40_log_fill_lli(&lli->src[i],
-                                        dev_addr,
-                                        sg_dma_len(current_sg),
-                                        next_lli_off_src,
-                                        lcsp->lcsp1, src_data_width,
-                                        false,
-                                        false);
-               }
-       }
-       return total_size;
+       bool addr_inc = flags & LLI_ADDR_INC;
+       struct d40_log_lli *lli = lli_sg;
+       int size_rest = size;
+       int size_seg = 0;
+
+       do {
+               size_seg = d40_seg_size(size_rest, data_width1, data_width2);
+               size_rest -= size_seg;
+
+               d40_log_fill_lli(lli,
+                                addr,
+                                size_seg,
+                                lcsp13, data_width1,
+                                flags);
+               if (addr_inc)
+                       addr += size_seg;
+               lli++;
+       } while (size_rest);
+
+       return lli;
 }
 
-int d40_log_sg_to_lli(int lcla_id,
-                     struct scatterlist *sg,
+int d40_log_sg_to_lli(struct scatterlist *sg,
                      int sg_len,
+                     dma_addr_t dev_addr,
                      struct d40_log_lli *lli_sg,
                      u32 lcsp13, /* src or dst*/
-                     u32 data_width,
-                     bool term_int, int max_len, int llis_per_log)
+                     u32 data_width1, u32 data_width2)
 {
        int total_size = 0;
        struct scatterlist *current_sg = sg;
        int i;
-       u32 next_lli_off = 0;
+       struct d40_log_lli *lli = lli_sg;
+       unsigned long flags = 0;
+
+       if (!dev_addr)
+               flags |= LLI_ADDR_INC;
 
        for_each_sg(sg, current_sg, sg_len, i) {
-               total_size += sg_dma_len(current_sg);
+               dma_addr_t sg_addr = sg_dma_address(current_sg);
+               unsigned int len = sg_dma_len(current_sg);
+               dma_addr_t addr = dev_addr ?: sg_addr;
 
-               /*
-                * If this scatter list entry is the last one or
-                * max length, terminate link.
-                */
-               if (sg_len - 1 == i || ((i+1) % max_len == 0))
-                       next_lli_off = 0;
-               else {
-                       if (next_lli_off == 0)
-                               /* The first lli will be at next_lli_off */
-                               next_lli_off = lcla_id * llis_per_log + 1;
-                       else
-                               next_lli_off++;
-               }
+               total_size += sg_dma_len(current_sg);
 
-               d40_log_fill_lli(&lli_sg[i],
-                                sg_phys(current_sg),
-                                sg_dma_len(current_sg),
-                                next_lli_off,
-                                lcsp13, data_width,
-                                term_int && !next_lli_off,
-                                true);
+               lli = d40_log_buf_to_lli(lli, addr, len,
+                                        lcsp13,
+                                        data_width1,
+                                        data_width2,
+                                        flags);
        }
-       return total_size;
-}
-
-void d40_log_lli_write(struct d40_log_lli_full *lcpa,
-                      struct d40_log_lli *lcla_src,
-                      struct d40_log_lli *lcla_dst,
-                      struct d40_log_lli *lli_dst,
-                      struct d40_log_lli *lli_src,
-                      int llis_per_log)
-{
-       u32 slos;
-       u32 dlos;
-       int i;
 
-       writel(lli_src->lcsp02, &lcpa->lcsp0);
-       writel(lli_src->lcsp13, &lcpa->lcsp1);
-       writel(lli_dst->lcsp02, &lcpa->lcsp2);
-       writel(lli_dst->lcsp13, &lcpa->lcsp3);
-
-       slos = lli_src->lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
-       dlos = lli_dst->lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
-
-       for (i = 0; (i < llis_per_log) && slos && dlos; i++) {
-               writel(lli_src[i + 1].lcsp02, &lcla_src[i].lcsp02);
-               writel(lli_src[i + 1].lcsp13, &lcla_src[i].lcsp13);
-               writel(lli_dst[i + 1].lcsp02, &lcla_dst[i].lcsp02);
-               writel(lli_dst[i + 1].lcsp13, &lcla_dst[i].lcsp13);
-
-               slos = lli_src[i + 1].lcsp13 & D40_MEM_LCSP1_SLOS_MASK;
-               dlos = lli_dst[i + 1].lcsp13 & D40_MEM_LCSP3_DLOS_MASK;
-       }
+       return total_size;
 }