drivers/dma: Add export.h to ste_dma40.c
[linux-2.6.git] / drivers / dma / ste_dma40.c
index 7a4919b..13259ca 100644 (file)
@@ -1,16 +1,21 @@
 /*
- * Copyright (C) ST-Ericsson SA 2007-2010
- * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
+ * Copyright (C) Ericsson AB 2007-2008
+ * Copyright (C) ST-Ericsson SA 2008-2010
+ * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
  * License terms: GNU General Public License (GPL) version 2
  */
 
+#include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
+#include <linux/export.h>
 #include <linux/dmaengine.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/amba/bus.h>
 
 #include <plat/ste_dma40.h>
 
 
 /* Hardware requirement on LCLA alignment */
 #define LCLA_ALIGNMENT 0x40000
+
+/* Max number of links per event group */
+#define D40_LCLA_LINK_PER_EVENT_GRP 128
+#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
+
 /* Attempts before giving up to trying to get pages that are aligned */
 #define MAX_LCLA_ALLOC_ATTEMPTS 256
 
@@ -37,9 +47,6 @@
 #define D40_ALLOC_PHY          (1 << 30)
 #define D40_ALLOC_LOG_FREE     0
 
-/* Hardware designer of the block */
-#define D40_HW_DESIGNER 0x8
-
 /**
  * enum 40_command - The different commands and/or statuses.
  *
@@ -61,6 +68,7 @@ enum d40_command {
  * @base: Pointer to memory area when the pre_alloc_lli's are not large
  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
  * pre_alloc_lli is used.
+ * @dma_addr: DMA address, if mapped
  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
  * one buffer to one buffer.
@@ -68,6 +76,7 @@ enum d40_command {
 struct d40_lli_pool {
        void    *base;
        int      size;
+       dma_addr_t      dma_addr;
        /* Space for dst and src, plus an extra for padding */
        u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
 };
@@ -81,19 +90,16 @@ struct d40_lli_pool {
  * @lli_log: Same as above but for logical channels.
  * @lli_pool: The pool with two entries pre-allocated.
  * @lli_len: Number of llis of current descriptor.
- * @lli_count: Number of transfered llis.
- * @lli_tx_len: Max number of LLIs per transfer, there can be
- * many transfer for one descriptor.
+ * @lli_current: Number of transferred llis.
+ * @lcla_alloc: Number of LCLA entries allocated.
  * @txd: DMA engine struct. Used for among other things for communication
  * during a transfer.
  * @node: List entry.
  * @is_in_client_list: true if the client owns this descriptor.
- * @is_hw_linked: true if this job will automatically be continued for
  * the previous one.
  *
  * This descriptor is used for both logical and physical transfers.
  */
-
 struct d40_desc {
        /* LLI physical */
        struct d40_phy_lli_bidir         lli_phy;
@@ -102,14 +108,14 @@ struct d40_desc {
 
        struct d40_lli_pool              lli_pool;
        int                              lli_len;
-       int                              lli_count;
-       u32                              lli_tx_len;
+       int                              lli_current;
+       int                              lcla_alloc;
 
        struct dma_async_tx_descriptor   txd;
        struct list_head                 node;
 
        bool                             is_in_client_list;
-       bool                             is_hw_linked;
+       bool                             cyclic;
 };
 
 /**
@@ -121,17 +127,15 @@ struct d40_desc {
  * @pages: The number of pages needed for all physical channels.
  * Only used later for clean-up on error
  * @lock: Lock to protect the content in this struct.
- * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
- * @num_blocks: The number of entries of alloc_map. Equals to the
- * number of physical channels.
+ * @alloc_map: big map over which LCLA entry is own by which job.
  */
 struct d40_lcla_pool {
        void            *base;
+       dma_addr_t      dma_addr;
        void            *base_unaligned;
        int              pages;
        spinlock_t       lock;
-       u32             *alloc_map;
-       int              num_blocks;
+       struct d40_desc **alloc_map;
 };
 
 /**
@@ -171,15 +175,20 @@ struct d40_base;
  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
  * transfer and call client callback.
  * @client: Cliented owned descriptor list.
+ * @pending_queue: Submitted jobs, to be issued by issue_pending()
  * @active: Active descriptor.
  * @queue: Queued jobs.
+ * @prepare_queue: Prepared jobs.
  * @dma_cfg: The client configuration of this dma channel.
+ * @configured: whether the dma_cfg configuration is valid
  * @base: Pointer to the device instance struct.
  * @src_def_cfg: Default cfg register setting for src.
  * @dst_def_cfg: Default cfg register setting for dst.
  * @log_def: Default logical channel settings.
  * @lcla: Space for one dst src pair for logical channel transfers.
  * @lcpa: Pointer to dst and src lcpa settings.
+ * @runtime_addr: runtime configured address.
+ * @runtime_direction: runtime configured direction.
  *
  * This struct can either "be" a logical or a physical channel.
  */
@@ -194,15 +203,17 @@ struct d40_chan {
        struct dma_chan                  chan;
        struct tasklet_struct            tasklet;
        struct list_head                 client;
+       struct list_head                 pending_queue;
        struct list_head                 active;
        struct list_head                 queue;
+       struct list_head                 prepare_queue;
        struct stedma40_chan_cfg         dma_cfg;
+       bool                             configured;
        struct d40_base                 *base;
        /* Default register configurations */
        u32                              src_def_cfg;
        u32                              dst_def_cfg;
        struct d40_def_lcsp              log_def;
-       struct d40_lcla_elem             lcla;
        struct d40_log_lli_full         *lcpa;
        /* Runtime reconfiguration */
        dma_addr_t                      runtime_addr;
@@ -300,9 +311,37 @@ struct d40_reg_val {
        unsigned int val;
 };
 
-static int d40_pool_lli_alloc(struct d40_desc *d40d,
-                             int lli_len, bool is_log)
+static struct device *chan2dev(struct d40_chan *d40c)
+{
+       return &d40c->chan.dev->device;
+}
+
+static bool chan_is_physical(struct d40_chan *chan)
+{
+       return chan->log_num == D40_PHY_CHAN;
+}
+
+static bool chan_is_logical(struct d40_chan *chan)
+{
+       return !chan_is_physical(chan);
+}
+
+static void __iomem *chan_base(struct d40_chan *chan)
+{
+       return chan->base->virtbase + D40_DREG_PCBASE +
+              chan->phy_chan->num * D40_DREG_PCDELTA;
+}
+
+#define d40_err(dev, format, arg...)           \
+       dev_err(dev, "[%s] " format, __func__, ## arg)
+
+#define chan_err(d40c, format, arg...)         \
+       d40_err(chan2dev(d40c), format, ## arg)
+
+static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
+                             int lli_len)
 {
+       bool is_log = chan_is_logical(d40c);
        u32 align;
        void *base;
 
@@ -316,7 +355,7 @@ static int d40_pool_lli_alloc(struct d40_desc *d40d,
                d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
                d40d->lli_pool.base = NULL;
        } else {
-               d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
+               d40d->lli_pool.size = lli_len * 2 * align;
 
                base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
                d40d->lli_pool.base = base;
@@ -326,22 +365,37 @@ static int d40_pool_lli_alloc(struct d40_desc *d40d,
        }
 
        if (is_log) {
-               d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
-                                             align);
-               d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
-                                             align);
+               d40d->lli_log.src = PTR_ALIGN(base, align);
+               d40d->lli_log.dst = d40d->lli_log.src + lli_len;
+
+               d40d->lli_pool.dma_addr = 0;
        } else {
-               d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
-                                             align);
-               d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
-                                             align);
+               d40d->lli_phy.src = PTR_ALIGN(base, align);
+               d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
+
+               d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
+                                                        d40d->lli_phy.src,
+                                                        d40d->lli_pool.size,
+                                                        DMA_TO_DEVICE);
+
+               if (dma_mapping_error(d40c->base->dev,
+                                     d40d->lli_pool.dma_addr)) {
+                       kfree(d40d->lli_pool.base);
+                       d40d->lli_pool.base = NULL;
+                       d40d->lli_pool.dma_addr = 0;
+                       return -ENOMEM;
+               }
        }
 
        return 0;
 }
 
-static void d40_pool_lli_free(struct d40_desc *d40d)
+static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
 {
+       if (d40d->lli_pool.dma_addr)
+               dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
+                                d40d->lli_pool.size, DMA_TO_DEVICE);
+
        kfree(d40d->lli_pool.base);
        d40d->lli_pool.base = NULL;
        d40d->lli_pool.size = 0;
@@ -351,6 +405,67 @@ static void d40_pool_lli_free(struct d40_desc *d40d)
        d40d->lli_phy.dst = NULL;
 }
 
+static int d40_lcla_alloc_one(struct d40_chan *d40c,
+                             struct d40_desc *d40d)
+{
+       unsigned long flags;
+       int i;
+       int ret = -EINVAL;
+       int p;
+
+       spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
+
+       p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
+
+       /*
+        * Allocate both src and dst at the same time, therefore the half
+        * start on 1 since 0 can't be used since zero is used as end marker.
+        */
+       for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
+               if (!d40c->base->lcla_pool.alloc_map[p + i]) {
+                       d40c->base->lcla_pool.alloc_map[p + i] = d40d;
+                       d40d->lcla_alloc++;
+                       ret = i;
+                       break;
+               }
+       }
+
+       spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
+
+       return ret;
+}
+
+static int d40_lcla_free_all(struct d40_chan *d40c,
+                            struct d40_desc *d40d)
+{
+       unsigned long flags;
+       int i;
+       int ret = -EINVAL;
+
+       if (chan_is_physical(d40c))
+               return 0;
+
+       spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
+
+       for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
+               if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
+                                                   D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
+                       d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
+                                                       D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
+                       d40d->lcla_alloc--;
+                       if (d40d->lcla_alloc == 0) {
+                               ret = 0;
+                               break;
+                       }
+               }
+       }
+
+       spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
+
+       return ret;
+
+}
+
 static void d40_desc_remove(struct d40_desc *d40d)
 {
        list_del(&d40d->node);
@@ -358,28 +473,35 @@ static void d40_desc_remove(struct d40_desc *d40d)
 
 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 {
-       struct d40_desc *d;
-       struct d40_desc *_d;
+       struct d40_desc *desc = NULL;
 
        if (!list_empty(&d40c->client)) {
+               struct d40_desc *d;
+               struct d40_desc *_d;
+
                list_for_each_entry_safe(d, _d, &d40c->client, node)
                        if (async_tx_test_ack(&d->txd)) {
-                               d40_pool_lli_free(d);
                                d40_desc_remove(d);
+                               desc = d;
+                               memset(desc, 0, sizeof(*desc));
                                break;
                        }
-       } else {
-               d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT);
-               if (d != NULL) {
-                       memset(d, 0, sizeof(struct d40_desc));
-                       INIT_LIST_HEAD(&d->node);
-               }
        }
-       return d;
+
+       if (!desc)
+               desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
+
+       if (desc)
+               INIT_LIST_HEAD(&desc->node);
+
+       return desc;
 }
 
 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 {
+
+       d40_pool_lli_free(d40c, d40d);
+       d40_lcla_free_all(d40c, d40d);
        kmem_cache_free(d40c->base->desc_slab, d40d);
 }
 
@@ -388,6 +510,130 @@ static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
        list_add_tail(&desc->node, &d40c->active);
 }
 
+static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
+{
+       struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
+       struct d40_phy_lli *lli_src = desc->lli_phy.src;
+       void __iomem *base = chan_base(chan);
+
+       writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
+       writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
+       writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
+       writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
+
+       writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
+       writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
+       writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
+       writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
+}
+
+static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
+{
+       struct d40_lcla_pool *pool = &chan->base->lcla_pool;
+       struct d40_log_lli_bidir *lli = &desc->lli_log;
+       int lli_current = desc->lli_current;
+       int lli_len = desc->lli_len;
+       bool cyclic = desc->cyclic;
+       int curr_lcla = -EINVAL;
+       int first_lcla = 0;
+       bool linkback;
+
+       /*
+        * We may have partially running cyclic transfers, in case we did't get
+        * enough LCLA entries.
+        */
+       linkback = cyclic && lli_current == 0;
+
+       /*
+        * For linkback, we need one LCLA even with only one link, because we
+        * can't link back to the one in LCPA space
+        */
+       if (linkback || (lli_len - lli_current > 1)) {
+               curr_lcla = d40_lcla_alloc_one(chan, desc);
+               first_lcla = curr_lcla;
+       }
+
+       /*
+        * For linkback, we normally load the LCPA in the loop since we need to
+        * link it to the second LCLA and not the first.  However, if we
+        * couldn't even get a first LCLA, then we have to run in LCPA and
+        * reload manually.
+        */
+       if (!linkback || curr_lcla == -EINVAL) {
+               unsigned int flags = 0;
+
+               if (curr_lcla == -EINVAL)
+                       flags |= LLI_TERM_INT;
+
+               d40_log_lli_lcpa_write(chan->lcpa,
+                                      &lli->dst[lli_current],
+                                      &lli->src[lli_current],
+                                      curr_lcla,
+                                      flags);
+               lli_current++;
+       }
+
+       if (curr_lcla < 0)
+               goto out;
+
+       for (; lli_current < lli_len; lli_current++) {
+               unsigned int lcla_offset = chan->phy_chan->num * 1024 +
+                                          8 * curr_lcla * 2;
+               struct d40_log_lli *lcla = pool->base + lcla_offset;
+               unsigned int flags = 0;
+               int next_lcla;
+
+               if (lli_current + 1 < lli_len)
+                       next_lcla = d40_lcla_alloc_one(chan, desc);
+               else
+                       next_lcla = linkback ? first_lcla : -EINVAL;
+
+               if (cyclic || next_lcla == -EINVAL)
+                       flags |= LLI_TERM_INT;
+
+               if (linkback && curr_lcla == first_lcla) {
+                       /* First link goes in both LCPA and LCLA */
+                       d40_log_lli_lcpa_write(chan->lcpa,
+                                              &lli->dst[lli_current],
+                                              &lli->src[lli_current],
+                                              next_lcla, flags);
+               }
+
+               /*
+                * One unused LCLA in the cyclic case if the very first
+                * next_lcla fails...
+                */
+               d40_log_lli_lcla_write(lcla,
+                                      &lli->dst[lli_current],
+                                      &lli->src[lli_current],
+                                      next_lcla, flags);
+
+               dma_sync_single_range_for_device(chan->base->dev,
+                                       pool->dma_addr, lcla_offset,
+                                       2 * sizeof(struct d40_log_lli),
+                                       DMA_TO_DEVICE);
+
+               curr_lcla = next_lcla;
+
+               if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
+                       lli_current++;
+                       break;
+               }
+       }
+
+out:
+       desc->lli_current = lli_current;
+}
+
+static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
+{
+       if (chan_is_physical(d40c)) {
+               d40_phy_lli_load(d40c, d40d);
+               d40d->lli_current = d40d->lli_len;
+       } else
+               d40_log_lli_to_lcxa(d40c, d40d);
+}
+
 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 {
        struct d40_desc *d;
@@ -401,93 +647,100 @@ static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
        return d;
 }
 
+/* remove desc from current queue and add it to the pending_queue */
 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 {
-       list_add_tail(&desc->node, &d40c->queue);
+       d40_desc_remove(desc);
+       desc->is_in_client_list = false;
+       list_add_tail(&desc->node, &d40c->pending_queue);
 }
 
-static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
+static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
 {
        struct d40_desc *d;
 
-       if (list_empty(&d40c->queue))
+       if (list_empty(&d40c->pending_queue))
                return NULL;
 
-       d = list_first_entry(&d40c->queue,
+       d = list_first_entry(&d40c->pending_queue,
                             struct d40_desc,
                             node);
        return d;
 }
 
-static struct d40_desc *d40_last_queued(struct d40_chan *d40c)
+static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 {
        struct d40_desc *d;
 
        if (list_empty(&d40c->queue))
                return NULL;
-       list_for_each_entry(d, &d40c->queue, node)
-               if (list_is_last(&d->node, &d40c->queue))
-                       break;
+
+       d = list_first_entry(&d40c->queue,
+                            struct d40_desc,
+                            node);
        return d;
 }
 
-/* Support functions for logical channels */
-
-static int d40_lcla_id_get(struct d40_chan *d40c)
+static int d40_psize_2_burst_size(bool is_log, int psize)
 {
-       int src_id = 0;
-       int dst_id = 0;
-       struct d40_log_lli *lcla_lidx_base =
-               d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
-       int i;
-       int lli_per_log = d40c->base->plat_data->llis_per_log;
-       unsigned long flags;
+       if (is_log) {
+               if (psize == STEDMA40_PSIZE_LOG_1)
+                       return 1;
+       } else {
+               if (psize == STEDMA40_PSIZE_PHY_1)
+                       return 1;
+       }
 
-       if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
-               return 0;
+       return 2 << psize;
+}
 
-       if (d40c->base->lcla_pool.num_blocks > 32)
-               return -EINVAL;
+/*
+ * The dma only supports transmitting packages up to
+ * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
+ * dma elements required to send the entire sg list
+ */
+static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
+{
+       int dmalen;
+       u32 max_w = max(data_width1, data_width2);
+       u32 min_w = min(data_width1, data_width2);
+       u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
 
-       spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
+       if (seg_max > STEDMA40_MAX_SEG_SIZE)
+               seg_max -= (1 << max_w);
 
-       for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
-               if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
-                     (0x1 << i))) {
-                       d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
-                               (0x1 << i);
-                       break;
-               }
-       }
-       src_id = i;
-       if (src_id >= d40c->base->lcla_pool.num_blocks)
-               goto err;
+       if (!IS_ALIGNED(size, 1 << max_w))
+               return -EINVAL;
 
-       for (; i < d40c->base->lcla_pool.num_blocks; i++) {
-               if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
-                     (0x1 << i))) {
-                       d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
-                               (0x1 << i);
-                       break;
-               }
+       if (size <= seg_max)
+               dmalen = 1;
+       else {
+               dmalen = size / seg_max;
+               if (dmalen * seg_max < size)
+                       dmalen++;
        }
+       return dmalen;
+}
 
-       dst_id = i;
-       if (dst_id == src_id)
-               goto err;
-
-       d40c->lcla.src_id = src_id;
-       d40c->lcla.dst_id = dst_id;
-       d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
-       d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
+static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
+                          u32 data_width1, u32 data_width2)
+{
+       struct scatterlist *sg;
+       int i;
+       int len = 0;
+       int ret;
 
-       spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
-       return 0;
-err:
-       spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
-       return -EINVAL;
+       for_each_sg(sgl, sg, sg_len, i) {
+               ret = d40_size_2_dmalen(sg_dma_len(sg),
+                                       data_width1, data_width2);
+               if (ret < 0)
+                       return ret;
+               len += ret;
+       }
+       return len;
 }
 
+/* Support functions for logical channels */
 
 static int d40_channel_execute_command(struct d40_chan *d40c,
                                       enum d40_command command)
@@ -539,9 +792,9 @@ static int d40_channel_execute_command(struct d40_chan *d40c,
                }
 
                if (i == D40_SUSPEND_MAX_IT) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
-                               __func__, d40c->phy_chan->num, d40c->log_num,
+                       chan_err(d40c,
+                               "unable to suspend the chl %d (log: %d) status %x\n",
+                               d40c->phy_chan->num, d40c->log_num,
                                status);
                        dump_stack();
                        ret = -EBUSY;
@@ -556,7 +809,7 @@ done:
 static void d40_term_all(struct d40_chan *d40c)
 {
        struct d40_desc *d40d;
-       unsigned long flags;
+       struct d40_desc *_d;
 
        /* Release active descriptors */
        while ((d40d = d40_first_active_get(d40c))) {
@@ -570,33 +823,70 @@ static void d40_term_all(struct d40_chan *d40c)
                d40_desc_free(d40c, d40d);
        }
 
-       spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
-
-       d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
-               (~(0x1 << d40c->lcla.dst_id));
-       d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
-               (~(0x1 << d40c->lcla.src_id));
+       /* Release pending descriptors */
+       while ((d40d = d40_first_pending(d40c))) {
+               d40_desc_remove(d40d);
+               d40_desc_free(d40c, d40d);
+       }
 
-       d40c->lcla.src_id = -1;
-       d40c->lcla.dst_id = -1;
+       /* Release client owned descriptors */
+       if (!list_empty(&d40c->client))
+               list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
+                       d40_desc_remove(d40d);
+                       d40_desc_free(d40c, d40d);
+               }
 
-       spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
+       /* Release descriptors in prepare queue */
+       if (!list_empty(&d40c->prepare_queue))
+               list_for_each_entry_safe(d40d, _d,
+                                        &d40c->prepare_queue, node) {
+                       d40_desc_remove(d40d);
+                       d40_desc_free(d40c, d40d);
+               }
 
        d40c->pending_tx = 0;
        d40c->busy = false;
 }
 
+static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
+                                  u32 event, int reg)
+{
+       void __iomem *addr = chan_base(d40c) + reg;
+       int tries;
+
+       if (!enable) {
+               writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
+                      | ~D40_EVENTLINE_MASK(event), addr);
+               return;
+       }
+
+       /*
+        * The hardware sometimes doesn't register the enable when src and dst
+        * event lines are active on the same logical channel.  Retry to ensure
+        * it does.  Usually only one retry is sufficient.
+        */
+       tries = 100;
+       while (--tries) {
+               writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
+                      | ~D40_EVENTLINE_MASK(event), addr);
+
+               if (readl(addr) & D40_EVENTLINE_MASK(event))
+                       break;
+       }
+
+       if (tries != 99)
+               dev_dbg(chan2dev(d40c),
+                       "[%s] workaround enable S%cLNK (%d tries)\n",
+                       __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
+                       100 - tries);
+
+       WARN_ON(!tries);
+}
+
 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 {
-       u32 val;
        unsigned long flags;
 
-       /* Notice, that disable requires the physical channel to be stopped */
-       if (do_enable)
-               val = D40_ACTIVATE_EVENTLINE;
-       else
-               val = D40_DEACTIVATE_EVENTLINE;
-
        spin_lock_irqsave(&d40c->phy_chan->lock, flags);
 
        /* Enable event line connected to device (or memcpy) */
@@ -604,20 +894,15 @@ static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
            (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
                u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 
-               writel((val << D40_EVENTLINE_POS(event)) |
-                      ~D40_EVENTLINE_MASK(event),
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SSLNK);
+               __d40_config_set_event(d40c, do_enable, event,
+                                      D40_CHAN_REG_SSLNK);
        }
+
        if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
                u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 
-               writel((val << D40_EVENTLINE_POS(event)) |
-                      ~D40_EVENTLINE_MASK(event),
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SDLNK);
+               __d40_config_set_event(d40c, do_enable, event,
+                                      D40_CHAN_REG_SDLNK);
        }
 
        spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
@@ -625,18 +910,40 @@ static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
 
 static u32 d40_chan_has_events(struct d40_chan *d40c)
 {
+       void __iomem *chanbase = chan_base(d40c);
        u32 val;
 
-       val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                   d40c->phy_chan->num * D40_DREG_PCDELTA +
-                   D40_CHAN_REG_SSLNK);
+       val = readl(chanbase + D40_CHAN_REG_SSLNK);
+       val |= readl(chanbase + D40_CHAN_REG_SDLNK);
 
-       val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                    d40c->phy_chan->num * D40_DREG_PCDELTA +
-                    D40_CHAN_REG_SDLNK);
        return val;
 }
 
+static u32 d40_get_prmo(struct d40_chan *d40c)
+{
+       static const unsigned int phy_map[] = {
+               [STEDMA40_PCHAN_BASIC_MODE]
+                       = D40_DREG_PRMO_PCHAN_BASIC,
+               [STEDMA40_PCHAN_MODULO_MODE]
+                       = D40_DREG_PRMO_PCHAN_MODULO,
+               [STEDMA40_PCHAN_DOUBLE_DST_MODE]
+                       = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
+       };
+       static const unsigned int log_map[] = {
+               [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
+                       = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
+               [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
+                       = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
+               [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
+                       = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
+       };
+
+       if (chan_is_physical(d40c))
+               return phy_map[d40c->dma_cfg.mode_opt];
+       else
+               return log_map[d40c->dma_cfg.mode_opt];
+}
+
 static void d40_config_write(struct d40_chan *d40c)
 {
        u32 addr_base;
@@ -645,88 +952,43 @@ static void d40_config_write(struct d40_chan *d40c)
        /* Odd addresses are even addresses + 4 */
        addr_base = (d40c->phy_chan->num % 2) * 4;
        /* Setup channel mode to logical or physical */
-       var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
+       var = ((u32)(chan_is_logical(d40c)) + 1) <<
                D40_CHAN_POS(d40c->phy_chan->num);
        writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
 
        /* Setup operational mode option register */
-       var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
-              0x3) << D40_CHAN_POS(d40c->phy_chan->num);
+       var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
 
        writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
 
-       if (d40c->log_num != D40_PHY_CHAN) {
+       if (chan_is_logical(d40c)) {
+               int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
+                          & D40_SREG_ELEM_LOG_LIDX_MASK;
+               void __iomem *chanbase = chan_base(d40c);
+
                /* Set default config for CFG reg */
-               writel(d40c->src_def_cfg,
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SSCFG);
-               writel(d40c->dst_def_cfg,
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SDCFG);
+               writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
+               writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
 
                /* Set LIDX for lcla */
-               writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
-                      D40_SREG_ELEM_LOG_LIDX_MASK,
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SDELT);
-
-               writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
-                      D40_SREG_ELEM_LOG_LIDX_MASK,
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SSELT);
-
+               writel(lidx, chanbase + D40_CHAN_REG_SSELT);
+               writel(lidx, chanbase + D40_CHAN_REG_SDELT);
        }
 }
 
-static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
-{
-       if (d40d->lli_phy.dst && d40d->lli_phy.src) {
-               d40_phy_lli_write(d40c->base->virtbase,
-                                 d40c->phy_chan->num,
-                                 d40d->lli_phy.dst,
-                                 d40d->lli_phy.src);
-       } else if (d40d->lli_log.dst && d40d->lli_log.src) {
-               struct d40_log_lli *src = d40d->lli_log.src;
-               struct d40_log_lli *dst = d40d->lli_log.dst;
-               int s;
-
-               src += d40d->lli_count;
-               dst += d40d->lli_count;
-               s = d40_log_lli_write(d40c->lcpa,
-                                     d40c->lcla.src, d40c->lcla.dst,
-                                     dst, src,
-                                     d40c->base->plat_data->llis_per_log);
-
-               /* If s equals to zero, the job is not linked */
-               if (s > 0) {
-                       (void) dma_map_single(d40c->base->dev, d40c->lcla.src,
-                                             s * sizeof(struct d40_log_lli),
-                                             DMA_TO_DEVICE);
-                       (void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
-                                             s * sizeof(struct d40_log_lli),
-                                             DMA_TO_DEVICE);
-               }
-       }
-       d40d->lli_count += d40d->lli_tx_len;
-}
-
 static u32 d40_residue(struct d40_chan *d40c)
 {
        u32 num_elt;
 
-       if (d40c->log_num != D40_PHY_CHAN)
+       if (chan_is_logical(d40c))
                num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
                        >> D40_MEM_LCSP2_ECNT_POS;
-       else
-               num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                                d40c->phy_chan->num * D40_DREG_PCDELTA +
-                                D40_CHAN_REG_SDELT) &
-                          D40_SREG_ELEM_PHY_ECNT_MASK) >>
-                       D40_SREG_ELEM_PHY_ECNT_POS;
+       else {
+               u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
+               num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
+                         >> D40_SREG_ELEM_PHY_ECNT_POS;
+       }
+
        return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
 }
 
@@ -734,28 +996,28 @@ static bool d40_tx_is_linked(struct d40_chan *d40c)
 {
        bool is_link;
 
-       if (d40c->log_num != D40_PHY_CHAN)
+       if (chan_is_logical(d40c))
                is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
        else
-               is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                               d40c->phy_chan->num * D40_DREG_PCDELTA +
-                               D40_CHAN_REG_SDLNK) &
-                       D40_SREG_LNK_PHYS_LNK_MASK;
+               is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
+                         & D40_SREG_LNK_PHYS_LNK_MASK;
+
        return is_link;
 }
 
-static int d40_pause(struct dma_chan *chan)
+static int d40_pause(struct d40_chan *d40c)
 {
-       struct d40_chan *d40c =
-               container_of(chan, struct d40_chan, chan);
        int res = 0;
        unsigned long flags;
 
+       if (!d40c->busy)
+               return 0;
+
        spin_lock_irqsave(&d40c->lock, flags);
 
        res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
        if (res == 0) {
-               if (d40c->log_num != D40_PHY_CHAN) {
+               if (chan_is_logical(d40c)) {
                        d40_config_set_event(d40c, false);
                        /* Resume the other logical channels if any */
                        if (d40_chan_has_events(d40c))
@@ -768,17 +1030,18 @@ static int d40_pause(struct dma_chan *chan)
        return res;
 }
 
-static int d40_resume(struct dma_chan *chan)
+static int d40_resume(struct d40_chan *d40c)
 {
-       struct d40_chan *d40c =
-               container_of(chan, struct d40_chan, chan);
        int res = 0;
        unsigned long flags;
 
+       if (!d40c->busy)
+               return 0;
+
        spin_lock_irqsave(&d40c->lock, flags);
 
        if (d40c->base->rev == 0)
-               if (d40c->log_num != D40_PHY_CHAN) {
+               if (chan_is_logical(d40c)) {
                        res = d40_channel_execute_command(d40c,
                                                          D40_DMA_SUSPEND_REQ);
                        goto no_suspend;
@@ -787,7 +1050,7 @@ static int d40_resume(struct dma_chan *chan)
        /* If bytes left to transfer or linked tx resume job */
        if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
 
-               if (d40c->log_num != D40_PHY_CHAN)
+               if (chan_is_logical(d40c))
                        d40_config_set_event(d40c, true);
 
                res = d40_channel_execute_command(d40c, D40_DMA_RUN);
@@ -798,75 +1061,20 @@ no_suspend:
        return res;
 }
 
-static void d40_tx_submit_log(struct d40_chan *d40c, struct d40_desc *d40d)
-{
-       /* TODO: Write */
-}
-
-static void d40_tx_submit_phy(struct d40_chan *d40c, struct d40_desc *d40d)
+static int d40_terminate_all(struct d40_chan *chan)
 {
-       struct d40_desc *d40d_prev = NULL;
-       int i;
-       u32 val;
-
-       if (!list_empty(&d40c->queue))
-               d40d_prev = d40_last_queued(d40c);
-       else if (!list_empty(&d40c->active))
-               d40d_prev = d40_first_active_get(d40c);
-
-       if (!d40d_prev)
-               return;
-
-       /* Here we try to join this job with previous jobs */
-       val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                   d40c->phy_chan->num * D40_DREG_PCDELTA +
-                   D40_CHAN_REG_SSLNK);
-
-       /* Figure out which link we're currently transmitting */
-       for (i = 0; i < d40d_prev->lli_len; i++)
-               if (val == d40d_prev->lli_phy.src[i].reg_lnk)
-                       break;
-
-       val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
-                   d40c->phy_chan->num * D40_DREG_PCDELTA +
-                   D40_CHAN_REG_SSELT) >> D40_SREG_ELEM_LOG_ECNT_POS;
-
-       if (i == (d40d_prev->lli_len - 1) && val > 0) {
-               /* Change the current one */
-               writel(virt_to_phys(d40d->lli_phy.src),
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SSLNK);
-               writel(virt_to_phys(d40d->lli_phy.dst),
-                      d40c->base->virtbase + D40_DREG_PCBASE +
-                      d40c->phy_chan->num * D40_DREG_PCDELTA +
-                      D40_CHAN_REG_SDLNK);
-
-               d40d->is_hw_linked = true;
-
-       } else if (i < d40d_prev->lli_len) {
-               (void) dma_unmap_single(d40c->base->dev,
-                                       virt_to_phys(d40d_prev->lli_phy.src),
-                                       d40d_prev->lli_pool.size,
-                                       DMA_TO_DEVICE);
+       unsigned long flags;
+       int ret = 0;
 
-               /* Keep the settings */
-               val = d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk &
-                       ~D40_SREG_LNK_PHYS_LNK_MASK;
-               d40d_prev->lli_phy.src[d40d_prev->lli_len - 1].reg_lnk =
-                       val | virt_to_phys(d40d->lli_phy.src);
+       ret = d40_pause(chan);
+       if (!ret && chan_is_physical(chan))
+               ret = d40_channel_execute_command(chan, D40_DMA_STOP);
 
-               val = d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk &
-                       ~D40_SREG_LNK_PHYS_LNK_MASK;
-               d40d_prev->lli_phy.dst[d40d_prev->lli_len - 1].reg_lnk =
-                       val | virt_to_phys(d40d->lli_phy.dst);
+       spin_lock_irqsave(&chan->lock, flags);
+       d40_term_all(chan);
+       spin_unlock_irqrestore(&chan->lock, flags);
 
-               (void) dma_map_single(d40c->base->dev,
-                                     d40d_prev->lli_phy.src,
-                                     d40d_prev->lli_pool.size,
-                                     DMA_TO_DEVICE);
-               d40d->is_hw_linked = true;
-       }
+       return ret;
 }
 
 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
@@ -877,8 +1085,6 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
        struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
        unsigned long flags;
 
-       (void) d40_pause(&d40c->chan);
-
        spin_lock_irqsave(&d40c->lock, flags);
 
        d40c->chan.cookie++;
@@ -888,17 +1094,10 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 
        d40d->txd.cookie = d40c->chan.cookie;
 
-       if (d40c->log_num == D40_PHY_CHAN)
-               d40_tx_submit_phy(d40c, d40d);
-       else
-               d40_tx_submit_log(d40c, d40d);
-
        d40_desc_queue(d40c, d40d);
 
        spin_unlock_irqrestore(&d40c->lock, flags);
 
-       (void) d40_resume(&d40c->chan);
-
        return tx->cookie;
 }
 
@@ -907,7 +1106,7 @@ static int d40_start(struct d40_chan *d40c)
        if (d40c->base->rev == 0) {
                int err;
 
-               if (d40c->log_num != D40_PHY_CHAN) {
+               if (chan_is_logical(d40c)) {
                        err = d40_channel_execute_command(d40c,
                                                          D40_DMA_SUSPEND_REQ);
                        if (err)
@@ -915,7 +1114,7 @@ static int d40_start(struct d40_chan *d40c)
                }
        }
 
-       if (d40c->log_num != D40_PHY_CHAN)
+       if (chan_is_logical(d40c))
                d40_config_set_event(d40c, true);
 
        return d40_channel_execute_command(d40c, D40_DMA_RUN);
@@ -938,20 +1137,14 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
                /* Add to active queue */
                d40_desc_submit(d40c, d40d);
 
-               /*
-                * If this job is already linked in hw,
-                * do not submit it.
-                */
-               if (!d40d->is_hw_linked) {
-                       /* Initiate DMA job */
-                       d40_desc_load(d40c, d40d);
+               /* Initiate DMA job */
+               d40_desc_load(d40c, d40d);
 
-                       /* Start dma job */
-                       err = d40_start(d40c);
+               /* Start dma job */
+               err = d40_start(d40c);
 
-                       if (err)
-                               return NULL;
-               }
+               if (err)
+                       return NULL;
        }
 
        return d40d;
@@ -968,16 +1161,36 @@ static void dma_tc_handle(struct d40_chan *d40c)
        if (d40d == NULL)
                return;
 
-       if (d40d->lli_count < d40d->lli_len) {
+       if (d40d->cyclic) {
+               /*
+                * If this was a paritially loaded list, we need to reloaded
+                * it, and only when the list is completed.  We need to check
+                * for done because the interrupt will hit for every link, and
+                * not just the last one.
+                */
+               if (d40d->lli_current < d40d->lli_len
+                   && !d40_tx_is_linked(d40c)
+                   && !d40_residue(d40c)) {
+                       d40_lcla_free_all(d40c, d40d);
+                       d40_desc_load(d40c, d40d);
+                       (void) d40_start(d40c);
 
-               d40_desc_load(d40c, d40d);
-               /* Start dma job */
-               (void) d40_start(d40c);
-               return;
-       }
+                       if (d40d->lli_current == d40d->lli_len)
+                               d40d->lli_current = 0;
+               }
+       } else {
+               d40_lcla_free_all(d40c, d40d);
 
-       if (d40_queue_start(d40c) == NULL)
-               d40c->busy = false;
+               if (d40d->lli_current < d40d->lli_len) {
+                       d40_desc_load(d40c, d40d);
+                       /* Start dma job */
+                       (void) d40_start(d40c);
+                       return;
+               }
+
+               if (d40_queue_start(d40c) == NULL)
+                       d40c->busy = false;
+       }
 
        d40c->pending_tx++;
        tasklet_schedule(&d40c->tasklet);
@@ -996,11 +1209,11 @@ static void dma_tasklet(unsigned long data)
 
        /* Get first active entry from list */
        d40d = d40_first_active_get(d40c);
-
        if (d40d == NULL)
                goto err;
 
-       d40c->completed = d40d->txd.cookie;
+       if (!d40d->cyclic)
+               d40c->completed = d40d->txd.cookie;
 
        /*
         * If terminating a channel pending_tx is set to zero.
@@ -1015,15 +1228,17 @@ static void dma_tasklet(unsigned long data)
        callback = d40d->txd.callback;
        callback_param = d40d->txd.callback_param;
 
-       if (async_tx_test_ack(&d40d->txd)) {
-               d40_pool_lli_free(d40d);
-               d40_desc_remove(d40d);
-               d40_desc_free(d40c, d40d);
-       } else {
-               if (!d40d->is_in_client_list) {
+       if (!d40d->cyclic) {
+               if (async_tx_test_ack(&d40d->txd)) {
                        d40_desc_remove(d40d);
-                       list_add_tail(&d40d->node, &d40c->client);
-                       d40d->is_in_client_list = true;
+                       d40_desc_free(d40c, d40d);
+               } else {
+                       if (!d40d->is_in_client_list) {
+                               d40_desc_remove(d40d);
+                               d40_lcla_free_all(d40c, d40d);
+                               list_add_tail(&d40d->node, &d40c->client);
+                               d40d->is_in_client_list = true;
+                       }
                }
        }
 
@@ -1040,7 +1255,7 @@ static void dma_tasklet(unsigned long data)
        return;
 
  err:
-       /* Rescue manouver if receiving double interrupts */
+       /* Rescue manoeuvre if receiving double interrupts */
        if (d40c->pending_tx > 0)
                d40c->pending_tx--;
        spin_unlock_irqrestore(&d40c->lock, flags);
@@ -1100,9 +1315,8 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data)
                if (!il[row].is_error)
                        dma_tc_handle(d40c);
                else
-                       dev_err(base->dev,
-                               "[%s] IRQ chan: %ld offset %d idx %d\n",
-                               __func__, chan, il[row].offset, idx);
+                       d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
+                               chan, il[row].offset, idx);
 
                spin_unlock(&d40c->lock);
        }
@@ -1118,12 +1332,10 @@ static int d40_validate_conf(struct d40_chan *d40c,
        int res = 0;
        u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
        u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
-       bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
-               == STEDMA40_CHANNEL_IN_LOG_MODE;
+       bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
 
        if (!conf->dir) {
-               dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
-                       __func__);
+               chan_err(d40c, "Invalid direction.\n");
                res = -EINVAL;
        }
 
@@ -1131,46 +1343,40 @@ static int d40_validate_conf(struct d40_chan *d40c,
            d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
            d40c->runtime_addr == 0) {
 
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Invalid TX channel address (%d)\n",
-                       __func__, conf->dst_dev_type);
+               chan_err(d40c, "Invalid TX channel address (%d)\n",
+                        conf->dst_dev_type);
                res = -EINVAL;
        }
 
        if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
            d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
            d40c->runtime_addr == 0) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Invalid RX channel address (%d)\n",
-                       __func__, conf->src_dev_type);
+               chan_err(d40c, "Invalid RX channel address (%d)\n",
+                       conf->src_dev_type);
                res = -EINVAL;
        }
 
        if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
            dst_event_group == STEDMA40_DEV_DST_MEMORY) {
-               dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
-                       __func__);
+               chan_err(d40c, "Invalid dst\n");
                res = -EINVAL;
        }
 
        if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
            src_event_group == STEDMA40_DEV_SRC_MEMORY) {
-               dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
-                       __func__);
+               chan_err(d40c, "Invalid src\n");
                res = -EINVAL;
        }
 
        if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
            dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] No event line\n", __func__);
+               chan_err(d40c, "No event line\n");
                res = -EINVAL;
        }
 
        if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
            (src_event_group != dst_event_group)) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Invalid event group\n", __func__);
+               chan_err(d40c, "Invalid event group\n");
                res = -EINVAL;
        }
 
@@ -1179,9 +1385,20 @@ static int d40_validate_conf(struct d40_chan *d40c,
                 * DMAC HW supports it. Will be added to this driver,
                 * in case any dma client requires it.
                 */
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] periph to periph not supported\n",
-                       __func__);
+               chan_err(d40c, "periph to periph not supported\n");
+               res = -EINVAL;
+       }
+
+       if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
+           (1 << conf->src_info.data_width) !=
+           d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
+           (1 << conf->dst_info.data_width)) {
+               /*
+                * The DMAC hardware only supports
+                * src (burst x width) == dst (burst x width)
+                */
+
+               chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
                res = -EINVAL;
        }
 
@@ -1247,7 +1464,6 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
 
        spin_lock_irqsave(&phy->lock, flags);
        if (!log_event_line) {
-               /* Physical interrupts are masked per physical full channel */
                phy->allocated_dst = D40_ALLOC_FREE;
                phy->allocated_src = D40_ALLOC_FREE;
                is_free = true;
@@ -1284,10 +1500,7 @@ static int d40_allocate_channel(struct d40_chan *d40c)
        int j;
        int log_num;
        bool is_src;
-       bool is_log = (d40c->dma_cfg.channel_type &
-                      STEDMA40_CHANNEL_IN_OPER_MODE)
-               == STEDMA40_CHANNEL_IN_LOG_MODE;
-
+       bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
 
        phys = d40c->base->phy_res;
 
@@ -1388,8 +1601,7 @@ static int d40_config_memcpy(struct d40_chan *d40c)
                   dma_has_cap(DMA_SLAVE, cap)) {
                d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
        } else {
-               dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
-                       __func__);
+               chan_err(d40c, "No memcpy\n");
                return -EINVAL;
        }
 
@@ -1404,31 +1616,18 @@ static int d40_free_dma(struct d40_chan *d40c)
        u32 event;
        struct d40_phy_res *phy = d40c->phy_chan;
        bool is_src;
-       struct d40_desc *d;
-       struct d40_desc *_d;
-
 
        /* Terminate all queued and active transfers */
        d40_term_all(d40c);
 
-       /* Release client owned descriptors */
-       if (!list_empty(&d40c->client))
-               list_for_each_entry_safe(d, _d, &d40c->client, node) {
-                       d40_pool_lli_free(d);
-                       d40_desc_remove(d);
-                       d40_desc_free(d40c, d);
-               }
-
        if (phy == NULL) {
-               dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
-                       __func__);
+               chan_err(d40c, "phy == null\n");
                return -EINVAL;
        }
 
        if (phy->allocated_src == D40_ALLOC_FREE &&
            phy->allocated_dst == D40_ALLOC_FREE) {
-               dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
-                       __func__);
+               chan_err(d40c, "channel already free\n");
                return -EINVAL;
        }
 
@@ -1440,19 +1639,17 @@ static int d40_free_dma(struct d40_chan *d40c)
                event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
                is_src = true;
        } else {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Unknown direction\n", __func__);
+               chan_err(d40c, "Unknown direction\n");
                return -EINVAL;
        }
 
        res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
        if (res) {
-               dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
-                       __func__);
+               chan_err(d40c, "suspend failed\n");
                return res;
        }
 
-       if (d40c->log_num != D40_PHY_CHAN) {
+       if (chan_is_logical(d40c)) {
                /* Release logical channel, deactivate the event line */
 
                d40_config_set_event(d40c, false);
@@ -1468,9 +1665,8 @@ static int d40_free_dma(struct d40_chan *d40c)
                                res = d40_channel_execute_command(d40c,
                                                                  D40_DMA_RUN);
                                if (res) {
-                                       dev_err(&d40c->chan.dev->device,
-                                               "[%s] Executing RUN command\n",
-                                               __func__);
+                                       chan_err(d40c,
+                                               "Executing RUN command\n");
                                        return res;
                                }
                        }
@@ -1483,13 +1679,11 @@ static int d40_free_dma(struct d40_chan *d40c)
        /* Release physical channel */
        res = d40_channel_execute_command(d40c, D40_DMA_STOP);
        if (res) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Failed to stop channel\n", __func__);
+               chan_err(d40c, "Failed to stop channel\n");
                return res;
        }
        d40c->phy_chan = NULL;
-       /* Invalidate channel type */
-       d40c->dma_cfg.channel_type = 0;
+       d40c->configured = false;
        d40c->base->lookup_phy_chans[phy->num] = NULL;
 
        return 0;
@@ -1497,6 +1691,7 @@ static int d40_free_dma(struct d40_chan *d40c)
 
 static bool d40_is_paused(struct d40_chan *d40c)
 {
+       void __iomem *chanbase = chan_base(d40c);
        bool is_paused = false;
        unsigned long flags;
        void __iomem *active_reg;
@@ -1505,7 +1700,7 @@ static bool d40_is_paused(struct d40_chan *d40c)
 
        spin_lock_irqsave(&d40c->lock, flags);
 
-       if (d40c->log_num == D40_PHY_CHAN) {
+       if (chan_is_physical(d40c)) {
                if (d40c->phy_chan->num % 2 == 0)
                        active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
                else
@@ -1521,16 +1716,17 @@ static bool d40_is_paused(struct d40_chan *d40c)
        }
 
        if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
-           d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
+           d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
                event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
-       else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+               status = readl(chanbase + D40_CHAN_REG_SDLNK);
+       } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
                event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
-       else {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Unknown direction\n", __func__);
+               status = readl(chanbase + D40_CHAN_REG_SSLNK);
+       } else {
+               chan_err(d40c, "Unknown direction\n");
                goto _exit;
        }
-       status = d40_chan_has_events(d40c);
+
        status = (status & D40_EVENTLINE_MASK(event)) >>
                D40_EVENTLINE_POS(event);
 
@@ -1557,164 +1753,190 @@ static u32 stedma40_residue(struct dma_chan *chan)
        return bytes_left;
 }
 
-/* Public DMA functions in addition to the DMA engine framework */
+static int
+d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
+               struct scatterlist *sg_src, struct scatterlist *sg_dst,
+               unsigned int sg_len, dma_addr_t src_dev_addr,
+               dma_addr_t dst_dev_addr)
+{
+       struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
+       struct stedma40_half_channel_info *src_info = &cfg->src_info;
+       struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
+       int ret;
+
+       ret = d40_log_sg_to_lli(sg_src, sg_len,
+                               src_dev_addr,
+                               desc->lli_log.src,
+                               chan->log_def.lcsp1,
+                               src_info->data_width,
+                               dst_info->data_width);
+
+       ret = d40_log_sg_to_lli(sg_dst, sg_len,
+                               dst_dev_addr,
+                               desc->lli_log.dst,
+                               chan->log_def.lcsp3,
+                               dst_info->data_width,
+                               src_info->data_width);
+
+       return ret < 0 ? ret : 0;
+}
 
-int stedma40_set_psize(struct dma_chan *chan,
-                      int src_psize,
-                      int dst_psize)
+static int
+d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
+               struct scatterlist *sg_src, struct scatterlist *sg_dst,
+               unsigned int sg_len, dma_addr_t src_dev_addr,
+               dma_addr_t dst_dev_addr)
 {
-       struct d40_chan *d40c =
-               container_of(chan, struct d40_chan, chan);
-       unsigned long flags;
+       struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
+       struct stedma40_half_channel_info *src_info = &cfg->src_info;
+       struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
+       unsigned long flags = 0;
+       int ret;
 
-       spin_lock_irqsave(&d40c->lock, flags);
+       if (desc->cyclic)
+               flags |= LLI_CYCLIC | LLI_TERM_INT;
 
-       if (d40c->log_num != D40_PHY_CHAN) {
-               d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
-               d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
-               d40c->log_def.lcsp1 |= src_psize <<
-                       D40_MEM_LCSP1_SCFG_PSIZE_POS;
-               d40c->log_def.lcsp3 |= dst_psize <<
-                       D40_MEM_LCSP1_SCFG_PSIZE_POS;
-               goto out;
-       }
+       ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
+                               desc->lli_phy.src,
+                               virt_to_phys(desc->lli_phy.src),
+                               chan->src_def_cfg,
+                               src_info, dst_info, flags);
 
-       if (src_psize == STEDMA40_PSIZE_PHY_1)
-               d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
-       else {
-               d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-               d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
-                                      D40_SREG_CFG_PSIZE_POS);
-               d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS;
-       }
+       ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
+                               desc->lli_phy.dst,
+                               virt_to_phys(desc->lli_phy.dst),
+                               chan->dst_def_cfg,
+                               dst_info, src_info, flags);
 
-       if (dst_psize == STEDMA40_PSIZE_PHY_1)
-               d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
-       else {
-               d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
-               d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
-                                      D40_SREG_CFG_PSIZE_POS);
-               d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
-       }
-out:
-       spin_unlock_irqrestore(&d40c->lock, flags);
-       return 0;
+       dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
+                                  desc->lli_pool.size, DMA_TO_DEVICE);
+
+       return ret < 0 ? ret : 0;
 }
-EXPORT_SYMBOL(stedma40_set_psize);
 
-struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
-                                                  struct scatterlist *sgl_dst,
-                                                  struct scatterlist *sgl_src,
-                                                  unsigned int sgl_len,
-                                                  unsigned long dma_flags)
+
+static struct d40_desc *
+d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
+             unsigned int sg_len, unsigned long dma_flags)
 {
-       int res;
-       struct d40_desc *d40d;
-       struct d40_chan *d40c = container_of(chan, struct d40_chan,
-                                            chan);
-       unsigned long flags;
+       struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
+       struct d40_desc *desc;
+       int ret;
 
-       if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Unallocated channel.\n", __func__);
-               return ERR_PTR(-EINVAL);
-       }
+       desc = d40_desc_get(chan);
+       if (!desc)
+               return NULL;
 
-       spin_lock_irqsave(&d40c->lock, flags);
-       d40d = d40_desc_get(d40c);
+       desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
+                                       cfg->dst_info.data_width);
+       if (desc->lli_len < 0) {
+               chan_err(chan, "Unaligned size\n");
+               goto err;
+       }
 
-       if (d40d == NULL)
+       ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
+       if (ret < 0) {
+               chan_err(chan, "Could not allocate lli\n");
                goto err;
+       }
 
-       d40d->lli_len = sgl_len;
-       d40d->lli_tx_len = d40d->lli_len;
-       d40d->txd.flags = dma_flags;
 
-       if (d40c->log_num != D40_PHY_CHAN) {
-               if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
-                       d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
+       desc->lli_current = 0;
+       desc->txd.flags = dma_flags;
+       desc->txd.tx_submit = d40_tx_submit;
 
-               if (sgl_len > 1)
-                       /*
-                        * Check if there is space available in lcla. If not,
-                        * split list into 1-length and run only in lcpa
-                        * space.
-                        */
-                       if (d40_lcla_id_get(d40c) != 0)
-                               d40d->lli_tx_len = 1;
+       dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
 
-               if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s] Out of memory\n", __func__);
-                       goto err;
-               }
+       return desc;
 
-               (void) d40_log_sg_to_lli(d40c->lcla.src_id,
-                                        sgl_src,
-                                        sgl_len,
-                                        d40d->lli_log.src,
-                                        d40c->log_def.lcsp1,
-                                        d40c->dma_cfg.src_info.data_width,
-                                        d40d->lli_tx_len,
-                                        d40c->base->plat_data->llis_per_log);
-
-               (void) d40_log_sg_to_lli(d40c->lcla.dst_id,
-                                        sgl_dst,
-                                        sgl_len,
-                                        d40d->lli_log.dst,
-                                        d40c->log_def.lcsp3,
-                                        d40c->dma_cfg.dst_info.data_width,
-                                        d40d->lli_tx_len,
-                                        d40c->base->plat_data->llis_per_log);
+err:
+       d40_desc_free(chan, desc);
+       return NULL;
+}
 
+static dma_addr_t
+d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
+{
+       struct stedma40_platform_data *plat = chan->base->plat_data;
+       struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
+       dma_addr_t addr = 0;
 
-       } else {
-               if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s] Out of memory\n", __func__);
-                       goto err;
-               }
+       if (chan->runtime_addr)
+               return chan->runtime_addr;
 
-               res = d40_phy_sg_to_lli(sgl_src,
-                                       sgl_len,
-                                       0,
-                                       d40d->lli_phy.src,
-                                       virt_to_phys(d40d->lli_phy.src),
-                                       d40c->src_def_cfg,
-                                       d40c->dma_cfg.src_info.data_width,
-                                       d40c->dma_cfg.src_info.psize);
+       if (direction == DMA_FROM_DEVICE)
+               addr = plat->dev_rx[cfg->src_dev_type];
+       else if (direction == DMA_TO_DEVICE)
+               addr = plat->dev_tx[cfg->dst_dev_type];
 
-               if (res < 0)
-                       goto err;
+       return addr;
+}
 
-               res = d40_phy_sg_to_lli(sgl_dst,
-                                       sgl_len,
-                                       0,
-                                       d40d->lli_phy.dst,
-                                       virt_to_phys(d40d->lli_phy.dst),
-                                       d40c->dst_def_cfg,
-                                       d40c->dma_cfg.dst_info.data_width,
-                                       d40c->dma_cfg.dst_info.psize);
+static struct dma_async_tx_descriptor *
+d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
+           struct scatterlist *sg_dst, unsigned int sg_len,
+           enum dma_data_direction direction, unsigned long dma_flags)
+{
+       struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
+       dma_addr_t src_dev_addr = 0;
+       dma_addr_t dst_dev_addr = 0;
+       struct d40_desc *desc;
+       unsigned long flags;
+       int ret;
 
-               if (res < 0)
-                       goto err;
+       if (!chan->phy_chan) {
+               chan_err(chan, "Cannot prepare unallocated channel\n");
+               return NULL;
+       }
+
+
+       spin_lock_irqsave(&chan->lock, flags);
+
+       desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
+       if (desc == NULL)
+               goto err;
 
-               (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
-                                     d40d->lli_pool.size, DMA_TO_DEVICE);
+       if (sg_next(&sg_src[sg_len - 1]) == sg_src)
+               desc->cyclic = true;
+
+       if (direction != DMA_NONE) {
+               dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
+
+               if (direction == DMA_FROM_DEVICE)
+                       src_dev_addr = dev_addr;
+               else if (direction == DMA_TO_DEVICE)
+                       dst_dev_addr = dev_addr;
        }
 
-       dma_async_tx_descriptor_init(&d40d->txd, chan);
+       if (chan_is_logical(chan))
+               ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
+                                     sg_len, src_dev_addr, dst_dev_addr);
+       else
+               ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
+                                     sg_len, src_dev_addr, dst_dev_addr);
 
-       d40d->txd.tx_submit = d40_tx_submit;
+       if (ret) {
+               chan_err(chan, "Failed to prepare %s sg job: %d\n",
+                        chan_is_logical(chan) ? "log" : "phy", ret);
+               goto err;
+       }
 
-       spin_unlock_irqrestore(&d40c->lock, flags);
+       /*
+        * add descriptor to the prepare queue in order to be able
+        * to free them later in terminate_all
+        */
+       list_add_tail(&desc->node, &chan->prepare_queue);
+
+       spin_unlock_irqrestore(&chan->lock, flags);
+
+       return &desc->txd;
 
-       return &d40d->txd;
 err:
-       spin_unlock_irqrestore(&d40c->lock, flags);
+       if (desc)
+               d40_desc_free(chan, desc);
+       spin_unlock_irqrestore(&chan->lock, flags);
        return NULL;
 }
-EXPORT_SYMBOL(stedma40_memcpy_sg);
 
 bool stedma40_filter(struct dma_chan *chan, void *data)
 {
@@ -1730,10 +1952,45 @@ bool stedma40_filter(struct dma_chan *chan, void *data)
        } else
                err = d40_config_memcpy(d40c);
 
+       if (!err)
+               d40c->configured = true;
+
        return err == 0;
 }
 EXPORT_SYMBOL(stedma40_filter);
 
+static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
+{
+       bool realtime = d40c->dma_cfg.realtime;
+       bool highprio = d40c->dma_cfg.high_priority;
+       u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
+       u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
+       u32 event = D40_TYPE_TO_EVENT(dev_type);
+       u32 group = D40_TYPE_TO_GROUP(dev_type);
+       u32 bit = 1 << event;
+
+       /* Destination event lines are stored in the upper halfword */
+       if (!src)
+               bit <<= 16;
+
+       writel(bit, d40c->base->virtbase + prioreg + group * 4);
+       writel(bit, d40c->base->virtbase + rtreg + group * 4);
+}
+
+static void d40_set_prio_realtime(struct d40_chan *d40c)
+{
+       if (d40c->base->rev < 3)
+               return;
+
+       if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
+           (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+               __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
+
+       if ((d40c->dma_cfg.dir ==  STEDMA40_MEM_TO_PERIPH) ||
+           (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+               __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
+}
+
 /* DMA ENGINE functions */
 static int d40_alloc_chan_resources(struct dma_chan *chan)
 {
@@ -1746,17 +2003,11 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 
        d40c->completed = chan->cookie = 1;
 
-       /*
-        * If no dma configuration is set (channel_type == 0)
-        * use default configuration (memcpy)
-        */
-       if (d40c->dma_cfg.channel_type == 0) {
-
+       /* If no dma configuration is set use default configuration (memcpy) */
+       if (!d40c->configured) {
                err = d40_config_memcpy(d40c);
                if (err) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s] Failed to configure memcpy channel\n",
-                               __func__);
+                       chan_err(d40c, "Failed to configure memcpy channel\n");
                        goto fail;
                }
        }
@@ -1764,16 +2015,17 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
 
        err = d40_allocate_channel(d40c);
        if (err) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Failed to allocate channel\n", __func__);
+               chan_err(d40c, "Failed to allocate channel\n");
                goto fail;
        }
 
        /* Fill in basic CFG register values */
        d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
-                   &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
+                   &d40c->dst_def_cfg, chan_is_logical(d40c));
 
-       if (d40c->log_num != D40_PHY_CHAN) {
+       d40_set_prio_realtime(d40c);
+
+       if (chan_is_logical(d40c)) {
                d40_log_cfg(&d40c->dma_cfg,
                            &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
 
@@ -1806,8 +2058,7 @@ static void d40_free_chan_resources(struct dma_chan *chan)
        unsigned long flags;
 
        if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Cannot free unallocated channel\n", __func__);
+               chan_err(d40c, "Cannot free unallocated channel\n");
                return;
        }
 
@@ -1817,8 +2068,7 @@ static void d40_free_chan_resources(struct dma_chan *chan)
        err = d40_free_dma(d40c);
 
        if (err)
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Failed to free channel\n", __func__);
+               chan_err(d40c, "Failed to free channel\n");
        spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
@@ -1828,229 +2078,31 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
                                                       size_t size,
                                                       unsigned long dma_flags)
 {
-       struct d40_desc *d40d;
-       struct d40_chan *d40c = container_of(chan, struct d40_chan,
-                                            chan);
-       unsigned long flags;
-       int err = 0;
-
-       if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Channel is not allocated.\n", __func__);
-               return ERR_PTR(-EINVAL);
-       }
-
-       spin_lock_irqsave(&d40c->lock, flags);
-       d40d = d40_desc_get(d40c);
-
-       if (d40d == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Descriptor is NULL\n", __func__);
-               goto err;
-       }
-
-       d40d->txd.flags = dma_flags;
-
-       dma_async_tx_descriptor_init(&d40d->txd, chan);
-
-       d40d->txd.tx_submit = d40_tx_submit;
-
-       if (d40c->log_num != D40_PHY_CHAN) {
-
-               if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s] Out of memory\n", __func__);
-                       goto err;
-               }
-               d40d->lli_len = 1;
-               d40d->lli_tx_len = 1;
-
-               d40_log_fill_lli(d40d->lli_log.src,
-                                src,
-                                size,
-                                0,
-                                d40c->log_def.lcsp1,
-                                d40c->dma_cfg.src_info.data_width,
-                                false, true);
-
-               d40_log_fill_lli(d40d->lli_log.dst,
-                                dst,
-                                size,
-                                0,
-                                d40c->log_def.lcsp3,
-                                d40c->dma_cfg.dst_info.data_width,
-                                true, true);
-
-       } else {
-
-               if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
-                       dev_err(&d40c->chan.dev->device,
-                               "[%s] Out of memory\n", __func__);
-                       goto err;
-               }
-
-               err = d40_phy_fill_lli(d40d->lli_phy.src,
-                                      src,
-                                      size,
-                                      d40c->dma_cfg.src_info.psize,
-                                      0,
-                                      d40c->src_def_cfg,
-                                      true,
-                                      d40c->dma_cfg.src_info.data_width,
-                                      false);
-               if (err)
-                       goto err_fill_lli;
-
-               err = d40_phy_fill_lli(d40d->lli_phy.dst,
-                                      dst,
-                                      size,
-                                      d40c->dma_cfg.dst_info.psize,
-                                      0,
-                                      d40c->dst_def_cfg,
-                                      true,
-                                      d40c->dma_cfg.dst_info.data_width,
-                                      false);
-
-               if (err)
-                       goto err_fill_lli;
-
-               (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
-                                     d40d->lli_pool.size, DMA_TO_DEVICE);
-       }
-
-       spin_unlock_irqrestore(&d40c->lock, flags);
-       return &d40d->txd;
-
-err_fill_lli:
-       dev_err(&d40c->chan.dev->device,
-               "[%s] Failed filling in PHY LLI\n", __func__);
-       d40_pool_lli_free(d40d);
-err:
-       spin_unlock_irqrestore(&d40c->lock, flags);
-       return NULL;
-}
-
-static int d40_prep_slave_sg_log(struct d40_desc *d40d,
-                                struct d40_chan *d40c,
-                                struct scatterlist *sgl,
-                                unsigned int sg_len,
-                                enum dma_data_direction direction,
-                                unsigned long dma_flags)
-{
-       dma_addr_t dev_addr = 0;
-       int total_size;
+       struct scatterlist dst_sg;
+       struct scatterlist src_sg;
 
-       if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Out of memory\n", __func__);
-               return -ENOMEM;
-       }
+       sg_init_table(&dst_sg, 1);
+       sg_init_table(&src_sg, 1);
 
-       d40d->lli_len = sg_len;
-       if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
-               d40d->lli_tx_len = d40d->lli_len;
-       else
-               d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
+       sg_dma_address(&dst_sg) = dst;
+       sg_dma_address(&src_sg) = src;
 
-       if (sg_len > 1)
-               /*
-                * Check if there is space available in lcla.
-                * If not, split list into 1-length and run only
-                * in lcpa space.
-                */
-               if (d40_lcla_id_get(d40c) != 0)
-                       d40d->lli_tx_len = 1;
+       sg_dma_len(&dst_sg) = size;
+       sg_dma_len(&src_sg) = size;
 
-       if (direction == DMA_FROM_DEVICE)
-               if (d40c->runtime_addr)
-                       dev_addr = d40c->runtime_addr;
-               else
-                       dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
-       else if (direction == DMA_TO_DEVICE)
-               if (d40c->runtime_addr)
-                       dev_addr = d40c->runtime_addr;
-               else
-                       dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
-
-       else
-               return -EINVAL;
-
-       total_size = d40_log_sg_to_dev(&d40c->lcla,
-                                      sgl, sg_len,
-                                      &d40d->lli_log,
-                                      &d40c->log_def,
-                                      d40c->dma_cfg.src_info.data_width,
-                                      d40c->dma_cfg.dst_info.data_width,
-                                      direction,
-                                      dev_addr, d40d->lli_tx_len,
-                                      d40c->base->plat_data->llis_per_log);
-
-       if (total_size < 0)
-               return -EINVAL;
-
-       return 0;
+       return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
 }
 
-static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
-                                struct d40_chan *d40c,
-                                struct scatterlist *sgl,
-                                unsigned int sgl_len,
-                                enum dma_data_direction direction,
-                                unsigned long dma_flags)
+static struct dma_async_tx_descriptor *
+d40_prep_memcpy_sg(struct dma_chan *chan,
+                  struct scatterlist *dst_sg, unsigned int dst_nents,
+                  struct scatterlist *src_sg, unsigned int src_nents,
+                  unsigned long dma_flags)
 {
-       dma_addr_t src_dev_addr;
-       dma_addr_t dst_dev_addr;
-       int res;
-
-       if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Out of memory\n", __func__);
-               return -ENOMEM;
-       }
-
-       d40d->lli_len = sgl_len;
-       d40d->lli_tx_len = sgl_len;
-
-       if (direction == DMA_FROM_DEVICE) {
-               dst_dev_addr = 0;
-               if (d40c->runtime_addr)
-                       src_dev_addr = d40c->runtime_addr;
-               else
-                       src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
-       } else if (direction == DMA_TO_DEVICE) {
-               if (d40c->runtime_addr)
-                       dst_dev_addr = d40c->runtime_addr;
-               else
-                       dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
-               src_dev_addr = 0;
-       } else
-               return -EINVAL;
-
-       res = d40_phy_sg_to_lli(sgl,
-                               sgl_len,
-                               src_dev_addr,
-                               d40d->lli_phy.src,
-                               virt_to_phys(d40d->lli_phy.src),
-                               d40c->src_def_cfg,
-                               d40c->dma_cfg.src_info.data_width,
-                               d40c->dma_cfg.src_info.psize);
-       if (res < 0)
-               return res;
-
-       res = d40_phy_sg_to_lli(sgl,
-                               sgl_len,
-                               dst_dev_addr,
-                               d40d->lli_phy.dst,
-                               virt_to_phys(d40d->lli_phy.dst),
-                               d40c->dst_def_cfg,
-                               d40c->dma_cfg.dst_info.data_width,
-                               d40c->dma_cfg.dst_info.psize);
-       if (res < 0)
-               return res;
+       if (dst_nents != src_nents)
+               return NULL;
 
-       (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
-                             d40d->lli_pool.size, DMA_TO_DEVICE);
-       return 0;
+       return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
 }
 
 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
@@ -2059,51 +2111,40 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
                                                         enum dma_data_direction direction,
                                                         unsigned long dma_flags)
 {
-       struct d40_desc *d40d;
-       struct d40_chan *d40c = container_of(chan, struct d40_chan,
-                                            chan);
-       unsigned long flags;
-       int err;
-
-       if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Cannot prepare unallocated channel\n", __func__);
-               return ERR_PTR(-EINVAL);
-       }
-
-       if (d40c->dma_cfg.pre_transfer)
-               d40c->dma_cfg.pre_transfer(chan,
-                                          d40c->dma_cfg.pre_transfer_data,
-                                          sg_dma_len(sgl));
+       if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
+               return NULL;
 
-       spin_lock_irqsave(&d40c->lock, flags);
-       d40d = d40_desc_get(d40c);
-       spin_unlock_irqrestore(&d40c->lock, flags);
+       return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
+}
 
-       if (d40d == NULL)
-               return NULL;
+static struct dma_async_tx_descriptor *
+dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
+                    size_t buf_len, size_t period_len,
+                    enum dma_data_direction direction)
+{
+       unsigned int periods = buf_len / period_len;
+       struct dma_async_tx_descriptor *txd;
+       struct scatterlist *sg;
+       int i;
 
-       if (d40c->log_num != D40_PHY_CHAN)
-               err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
-                                           direction, dma_flags);
-       else
-               err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
-                                           direction, dma_flags);
-       if (err) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Failed to prepare %s slave sg job: %d\n",
-                       __func__,
-                       d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
-               return NULL;
+       sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
+       for (i = 0; i < periods; i++) {
+               sg_dma_address(&sg[i]) = dma_addr;
+               sg_dma_len(&sg[i]) = period_len;
+               dma_addr += period_len;
        }
 
-       d40d->txd.flags = dma_flags;
+       sg[periods].offset = 0;
+       sg[periods].length = 0;
+       sg[periods].page_link =
+               ((unsigned long)sg | 0x01) & ~0x02;
 
-       dma_async_tx_descriptor_init(&d40d->txd, chan);
+       txd = d40_prep_sg(chan, sg, sg, periods, direction,
+                         DMA_PREP_INTERRUPT);
 
-       d40d->txd.tx_submit = d40_tx_submit;
+       kfree(sg);
 
-       return &d40d->txd;
+       return txd;
 }
 
 static enum dma_status d40_tx_status(struct dma_chan *chan,
@@ -2116,9 +2157,7 @@ static enum dma_status d40_tx_status(struct dma_chan *chan,
        int ret;
 
        if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Cannot read status of unallocated channel\n",
-                       __func__);
+               chan_err(d40c, "Cannot read status of unallocated channel\n");
                return -EINVAL;
        }
 
@@ -2142,31 +2181,93 @@ static void d40_issue_pending(struct dma_chan *chan)
        unsigned long flags;
 
        if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Channel is not allocated!\n", __func__);
+               chan_err(d40c, "Channel is not allocated!\n");
                return;
        }
 
        spin_lock_irqsave(&d40c->lock, flags);
 
-       /* Busy means that pending jobs are already being processed */
+       list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
+
+       /* Busy means that queued jobs are already being processed */
        if (!d40c->busy)
                (void) d40_queue_start(d40c);
 
        spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
+static int
+dma40_config_to_halfchannel(struct d40_chan *d40c,
+                           struct stedma40_half_channel_info *info,
+                           enum dma_slave_buswidth width,
+                           u32 maxburst)
+{
+       enum stedma40_periph_data_width addr_width;
+       int psize;
+
+       switch (width) {
+       case DMA_SLAVE_BUSWIDTH_1_BYTE:
+               addr_width = STEDMA40_BYTE_WIDTH;
+               break;
+       case DMA_SLAVE_BUSWIDTH_2_BYTES:
+               addr_width = STEDMA40_HALFWORD_WIDTH;
+               break;
+       case DMA_SLAVE_BUSWIDTH_4_BYTES:
+               addr_width = STEDMA40_WORD_WIDTH;
+               break;
+       case DMA_SLAVE_BUSWIDTH_8_BYTES:
+               addr_width = STEDMA40_DOUBLEWORD_WIDTH;
+               break;
+       default:
+               dev_err(d40c->base->dev,
+                       "illegal peripheral address width "
+                       "requested (%d)\n",
+                       width);
+               return -EINVAL;
+       }
+
+       if (chan_is_logical(d40c)) {
+               if (maxburst >= 16)
+                       psize = STEDMA40_PSIZE_LOG_16;
+               else if (maxburst >= 8)
+                       psize = STEDMA40_PSIZE_LOG_8;
+               else if (maxburst >= 4)
+                       psize = STEDMA40_PSIZE_LOG_4;
+               else
+                       psize = STEDMA40_PSIZE_LOG_1;
+       } else {
+               if (maxburst >= 16)
+                       psize = STEDMA40_PSIZE_PHY_16;
+               else if (maxburst >= 8)
+                       psize = STEDMA40_PSIZE_PHY_8;
+               else if (maxburst >= 4)
+                       psize = STEDMA40_PSIZE_PHY_4;
+               else
+                       psize = STEDMA40_PSIZE_PHY_1;
+       }
+
+       info->data_width = addr_width;
+       info->psize = psize;
+       info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
+
+       return 0;
+}
+
 /* Runtime reconfiguration extension */
-static void d40_set_runtime_config(struct dma_chan *chan,
-                              struct dma_slave_config *config)
+static int d40_set_runtime_config(struct dma_chan *chan,
+                                 struct dma_slave_config *config)
 {
        struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
        struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
-       enum dma_slave_buswidth config_addr_width;
+       enum dma_slave_buswidth src_addr_width, dst_addr_width;
        dma_addr_t config_addr;
-       u32 config_maxburst;
-       enum stedma40_periph_data_width addr_width;
-       int psize;
+       u32 src_maxburst, dst_maxburst;
+       int ret;
+
+       src_addr_width = config->src_addr_width;
+       src_maxburst = config->src_maxburst;
+       dst_addr_width = config->dst_addr_width;
+       dst_maxburst = config->dst_maxburst;
 
        if (config->direction == DMA_FROM_DEVICE) {
                dma_addr_t dev_addr_rx =
@@ -2185,8 +2286,11 @@ static void d40_set_runtime_config(struct dma_chan *chan,
                                cfg->dir);
                cfg->dir = STEDMA40_PERIPH_TO_MEM;
 
-               config_addr_width = config->src_addr_width;
-               config_maxburst = config->src_maxburst;
+               /* Configure the memory side */
+               if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+                       dst_addr_width = src_addr_width;
+               if (dst_maxburst == 0)
+                       dst_maxburst = src_maxburst;
 
        } else if (config->direction == DMA_TO_DEVICE) {
                dma_addr_t dev_addr_tx =
@@ -2205,94 +2309,81 @@ static void d40_set_runtime_config(struct dma_chan *chan,
                                cfg->dir);
                cfg->dir = STEDMA40_MEM_TO_PERIPH;
 
-               config_addr_width = config->dst_addr_width;
-               config_maxburst = config->dst_maxburst;
-
+               /* Configure the memory side */
+               if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+                       src_addr_width = dst_addr_width;
+               if (src_maxburst == 0)
+                       src_maxburst = dst_maxburst;
        } else {
                dev_err(d40c->base->dev,
                        "unrecognized channel direction %d\n",
                        config->direction);
-               return;
+               return -EINVAL;
        }
 
-       switch (config_addr_width) {
-       case DMA_SLAVE_BUSWIDTH_1_BYTE:
-               addr_width = STEDMA40_BYTE_WIDTH;
-               break;
-       case DMA_SLAVE_BUSWIDTH_2_BYTES:
-               addr_width = STEDMA40_HALFWORD_WIDTH;
-               break;
-       case DMA_SLAVE_BUSWIDTH_4_BYTES:
-               addr_width = STEDMA40_WORD_WIDTH;
-               break;
-       case DMA_SLAVE_BUSWIDTH_8_BYTES:
-               addr_width = STEDMA40_DOUBLEWORD_WIDTH;
-               break;
-       default:
+       if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
                dev_err(d40c->base->dev,
-                       "illegal peripheral address width "
-                       "requested (%d)\n",
-                       config->src_addr_width);
-               return;
+                       "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
+                       src_maxburst,
+                       src_addr_width,
+                       dst_maxburst,
+                       dst_addr_width);
+               return -EINVAL;
        }
 
-       if (config_maxburst >= 16)
-               psize = STEDMA40_PSIZE_LOG_16;
-       else if (config_maxburst >= 8)
-               psize = STEDMA40_PSIZE_LOG_8;
-       else if (config_maxburst >= 4)
-               psize = STEDMA40_PSIZE_LOG_4;
+       ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
+                                         src_addr_width,
+                                         src_maxburst);
+       if (ret)
+               return ret;
+
+       ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
+                                         dst_addr_width,
+                                         dst_maxburst);
+       if (ret)
+               return ret;
+
+       /* Fill in register values */
+       if (chan_is_logical(d40c))
+               d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
        else
-               psize = STEDMA40_PSIZE_LOG_1;
-
-       /* Set up all the endpoint configs */
-       cfg->src_info.data_width = addr_width;
-       cfg->src_info.psize = psize;
-       cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN;
-       cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
-       cfg->dst_info.data_width = addr_width;
-       cfg->dst_info.psize = psize;
-       cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN;
-       cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
+               d40_phy_cfg(cfg, &d40c->src_def_cfg,
+                           &d40c->dst_def_cfg, false);
 
        /* These settings will take precedence later */
        d40c->runtime_addr = config_addr;
        d40c->runtime_direction = config->direction;
        dev_dbg(d40c->base->dev,
-               "configured channel %s for %s, data width %d, "
-               "maxburst %d bytes, LE, no flow control\n",
+               "configured channel %s for %s, data width %d/%d, "
+               "maxburst %d/%d elements, LE, no flow control\n",
                dma_chan_name(chan),
                (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
-               config_addr_width,
-               config_maxburst);
+               src_addr_width, dst_addr_width,
+               src_maxburst, dst_maxburst);
+
+       return 0;
 }
 
 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                       unsigned long arg)
 {
-       unsigned long flags;
        struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
 
        if (d40c->phy_chan == NULL) {
-               dev_err(&d40c->chan.dev->device,
-                       "[%s] Channel is not allocated!\n", __func__);
+               chan_err(d40c, "Channel is not allocated!\n");
                return -EINVAL;
        }
 
        switch (cmd) {
        case DMA_TERMINATE_ALL:
-               spin_lock_irqsave(&d40c->lock, flags);
-               d40_term_all(d40c);
-               spin_unlock_irqrestore(&d40c->lock, flags);
-               return 0;
+               return d40_terminate_all(d40c);
        case DMA_PAUSE:
-               return d40_pause(chan);
+               return d40_pause(d40c);
        case DMA_RESUME:
-               return d40_resume(chan);
+               return d40_resume(d40c);
        case DMA_SLAVE_CONFIG:
-               d40_set_runtime_config(chan,
+               return d40_set_runtime_config(chan,
                        (struct dma_slave_config *) arg);
-               return 0;
        default:
                break;
        }
@@ -2317,17 +2408,15 @@ static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
                d40c->base = base;
                d40c->chan.device = dma;
 
-               /* Invalidate lcla element */
-               d40c->lcla.src_id = -1;
-               d40c->lcla.dst_id = -1;
-
                spin_lock_init(&d40c->lock);
 
                d40c->log_num = D40_PHY_CHAN;
 
                INIT_LIST_HEAD(&d40c->active);
                INIT_LIST_HEAD(&d40c->queue);
+               INIT_LIST_HEAD(&d40c->pending_queue);
                INIT_LIST_HEAD(&d40c->client);
+               INIT_LIST_HEAD(&d40c->prepare_queue);
 
                tasklet_init(&d40c->tasklet, dma_tasklet,
                             (unsigned long) d40c);
@@ -2337,6 +2426,35 @@ static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
        }
 }
 
+static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
+{
+       if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
+               dev->device_prep_slave_sg = d40_prep_slave_sg;
+
+       if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
+               dev->device_prep_dma_memcpy = d40_prep_memcpy;
+
+               /*
+                * This controller can only access address at even
+                * 32bit boundaries, i.e. 2^2
+                */
+               dev->copy_align = 2;
+       }
+
+       if (dma_has_cap(DMA_SG, dev->cap_mask))
+               dev->device_prep_dma_sg = d40_prep_memcpy_sg;
+
+       if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
+               dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
+
+       dev->device_alloc_chan_resources = d40_alloc_chan_resources;
+       dev->device_free_chan_resources = d40_free_chan_resources;
+       dev->device_issue_pending = d40_issue_pending;
+       dev->device_tx_status = d40_tx_status;
+       dev->device_control = d40_control;
+       dev->dev = base->dev;
+}
+
 static int __init d40_dmaengine_init(struct d40_base *base,
                                     int num_reserved_chans)
 {
@@ -2347,22 +2465,14 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 
        dma_cap_zero(base->dma_slave.cap_mask);
        dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
+       dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
 
-       base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
-       base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
-       base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
-       base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
-       base->dma_slave.device_tx_status = d40_tx_status;
-       base->dma_slave.device_issue_pending = d40_issue_pending;
-       base->dma_slave.device_control = d40_control;
-       base->dma_slave.dev = base->dev;
+       d40_ops_init(base, &base->dma_slave);
 
        err = dma_async_device_register(&base->dma_slave);
 
        if (err) {
-               dev_err(base->dev,
-                       "[%s] Failed to register slave channels\n",
-                       __func__);
+               d40_err(base->dev, "Failed to register slave channels\n");
                goto failure1;
        }
 
@@ -2371,27 +2481,15 @@ static int __init d40_dmaengine_init(struct d40_base *base,
 
        dma_cap_zero(base->dma_memcpy.cap_mask);
        dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
+       dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
 
-       base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
-       base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
-       base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
-       base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
-       base->dma_memcpy.device_tx_status = d40_tx_status;
-       base->dma_memcpy.device_issue_pending = d40_issue_pending;
-       base->dma_memcpy.device_control = d40_control;
-       base->dma_memcpy.dev = base->dev;
-       /*
-        * This controller can only access address at even
-        * 32bit boundaries, i.e. 2^2
-        */
-       base->dma_memcpy.copy_align = 2;
+       d40_ops_init(base, &base->dma_memcpy);
 
        err = dma_async_device_register(&base->dma_memcpy);
 
        if (err) {
-               dev_err(base->dev,
-                       "[%s] Failed to regsiter memcpy only channels\n",
-                       __func__);
+               d40_err(base->dev,
+                       "Failed to regsiter memcpy only channels\n");
                goto failure2;
        }
 
@@ -2401,22 +2499,15 @@ static int __init d40_dmaengine_init(struct d40_base *base,
        dma_cap_zero(base->dma_both.cap_mask);
        dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
        dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
+       dma_cap_set(DMA_SG, base->dma_both.cap_mask);
+       dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
 
-       base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
-       base->dma_both.device_free_chan_resources = d40_free_chan_resources;
-       base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
-       base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
-       base->dma_both.device_tx_status = d40_tx_status;
-       base->dma_both.device_issue_pending = d40_issue_pending;
-       base->dma_both.device_control = d40_control;
-       base->dma_both.dev = base->dev;
-       base->dma_both.copy_align = 2;
+       d40_ops_init(base, &base->dma_both);
        err = dma_async_device_register(&base->dma_both);
 
        if (err) {
-               dev_err(base->dev,
-                       "[%s] Failed to register logical and physical capable channels\n",
-                       __func__);
+               d40_err(base->dev,
+                       "Failed to register logical and physical capable channels\n");
                goto failure3;
        }
        return 0;
@@ -2457,9 +2548,11 @@ static int __init d40_phy_res_init(struct d40_base *base)
 
        /* Mark disabled channels as occupied */
        for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
-                       base->phy_res[i].allocated_src = D40_ALLOC_PHY;
-                       base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
-                       num_phy_chans_avail--;
+               int chan = base->plat_data->disabled_channels[i];
+
+               base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
+               base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
+               num_phy_chans_avail--;
        }
 
        dev_info(base->dev, "%d of %d physical DMA channels available\n",
@@ -2484,24 +2577,6 @@ static int __init d40_phy_res_init(struct d40_base *base)
 
 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
 {
-       static const struct d40_reg_val dma_id_regs[] = {
-               /* Peripheral Id */
-               { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
-               { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
-               /*
-                * D40_DREG_PERIPHID2 Depends on HW revision:
-                *  MOP500/HREF ED has 0x0008,
-                *  ? has 0x0018,
-                *  HREF V1 has 0x0028
-                */
-               { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
-
-               /* PCell Id */
-               { .reg = D40_DREG_CELLID0, .val = 0x000d},
-               { .reg = D40_DREG_CELLID1, .val = 0x00f0},
-               { .reg = D40_DREG_CELLID2, .val = 0x0005},
-               { .reg = D40_DREG_CELLID3, .val = 0x00b1}
-       };
        struct stedma40_platform_data *plat_data;
        struct clk *clk = NULL;
        void __iomem *virtbase = NULL;
@@ -2510,14 +2585,14 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
        int num_log_chans = 0;
        int num_phy_chans;
        int i;
-       u32 val;
-       u32 rev;
+       u32 pid;
+       u32 cid;
+       u8 rev;
 
        clk = clk_get(&pdev->dev, NULL);
 
        if (IS_ERR(clk)) {
-               dev_err(&pdev->dev, "[%s] No matching clock found\n",
-                       __func__);
+               d40_err(&pdev->dev, "No matching clock found\n");
                goto failure;
        }
 
@@ -2536,34 +2611,32 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
        if (!virtbase)
                goto failure;
 
-       /* HW version check */
-       for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
-               if (dma_id_regs[i].val !=
-                   readl(virtbase + dma_id_regs[i].reg)) {
-                       dev_err(&pdev->dev,
-                               "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
-                               __func__,
-                               dma_id_regs[i].val,
-                               dma_id_regs[i].reg,
-                               readl(virtbase + dma_id_regs[i].reg));
-                       goto failure;
-               }
-       }
-
-       /* Get silicon revision and designer */
-       val = readl(virtbase + D40_DREG_PERIPHID2);
+       /* This is just a regular AMBA PrimeCell ID actually */
+       for (pid = 0, i = 0; i < 4; i++)
+               pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
+                       & 255) << (i * 8);
+       for (cid = 0, i = 0; i < 4; i++)
+               cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
+                       & 255) << (i * 8);
 
-       if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
-           D40_HW_DESIGNER) {
-               dev_err(&pdev->dev,
-                       "[%s] Unknown designer! Got %x wanted %x\n",
-                       __func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
-                       D40_HW_DESIGNER);
+       if (cid != AMBA_CID) {
+               d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
                goto failure;
        }
-
-       rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
-               D40_DREG_PERIPHID2_REV_POS;
+       if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
+               d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
+                       AMBA_MANF_BITS(pid),
+                       AMBA_VENDOR_ST);
+               goto failure;
+       }
+       /*
+        * HW revision:
+        * DB8500ed has revision 0
+        * ? has revision 1
+        * DB8500v1 has revision 2
+        * DB8500v2 has revision 3
+        */
+       rev = AMBA_REV_BITS(pid);
 
        /* The number of physical channels on this HW */
        num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
@@ -2587,7 +2660,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
                       sizeof(struct d40_chan), GFP_KERNEL);
 
        if (base == NULL) {
-               dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
+               d40_err(&pdev->dev, "Out of memory\n");
                goto failure;
        }
 
@@ -2625,7 +2698,10 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
                if (!base->lookup_log_chans)
                        goto failure;
        }
-       base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32),
+
+       base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
+                                           sizeof(struct d40_desc *) *
+                                           D40_LCLA_LINK_PER_EVENT_GRP,
                                            GFP_KERNEL);
        if (!base->lcla_pool.alloc_map)
                goto failure;
@@ -2639,7 +2715,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
        return base;
 
 failure:
-       if (clk) {
+       if (!IS_ERR(clk)) {
                clk_disable(clk);
                clk_put(clk);
        }
@@ -2731,6 +2807,7 @@ static void __init d40_hw_init(struct d40_base *base)
 
 static int __init d40_lcla_allocate(struct d40_base *base)
 {
+       struct d40_lcla_pool *pool = &base->lcla_pool;
        unsigned long *page_list;
        int i, j;
        int ret = 0;
@@ -2756,9 +2833,8 @@ static int __init d40_lcla_allocate(struct d40_base *base)
                                                base->lcla_pool.pages);
                if (!page_list[i]) {
 
-                       dev_err(base->dev,
-                               "[%s] Failed to allocate %d pages.\n",
-                               __func__, base->lcla_pool.pages);
+                       d40_err(base->dev, "Failed to allocate %d pages.\n",
+                               base->lcla_pool.pages);
 
                        for (j = 0; j < i; j++)
                                free_pages(page_list[j], base->lcla_pool.pages);
@@ -2796,6 +2872,15 @@ static int __init d40_lcla_allocate(struct d40_base *base)
                                                 LCLA_ALIGNMENT);
        }
 
+       pool->dma_addr = dma_map_single(base->dev, pool->base,
+                                       SZ_1K * base->num_phy_chans,
+                                       DMA_TO_DEVICE);
+       if (dma_mapping_error(base->dev, pool->dma_addr)) {
+               pool->dma_addr = 0;
+               ret = -ENOMEM;
+               goto failure;
+       }
+
        writel(virt_to_phys(base->lcla_pool.base),
               base->virtbase + D40_DREG_LCLA);
 failure:
@@ -2828,9 +2913,7 @@ static int __init d40_probe(struct platform_device *pdev)
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
        if (!res) {
                ret = -ENOENT;
-               dev_err(&pdev->dev,
-                       "[%s] No \"lcpa\" memory resource\n",
-                       __func__);
+               d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
                goto failure;
        }
        base->lcpa_size = resource_size(res);
@@ -2839,9 +2922,9 @@ static int __init d40_probe(struct platform_device *pdev)
        if (request_mem_region(res->start, resource_size(res),
                               D40_NAME " I/O lcpa") == NULL) {
                ret = -EBUSY;
-               dev_err(&pdev->dev,
-                       "[%s] Failed to request LCPA region 0x%x-0x%x\n",
-                       __func__, res->start, res->end);
+               d40_err(&pdev->dev,
+                       "Failed to request LCPA region 0x%x-0x%x\n",
+                       res->start, res->end);
                goto failure;
        }
 
@@ -2857,29 +2940,23 @@ static int __init d40_probe(struct platform_device *pdev)
        base->lcpa_base = ioremap(res->start, resource_size(res));
        if (!base->lcpa_base) {
                ret = -ENOMEM;
-               dev_err(&pdev->dev,
-                       "[%s] Failed to ioremap LCPA region\n",
-                       __func__);
+               d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
                goto failure;
        }
 
        ret = d40_lcla_allocate(base);
        if (ret) {
-               dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
-                       __func__);
+               d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
                goto failure;
        }
 
        spin_lock_init(&base->lcla_pool.lock);
 
-       base->lcla_pool.num_blocks = base->num_phy_chans;
-
        base->irq = platform_get_irq(pdev, 0);
 
        ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
-
        if (ret) {
-               dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
+               d40_err(&pdev->dev, "No IRQ defined\n");
                goto failure;
        }
 
@@ -2898,6 +2975,12 @@ failure:
                        kmem_cache_destroy(base->desc_slab);
                if (base->virtbase)
                        iounmap(base->virtbase);
+
+               if (base->lcla_pool.dma_addr)
+                       dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
+                                        SZ_1K * base->num_phy_chans,
+                                        DMA_TO_DEVICE);
+
                if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
                        free_pages((unsigned long)base->lcla_pool.base,
                                   base->lcla_pool.pages);
@@ -2922,7 +3005,7 @@ failure:
                kfree(base);
        }
 
-       dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
+       d40_err(&pdev->dev, "probe failed\n");
        return ret;
 }
 
@@ -2933,8 +3016,8 @@ static struct platform_driver d40_driver = {
        },
 };
 
-int __init stedma40_init(void)
+static int __init stedma40_init(void)
 {
        return platform_driver_probe(&d40_driver, d40_probe);
 }
-arch_initcall(stedma40_init);
+subsys_initcall(stedma40_init);