Merge branch 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm...
[linux-2.6.git] / drivers / dma / fsldma.c
index f18d1bd..8a78154 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * Freescale MPC85xx, MPC83xx DMA Engine support
  *
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author:
  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
  * Description:
  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
- *   The support for MPC8349 DMA contorller is also added.
+ *   The support for MPC8349 DMA controller is also added.
+ *
+ * This driver instructs the DMA controller to issue the PCI Read Multiple
+ * command for PCI read operations, instead of using the default PCI Read Line
+ * command. Please be aware that this setting may result in read pre-fetching
+ * on some platforms.
  *
  * This is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,6 +27,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/dmaengine.h>
 #include <linux/delay.h>
 
 #include "fsldma.h"
 
-static void dma_init(struct fsl_dma_chan *fsl_chan)
+#define chan_dbg(chan, fmt, arg...)                                    \
+       dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
+#define chan_err(chan, fmt, arg...)                                    \
+       dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
+
+static const char msg_ld_oom[] = "No free memory for link descriptor";
+
+/*
+ * Register Helpers
+ */
+
+static void set_sr(struct fsldma_chan *chan, u32 val)
 {
-       /* Reset the channel */
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
+       DMA_OUT(chan, &chan->regs->sr, val, 32);
+}
 
-       switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
-       case FSL_DMA_IP_85XX:
-               /* Set the channel to below modes:
-                * EIE - Error interrupt enable
-                * EOSIE - End of segments interrupt enable (basic mode)
-                * EOLNIE - End of links interrupt enable
-                */
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
-                               | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
-               break;
-       case FSL_DMA_IP_83XX:
-               /* Set the channel to below modes:
-                * EOTIE - End-of-transfer interrupt enable
-                */
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
-                               32);
-               break;
-       }
+static u32 get_sr(struct fsldma_chan *chan)
+{
+       return DMA_IN(chan, &chan->regs->sr, 32);
+}
 
+static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
+{
+       DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
 }
 
-static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
+static dma_addr_t get_cdar(struct fsldma_chan *chan)
 {
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
+       return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
 }
 
-static u32 get_sr(struct fsl_dma_chan *fsl_chan)
+static u32 get_bcr(struct fsldma_chan *chan)
 {
-       return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
+       return DMA_IN(chan, &chan->regs->bcr, 32);
 }
 
-static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
+/*
+ * Descriptor Helpers
+ */
+
+static void set_desc_cnt(struct fsldma_chan *chan,
                                struct fsl_dma_ld_hw *hw, u32 count)
 {
-       hw->count = CPU_TO_DMA(fsl_chan, count, 32);
+       hw->count = CPU_TO_DMA(chan, count, 32);
+}
+
+static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
+{
+       return DMA_TO_CPU(chan, desc->hw.count, 32);
 }
 
-static void set_desc_src(struct fsl_dma_chan *fsl_chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t src)
+static void set_desc_src(struct fsldma_chan *chan,
+                        struct fsl_dma_ld_hw *hw, dma_addr_t src)
 {
        u64 snoop_bits;
 
-       snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
                ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
-       hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
+       hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
 }
 
-static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t dest)
+static dma_addr_t get_desc_src(struct fsldma_chan *chan,
+                              struct fsl_desc_sw *desc)
 {
        u64 snoop_bits;
 
-       snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
-               ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
-       hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+               ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
+       return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits;
 }
 
-static void set_desc_next(struct fsl_dma_chan *fsl_chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t next)
+static void set_desc_dst(struct fsldma_chan *chan,
+                        struct fsl_dma_ld_hw *hw, dma_addr_t dst)
 {
        u64 snoop_bits;
 
-       snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
-               ? FSL_DMA_SNEN : 0;
-       hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+               ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
+       hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
 }
 
-static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
+static dma_addr_t get_desc_dst(struct fsldma_chan *chan,
+                              struct fsl_desc_sw *desc)
 {
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
-}
+       u64 snoop_bits;
 
-static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
-{
-       return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+               ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
+       return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits;
 }
 
-static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
+static void set_desc_next(struct fsldma_chan *chan,
+                         struct fsl_dma_ld_hw *hw, dma_addr_t next)
 {
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
+       u64 snoop_bits;
+
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+               ? FSL_DMA_SNEN : 0;
+       hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
 }
 
-static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
+static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
 {
-       return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
+       u64 snoop_bits;
+
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+               ? FSL_DMA_SNEN : 0;
+
+       desc->hw.next_ln_addr = CPU_TO_DMA(chan,
+               DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
+                       | snoop_bits, 64);
 }
 
-static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
+/*
+ * DMA Engine Hardware Control Helpers
+ */
+
+static void dma_init(struct fsldma_chan *chan)
 {
-       return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
+       /* Reset the channel */
+       DMA_OUT(chan, &chan->regs->mr, 0, 32);
+
+       switch (chan->feature & FSL_DMA_IP_MASK) {
+       case FSL_DMA_IP_85XX:
+               /* Set the channel to below modes:
+                * EIE - Error interrupt enable
+                * EOLNIE - End of links interrupt enable
+                * BWC - Bandwidth sharing among channels
+                */
+               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+                               | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
+               break;
+       case FSL_DMA_IP_83XX:
+               /* Set the channel to below modes:
+                * EOTIE - End-of-transfer interrupt enable
+                * PRC_RM - PCI read multiple
+                */
+               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
+                               | FSL_DMA_MR_PRC_RM, 32);
+               break;
+       }
 }
 
-static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
+static int dma_is_idle(struct fsldma_chan *chan)
 {
-       u32 sr = get_sr(fsl_chan);
+       u32 sr = get_sr(chan);
        return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 }
 
-static void dma_start(struct fsl_dma_chan *fsl_chan)
+/*
+ * Start the DMA controller
+ *
+ * Preconditions:
+ * - the CDAR register must point to the start descriptor
+ * - the MRn[CS] bit must be cleared
+ */
+static void dma_start(struct fsldma_chan *chan)
 {
-       u32 mr_set = 0;;
-
-       if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
-               mr_set |= FSL_DMA_MR_EMP_EN;
-       } else
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                               & ~FSL_DMA_MR_EMP_EN, 32);
-
-       if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
-               mr_set |= FSL_DMA_MR_EMS_EN;
-       else
-               mr_set |= FSL_DMA_MR_CS;
+       u32 mode;
 
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                       | mr_set, 32);
-}
-
-static void dma_halt(struct fsl_dma_chan *fsl_chan)
-{
-       int i;
+       mode = DMA_IN(chan, &chan->regs->mr, 32);
 
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-               DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
-               32);
-       DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-               DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
-               | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
+       if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
+               DMA_OUT(chan, &chan->regs->bcr, 0, 32);
+               mode |= FSL_DMA_MR_EMP_EN;
+       } else {
+               mode &= ~FSL_DMA_MR_EMP_EN;
+       }
 
-       for (i = 0; i < 100; i++) {
-               if (dma_is_idle(fsl_chan))
-                       break;
-               udelay(10);
+       if (chan->feature & FSL_DMA_CHAN_START_EXT) {
+               mode |= FSL_DMA_MR_EMS_EN;
+       } else {
+               mode &= ~FSL_DMA_MR_EMS_EN;
+               mode |= FSL_DMA_MR_CS;
        }
-       if (i >= 100 && !dma_is_idle(fsl_chan))
-               dev_err(fsl_chan->dev, "DMA halt timeout!\n");
+
+       DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
-static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
-                       struct fsl_desc_sw *desc)
+static void dma_halt(struct fsldma_chan *chan)
 {
-       u64 snoop_bits;
+       u32 mode;
+       int i;
 
-       snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
-               ? FSL_DMA_SNEN : 0;
+       /* read the mode register */
+       mode = DMA_IN(chan, &chan->regs->mr, 32);
 
-       desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
-               DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
-                       | snoop_bits, 64);
-}
+       /*
+        * The 85xx controller supports channel abort, which will stop
+        * the current transfer. On 83xx, this bit is the transfer error
+        * mask bit, which should not be changed.
+        */
+       if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+               mode |= FSL_DMA_MR_CA;
+               DMA_OUT(chan, &chan->regs->mr, mode, 32);
 
-static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
-               struct fsl_desc_sw *new_desc)
-{
-       struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
+               mode &= ~FSL_DMA_MR_CA;
+       }
 
-       if (list_empty(&fsl_chan->ld_queue))
-               return;
+       /* stop the DMA controller */
+       mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
+       DMA_OUT(chan, &chan->regs->mr, mode, 32);
 
-       /* Link to the new descriptor physical address and
-        * Enable End-of-segment interrupt for
-        * the last link descriptor.
-        * (the previous node's next link descriptor)
-        *
-        * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
-        */
-       queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
-                       new_desc->async_tx.phys | FSL_DMA_EOSIE |
-                       (((fsl_chan->feature & FSL_DMA_IP_MASK)
-                               == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
+       /* wait for the DMA controller to become idle */
+       for (i = 0; i < 100; i++) {
+               if (dma_is_idle(chan))
+                       return;
+
+               udelay(10);
+       }
+
+       if (!dma_is_idle(chan))
+               chan_err(chan, "DMA halt timeout!\n");
 }
 
 /**
  * fsl_chan_set_src_loop_size - Set source address hold transfer size
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @size     : Address loop size, 0 for disable loop
  *
  * The set source address hold transfer size. The source
@@ -221,29 +263,30 @@ static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
  * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
  * SA + 1 ... and so on.
  */
-static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
 {
+       u32 mode;
+
+       mode = DMA_IN(chan, &chan->regs->mr, 32);
+
        switch (size) {
        case 0:
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
-                       (~FSL_DMA_MR_SAHE), 32);
+               mode &= ~FSL_DMA_MR_SAHE;
                break;
        case 1:
        case 2:
        case 4:
        case 8:
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
-                       FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
-                       32);
+               mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
                break;
        }
+
+       DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
 /**
- * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
- * @fsl_chan : Freescale DMA channel
+ * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
+ * @chan : Freescale DMA channel
  * @size     : Address loop size, 0 for disable loop
  *
  * The set destination address hold transfer size. The destination
@@ -252,55 +295,71 @@ static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
  * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
  * TA + 1 ... and so on.
  */
-static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
 {
+       u32 mode;
+
+       mode = DMA_IN(chan, &chan->regs->mr, 32);
+
        switch (size) {
        case 0:
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
-                       (~FSL_DMA_MR_DAHE), 32);
+               mode &= ~FSL_DMA_MR_DAHE;
                break;
        case 1:
        case 2:
        case 4:
        case 8:
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
-                       FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
-                       32);
+               mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
                break;
        }
+
+       DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
 
 /**
- * fsl_chan_toggle_ext_pause - Toggle channel external pause status
- * @fsl_chan : Freescale DMA channel
- * @size     : Pause control size, 0 for disable external pause control.
- *             The maximum is 1024.
+ * fsl_chan_set_request_count - Set DMA Request Count for external control
+ * @chan : Freescale DMA channel
+ * @size     : Number of bytes to transfer in a single request
  *
- * The Freescale DMA channel can be controlled by the external
- * signal DREQ#. The pause control size is how many bytes are allowed
- * to transfer before pausing the channel, after which a new assertion
- * of DREQ# resumes channel operation.
+ * The Freescale DMA channel can be controlled by the external signal DREQ#.
+ * The DMA request count is how many bytes are allowed to transfer before
+ * pausing the channel, after which a new assertion of DREQ# resumes channel
+ * operation.
+ *
+ * A size of 0 disables external pause control. The maximum size is 1024.
  */
-static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
+static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
 {
-       if (size > 1024)
-               return;
+       u32 mode;
+
+       BUG_ON(size > 1024);
 
-       if (size) {
-               DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
-                       DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
-                               | ((__ilog2(size) << 24) & 0x0f000000),
-                       32);
-               fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
-       } else
-               fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
+       mode = DMA_IN(chan, &chan->regs->mr, 32);
+       mode |= (__ilog2(size) << 24) & 0x0f000000;
+
+       DMA_OUT(chan, &chan->regs->mr, mode, 32);
+}
+
+/**
+ * fsl_chan_toggle_ext_pause - Toggle channel external pause status
+ * @chan : Freescale DMA channel
+ * @enable   : 0 is disabled, 1 is enabled.
+ *
+ * The Freescale DMA channel can be controlled by the external signal DREQ#.
+ * The DMA Request Count feature should be used in addition to this feature
+ * to set the number of bytes to transfer before pausing the channel.
+ */
+static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
+{
+       if (enable)
+               chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
+       else
+               chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
 }
 
 /**
  * fsl_chan_toggle_ext_start - Toggle channel external start status
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  * @enable   : 0 is disabled, 1 is enabled.
  *
  * If enable the external start, the channel can be started by an
@@ -308,139 +367,201 @@ static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
  * transfer immediately. The DMA channel will wait for the
  * control pin asserted.
  */
-static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
+static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
 {
        if (enable)
-               fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
+               chan->feature |= FSL_DMA_CHAN_START_EXT;
        else
-               fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
+               chan->feature &= ~FSL_DMA_CHAN_START_EXT;
+}
+
+static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
+{
+       struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
+
+       if (list_empty(&chan->ld_pending))
+               goto out_splice;
+
+       /*
+        * Add the hardware descriptor to the chain of hardware descriptors
+        * that already exists in memory.
+        *
+        * This will un-set the EOL bit of the existing transaction, and the
+        * last link in this transaction will become the EOL descriptor.
+        */
+       set_desc_next(chan, &tail->hw, desc->async_tx.phys);
+
+       /*
+        * Add the software descriptor and all children to the list
+        * of pending transactions
+        */
+out_splice:
+       list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
 }
 
 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-       struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
-       struct fsl_desc_sw *desc;
+       struct fsldma_chan *chan = to_fsl_chan(tx->chan);
+       struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
+       struct fsl_desc_sw *child;
        unsigned long flags;
        dma_cookie_t cookie;
 
-       /* cookie increment and adding to ld_queue must be atomic */
-       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+       spin_lock_irqsave(&chan->desc_lock, flags);
 
-       cookie = fsl_chan->common.cookie;
-       list_for_each_entry(desc, &tx->tx_list, node) {
+       /*
+        * assign cookies to all of the software descriptors
+        * that make up this transaction
+        */
+       cookie = chan->common.cookie;
+       list_for_each_entry(child, &desc->tx_list, node) {
                cookie++;
-               if (cookie < 0)
-                       cookie = 1;
+               if (cookie < DMA_MIN_COOKIE)
+                       cookie = DMA_MIN_COOKIE;
 
-               desc->async_tx.cookie = cookie;
+               child->async_tx.cookie = cookie;
        }
 
-       fsl_chan->common.cookie = cookie;
-       append_ld_queue(fsl_chan, tx_to_fsl_desc(tx));
-       list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev);
+       chan->common.cookie = cookie;
+
+       /* put this transaction onto the tail of the pending queue */
+       append_ld_queue(chan, desc);
 
-       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 
        return cookie;
 }
 
 /**
  * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  *
  * Return - The descriptor allocated. NULL for failed.
  */
-static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
-                                       struct fsl_dma_chan *fsl_chan)
+static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
 {
+       struct fsl_desc_sw *desc;
        dma_addr_t pdesc;
-       struct fsl_desc_sw *desc_sw;
-
-       desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
-       if (desc_sw) {
-               memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
-               dma_async_tx_descriptor_init(&desc_sw->async_tx,
-                                               &fsl_chan->common);
-               desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
-               desc_sw->async_tx.phys = pdesc;
+
+       desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
+       if (!desc) {
+               chan_dbg(chan, "out of memory for link descriptor\n");
+               return NULL;
        }
 
-       return desc_sw;
-}
+       memset(desc, 0, sizeof(*desc));
+       INIT_LIST_HEAD(&desc->tx_list);
+       dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
+       desc->async_tx.tx_submit = fsl_dma_tx_submit;
+       desc->async_tx.phys = pdesc;
+
+#ifdef FSL_DMA_LD_DEBUG
+       chan_dbg(chan, "LD %p allocated\n", desc);
+#endif
 
+       return desc;
+}
 
 /**
  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
- * @fsl_chan : Freescale DMA channel
+ * @chan : Freescale DMA channel
  *
  * This function will create a dma pool for descriptor allocation.
  *
  * Return - The number of descriptors allocated.
  */
-static int fsl_dma_alloc_chan_resources(struct dma_chan *chan)
+static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
 {
-       struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
 
        /* Has this channel already been allocated? */
-       if (fsl_chan->desc_pool)
+       if (chan->desc_pool)
                return 1;
 
-       /* We need the descriptor to be aligned to 32bytes
+       /*
+        * We need the descriptor to be aligned to 32bytes
         * for meeting FSL DMA specification requirement.
         */
-       fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
-                       fsl_chan->dev, sizeof(struct fsl_desc_sw),
-                       32, 0);
-       if (!fsl_chan->desc_pool) {
-               dev_err(fsl_chan->dev, "No memory for channel %d "
-                       "descriptor dma pool.\n", fsl_chan->id);
-               return 0;
+       chan->desc_pool = dma_pool_create(chan->name, chan->dev,
+                                         sizeof(struct fsl_desc_sw),
+                                         __alignof__(struct fsl_desc_sw), 0);
+       if (!chan->desc_pool) {
+               chan_err(chan, "unable to allocate descriptor pool\n");
+               return -ENOMEM;
        }
 
+       /* there is at least one descriptor free to be allocated */
        return 1;
 }
 
 /**
- * fsl_dma_free_chan_resources - Free all resources of the channel.
- * @fsl_chan : Freescale DMA channel
+ * fsldma_free_desc_list - Free all descriptors in a queue
+ * @chan: Freescae DMA channel
+ * @list: the list to free
+ *
+ * LOCKING: must hold chan->desc_lock
  */
-static void fsl_dma_free_chan_resources(struct dma_chan *chan)
+static void fsldma_free_desc_list(struct fsldma_chan *chan,
+                                 struct list_head *list)
 {
-       struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
        struct fsl_desc_sw *desc, *_desc;
-       unsigned long flags;
 
-       dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
-       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-       list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
+       list_for_each_entry_safe(desc, _desc, list, node) {
+               list_del(&desc->node);
 #ifdef FSL_DMA_LD_DEBUG
-               dev_dbg(fsl_chan->dev,
-                               "LD %p will be released.\n", desc);
+               chan_dbg(chan, "LD %p free\n", desc);
 #endif
+               dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+       }
+}
+
+static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
+                                         struct list_head *list)
+{
+       struct fsl_desc_sw *desc, *_desc;
+
+       list_for_each_entry_safe_reverse(desc, _desc, list, node) {
                list_del(&desc->node);
-               /* free link descriptor */
-               dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
+#ifdef FSL_DMA_LD_DEBUG
+               chan_dbg(chan, "LD %p free\n", desc);
+#endif
+               dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
        }
-       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-       dma_pool_destroy(fsl_chan->desc_pool);
+}
+
+/**
+ * fsl_dma_free_chan_resources - Free all resources of the channel.
+ * @chan : Freescale DMA channel
+ */
+static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
+{
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
+       unsigned long flags;
+
+       chan_dbg(chan, "free all channel resources\n");
+       spin_lock_irqsave(&chan->desc_lock, flags);
+       fsldma_free_desc_list(chan, &chan->ld_pending);
+       fsldma_free_desc_list(chan, &chan->ld_running);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 
-       fsl_chan->desc_pool = NULL;
+       dma_pool_destroy(chan->desc_pool);
+       chan->desc_pool = NULL;
 }
 
 static struct dma_async_tx_descriptor *
-fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
+fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
 {
-       struct fsl_dma_chan *fsl_chan;
+       struct fsldma_chan *chan;
        struct fsl_desc_sw *new;
 
-       if (!chan)
+       if (!dchan)
                return NULL;
 
-       fsl_chan = to_fsl_chan(chan);
+       chan = to_fsl_chan(dchan);
 
-       new = fsl_dma_alloc_descriptor(fsl_chan);
+       new = fsl_dma_alloc_descriptor(chan);
        if (!new) {
-               dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
+               chan_err(chan, "%s\n", msg_ld_oom);
                return NULL;
        }
 
@@ -448,54 +569,50 @@ fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
        new->async_tx.flags = flags;
 
        /* Insert the link descriptor to the LD ring */
-       list_add_tail(&new->node, &new->async_tx.tx_list);
+       list_add_tail(&new->node, &new->tx_list);
 
-       /* Set End-of-link to the last link descriptor of new list*/
-       set_ld_eol(fsl_chan, new);
+       /* Set End-of-link to the last link descriptor of new list */
+       set_ld_eol(chan, new);
 
        return &new->async_tx;
 }
 
-static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
-       struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
+static struct dma_async_tx_descriptor *
+fsl_dma_prep_memcpy(struct dma_chan *dchan,
+       dma_addr_t dma_dst, dma_addr_t dma_src,
        size_t len, unsigned long flags)
 {
-       struct fsl_dma_chan *fsl_chan;
+       struct fsldma_chan *chan;
        struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
-       struct list_head *list;
        size_t copy;
 
-       if (!chan)
+       if (!dchan)
                return NULL;
 
        if (!len)
                return NULL;
 
-       fsl_chan = to_fsl_chan(chan);
+       chan = to_fsl_chan(dchan);
 
        do {
 
                /* Allocate the link descriptor from DMA pool */
-               new = fsl_dma_alloc_descriptor(fsl_chan);
+               new = fsl_dma_alloc_descriptor(chan);
                if (!new) {
-                       dev_err(fsl_chan->dev,
-                                       "No free memory for link descriptor\n");
+                       chan_err(chan, "%s\n", msg_ld_oom);
                        goto fail;
                }
-#ifdef FSL_DMA_LD_DEBUG
-               dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
-#endif
 
                copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 
-               set_desc_cnt(fsl_chan, &new->hw, copy);
-               set_desc_src(fsl_chan, &new->hw, dma_src);
-               set_desc_dest(fsl_chan, &new->hw, dma_dest);
+               set_desc_cnt(chan, &new->hw, copy);
+               set_desc_src(chan, &new->hw, dma_src);
+               set_desc_dst(chan, &new->hw, dma_dst);
 
                if (!first)
                        first = new;
                else
-                       set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
+                       set_desc_next(chan, &prev->hw, new->async_tx.phys);
 
                new->async_tx.cookie = 0;
                async_tx_ack(&new->async_tx);
@@ -503,17 +620,17 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
                prev = new;
                len -= copy;
                dma_src += copy;
-               dma_dest += copy;
+               dma_dst += copy;
 
                /* Insert the link descriptor to the LD ring */
-               list_add_tail(&new->node, &first->async_tx.tx_list);
+               list_add_tail(&new->node, &first->tx_list);
        } while (len);
 
        new->async_tx.flags = flags; /* client is in control of this ack */
        new->async_tx.cookie = -EBUSY;
 
-       /* Set End-of-link to the last link descriptor of new list*/
-       set_ld_eol(fsl_chan, new);
+       /* Set End-of-link to the last link descriptor of new list */
+       set_ld_eol(chan, new);
 
        return &first->async_tx;
 
@@ -521,543 +638,843 @@ fail:
        if (!first)
                return NULL;
 
-       list = &first->async_tx.tx_list;
-       list_for_each_entry_safe_reverse(new, prev, list, node) {
-               list_del(&new->node);
-               dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
-       }
-
+       fsldma_free_desc_list_reverse(chan, &first->tx_list);
        return NULL;
 }
 
-/**
- * fsl_dma_update_completed_cookie - Update the completed cookie.
- * @fsl_chan : Freescale DMA channel
- */
-static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
+static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
+       struct scatterlist *dst_sg, unsigned int dst_nents,
+       struct scatterlist *src_sg, unsigned int src_nents,
+       unsigned long flags)
 {
-       struct fsl_desc_sw *cur_desc, *desc;
-       dma_addr_t ld_phy;
+       struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
+       size_t dst_avail, src_avail;
+       dma_addr_t dst, src;
+       size_t len;
+
+       /* basic sanity checks */
+       if (dst_nents == 0 || src_nents == 0)
+               return NULL;
+
+       if (dst_sg == NULL || src_sg == NULL)
+               return NULL;
+
+       /*
+        * TODO: should we check that both scatterlists have the same
+        * TODO: number of bytes in total? Is that really an error?
+        */
+
+       /* get prepared for the loop */
+       dst_avail = sg_dma_len(dst_sg);
+       src_avail = sg_dma_len(src_sg);
 
-       ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
+       /* run until we are out of scatterlist entries */
+       while (true) {
 
-       if (ld_phy) {
-               cur_desc = NULL;
-               list_for_each_entry(desc, &fsl_chan->ld_queue, node)
-                       if (desc->async_tx.phys == ld_phy) {
-                               cur_desc = desc;
+               /* create the largest transaction possible */
+               len = min_t(size_t, src_avail, dst_avail);
+               len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
+               if (len == 0)
+                       goto fetch;
+
+               dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
+               src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
+
+               /* allocate and populate the descriptor */
+               new = fsl_dma_alloc_descriptor(chan);
+               if (!new) {
+                       chan_err(chan, "%s\n", msg_ld_oom);
+                       goto fail;
+               }
+
+               set_desc_cnt(chan, &new->hw, len);
+               set_desc_src(chan, &new->hw, src);
+               set_desc_dst(chan, &new->hw, dst);
+
+               if (!first)
+                       first = new;
+               else
+                       set_desc_next(chan, &prev->hw, new->async_tx.phys);
+
+               new->async_tx.cookie = 0;
+               async_tx_ack(&new->async_tx);
+               prev = new;
+
+               /* Insert the link descriptor to the LD ring */
+               list_add_tail(&new->node, &first->tx_list);
+
+               /* update metadata */
+               dst_avail -= len;
+               src_avail -= len;
+
+fetch:
+               /* fetch the next dst scatterlist entry */
+               if (dst_avail == 0) {
+
+                       /* no more entries: we're done */
+                       if (dst_nents == 0)
+                               break;
+
+                       /* fetch the next entry: if there are no more: done */
+                       dst_sg = sg_next(dst_sg);
+                       if (dst_sg == NULL)
                                break;
-                       }
-
-               if (cur_desc && cur_desc->async_tx.cookie) {
-                       if (dma_is_idle(fsl_chan))
-                               fsl_chan->completed_cookie =
-                                       cur_desc->async_tx.cookie;
-                       else
-                               fsl_chan->completed_cookie =
-                                       cur_desc->async_tx.cookie - 1;
+
+                       dst_nents--;
+                       dst_avail = sg_dma_len(dst_sg);
+               }
+
+               /* fetch the next src scatterlist entry */
+               if (src_avail == 0) {
+
+                       /* no more entries: we're done */
+                       if (src_nents == 0)
+                               break;
+
+                       /* fetch the next entry: if there are no more: done */
+                       src_sg = sg_next(src_sg);
+                       if (src_sg == NULL)
+                               break;
+
+                       src_nents--;
+                       src_avail = sg_dma_len(src_sg);
                }
        }
+
+       new->async_tx.flags = flags; /* client is in control of this ack */
+       new->async_tx.cookie = -EBUSY;
+
+       /* Set End-of-link to the last link descriptor of new list */
+       set_ld_eol(chan, new);
+
+       return &first->async_tx;
+
+fail:
+       if (!first)
+               return NULL;
+
+       fsldma_free_desc_list_reverse(chan, &first->tx_list);
+       return NULL;
 }
 
 /**
- * fsl_chan_ld_cleanup - Clean up link descriptors
- * @fsl_chan : Freescale DMA channel
+ * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
+ * @chan: DMA channel
+ * @sgl: scatterlist to transfer to/from
+ * @sg_len: number of entries in @scatterlist
+ * @direction: DMA direction
+ * @flags: DMAEngine flags
  *
- * This function clean up the ld_queue of DMA channel.
- * If 'in_intr' is set, the function will move the link descriptor to
- * the recycle list. Otherwise, free it directly.
+ * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
+ * DMA_SLAVE API, this gets the device-specific information from the
+ * chan->private variable.
  */
-static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
+static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
+       struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
+       enum dma_data_direction direction, unsigned long flags)
 {
-       struct fsl_desc_sw *desc, *_desc;
+       /*
+        * This operation is not supported on the Freescale DMA controller
+        *
+        * However, we need to provide the function pointer to allow the
+        * device_control() method to work.
+        */
+       return NULL;
+}
+
+static int fsl_dma_device_control(struct dma_chan *dchan,
+                                 enum dma_ctrl_cmd cmd, unsigned long arg)
+{
+       struct dma_slave_config *config;
+       struct fsldma_chan *chan;
        unsigned long flags;
+       int size;
 
-       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
+       if (!dchan)
+               return -EINVAL;
 
-       dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
-                       fsl_chan->completed_cookie);
-       list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
-               dma_async_tx_callback callback;
-               void *callback_param;
+       chan = to_fsl_chan(dchan);
 
-               if (dma_async_is_complete(desc->async_tx.cookie,
-                           fsl_chan->completed_cookie, fsl_chan->common.cookie)
-                               == DMA_IN_PROGRESS)
-                       break;
+       switch (cmd) {
+       case DMA_TERMINATE_ALL:
+               spin_lock_irqsave(&chan->desc_lock, flags);
 
-               callback = desc->async_tx.callback;
-               callback_param = desc->async_tx.callback_param;
+               /* Halt the DMA engine */
+               dma_halt(chan);
 
-               /* Remove from ld_queue list */
-               list_del(&desc->node);
+               /* Remove and free all of the descriptors in the LD queue */
+               fsldma_free_desc_list(chan, &chan->ld_pending);
+               fsldma_free_desc_list(chan, &chan->ld_running);
+               chan->idle = true;
 
-               dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
-                               desc);
-               dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
-
-               /* Run the link descriptor callback function */
-               if (callback) {
-                       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-                       dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
-                                       desc);
-                       callback(callback_param);
-                       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-               }
+               spin_unlock_irqrestore(&chan->desc_lock, flags);
+               return 0;
+
+       case DMA_SLAVE_CONFIG:
+               config = (struct dma_slave_config *)arg;
+
+               /* make sure the channel supports setting burst size */
+               if (!chan->set_request_count)
+                       return -ENXIO;
+
+               /* we set the controller burst size depending on direction */
+               if (config->direction == DMA_TO_DEVICE)
+                       size = config->dst_addr_width * config->dst_maxburst;
+               else
+                       size = config->src_addr_width * config->src_maxburst;
+
+               chan->set_request_count(chan, size);
+               return 0;
+
+       case FSLDMA_EXTERNAL_START:
+
+               /* make sure the channel supports external start */
+               if (!chan->toggle_ext_start)
+                       return -ENXIO;
+
+               chan->toggle_ext_start(chan, arg);
+               return 0;
+
+       default:
+               return -ENXIO;
        }
-       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+
+       return 0;
 }
 
 /**
- * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
- * @fsl_chan : Freescale DMA channel
+ * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
+ * @chan: Freescale DMA channel
+ * @desc: descriptor to cleanup and free
+ *
+ * This function is used on a descriptor which has been executed by the DMA
+ * controller. It will run any callbacks, submit any dependencies, and then
+ * free the descriptor.
  */
-static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
+static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
+                                     struct fsl_desc_sw *desc)
 {
-       struct list_head *ld_node;
-       dma_addr_t next_dest_addr;
-       unsigned long flags;
-
-       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-
-       if (!dma_is_idle(fsl_chan))
-               goto out_unlock;
+       struct dma_async_tx_descriptor *txd = &desc->async_tx;
+       struct device *dev = chan->common.device->dev;
+       dma_addr_t src = get_desc_src(chan, desc);
+       dma_addr_t dst = get_desc_dst(chan, desc);
+       u32 len = get_desc_cnt(chan, desc);
+
+       /* Run the link descriptor callback function */
+       if (txd->callback) {
+#ifdef FSL_DMA_LD_DEBUG
+               chan_dbg(chan, "LD %p callback\n", desc);
+#endif
+               txd->callback(txd->callback_param);
+       }
 
-       dma_halt(fsl_chan);
+       /* Run any dependencies */
+       dma_run_dependencies(txd);
 
-       /* If there are some link descriptors
-        * not transfered in queue. We need to start it.
-        */
+       /* Unmap the dst buffer, if requested */
+       if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
+               if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
+                       dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE);
+               else
+                       dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE);
+       }
 
-       /* Find the first un-transfer desciptor */
-       for (ld_node = fsl_chan->ld_queue.next;
-               (ld_node != &fsl_chan->ld_queue)
-                       && (dma_async_is_complete(
-                               to_fsl_desc(ld_node)->async_tx.cookie,
-                               fsl_chan->completed_cookie,
-                               fsl_chan->common.cookie) == DMA_SUCCESS);
-               ld_node = ld_node->next);
-
-       if (ld_node != &fsl_chan->ld_queue) {
-               /* Get the ld start address from ld_queue */
-               next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
-               dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
-                               (unsigned long long)next_dest_addr);
-               set_cdar(fsl_chan, next_dest_addr);
-               dma_start(fsl_chan);
-       } else {
-               set_cdar(fsl_chan, 0);
-               set_ndar(fsl_chan, 0);
+       /* Unmap the src buffer, if requested */
+       if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
+               if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
+                       dma_unmap_single(dev, src, len, DMA_TO_DEVICE);
+               else
+                       dma_unmap_page(dev, src, len, DMA_TO_DEVICE);
        }
 
-out_unlock:
-       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+#ifdef FSL_DMA_LD_DEBUG
+       chan_dbg(chan, "LD %p free\n", desc);
+#endif
+       dma_pool_free(chan->desc_pool, desc, txd->phys);
 }
 
 /**
- * fsl_dma_memcpy_issue_pending - Issue the DMA start command
- * @fsl_chan : Freescale DMA channel
+ * fsl_chan_xfer_ld_queue - transfer any pending transactions
+ * @chan : Freescale DMA channel
+ *
+ * HARDWARE STATE: idle
+ * LOCKING: must hold chan->desc_lock
  */
-static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
+static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
 {
-       struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
+       struct fsl_desc_sw *desc;
 
-#ifdef FSL_DMA_LD_DEBUG
-       struct fsl_desc_sw *ld;
-       unsigned long flags;
+       /*
+        * If the list of pending descriptors is empty, then we
+        * don't need to do any work at all
+        */
+       if (list_empty(&chan->ld_pending)) {
+               chan_dbg(chan, "no pending LDs\n");
+               return;
+       }
 
-       spin_lock_irqsave(&fsl_chan->desc_lock, flags);
-       if (list_empty(&fsl_chan->ld_queue)) {
-               spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
+       /*
+        * The DMA controller is not idle, which means that the interrupt
+        * handler will start any queued transactions when it runs after
+        * this transaction finishes
+        */
+       if (!chan->idle) {
+               chan_dbg(chan, "DMA controller still busy\n");
                return;
        }
 
-       dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
-       list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
-               int i;
-               dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
-                               fsl_chan->id, ld->async_tx.phys);
-               for (i = 0; i < 8; i++)
-                       dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
-                                       i, *(((u32 *)&ld->hw) + i));
+       /*
+        * If there are some link descriptors which have not been
+        * transferred, we need to start the controller
+        */
+
+       /*
+        * Move all elements from the queue of pending transactions
+        * onto the list of running transactions
+        */
+       chan_dbg(chan, "idle, starting controller\n");
+       desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
+       list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
+
+       /*
+        * The 85xx DMA controller doesn't clear the channel start bit
+        * automatically at the end of a transfer. Therefore we must clear
+        * it in software before starting the transfer.
+        */
+       if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+               u32 mode;
+
+               mode = DMA_IN(chan, &chan->regs->mr, 32);
+               mode &= ~FSL_DMA_MR_CS;
+               DMA_OUT(chan, &chan->regs->mr, mode, 32);
        }
-       dev_dbg(fsl_chan->dev, "----------------\n");
-       spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
-#endif
 
-       fsl_chan_xfer_ld_queue(fsl_chan);
+       /*
+        * Program the descriptor's address into the DMA controller,
+        * then start the DMA transaction
+        */
+       set_cdar(chan, desc->async_tx.phys);
+       get_cdar(chan);
+
+       dma_start(chan);
+       chan->idle = false;
+}
+
+/**
+ * fsl_dma_memcpy_issue_pending - Issue the DMA start command
+ * @chan : Freescale DMA channel
+ */
+static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
+{
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
+       unsigned long flags;
+
+       spin_lock_irqsave(&chan->desc_lock, flags);
+       fsl_chan_xfer_ld_queue(chan);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 }
 
 /**
- * fsl_dma_is_complete - Determine the DMA status
- * @fsl_chan : Freescale DMA channel
+ * fsl_tx_status - Determine the DMA status
+ * @chan : Freescale DMA channel
  */
-static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
+static enum dma_status fsl_tx_status(struct dma_chan *dchan,
                                        dma_cookie_t cookie,
-                                       dma_cookie_t *done,
-                                       dma_cookie_t *used)
+                                       struct dma_tx_state *txstate)
 {
-       struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
-       dma_cookie_t last_used;
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
        dma_cookie_t last_complete;
+       dma_cookie_t last_used;
+       unsigned long flags;
 
-       fsl_chan_ld_cleanup(fsl_chan);
-
-       last_used = chan->cookie;
-       last_complete = fsl_chan->completed_cookie;
+       spin_lock_irqsave(&chan->desc_lock, flags);
 
-       if (done)
-               *done = last_complete;
+       last_complete = chan->completed_cookie;
+       last_used = dchan->cookie;
 
-       if (used)
-               *used = last_used;
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 
+       dma_set_tx_state(txstate, last_complete, last_used, 0);
        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
-static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
+/*----------------------------------------------------------------------------*/
+/* Interrupt Handling                                                         */
+/*----------------------------------------------------------------------------*/
+
+static irqreturn_t fsldma_chan_irq(int irq, void *data)
 {
-       struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
+       struct fsldma_chan *chan = data;
        u32 stat;
-       int update_cookie = 0;
-       int xfer_ld_q = 0;
 
-       stat = get_sr(fsl_chan);
-       dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
-                                               fsl_chan->id, stat);
-       set_sr(fsl_chan, stat);         /* Clear the event register */
+       /* save and clear the status register */
+       stat = get_sr(chan);
+       set_sr(chan, stat);
+       chan_dbg(chan, "irq: stat = 0x%x\n", stat);
 
+       /* check that this was really our device */
        stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
        if (!stat)
                return IRQ_NONE;
 
        if (stat & FSL_DMA_SR_TE)
-               dev_err(fsl_chan->dev, "Transfer Error!\n");
+               chan_err(chan, "Transfer Error!\n");
 
-       /* Programming Error
+       /*
+        * Programming Error
         * The DMA_INTERRUPT async_tx is a NULL transfer, which will
         * triger a PE interrupt.
         */
        if (stat & FSL_DMA_SR_PE) {
-               dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
-               if (get_bcr(fsl_chan) == 0) {
-                       /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
-                        * Now, update the completed cookie, and continue the
-                        * next uncompleted transfer.
-                        */
-                       update_cookie = 1;
-                       xfer_ld_q = 1;
-               }
+               chan_dbg(chan, "irq: Programming Error INT\n");
                stat &= ~FSL_DMA_SR_PE;
+               if (get_bcr(chan) != 0)
+                       chan_err(chan, "Programming Error!\n");
        }
 
-       /* If the link descriptor segment transfer finishes,
-        * we will recycle the used descriptor.
-        */
-       if (stat & FSL_DMA_SR_EOSI) {
-               dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
-               dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
-                       (unsigned long long)get_cdar(fsl_chan),
-                       (unsigned long long)get_ndar(fsl_chan));
-               stat &= ~FSL_DMA_SR_EOSI;
-               update_cookie = 1;
-       }
-
-       /* For MPC8349, EOCDI event need to update cookie
+       /*
+        * For MPC8349, EOCDI event need to update cookie
         * and start the next transfer if it exist.
         */
        if (stat & FSL_DMA_SR_EOCDI) {
-               dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
+               chan_dbg(chan, "irq: End-of-Chain link INT\n");
                stat &= ~FSL_DMA_SR_EOCDI;
-               update_cookie = 1;
-               xfer_ld_q = 1;
        }
 
-       /* If it current transfer is the end-of-transfer,
+       /*
+        * If it current transfer is the end-of-transfer,
         * we should clear the Channel Start bit for
         * prepare next transfer.
         */
        if (stat & FSL_DMA_SR_EOLNI) {
-               dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
+               chan_dbg(chan, "irq: End-of-link INT\n");
                stat &= ~FSL_DMA_SR_EOLNI;
-               xfer_ld_q = 1;
        }
 
-       if (update_cookie)
-               fsl_dma_update_completed_cookie(fsl_chan);
-       if (xfer_ld_q)
-               fsl_chan_xfer_ld_queue(fsl_chan);
+       /* check that the DMA controller is really idle */
+       if (!dma_is_idle(chan))
+               chan_err(chan, "irq: controller not idle!\n");
+
+       /* check that we handled all of the bits */
        if (stat)
-               dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
-                                       stat);
+               chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
 
-       dev_dbg(fsl_chan->dev, "event: Exit\n");
-       tasklet_schedule(&fsl_chan->tasklet);
+       /*
+        * Schedule the tasklet to handle all cleanup of the current
+        * transaction. It will start a new transaction if there is
+        * one pending.
+        */
+       tasklet_schedule(&chan->tasklet);
+       chan_dbg(chan, "irq: Exit\n");
        return IRQ_HANDLED;
 }
 
-static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
+static void dma_do_tasklet(unsigned long data)
 {
-       struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
-       u32 gsr;
-       int ch_nr;
+       struct fsldma_chan *chan = (struct fsldma_chan *)data;
+       struct fsl_desc_sw *desc, *_desc;
+       LIST_HEAD(ld_cleanup);
+       unsigned long flags;
+
+       chan_dbg(chan, "tasklet entry\n");
+
+       spin_lock_irqsave(&chan->desc_lock, flags);
+
+       /* update the cookie if we have some descriptors to cleanup */
+       if (!list_empty(&chan->ld_running)) {
+               dma_cookie_t cookie;
 
-       gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
-                       : in_le32(fdev->reg_base);
-       ch_nr = (32 - ffs(gsr)) / 8;
+               desc = to_fsl_desc(chan->ld_running.prev);
+               cookie = desc->async_tx.cookie;
 
-       return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
-                       fdev->chan[ch_nr]) : IRQ_NONE;
+               chan->completed_cookie = cookie;
+               chan_dbg(chan, "completed_cookie=%d\n", cookie);
+       }
+
+       /*
+        * move the descriptors to a temporary list so we can drop the lock
+        * during the entire cleanup operation
+        */
+       list_splice_tail_init(&chan->ld_running, &ld_cleanup);
+
+       /* the hardware is now idle and ready for more */
+       chan->idle = true;
+
+       /*
+        * Start any pending transactions automatically
+        *
+        * In the ideal case, we keep the DMA controller busy while we go
+        * ahead and free the descriptors below.
+        */
+       fsl_chan_xfer_ld_queue(chan);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+       /* Run the callback for each descriptor, in order */
+       list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
+
+               /* Remove from the list of transactions */
+               list_del(&desc->node);
+
+               /* Run all cleanup for this descriptor */
+               fsldma_cleanup_descriptor(chan, desc);
+       }
+
+       chan_dbg(chan, "tasklet exit\n");
 }
 
-static void dma_do_tasklet(unsigned long data)
+static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
+{
+       struct fsldma_device *fdev = data;
+       struct fsldma_chan *chan;
+       unsigned int handled = 0;
+       u32 gsr, mask;
+       int i;
+
+       gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
+                                                  : in_le32(fdev->regs);
+       mask = 0xff000000;
+       dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
+
+       for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+               chan = fdev->chan[i];
+               if (!chan)
+                       continue;
+
+               if (gsr & mask) {
+                       dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
+                       fsldma_chan_irq(irq, chan);
+                       handled++;
+               }
+
+               gsr &= ~mask;
+               mask >>= 8;
+       }
+
+       return IRQ_RETVAL(handled);
+}
+
+static void fsldma_free_irqs(struct fsldma_device *fdev)
 {
-       struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
-       fsl_chan_ld_cleanup(fsl_chan);
+       struct fsldma_chan *chan;
+       int i;
+
+       if (fdev->irq != NO_IRQ) {
+               dev_dbg(fdev->dev, "free per-controller IRQ\n");
+               free_irq(fdev->irq, fdev);
+               return;
+       }
+
+       for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+               chan = fdev->chan[i];
+               if (chan && chan->irq != NO_IRQ) {
+                       chan_dbg(chan, "free per-channel IRQ\n");
+                       free_irq(chan->irq, chan);
+               }
+       }
 }
 
-static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
+static int fsldma_request_irqs(struct fsldma_device *fdev)
+{
+       struct fsldma_chan *chan;
+       int ret;
+       int i;
+
+       /* if we have a per-controller IRQ, use that */
+       if (fdev->irq != NO_IRQ) {
+               dev_dbg(fdev->dev, "request per-controller IRQ\n");
+               ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
+                                 "fsldma-controller", fdev);
+               return ret;
+       }
+
+       /* no per-controller IRQ, use the per-channel IRQs */
+       for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
+               chan = fdev->chan[i];
+               if (!chan)
+                       continue;
+
+               if (chan->irq == NO_IRQ) {
+                       chan_err(chan, "interrupts property missing in device tree\n");
+                       ret = -ENODEV;
+                       goto out_unwind;
+               }
+
+               chan_dbg(chan, "request per-channel IRQ\n");
+               ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
+                                 "fsldma-chan", chan);
+               if (ret) {
+                       chan_err(chan, "unable to request per-channel IRQ\n");
+                       goto out_unwind;
+               }
+       }
+
+       return 0;
+
+out_unwind:
+       for (/* none */; i >= 0; i--) {
+               chan = fdev->chan[i];
+               if (!chan)
+                       continue;
+
+               if (chan->irq == NO_IRQ)
+                       continue;
+
+               free_irq(chan->irq, chan);
+       }
+
+       return ret;
+}
+
+/*----------------------------------------------------------------------------*/
+/* OpenFirmware Subsystem                                                     */
+/*----------------------------------------------------------------------------*/
+
+static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
        struct device_node *node, u32 feature, const char *compatible)
 {
-       struct fsl_dma_chan *new_fsl_chan;
+       struct fsldma_chan *chan;
+       struct resource res;
        int err;
 
        /* alloc channel */
-       new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
-       if (!new_fsl_chan) {
-               dev_err(fdev->dev, "No free memory for allocating "
-                               "dma channels!\n");
-               return -ENOMEM;
+       chan = kzalloc(sizeof(*chan), GFP_KERNEL);
+       if (!chan) {
+               dev_err(fdev->dev, "no free memory for DMA channels!\n");
+               err = -ENOMEM;
+               goto out_return;
        }
 
-       /* get dma channel register base */
-       err = of_address_to_resource(node, 0, &new_fsl_chan->reg);
-       if (err) {
-               dev_err(fdev->dev, "Can't get %s property 'reg'\n",
-                               node->full_name);
-               goto err_no_reg;
+       /* ioremap registers for use */
+       chan->regs = of_iomap(node, 0);
+       if (!chan->regs) {
+               dev_err(fdev->dev, "unable to ioremap registers\n");
+               err = -ENOMEM;
+               goto out_free_chan;
        }
 
-       new_fsl_chan->feature = feature;
+       err = of_address_to_resource(node, 0, &res);
+       if (err) {
+               dev_err(fdev->dev, "unable to find 'reg' property\n");
+               goto out_iounmap_regs;
+       }
 
+       chan->feature = feature;
        if (!fdev->feature)
-               fdev->feature = new_fsl_chan->feature;
+               fdev->feature = chan->feature;
 
-       /* If the DMA device's feature is different than its channels',
-        * report the bug.
+       /*
+        * If the DMA device's feature is different than the feature
+        * of its channels, report the bug
         */
-       WARN_ON(fdev->feature != new_fsl_chan->feature);
-
-       new_fsl_chan->dev = fdev->dev;
-       new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
-                       new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
+       WARN_ON(fdev->feature != chan->feature);
 
-       new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
-       if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
-               dev_err(fdev->dev, "There is no %d channel!\n",
-                               new_fsl_chan->id);
+       chan->dev = fdev->dev;
+       chan->id = ((res.start - 0x100) & 0xfff) >> 7;
+       if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
+               dev_err(fdev->dev, "too many channels for device\n");
                err = -EINVAL;
-               goto err_no_chan;
+               goto out_iounmap_regs;
        }
-       fdev->chan[new_fsl_chan->id] = new_fsl_chan;
-       tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
-                       (unsigned long)new_fsl_chan);
 
-       /* Init the channel */
-       dma_init(new_fsl_chan);
+       fdev->chan[chan->id] = chan;
+       tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+       snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
+
+       /* Initialize the channel */
+       dma_init(chan);
 
        /* Clear cdar registers */
-       set_cdar(new_fsl_chan, 0);
+       set_cdar(chan, 0);
 
-       switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
+       switch (chan->feature & FSL_DMA_IP_MASK) {
        case FSL_DMA_IP_85XX:
-               new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
-               new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
+               chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
        case FSL_DMA_IP_83XX:
-               new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
-               new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
+               chan->toggle_ext_start = fsl_chan_toggle_ext_start;
+               chan->set_src_loop_size = fsl_chan_set_src_loop_size;
+               chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
+               chan->set_request_count = fsl_chan_set_request_count;
        }
 
-       spin_lock_init(&new_fsl_chan->desc_lock);
-       INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
+       spin_lock_init(&chan->desc_lock);
+       INIT_LIST_HEAD(&chan->ld_pending);
+       INIT_LIST_HEAD(&chan->ld_running);
+       chan->idle = true;
 
-       new_fsl_chan->common.device = &fdev->common;
+       chan->common.device = &fdev->common;
+
+       /* find the IRQ line, if it exists in the device tree */
+       chan->irq = irq_of_parse_and_map(node, 0);
 
        /* Add the channel to DMA device channel list */
-       list_add_tail(&new_fsl_chan->common.device_node,
-                       &fdev->common.channels);
+       list_add_tail(&chan->common.device_node, &fdev->common.channels);
        fdev->common.chancnt++;
 
-       new_fsl_chan->irq = irq_of_parse_and_map(node, 0);
-       if (new_fsl_chan->irq != NO_IRQ) {
-               err = request_irq(new_fsl_chan->irq,
-                                       &fsl_dma_chan_do_interrupt, IRQF_SHARED,
-                                       "fsldma-channel", new_fsl_chan);
-               if (err) {
-                       dev_err(fdev->dev, "DMA channel %s request_irq error "
-                               "with return %d\n", node->full_name, err);
-                       goto err_no_irq;
-               }
-       }
-
-       dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
-                compatible,
-                new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq);
+       dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
+                chan->irq != NO_IRQ ? chan->irq : fdev->irq);
 
        return 0;
 
-err_no_irq:
-       list_del(&new_fsl_chan->common.device_node);
-err_no_chan:
-       iounmap(new_fsl_chan->reg_base);
-err_no_reg:
-       kfree(new_fsl_chan);
+out_iounmap_regs:
+       iounmap(chan->regs);
+out_free_chan:
+       kfree(chan);
+out_return:
        return err;
 }
 
-static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan)
+static void fsl_dma_chan_remove(struct fsldma_chan *chan)
 {
-       if (fchan->irq != NO_IRQ)
-               free_irq(fchan->irq, fchan);
-       list_del(&fchan->common.device_node);
-       iounmap(fchan->reg_base);
-       kfree(fchan);
+       irq_dispose_mapping(chan->irq);
+       list_del(&chan->common.device_node);
+       iounmap(chan->regs);
+       kfree(chan);
 }
 
-static int __devinit of_fsl_dma_probe(struct of_device *dev,
-                       const struct of_device_id *match)
+static int __devinit fsldma_of_probe(struct platform_device *op)
 {
-       int err;
-       struct fsl_dma_device *fdev;
+       struct fsldma_device *fdev;
        struct device_node *child;
+       int err;
 
-       fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
+       fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
        if (!fdev) {
-               dev_err(&dev->dev, "No enough memory for 'priv'\n");
-               return -ENOMEM;
+               dev_err(&op->dev, "No enough memory for 'priv'\n");
+               err = -ENOMEM;
+               goto out_return;
        }
-       fdev->dev = &dev->dev;
+
+       fdev->dev = &op->dev;
        INIT_LIST_HEAD(&fdev->common.channels);
 
-       /* get DMA controller register base */
-       err = of_address_to_resource(dev->node, 0, &fdev->reg);
-       if (err) {
-               dev_err(&dev->dev, "Can't get %s property 'reg'\n",
-                               dev->node->full_name);
-               goto err_no_reg;
+       /* ioremap the registers for use */
+       fdev->regs = of_iomap(op->dev.of_node, 0);
+       if (!fdev->regs) {
+               dev_err(&op->dev, "unable to ioremap registers\n");
+               err = -ENOMEM;
+               goto out_free_fdev;
        }
 
-       dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
-                       "controller at 0x%llx...\n",
-                       match->compatible, (unsigned long long)fdev->reg.start);
-       fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
-                                               - fdev->reg.start + 1);
+       /* map the channel IRQ if it exists, but don't hookup the handler yet */
+       fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 
        dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
        dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
+       dma_cap_set(DMA_SG, fdev->common.cap_mask);
+       dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
        fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
        fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
        fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
        fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
-       fdev->common.device_is_tx_complete = fsl_dma_is_complete;
+       fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
+       fdev->common.device_tx_status = fsl_tx_status;
        fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
-       fdev->common.dev = &dev->dev;
+       fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
+       fdev->common.device_control = fsl_dma_device_control;
+       fdev->common.dev = &op->dev;
 
-       fdev->irq = irq_of_parse_and_map(dev->node, 0);
-       if (fdev->irq != NO_IRQ) {
-               err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED,
-                                       "fsldma-device", fdev);
-               if (err) {
-                       dev_err(&dev->dev, "DMA device request_irq error "
-                               "with return %d\n", err);
-                       goto err;
-               }
-       }
+       dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
 
-       dev_set_drvdata(&(dev->dev), fdev);
+       dev_set_drvdata(&op->dev, fdev);
 
-       /* We cannot use of_platform_bus_probe() because there is no
-        * of_platform_bus_remove.  Instead, we manually instantiate every DMA
+       /*
+        * We cannot use of_platform_bus_probe() because there is no
+        * of_platform_bus_remove(). Instead, we manually instantiate every DMA
         * channel object.
         */
-       for_each_child_of_node(dev->node, child) {
-               if (of_device_is_compatible(child, "fsl,eloplus-dma-channel"))
+       for_each_child_of_node(op->dev.of_node, child) {
+               if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
                        fsl_dma_chan_probe(fdev, child,
                                FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
                                "fsl,eloplus-dma-channel");
-               if (of_device_is_compatible(child, "fsl,elo-dma-channel"))
+               }
+
+               if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
                        fsl_dma_chan_probe(fdev, child,
                                FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
                                "fsl,elo-dma-channel");
+               }
+       }
+
+       /*
+        * Hookup the IRQ handler(s)
+        *
+        * If we have a per-controller interrupt, we prefer that to the
+        * per-channel interrupts to reduce the number of shared interrupt
+        * handlers on the same IRQ line
+        */
+       err = fsldma_request_irqs(fdev);
+       if (err) {
+               dev_err(fdev->dev, "unable to request IRQs\n");
+               goto out_free_fdev;
        }
 
        dma_async_device_register(&fdev->common);
        return 0;
 
-err:
-       iounmap(fdev->reg_base);
-err_no_reg:
+out_free_fdev:
+       irq_dispose_mapping(fdev->irq);
        kfree(fdev);
+out_return:
        return err;
 }
 
-static int of_fsl_dma_remove(struct of_device *of_dev)
+static int fsldma_of_remove(struct platform_device *op)
 {
-       struct fsl_dma_device *fdev;
+       struct fsldma_device *fdev;
        unsigned int i;
 
-       fdev = dev_get_drvdata(&of_dev->dev);
-
+       fdev = dev_get_drvdata(&op->dev);
        dma_async_device_unregister(&fdev->common);
 
-       for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++)
+       fsldma_free_irqs(fdev);
+
+       for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
                if (fdev->chan[i])
                        fsl_dma_chan_remove(fdev->chan[i]);
+       }
 
-       if (fdev->irq != NO_IRQ)
-               free_irq(fdev->irq, fdev);
-
-       iounmap(fdev->reg_base);
-
+       iounmap(fdev->regs);
+       dev_set_drvdata(&op->dev, NULL);
        kfree(fdev);
-       dev_set_drvdata(&of_dev->dev, NULL);
 
        return 0;
 }
 
-static struct of_device_id of_fsl_dma_ids[] = {
+static const struct of_device_id fsldma_of_ids[] = {
        { .compatible = "fsl,eloplus-dma", },
        { .compatible = "fsl,elo-dma", },
        {}
 };
 
-static struct of_platform_driver of_fsl_dma_driver = {
-       .name = "fsl-elo-dma",
-       .match_table = of_fsl_dma_ids,
-       .probe = of_fsl_dma_probe,
-       .remove = of_fsl_dma_remove,
+static struct platform_driver fsldma_of_driver = {
+       .driver = {
+               .name = "fsl-elo-dma",
+               .owner = THIS_MODULE,
+               .of_match_table = fsldma_of_ids,
+       },
+       .probe = fsldma_of_probe,
+       .remove = fsldma_of_remove,
 };
 
-static __init int of_fsl_dma_init(void)
-{
-       int ret;
+/*----------------------------------------------------------------------------*/
+/* Module Init / Exit                                                         */
+/*----------------------------------------------------------------------------*/
 
+static __init int fsldma_init(void)
+{
        pr_info("Freescale Elo / Elo Plus DMA driver\n");
-
-       ret = of_register_platform_driver(&of_fsl_dma_driver);
-       if (ret)
-               pr_err("fsldma: failed to register platform driver\n");
-
-       return ret;
+       return platform_driver_register(&fsldma_of_driver);
 }
 
-static void __exit of_fsl_dma_exit(void)
+static void __exit fsldma_exit(void)
 {
-       of_unregister_platform_driver(&of_fsl_dma_driver);
+       platform_driver_unregister(&fsldma_of_driver);
 }
 
-subsys_initcall(of_fsl_dma_init);
-module_exit(of_fsl_dma_exit);
+subsys_initcall(fsldma_init);
+module_exit(fsldma_exit);
 
 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
 MODULE_LICENSE("GPL");