Merge branch 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm...
[linux-2.6.git] / drivers / dma / fsldma.c
index bbb4be5..8a78154 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * Freescale MPC85xx, MPC83xx DMA Engine support
  *
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author:
  *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
@@ -10,7 +10,7 @@
  * Description:
  *   DMA engine driver for Freescale MPC8540 DMA controller, which is
  *   also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
- *   The support for MPC8349 DMA contorller is also added.
+ *   The support for MPC8349 DMA controller is also added.
  *
  * This driver instructs the DMA controller to issue the PCI Read Multiple
  * command for PCI read operations, instead of using the default PCI Read Line
@@ -27,6 +27,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/dmaengine.h>
 #include <linux/delay.h>
 #include <linux/dmapool.h>
 #include <linux/of_platform.h>
 
-#include <asm/fsldma.h>
 #include "fsldma.h"
 
-static void dma_init(struct fsldma_chan *chan)
-{
-       /* Reset the channel */
-       DMA_OUT(chan, &chan->regs->mr, 0, 32);
+#define chan_dbg(chan, fmt, arg...)                                    \
+       dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
+#define chan_err(chan, fmt, arg...)                                    \
+       dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
 
-       switch (chan->feature & FSL_DMA_IP_MASK) {
-       case FSL_DMA_IP_85XX:
-               /* Set the channel to below modes:
-                * EIE - Error interrupt enable
-                * EOSIE - End of segments interrupt enable (basic mode)
-                * EOLNIE - End of links interrupt enable
-                */
-               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
-                               | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
-               break;
-       case FSL_DMA_IP_83XX:
-               /* Set the channel to below modes:
-                * EOTIE - End-of-transfer interrupt enable
-                * PRC_RM - PCI read multiple
-                */
-               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
-                               | FSL_DMA_MR_PRC_RM, 32);
-               break;
-       }
-}
+static const char msg_ld_oom[] = "No free memory for link descriptor";
+
+/*
+ * Register Helpers
+ */
 
 static void set_sr(struct fsldma_chan *chan, u32 val)
 {
@@ -73,14 +58,38 @@ static u32 get_sr(struct fsldma_chan *chan)
        return DMA_IN(chan, &chan->regs->sr, 32);
 }
 
+static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
+{
+       DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
+}
+
+static dma_addr_t get_cdar(struct fsldma_chan *chan)
+{
+       return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
+}
+
+static u32 get_bcr(struct fsldma_chan *chan)
+{
+       return DMA_IN(chan, &chan->regs->bcr, 32);
+}
+
+/*
+ * Descriptor Helpers
+ */
+
 static void set_desc_cnt(struct fsldma_chan *chan,
                                struct fsl_dma_ld_hw *hw, u32 count)
 {
        hw->count = CPU_TO_DMA(chan, count, 32);
 }
 
+static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
+{
+       return DMA_TO_CPU(chan, desc->hw.count, 32);
+}
+
 static void set_desc_src(struct fsldma_chan *chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t src)
+                        struct fsl_dma_ld_hw *hw, dma_addr_t src)
 {
        u64 snoop_bits;
 
@@ -89,8 +98,18 @@ static void set_desc_src(struct fsldma_chan *chan,
        hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
 }
 
+static dma_addr_t get_desc_src(struct fsldma_chan *chan,
+                              struct fsl_desc_sw *desc)
+{
+       u64 snoop_bits;
+
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+               ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
+       return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits;
+}
+
 static void set_desc_dst(struct fsldma_chan *chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t dst)
+                        struct fsl_dma_ld_hw *hw, dma_addr_t dst)
 {
        u64 snoop_bits;
 
@@ -99,8 +118,18 @@ static void set_desc_dst(struct fsldma_chan *chan,
        hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
 }
 
+static dma_addr_t get_desc_dst(struct fsldma_chan *chan,
+                              struct fsl_desc_sw *desc)
+{
+       u64 snoop_bits;
+
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
+               ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
+       return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits;
+}
+
 static void set_desc_next(struct fsldma_chan *chan,
-                               struct fsl_dma_ld_hw *hw, dma_addr_t next)
+                         struct fsl_dma_ld_hw *hw, dma_addr_t next)
 {
        u64 snoop_bits;
 
@@ -109,24 +138,46 @@ static void set_desc_next(struct fsldma_chan *chan,
        hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
 }
 
-static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
+static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
 {
-       DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
-}
+       u64 snoop_bits;
 
-static dma_addr_t get_cdar(struct fsldma_chan *chan)
-{
-       return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
-}
+       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
+               ? FSL_DMA_SNEN : 0;
 
-static dma_addr_t get_ndar(struct fsldma_chan *chan)
-{
-       return DMA_IN(chan, &chan->regs->ndar, 64);
+       desc->hw.next_ln_addr = CPU_TO_DMA(chan,
+               DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
+                       | snoop_bits, 64);
 }
 
-static u32 get_bcr(struct fsldma_chan *chan)
+/*
+ * DMA Engine Hardware Control Helpers
+ */
+
+static void dma_init(struct fsldma_chan *chan)
 {
-       return DMA_IN(chan, &chan->regs->bcr, 32);
+       /* Reset the channel */
+       DMA_OUT(chan, &chan->regs->mr, 0, 32);
+
+       switch (chan->feature & FSL_DMA_IP_MASK) {
+       case FSL_DMA_IP_85XX:
+               /* Set the channel to below modes:
+                * EIE - Error interrupt enable
+                * EOLNIE - End of links interrupt enable
+                * BWC - Bandwidth sharing among channels
+                */
+               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+                               | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
+               break;
+       case FSL_DMA_IP_83XX:
+               /* Set the channel to below modes:
+                * EOTIE - End-of-transfer interrupt enable
+                * PRC_RM - PCI read multiple
+                */
+               DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
+                               | FSL_DMA_MR_PRC_RM, 32);
+               break;
+       }
 }
 
 static int dma_is_idle(struct fsldma_chan *chan)
@@ -135,25 +186,32 @@ static int dma_is_idle(struct fsldma_chan *chan)
        return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
 }
 
+/*
+ * Start the DMA controller
+ *
+ * Preconditions:
+ * - the CDAR register must point to the start descriptor
+ * - the MRn[CS] bit must be cleared
+ */
 static void dma_start(struct fsldma_chan *chan)
 {
        u32 mode;
 
        mode = DMA_IN(chan, &chan->regs->mr, 32);
 
-       if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
-               if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
-                       DMA_OUT(chan, &chan->regs->bcr, 0, 32);
-                       mode |= FSL_DMA_MR_EMP_EN;
-               } else {
-                       mode &= ~FSL_DMA_MR_EMP_EN;
-               }
+       if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
+               DMA_OUT(chan, &chan->regs->bcr, 0, 32);
+               mode |= FSL_DMA_MR_EMP_EN;
+       } else {
+               mode &= ~FSL_DMA_MR_EMP_EN;
        }
 
-       if (chan->feature & FSL_DMA_CHAN_START_EXT)
+       if (chan->feature & FSL_DMA_CHAN_START_EXT) {
                mode |= FSL_DMA_MR_EMS_EN;
-       else
+       } else {
+               mode &= ~FSL_DMA_MR_EMS_EN;
                mode |= FSL_DMA_MR_CS;
+       }
 
        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 }
@@ -163,13 +221,26 @@ static void dma_halt(struct fsldma_chan *chan)
        u32 mode;
        int i;
 
+       /* read the mode register */
        mode = DMA_IN(chan, &chan->regs->mr, 32);
-       mode |= FSL_DMA_MR_CA;
-       DMA_OUT(chan, &chan->regs->mr, mode, 32);
 
-       mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
+       /*
+        * The 85xx controller supports channel abort, which will stop
+        * the current transfer. On 83xx, this bit is the transfer error
+        * mask bit, which should not be changed.
+        */
+       if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+               mode |= FSL_DMA_MR_CA;
+               DMA_OUT(chan, &chan->regs->mr, mode, 32);
+
+               mode &= ~FSL_DMA_MR_CA;
+       }
+
+       /* stop the DMA controller */
+       mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
        DMA_OUT(chan, &chan->regs->mr, mode, 32);
 
+       /* wait for the DMA controller to become idle */
        for (i = 0; i < 100; i++) {
                if (dma_is_idle(chan))
                        return;
@@ -178,20 +249,7 @@ static void dma_halt(struct fsldma_chan *chan)
        }
 
        if (!dma_is_idle(chan))
-               dev_err(chan->dev, "DMA halt timeout!\n");
-}
-
-static void set_ld_eol(struct fsldma_chan *chan,
-                       struct fsl_desc_sw *desc)
-{
-       u64 snoop_bits;
-
-       snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
-               ? FSL_DMA_SNEN : 0;
-
-       desc->hw.next_ln_addr = CPU_TO_DMA(chan,
-               DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
-                       | snoop_bits, 64);
+               chan_err(chan, "DMA halt timeout!\n");
 }
 
 /**
@@ -317,8 +375,7 @@ static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
                chan->feature &= ~FSL_DMA_CHAN_START_EXT;
 }
 
-static void append_ld_queue(struct fsldma_chan *chan,
-                           struct fsl_desc_sw *desc)
+static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
 {
        struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
 
@@ -359,8 +416,8 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
        cookie = chan->common.cookie;
        list_for_each_entry(child, &desc->tx_list, node) {
                cookie++;
-               if (cookie < 0)
-                       cookie = 1;
+               if (cookie < DMA_MIN_COOKIE)
+                       cookie = DMA_MIN_COOKIE;
 
                child->async_tx.cookie = cookie;
        }
@@ -381,15 +438,14 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
  *
  * Return - The descriptor allocated. NULL for failed.
  */
-static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
-                                       struct fsldma_chan *chan)
+static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
 {
        struct fsl_desc_sw *desc;
        dma_addr_t pdesc;
 
        desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
        if (!desc) {
-               dev_dbg(chan->dev, "out of memory for link desc\n");
+               chan_dbg(chan, "out of memory for link descriptor\n");
                return NULL;
        }
 
@@ -399,10 +455,13 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
        desc->async_tx.tx_submit = fsl_dma_tx_submit;
        desc->async_tx.phys = pdesc;
 
+#ifdef FSL_DMA_LD_DEBUG
+       chan_dbg(chan, "LD %p allocated\n", desc);
+#endif
+
        return desc;
 }
 
-
 /**
  * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
  * @chan : Freescale DMA channel
@@ -423,13 +482,11 @@ static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
         * We need the descriptor to be aligned to 32bytes
         * for meeting FSL DMA specification requirement.
         */
-       chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
-                                         chan->dev,
+       chan->desc_pool = dma_pool_create(chan->name, chan->dev,
                                          sizeof(struct fsl_desc_sw),
                                          __alignof__(struct fsl_desc_sw), 0);
        if (!chan->desc_pool) {
-               dev_err(chan->dev, "unable to allocate channel %d "
-                                  "descriptor pool\n", chan->id);
+               chan_err(chan, "unable to allocate descriptor pool\n");
                return -ENOMEM;
        }
 
@@ -451,6 +508,9 @@ static void fsldma_free_desc_list(struct fsldma_chan *chan,
 
        list_for_each_entry_safe(desc, _desc, list, node) {
                list_del(&desc->node);
+#ifdef FSL_DMA_LD_DEBUG
+               chan_dbg(chan, "LD %p free\n", desc);
+#endif
                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
        }
 }
@@ -462,6 +522,9 @@ static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
 
        list_for_each_entry_safe_reverse(desc, _desc, list, node) {
                list_del(&desc->node);
+#ifdef FSL_DMA_LD_DEBUG
+               chan_dbg(chan, "LD %p free\n", desc);
+#endif
                dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
        }
 }
@@ -475,7 +538,7 @@ static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
        struct fsldma_chan *chan = to_fsl_chan(dchan);
        unsigned long flags;
 
-       dev_dbg(chan->dev, "Free all channel resources.\n");
+       chan_dbg(chan, "free all channel resources\n");
        spin_lock_irqsave(&chan->desc_lock, flags);
        fsldma_free_desc_list(chan, &chan->ld_pending);
        fsldma_free_desc_list(chan, &chan->ld_running);
@@ -498,7 +561,7 @@ fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
 
        new = fsl_dma_alloc_descriptor(chan);
        if (!new) {
-               dev_err(chan->dev, "No free memory for link descriptor\n");
+               chan_err(chan, "%s\n", msg_ld_oom);
                return NULL;
        }
 
@@ -508,14 +571,15 @@ fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
        /* Insert the link descriptor to the LD ring */
        list_add_tail(&new->node, &new->tx_list);
 
-       /* Set End-of-link to the last link descriptor of new list*/
+       /* Set End-of-link to the last link descriptor of new list */
        set_ld_eol(chan, new);
 
        return &new->async_tx;
 }
 
-static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
-       struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
+static struct dma_async_tx_descriptor *
+fsl_dma_prep_memcpy(struct dma_chan *dchan,
+       dma_addr_t dma_dst, dma_addr_t dma_src,
        size_t len, unsigned long flags)
 {
        struct fsldma_chan *chan;
@@ -535,13 +599,9 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
                /* Allocate the link descriptor from DMA pool */
                new = fsl_dma_alloc_descriptor(chan);
                if (!new) {
-                       dev_err(chan->dev,
-                                       "No free memory for link descriptor\n");
+                       chan_err(chan, "%s\n", msg_ld_oom);
                        goto fail;
                }
-#ifdef FSL_DMA_LD_DEBUG
-               dev_dbg(chan->dev, "new link desc alloc %p\n", new);
-#endif
 
                copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
 
@@ -569,7 +629,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
        new->async_tx.flags = flags; /* client is in control of this ack */
        new->async_tx.cookie = -EBUSY;
 
-       /* Set End-of-link to the last link descriptor of new list*/
+       /* Set End-of-link to the last link descriptor of new list */
        set_ld_eol(chan, new);
 
        return &first->async_tx;
@@ -582,355 +642,289 @@ fail:
        return NULL;
 }
 
-/**
- * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
- * @chan: DMA channel
- * @sgl: scatterlist to transfer to/from
- * @sg_len: number of entries in @scatterlist
- * @direction: DMA direction
- * @flags: DMAEngine flags
- *
- * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
- * DMA_SLAVE API, this gets the device-specific information from the
- * chan->private variable.
- */
-static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
-       struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
-       enum dma_data_direction direction, unsigned long flags)
+static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
+       struct scatterlist *dst_sg, unsigned int dst_nents,
+       struct scatterlist *src_sg, unsigned int src_nents,
+       unsigned long flags)
 {
-       struct fsldma_chan *chan;
        struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
-       struct fsl_dma_slave *slave;
-       size_t copy;
-
-       int i;
-       struct scatterlist *sg;
-       size_t sg_used;
-       size_t hw_used;
-       struct fsl_dma_hw_addr *hw;
-       dma_addr_t dma_dst, dma_src;
+       struct fsldma_chan *chan = to_fsl_chan(dchan);
+       size_t dst_avail, src_avail;
+       dma_addr_t dst, src;
+       size_t len;
 
-       if (!dchan)
+       /* basic sanity checks */
+       if (dst_nents == 0 || src_nents == 0)
                return NULL;
 
-       if (!dchan->private)
+       if (dst_sg == NULL || src_sg == NULL)
                return NULL;
 
-       chan = to_fsl_chan(dchan);
-       slave = dchan->private;
+       /*
+        * TODO: should we check that both scatterlists have the same
+        * TODO: number of bytes in total? Is that really an error?
+        */
 
-       if (list_empty(&slave->addresses))
-               return NULL;
+       /* get prepared for the loop */
+       dst_avail = sg_dma_len(dst_sg);
+       src_avail = sg_dma_len(src_sg);
 
-       hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
-       hw_used = 0;
+       /* run until we are out of scatterlist entries */
+       while (true) {
 
-       /*
-        * Build the hardware transaction to copy from the scatterlist to
-        * the hardware, or from the hardware to the scatterlist
-        *
-        * If you are copying from the hardware to the scatterlist and it
-        * takes two hardware entries to fill an entire page, then both
-        * hardware entries will be coalesced into the same page
-        *
-        * If you are copying from the scatterlist to the hardware and a
-        * single page can fill two hardware entries, then the data will
-        * be read out of the page into the first hardware entry, and so on
-        */
-       for_each_sg(sgl, sg, sg_len, i) {
-               sg_used = 0;
-
-               /* Loop until the entire scatterlist entry is used */
-               while (sg_used < sg_dma_len(sg)) {
-
-                       /*
-                        * If we've used up the current hardware address/length
-                        * pair, we need to load a new one
-                        *
-                        * This is done in a while loop so that descriptors with
-                        * length == 0 will be skipped
-                        */
-                       while (hw_used >= hw->length) {
-
-                               /*
-                                * If the current hardware entry is the last
-                                * entry in the list, we're finished
-                                */
-                               if (list_is_last(&hw->entry, &slave->addresses))
-                                       goto finished;
-
-                               /* Get the next hardware address/length pair */
-                               hw = list_entry(hw->entry.next,
-                                               struct fsl_dma_hw_addr, entry);
-                               hw_used = 0;
-                       }
-
-                       /* Allocate the link descriptor from DMA pool */
-                       new = fsl_dma_alloc_descriptor(chan);
-                       if (!new) {
-                               dev_err(chan->dev, "No free memory for "
-                                                      "link descriptor\n");
-                               goto fail;
-                       }
-#ifdef FSL_DMA_LD_DEBUG
-                       dev_dbg(chan->dev, "new link desc alloc %p\n", new);
-#endif
+               /* create the largest transaction possible */
+               len = min_t(size_t, src_avail, dst_avail);
+               len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
+               if (len == 0)
+                       goto fetch;
+
+               dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
+               src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
 
-                       /*
-                        * Calculate the maximum number of bytes to transfer,
-                        * making sure it is less than the DMA controller limit
-                        */
-                       copy = min_t(size_t, sg_dma_len(sg) - sg_used,
-                                            hw->length - hw_used);
-                       copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
-
-                       /*
-                        * DMA_FROM_DEVICE
-                        * from the hardware to the scatterlist
-                        *
-                        * DMA_TO_DEVICE
-                        * from the scatterlist to the hardware
-                        */
-                       if (direction == DMA_FROM_DEVICE) {
-                               dma_src = hw->address + hw_used;
-                               dma_dst = sg_dma_address(sg) + sg_used;
-                       } else {
-                               dma_src = sg_dma_address(sg) + sg_used;
-                               dma_dst = hw->address + hw_used;
-                       }
-
-                       /* Fill in the descriptor */
-                       set_desc_cnt(chan, &new->hw, copy);
-                       set_desc_src(chan, &new->hw, dma_src);
-                       set_desc_dst(chan, &new->hw, dma_dst);
-
-                       /*
-                        * If this is not the first descriptor, chain the
-                        * current descriptor after the previous descriptor
-                        */
-                       if (!first) {
-                               first = new;
-                       } else {
-                               set_desc_next(chan, &prev->hw,
-                                             new->async_tx.phys);
-                       }
-
-                       new->async_tx.cookie = 0;
-                       async_tx_ack(&new->async_tx);
-
-                       prev = new;
-                       sg_used += copy;
-                       hw_used += copy;
-
-                       /* Insert the link descriptor into the LD ring */
-                       list_add_tail(&new->node, &first->tx_list);
+               /* allocate and populate the descriptor */
+               new = fsl_dma_alloc_descriptor(chan);
+               if (!new) {
+                       chan_err(chan, "%s\n", msg_ld_oom);
+                       goto fail;
                }
-       }
 
-finished:
+               set_desc_cnt(chan, &new->hw, len);
+               set_desc_src(chan, &new->hw, src);
+               set_desc_dst(chan, &new->hw, dst);
 
-       /* All of the hardware address/length pairs had length == 0 */
-       if (!first || !new)
-               return NULL;
+               if (!first)
+                       first = new;
+               else
+                       set_desc_next(chan, &prev->hw, new->async_tx.phys);
 
-       new->async_tx.flags = flags;
-       new->async_tx.cookie = -EBUSY;
+               new->async_tx.cookie = 0;
+               async_tx_ack(&new->async_tx);
+               prev = new;
 
-       /* Set End-of-link to the last link descriptor of new list */
-       set_ld_eol(chan, new);
+               /* Insert the link descriptor to the LD ring */
+               list_add_tail(&new->node, &first->tx_list);
+
+               /* update metadata */
+               dst_avail -= len;
+               src_avail -= len;
 
-       /* Enable extra controller features */
-       if (chan->set_src_loop_size)
-               chan->set_src_loop_size(chan, slave->src_loop_size);
+fetch:
+               /* fetch the next dst scatterlist entry */
+               if (dst_avail == 0) {
 
-       if (chan->set_dst_loop_size)
-               chan->set_dst_loop_size(chan, slave->dst_loop_size);
+                       /* no more entries: we're done */
+                       if (dst_nents == 0)
+                               break;
 
-       if (chan->toggle_ext_start)
-               chan->toggle_ext_start(chan, slave->external_start);
+                       /* fetch the next entry: if there are no more: done */
+                       dst_sg = sg_next(dst_sg);
+                       if (dst_sg == NULL)
+                               break;
 
-       if (chan->toggle_ext_pause)
-               chan->toggle_ext_pause(chan, slave->external_pause);
+                       dst_nents--;
+                       dst_avail = sg_dma_len(dst_sg);
+               }
 
-       if (chan->set_request_count)
-               chan->set_request_count(chan, slave->request_count);
+               /* fetch the next src scatterlist entry */
+               if (src_avail == 0) {
+
+                       /* no more entries: we're done */
+                       if (src_nents == 0)
+                               break;
+
+                       /* fetch the next entry: if there are no more: done */
+                       src_sg = sg_next(src_sg);
+                       if (src_sg == NULL)
+                               break;
+
+                       src_nents--;
+                       src_avail = sg_dma_len(src_sg);
+               }
+       }
+
+       new->async_tx.flags = flags; /* client is in control of this ack */
+       new->async_tx.cookie = -EBUSY;
+
+       /* Set End-of-link to the last link descriptor of new list */
+       set_ld_eol(chan, new);
 
        return &first->async_tx;
 
 fail:
-       /* If first was not set, then we failed to allocate the very first
-        * descriptor, and we're done */
        if (!first)
                return NULL;
 
+       fsldma_free_desc_list_reverse(chan, &first->tx_list);
+       return NULL;
+}
+
+/**
+ * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
+ * @chan: DMA channel
+ * @sgl: scatterlist to transfer to/from
+ * @sg_len: number of entries in @scatterlist
+ * @direction: DMA direction
+ * @flags: DMAEngine flags
+ *
+ * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
+ * DMA_SLAVE API, this gets the device-specific information from the
+ * chan->private variable.
+ */
+static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
+       struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
+       enum dma_data_direction direction, unsigned long flags)
+{
        /*
-        * First is set, so all of the descriptors we allocated have been added
-        * to first->tx_list, INCLUDING "first" itself. Therefore we
-        * must traverse the list backwards freeing each descriptor in turn
+        * This operation is not supported on the Freescale DMA controller
         *
-        * We're re-using variables for the loop, oh well
+        * However, we need to provide the function pointer to allow the
+        * device_control() method to work.
         */
-       fsldma_free_desc_list_reverse(chan, &first->tx_list);
        return NULL;
 }
 
-static void fsl_dma_device_terminate_all(struct dma_chan *dchan)
+static int fsl_dma_device_control(struct dma_chan *dchan,
+                                 enum dma_ctrl_cmd cmd, unsigned long arg)
 {
+       struct dma_slave_config *config;
        struct fsldma_chan *chan;
        unsigned long flags;
+       int size;
 
        if (!dchan)
-               return;
+               return -EINVAL;
 
        chan = to_fsl_chan(dchan);
 
-       /* Halt the DMA engine */
-       dma_halt(chan);
+       switch (cmd) {
+       case DMA_TERMINATE_ALL:
+               spin_lock_irqsave(&chan->desc_lock, flags);
 
-       spin_lock_irqsave(&chan->desc_lock, flags);
+               /* Halt the DMA engine */
+               dma_halt(chan);
 
-       /* Remove and free all of the descriptors in the LD queue */
-       fsldma_free_desc_list(chan, &chan->ld_pending);
-       fsldma_free_desc_list(chan, &chan->ld_running);
+               /* Remove and free all of the descriptors in the LD queue */
+               fsldma_free_desc_list(chan, &chan->ld_pending);
+               fsldma_free_desc_list(chan, &chan->ld_running);
+               chan->idle = true;
 
-       spin_unlock_irqrestore(&chan->desc_lock, flags);
-}
+               spin_unlock_irqrestore(&chan->desc_lock, flags);
+               return 0;
 
-/**
- * fsl_dma_update_completed_cookie - Update the completed cookie.
- * @chan : Freescale DMA channel
- *
- * CONTEXT: hardirq
- */
-static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
-{
-       struct fsl_desc_sw *desc;
-       unsigned long flags;
-       dma_cookie_t cookie;
+       case DMA_SLAVE_CONFIG:
+               config = (struct dma_slave_config *)arg;
 
-       spin_lock_irqsave(&chan->desc_lock, flags);
+               /* make sure the channel supports setting burst size */
+               if (!chan->set_request_count)
+                       return -ENXIO;
 
-       if (list_empty(&chan->ld_running)) {
-               dev_dbg(chan->dev, "no running descriptors\n");
-               goto out_unlock;
-       }
+               /* we set the controller burst size depending on direction */
+               if (config->direction == DMA_TO_DEVICE)
+                       size = config->dst_addr_width * config->dst_maxburst;
+               else
+                       size = config->src_addr_width * config->src_maxburst;
 
-       /* Get the last descriptor, update the cookie to that */
-       desc = to_fsl_desc(chan->ld_running.prev);
-       if (dma_is_idle(chan))
-               cookie = desc->async_tx.cookie;
-       else {
-               cookie = desc->async_tx.cookie - 1;
-               if (unlikely(cookie < DMA_MIN_COOKIE))
-                       cookie = DMA_MAX_COOKIE;
-       }
+               chan->set_request_count(chan, size);
+               return 0;
 
-       chan->completed_cookie = cookie;
+       case FSLDMA_EXTERNAL_START:
 
-out_unlock:
-       spin_unlock_irqrestore(&chan->desc_lock, flags);
-}
+               /* make sure the channel supports external start */
+               if (!chan->toggle_ext_start)
+                       return -ENXIO;
 
-/**
- * fsldma_desc_status - Check the status of a descriptor
- * @chan: Freescale DMA channel
- * @desc: DMA SW descriptor
- *
- * This function will return the status of the given descriptor
- */
-static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
-                                         struct fsl_desc_sw *desc)
-{
-       return dma_async_is_complete(desc->async_tx.cookie,
-                                    chan->completed_cookie,
-                                    chan->common.cookie);
+               chan->toggle_ext_start(chan, arg);
+               return 0;
+
+       default:
+               return -ENXIO;
+       }
+
+       return 0;
 }
 
 /**
- * fsl_chan_ld_cleanup - Clean up link descriptors
- * @chan : Freescale DMA channel
+ * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
+ * @chan: Freescale DMA channel
+ * @desc: descriptor to cleanup and free
  *
- * This function clean up the ld_queue of DMA channel.
+ * This function is used on a descriptor which has been executed by the DMA
+ * controller. It will run any callbacks, submit any dependencies, and then
+ * free the descriptor.
  */
-static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
+static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
+                                     struct fsl_desc_sw *desc)
 {
-       struct fsl_desc_sw *desc, *_desc;
-       unsigned long flags;
-
-       spin_lock_irqsave(&chan->desc_lock, flags);
-
-       dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
-       list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
-               dma_async_tx_callback callback;
-               void *callback_param;
-
-               if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
-                       break;
+       struct dma_async_tx_descriptor *txd = &desc->async_tx;
+       struct device *dev = chan->common.device->dev;
+       dma_addr_t src = get_desc_src(chan, desc);
+       dma_addr_t dst = get_desc_dst(chan, desc);
+       u32 len = get_desc_cnt(chan, desc);
+
+       /* Run the link descriptor callback function */
+       if (txd->callback) {
+#ifdef FSL_DMA_LD_DEBUG
+               chan_dbg(chan, "LD %p callback\n", desc);
+#endif
+               txd->callback(txd->callback_param);
+       }
 
-               /* Remove from the list of running transactions */
-               list_del(&desc->node);
+       /* Run any dependencies */
+       dma_run_dependencies(txd);
 
-               /* Run the link descriptor callback function */
-               callback = desc->async_tx.callback;
-               callback_param = desc->async_tx.callback_param;
-               if (callback) {
-                       spin_unlock_irqrestore(&chan->desc_lock, flags);
-                       dev_dbg(chan->dev, "LD %p callback\n", desc);
-                       callback(callback_param);
-                       spin_lock_irqsave(&chan->desc_lock, flags);
-               }
+       /* Unmap the dst buffer, if requested */
+       if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
+               if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
+                       dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE);
+               else
+                       dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE);
+       }
 
-               /* Run any dependencies, then free the descriptor */
-               dma_run_dependencies(&desc->async_tx);
-               dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
+       /* Unmap the src buffer, if requested */
+       if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
+               if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
+                       dma_unmap_single(dev, src, len, DMA_TO_DEVICE);
+               else
+                       dma_unmap_page(dev, src, len, DMA_TO_DEVICE);
        }
 
-       spin_unlock_irqrestore(&chan->desc_lock, flags);
+#ifdef FSL_DMA_LD_DEBUG
+       chan_dbg(chan, "LD %p free\n", desc);
+#endif
+       dma_pool_free(chan->desc_pool, desc, txd->phys);
 }
 
 /**
  * fsl_chan_xfer_ld_queue - transfer any pending transactions
  * @chan : Freescale DMA channel
  *
- * This will make sure that any pending transactions will be run.
- * If the DMA controller is idle, it will be started. Otherwise,
- * the DMA controller's interrupt handler will start any pending
- * transactions when it becomes idle.
+ * HARDWARE STATE: idle
+ * LOCKING: must hold chan->desc_lock
  */
 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
 {
        struct fsl_desc_sw *desc;
-       unsigned long flags;
-
-       spin_lock_irqsave(&chan->desc_lock, flags);
 
        /*
         * If the list of pending descriptors is empty, then we
         * don't need to do any work at all
         */
        if (list_empty(&chan->ld_pending)) {
-               dev_dbg(chan->dev, "no pending LDs\n");
-               goto out_unlock;
+               chan_dbg(chan, "no pending LDs\n");
+               return;
        }
 
        /*
-        * The DMA controller is not idle, which means the interrupt
-        * handler will start any queued transactions when it runs
-        * at the end of the current transaction
+        * The DMA controller is not idle, which means that the interrupt
+        * handler will start any queued transactions when it runs after
+        * this transaction finishes
         */
-       if (!dma_is_idle(chan)) {
-               dev_dbg(chan->dev, "DMA controller still busy\n");
-               goto out_unlock;
+       if (!chan->idle) {
+               chan_dbg(chan, "DMA controller still busy\n");
+               return;
        }
 
        /*
-        * TODO:
-        * make sure the dma_halt() function really un-wedges the
-        * controller as much as possible
-        */
-       dma_halt(chan);
-
-       /*
         * If there are some link descriptors which have not been
         * transferred, we need to start the controller
         */
@@ -939,18 +933,32 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
         * Move all elements from the queue of pending transactions
         * onto the list of running transactions
         */
+       chan_dbg(chan, "idle, starting controller\n");
        desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
        list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
 
        /*
+        * The 85xx DMA controller doesn't clear the channel start bit
+        * automatically at the end of a transfer. Therefore we must clear
+        * it in software before starting the transfer.
+        */
+       if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+               u32 mode;
+
+               mode = DMA_IN(chan, &chan->regs->mr, 32);
+               mode &= ~FSL_DMA_MR_CS;
+               DMA_OUT(chan, &chan->regs->mr, mode, 32);
+       }
+
+       /*
         * Program the descriptor's address into the DMA controller,
         * then start the DMA transaction
         */
        set_cdar(chan, desc->async_tx.phys);
-       dma_start(chan);
+       get_cdar(chan);
 
-out_unlock:
-       spin_unlock_irqrestore(&chan->desc_lock, flags);
+       dma_start(chan);
+       chan->idle = false;
 }
 
 /**
@@ -960,33 +968,34 @@ out_unlock:
 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
 {
        struct fsldma_chan *chan = to_fsl_chan(dchan);
+       unsigned long flags;
+
+       spin_lock_irqsave(&chan->desc_lock, flags);
        fsl_chan_xfer_ld_queue(chan);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 }
 
 /**
- * fsl_dma_is_complete - Determine the DMA status
+ * fsl_tx_status - Determine the DMA status
  * @chan : Freescale DMA channel
  */
-static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan,
+static enum dma_status fsl_tx_status(struct dma_chan *dchan,
                                        dma_cookie_t cookie,
-                                       dma_cookie_t *done,
-                                       dma_cookie_t *used)
+                                       struct dma_tx_state *txstate)
 {
        struct fsldma_chan *chan = to_fsl_chan(dchan);
-       dma_cookie_t last_used;
        dma_cookie_t last_complete;
+       dma_cookie_t last_used;
+       unsigned long flags;
 
-       fsl_chan_ld_cleanup(chan);
+       spin_lock_irqsave(&chan->desc_lock, flags);
 
-       last_used = dchan->cookie;
        last_complete = chan->completed_cookie;
+       last_used = dchan->cookie;
 
-       if (done)
-               *done = last_complete;
-
-       if (used)
-               *used = last_used;
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
 
+       dma_set_tx_state(txstate, last_complete, last_used, 0);
        return dma_async_is_complete(cookie, last_complete, last_used);
 }
 
@@ -997,21 +1006,20 @@ static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan,
 static irqreturn_t fsldma_chan_irq(int irq, void *data)
 {
        struct fsldma_chan *chan = data;
-       int update_cookie = 0;
-       int xfer_ld_q = 0;
        u32 stat;
 
        /* save and clear the status register */
        stat = get_sr(chan);
        set_sr(chan, stat);
-       dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
+       chan_dbg(chan, "irq: stat = 0x%x\n", stat);
 
+       /* check that this was really our device */
        stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
        if (!stat)
                return IRQ_NONE;
 
        if (stat & FSL_DMA_SR_TE)
-               dev_err(chan->dev, "Transfer Error!\n");
+               chan_err(chan, "Transfer Error!\n");
 
        /*
         * Programming Error
@@ -1019,29 +1027,10 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
         * triger a PE interrupt.
         */
        if (stat & FSL_DMA_SR_PE) {
-               dev_dbg(chan->dev, "irq: Programming Error INT\n");
-               if (get_bcr(chan) == 0) {
-                       /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
-                        * Now, update the completed cookie, and continue the
-                        * next uncompleted transfer.
-                        */
-                       update_cookie = 1;
-                       xfer_ld_q = 1;
-               }
+               chan_dbg(chan, "irq: Programming Error INT\n");
                stat &= ~FSL_DMA_SR_PE;
-       }
-
-       /*
-        * If the link descriptor segment transfer finishes,
-        * we will recycle the used descriptor.
-        */
-       if (stat & FSL_DMA_SR_EOSI) {
-               dev_dbg(chan->dev, "irq: End-of-segments INT\n");
-               dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
-                       (unsigned long long)get_cdar(chan),
-                       (unsigned long long)get_ndar(chan));
-               stat &= ~FSL_DMA_SR_EOSI;
-               update_cookie = 1;
+               if (get_bcr(chan) != 0)
+                       chan_err(chan, "Programming Error!\n");
        }
 
        /*
@@ -1049,10 +1038,8 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
         * and start the next transfer if it exist.
         */
        if (stat & FSL_DMA_SR_EOCDI) {
-               dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
+               chan_dbg(chan, "irq: End-of-Chain link INT\n");
                stat &= ~FSL_DMA_SR_EOCDI;
-               update_cookie = 1;
-               xfer_ld_q = 1;
        }
 
        /*
@@ -1061,27 +1048,79 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
         * prepare next transfer.
         */
        if (stat & FSL_DMA_SR_EOLNI) {
-               dev_dbg(chan->dev, "irq: End-of-link INT\n");
+               chan_dbg(chan, "irq: End-of-link INT\n");
                stat &= ~FSL_DMA_SR_EOLNI;
-               xfer_ld_q = 1;
        }
 
-       if (update_cookie)
-               fsl_dma_update_completed_cookie(chan);
-       if (xfer_ld_q)
-               fsl_chan_xfer_ld_queue(chan);
+       /* check that the DMA controller is really idle */
+       if (!dma_is_idle(chan))
+               chan_err(chan, "irq: controller not idle!\n");
+
+       /* check that we handled all of the bits */
        if (stat)
-               dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
+               chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
 
-       dev_dbg(chan->dev, "irq: Exit\n");
+       /*
+        * Schedule the tasklet to handle all cleanup of the current
+        * transaction. It will start a new transaction if there is
+        * one pending.
+        */
        tasklet_schedule(&chan->tasklet);
+       chan_dbg(chan, "irq: Exit\n");
        return IRQ_HANDLED;
 }
 
 static void dma_do_tasklet(unsigned long data)
 {
        struct fsldma_chan *chan = (struct fsldma_chan *)data;
-       fsl_chan_ld_cleanup(chan);
+       struct fsl_desc_sw *desc, *_desc;
+       LIST_HEAD(ld_cleanup);
+       unsigned long flags;
+
+       chan_dbg(chan, "tasklet entry\n");
+
+       spin_lock_irqsave(&chan->desc_lock, flags);
+
+       /* update the cookie if we have some descriptors to cleanup */
+       if (!list_empty(&chan->ld_running)) {
+               dma_cookie_t cookie;
+
+               desc = to_fsl_desc(chan->ld_running.prev);
+               cookie = desc->async_tx.cookie;
+
+               chan->completed_cookie = cookie;
+               chan_dbg(chan, "completed_cookie=%d\n", cookie);
+       }
+
+       /*
+        * move the descriptors to a temporary list so we can drop the lock
+        * during the entire cleanup operation
+        */
+       list_splice_tail_init(&chan->ld_running, &ld_cleanup);
+
+       /* the hardware is now idle and ready for more */
+       chan->idle = true;
+
+       /*
+        * Start any pending transactions automatically
+        *
+        * In the ideal case, we keep the DMA controller busy while we go
+        * ahead and free the descriptors below.
+        */
+       fsl_chan_xfer_ld_queue(chan);
+       spin_unlock_irqrestore(&chan->desc_lock, flags);
+
+       /* Run the callback for each descriptor, in order */
+       list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
+
+               /* Remove from the list of transactions */
+               list_del(&desc->node);
+
+               /* Run all cleanup for this descriptor */
+               fsldma_cleanup_descriptor(chan, desc);
+       }
+
+       chan_dbg(chan, "tasklet exit\n");
 }
 
 static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
@@ -1129,7 +1168,7 @@ static void fsldma_free_irqs(struct fsldma_device *fdev)
        for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
                chan = fdev->chan[i];
                if (chan && chan->irq != NO_IRQ) {
-                       dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
+                       chan_dbg(chan, "free per-channel IRQ\n");
                        free_irq(chan->irq, chan);
                }
        }
@@ -1156,19 +1195,16 @@ static int fsldma_request_irqs(struct fsldma_device *fdev)
                        continue;
 
                if (chan->irq == NO_IRQ) {
-                       dev_err(fdev->dev, "no interrupts property defined for "
-                                          "DMA channel %d. Please fix your "
-                                          "device tree\n", chan->id);
+                       chan_err(chan, "interrupts property missing in device tree\n");
                        ret = -ENODEV;
                        goto out_unwind;
                }
 
-               dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
+               chan_dbg(chan, "request per-channel IRQ\n");
                ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
                                  "fsldma-chan", chan);
                if (ret) {
-                       dev_err(fdev->dev, "unable to request IRQ for DMA "
-                                          "channel %d\n", chan->id);
+                       chan_err(chan, "unable to request per-channel IRQ\n");
                        goto out_unwind;
                }
        }
@@ -1243,6 +1279,7 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
 
        fdev->chan[chan->id] = chan;
        tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
+       snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
 
        /* Initialize the channel */
        dma_init(chan);
@@ -1263,6 +1300,7 @@ static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
        spin_lock_init(&chan->desc_lock);
        INIT_LIST_HEAD(&chan->ld_pending);
        INIT_LIST_HEAD(&chan->ld_running);
+       chan->idle = true;
 
        chan->common.device = &fdev->common;
 
@@ -1294,8 +1332,7 @@ static void fsl_dma_chan_remove(struct fsldma_chan *chan)
        kfree(chan);
 }
 
-static int __devinit fsldma_of_probe(struct of_device *op,
-                       const struct of_device_id *match)
+static int __devinit fsldma_of_probe(struct platform_device *op)
 {
        struct fsldma_device *fdev;
        struct device_node *child;
@@ -1312,7 +1349,7 @@ static int __devinit fsldma_of_probe(struct of_device *op,
        INIT_LIST_HEAD(&fdev->common.channels);
 
        /* ioremap the registers for use */
-       fdev->regs = of_iomap(op->node, 0);
+       fdev->regs = of_iomap(op->dev.of_node, 0);
        if (!fdev->regs) {
                dev_err(&op->dev, "unable to ioremap registers\n");
                err = -ENOMEM;
@@ -1320,21 +1357,25 @@ static int __devinit fsldma_of_probe(struct of_device *op,
        }
 
        /* map the channel IRQ if it exists, but don't hookup the handler yet */
-       fdev->irq = irq_of_parse_and_map(op->node, 0);
+       fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
 
        dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
        dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
+       dma_cap_set(DMA_SG, fdev->common.cap_mask);
        dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
        fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
        fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
        fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
        fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
-       fdev->common.device_is_tx_complete = fsl_dma_is_complete;
+       fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
+       fdev->common.device_tx_status = fsl_tx_status;
        fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
        fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
-       fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
+       fdev->common.device_control = fsl_dma_device_control;
        fdev->common.dev = &op->dev;
 
+       dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
+
        dev_set_drvdata(&op->dev, fdev);
 
        /*
@@ -1342,7 +1383,7 @@ static int __devinit fsldma_of_probe(struct of_device *op,
         * of_platform_bus_remove(). Instead, we manually instantiate every DMA
         * channel object.
         */
-       for_each_child_of_node(op->node, child) {
+       for_each_child_of_node(op->dev.of_node, child) {
                if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
                        fsl_dma_chan_probe(fdev, child,
                                FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
@@ -1379,7 +1420,7 @@ out_return:
        return err;
 }
 
-static int fsldma_of_remove(struct of_device *op)
+static int fsldma_of_remove(struct platform_device *op)
 {
        struct fsldma_device *fdev;
        unsigned int i;
@@ -1407,11 +1448,14 @@ static const struct of_device_id fsldma_of_ids[] = {
        {}
 };
 
-static struct of_platform_driver fsldma_of_driver = {
-       .name           = "fsl-elo-dma",
-       .match_table    = fsldma_of_ids,
-       .probe          = fsldma_of_probe,
-       .remove         = fsldma_of_remove,
+static struct platform_driver fsldma_of_driver = {
+       .driver = {
+               .name = "fsl-elo-dma",
+               .owner = THIS_MODULE,
+               .of_match_table = fsldma_of_ids,
+       },
+       .probe = fsldma_of_probe,
+       .remove = fsldma_of_remove,
 };
 
 /*----------------------------------------------------------------------------*/
@@ -1420,20 +1464,13 @@ static struct of_platform_driver fsldma_of_driver = {
 
 static __init int fsldma_init(void)
 {
-       int ret;
-
        pr_info("Freescale Elo / Elo Plus DMA driver\n");
-
-       ret = of_register_platform_driver(&fsldma_of_driver);
-       if (ret)
-               pr_err("fsldma: failed to register platform driver\n");
-
-       return ret;
+       return platform_driver_register(&fsldma_of_driver);
 }
 
 static void __exit fsldma_exit(void)
 {
-       of_unregister_platform_driver(&fsldma_of_driver);
+       platform_driver_unregister(&fsldma_of_driver);
 }
 
 subsys_initcall(fsldma_init);