perf_events, x86: AMD event scheduling
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
index 092ad56..aa12f36 100644 (file)
@@ -23,6 +23,7 @@
 #include <linux/uaccess.h>
 #include <linux/highmem.h>
 #include <linux/cpu.h>
+#include <linux/bitops.h>
 
 #include <asm/apic.h>
 #include <asm/stacktrace.h>
@@ -76,6 +77,14 @@ struct event_constraint {
        };
        int     code;
        int     cmask;
+       int     weight;
+};
+
+struct amd_nb {
+       int nb_id;  /* NorthBridge id */
+       int refcnt; /* reference count */
+       struct perf_event *owners[X86_PMC_IDX_MAX];
+       struct event_constraint event_constraints[X86_PMC_IDX_MAX];
 };
 
 struct cpu_hw_events {
@@ -88,25 +97,31 @@ struct cpu_hw_events {
        int                     n_events;
        int                     n_added;
        int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
+       u64                     tags[X86_PMC_IDX_MAX];
        struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
+       struct amd_nb           *amd_nb;
 };
 
-#define EVENT_CONSTRAINT(c, n, m) {    \
+#define __EVENT_CONSTRAINT(c, n, m, w) {\
        { .idxmsk64[0] = (n) },         \
        .code = (c),                    \
        .cmask = (m),                   \
+       .weight = (w),                  \
 }
 
+#define EVENT_CONSTRAINT(c, n, m)      \
+       __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
+
 #define INTEL_EVENT_CONSTRAINT(c, n)   \
-       EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
+       EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 
 #define FIXED_EVENT_CONSTRAINT(c, n)   \
        EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
 
-#define EVENT_CONSTRAINT_END \
+#define EVENT_CONSTRAINT_END           \
        EVENT_CONSTRAINT(0, 0, 0)
 
-#define for_each_event_constraint(e, c) \
+#define for_each_event_constraint(e, c)        \
        for ((e) = (c); (e)->cmask; (e)++)
 
 /*
@@ -146,6 +161,8 @@ struct x86_pmu {
 
 static struct x86_pmu x86_pmu __read_mostly;
 
+static raw_spinlock_t amd_nb_lock;
+
 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
        .enabled = 1,
 };
@@ -225,6 +242,17 @@ static const u64 intel_perfmon_event_map[] =
 
 static struct event_constraint intel_core_event_constraints[] =
 {
+       INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
+       INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
+       INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
+       INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
+       INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
+       INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
+       EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_core2_event_constraints[] =
+{
        FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
        FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
        INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
@@ -241,18 +269,26 @@ static struct event_constraint intel_core_event_constraints[] =
 
 static struct event_constraint intel_nehalem_event_constraints[] =
 {
-       FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
-       FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+       FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+       FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
        INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
        INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
        INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
        INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
+       INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
        INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
-       INTEL_EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
        INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
-       INTEL_EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
-       INTEL_EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
-       INTEL_EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
+       INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
+       EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_westmere_event_constraints[] =
+{
+       FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+       FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+       INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
+       INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
+       INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
        EVENT_CONSTRAINT_END
 };
 
@@ -283,6 +319,97 @@ static u64 __read_mostly hw_cache_event_ids
                                [PERF_COUNT_HW_CACHE_OP_MAX]
                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
 
+static __initconst u64 westmere_hw_cache_event_ids
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
+               [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
+               [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
+               [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
+       },
+ },
+ [ C(L1I ) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
+               [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = -1,
+               [ C(RESULT_MISS)   ] = -1,
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = 0x0,
+               [ C(RESULT_MISS)   ] = 0x0,
+       },
+ },
+ [ C(LL  ) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
+               [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
+               [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
+               [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
+       },
+ },
+ [ C(DTLB) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
+               [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
+               [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = 0x0,
+               [ C(RESULT_MISS)   ] = 0x0,
+       },
+ },
+ [ C(ITLB) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
+               [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = -1,
+               [ C(RESULT_MISS)   ] = -1,
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = -1,
+               [ C(RESULT_MISS)   ] = -1,
+       },
+ },
+ [ C(BPU ) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
+               [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = -1,
+               [ C(RESULT_MISS)   ] = -1,
+       },
+       [ C(OP_PREFETCH) ] = {
+               [ C(RESULT_ACCESS) ] = -1,
+               [ C(RESULT_MISS)   ] = -1,
+       },
+ },
+};
+
 static __initconst u64 nehalem_hw_cache_event_ids
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -685,7 +812,7 @@ static u64 amd_pmu_event_map(int hw_event)
 
 static u64 amd_pmu_raw_event(u64 hw_event)
 {
-#define K7_EVNTSEL_EVENT_MASK  0x7000000FFULL
+#define K7_EVNTSEL_EVENT_MASK  0xF000000FFULL
 #define K7_EVNTSEL_UNIT_MASK   0x00000FF00ULL
 #define K7_EVNTSEL_EDGE_MASK   0x000040000ULL
 #define K7_EVNTSEL_INV_MASK    0x000800000ULL
@@ -1026,6 +1153,8 @@ static int __hw_perf_event_init(struct perf_event *event)
        hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 
        hwc->idx = -1;
+       hwc->last_cpu = -1;
+       hwc->last_tag = ~0ULL;
 
        /*
         * Count user and OS events unless requested not to.
@@ -1096,15 +1225,8 @@ static int __hw_perf_event_init(struct perf_event *event)
 
 static void p6_pmu_disable_all(void)
 {
-       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        u64 val;
 
-       if (!cpuc->enabled)
-               return;
-
-       cpuc->enabled = 0;
-       barrier();
-
        /* p6 only has one enable register */
        rdmsrl(MSR_P6_EVNTSEL0, val);
        val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -1115,44 +1237,27 @@ static void intel_pmu_disable_all(void)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-       if (!cpuc->enabled)
-               return;
-
-       cpuc->enabled = 0;
-       barrier();
-
        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 
        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
                intel_pmu_disable_bts();
 }
 
-static void amd_pmu_disable_all(void)
+static void x86_pmu_disable_all(void)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        int idx;
 
-       if (!cpuc->enabled)
-               return;
-
-       cpuc->enabled = 0;
-       /*
-        * ensure we write the disable before we start disabling the
-        * events proper, so that amd_pmu_enable_event() does the
-        * right thing.
-        */
-       barrier();
-
        for (idx = 0; idx < x86_pmu.num_events; idx++) {
                u64 val;
 
                if (!test_bit(idx, cpuc->active_mask))
                        continue;
-               rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
+               rdmsrl(x86_pmu.eventsel + idx, val);
                if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
                        continue;
                val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
-               wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
+               wrmsrl(x86_pmu.eventsel + idx, val);
        }
 }
 
@@ -1163,23 +1268,20 @@ void hw_perf_disable(void)
        if (!x86_pmu_initialized())
                return;
 
-       if (cpuc->enabled)
-               cpuc->n_added = 0;
+       if (!cpuc->enabled)
+               return;
+
+       cpuc->n_added = 0;
+       cpuc->enabled = 0;
+       barrier();
 
        x86_pmu.disable_all();
 }
 
 static void p6_pmu_enable_all(void)
 {
-       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        unsigned long val;
 
-       if (cpuc->enabled)
-               return;
-
-       cpuc->enabled = 1;
-       barrier();
-
        /* p6 only has one enable register */
        rdmsrl(MSR_P6_EVNTSEL0, val);
        val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
@@ -1190,12 +1292,6 @@ static void intel_pmu_enable_all(void)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-       if (cpuc->enabled)
-               return;
-
-       cpuc->enabled = 1;
-       barrier();
-
        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 
        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
@@ -1209,17 +1305,11 @@ static void intel_pmu_enable_all(void)
        }
 }
 
-static void amd_pmu_enable_all(void)
+static void x86_pmu_enable_all(void)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        int idx;
 
-       if (cpuc->enabled)
-               return;
-
-       cpuc->enabled = 1;
-       barrier();
-
        for (idx = 0; idx < x86_pmu.num_events; idx++) {
                struct perf_event *event = cpuc->events[idx];
                u64 val;
@@ -1229,7 +1319,7 @@ static void amd_pmu_enable_all(void)
 
                val = event->hw.config;
                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-               wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
+               wrmsrl(x86_pmu.eventsel + idx, val);
        }
 }
 
@@ -1242,10 +1332,9 @@ static inline int is_x86_event(struct perf_event *event)
 
 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 {
-       int i, j , w, num;
-       int weight, wmax;
        struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
        unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+       int i, j, w, wmax, num = 0;
        struct hw_perf_event *hwc;
 
        bitmap_zero(used_mask, X86_PMC_IDX_MAX);
@@ -1258,7 +1347,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
        /*
         * fastpath, try to reuse previous register
         */
-       for (i = 0, num = n; i < n; i++, num--) {
+       for (i = 0; i < n; i++) {
                hwc = &cpuc->event_list[i]->hw;
                c = constraints[i];
 
@@ -1274,19 +1363,11 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
                if (test_bit(hwc->idx, used_mask))
                        break;
 
-#if 0
-               pr_debug("CPU%d fast config=0x%llx idx=%d assign=%c\n",
-                        smp_processor_id(),
-                        hwc->config,
-                        hwc->idx,
-                        assign ? 'y' : 'n');
-#endif
-
                set_bit(hwc->idx, used_mask);
                if (assign)
                        assign[i] = hwc->idx;
        }
-       if (!num)
+       if (i == n)
                goto done;
 
        /*
@@ -1320,8 +1401,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
                        c = constraints[i];
                        hwc = &cpuc->event_list[i]->hw;
 
-                       weight = bitmap_weight(c->idxmsk, X86_PMC_IDX_MAX);
-                       if (weight != w)
+                       if (c->weight != w)
                                continue;
 
                        for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
@@ -1332,14 +1412,6 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
                        if (j == X86_PMC_IDX_MAX)
                                break;
 
-#if 0
-                       pr_debug("CPU%d slow config=0x%llx idx=%d assign=%c\n",
-                               smp_processor_id(),
-                               hwc->config,
-                               j,
-                               assign ? 'y' : 'n');
-#endif
-
                        set_bit(j, used_mask);
 
                        if (assign)
@@ -1398,11 +1470,14 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
        return n;
 }
 
-
 static inline void x86_assign_hw_event(struct perf_event *event,
-                               struct hw_perf_event *hwc, int idx)
+                               struct cpu_hw_events *cpuc, int i)
 {
-       hwc->idx = idx;
+       struct hw_perf_event *hwc = &event->hw;
+
+       hwc->idx = cpuc->assign[i];
+       hwc->last_cpu = smp_processor_id();
+       hwc->last_tag = ++cpuc->tags[i];
 
        if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
                hwc->config_base = 0;
@@ -1421,6 +1496,17 @@ static inline void x86_assign_hw_event(struct perf_event *event,
        }
 }
 
+static inline int match_prev_assignment(struct hw_perf_event *hwc,
+                                       struct cpu_hw_events *cpuc,
+                                       int i)
+{
+       return hwc->idx == cpuc->assign[i] &&
+               hwc->last_cpu == smp_processor_id() &&
+               hwc->last_tag == cpuc->tags[i];
+}
+
+static void x86_pmu_stop(struct perf_event *event);
+
 void hw_perf_enable(void)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
@@ -1430,6 +1516,10 @@ void hw_perf_enable(void)
 
        if (!x86_pmu_initialized())
                return;
+
+       if (cpuc->enabled)
+               return;
+
        if (cpuc->n_added) {
                /*
                 * apply assignment obtained either from
@@ -1443,16 +1533,17 @@ void hw_perf_enable(void)
                        event = cpuc->event_list[i];
                        hwc = &event->hw;
 
-                       if (hwc->idx == -1 || hwc->idx == cpuc->assign[i])
+                       /*
+                        * we can avoid reprogramming counter if:
+                        * - assigned same counter as last time
+                        * - running on same CPU as last time
+                        * - no other event has used the counter since
+                        */
+                       if (hwc->idx == -1 ||
+                           match_prev_assignment(hwc, cpuc, i))
                                continue;
 
-                       x86_pmu.disable(hwc, hwc->idx);
-
-                       clear_bit(hwc->idx, cpuc->active_mask);
-                       barrier();
-                       cpuc->events[hwc->idx] = NULL;
-
-                       x86_perf_event_update(event, hwc, hwc->idx);
+                       x86_pmu_stop(event);
 
                        hwc->idx = -1;
                }
@@ -1463,12 +1554,12 @@ void hw_perf_enable(void)
                        hwc = &event->hw;
 
                        if (hwc->idx == -1) {
-                               x86_assign_hw_event(event, hwc, cpuc->assign[i]);
+                               x86_assign_hw_event(event, cpuc, i);
                                x86_perf_event_set_period(event, hwc, hwc->idx);
                        }
                        /*
                         * need to mark as active because x86_pmu_disable()
-                        * clear active_mask and eventsp[] yet it preserves
+                        * clear active_mask and events[] yet it preserves
                         * idx
                         */
                        set_bit(hwc->idx, cpuc->active_mask);
@@ -1480,6 +1571,10 @@ void hw_perf_enable(void)
                cpuc->n_added = 0;
                perf_events_lapic_init();
        }
+
+       cpuc->enabled = 1;
+       barrier();
+
        x86_pmu.enable_all();
 }
 
@@ -1497,7 +1592,7 @@ static inline void intel_pmu_ack_status(u64 ack)
        wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 }
 
-static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
        (void)checking_wrmsrl(hwc->config_base + idx,
                              hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
@@ -1549,12 +1644,6 @@ intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
        x86_pmu_disable_event(hwc, idx);
 }
 
-static inline void
-amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-       x86_pmu_disable_event(hwc, idx);
-}
-
 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
 
 /*
@@ -1630,6 +1719,13 @@ intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
                bits |= 0x2;
        if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
                bits |= 0x1;
+
+       /*
+        * ANY bit is supported in v3 and up
+        */
+       if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
+               bits |= 0x4;
+
        bits <<= (idx * 4);
        mask = 0xfULL << (idx * 4);
 
@@ -1667,15 +1763,14 @@ static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
                return;
        }
 
-       x86_pmu_enable_event(hwc, idx);
+       __x86_pmu_enable_event(hwc, idx);
 }
 
-static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-
        if (cpuc->enabled)
-               x86_pmu_enable_event(hwc, idx);
+               __x86_pmu_enable_event(hwc, idx);
 }
 
 /*
@@ -1713,8 +1808,18 @@ static int x86_pmu_enable(struct perf_event *event)
        cpuc->n_events = n;
        cpuc->n_added  = n - n0;
 
-       if (hwc->idx != -1)
-               x86_perf_event_set_period(event, hwc, hwc->idx);
+       return 0;
+}
+
+static int x86_pmu_start(struct perf_event *event)
+{
+       struct hw_perf_event *hwc = &event->hw;
+
+       if (hwc->idx == -1)
+               return -EAGAIN;
+
+       x86_perf_event_set_period(event, hwc, hwc->idx);
+       x86_pmu.enable(hwc, hwc->idx);
 
        return 0;
 }
@@ -1842,11 +1947,11 @@ static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
        event->pending_kill = POLL_IN;
 }
 
-static void x86_pmu_disable(struct perf_event *event)
+static void x86_pmu_stop(struct perf_event *event)
 {
        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
-       int i, idx = hwc->idx;
+       int idx = hwc->idx;
 
        /*
         * Must be done before we disable, otherwise the nmi handler
@@ -1856,12 +1961,6 @@ static void x86_pmu_disable(struct perf_event *event)
        x86_pmu.disable(hwc, idx);
 
        /*
-        * Make sure the cleared pointer becomes visible before we
-        * (potentially) free the event:
-        */
-       barrier();
-
-       /*
         * Drain the remaining delta count out of a event
         * that we are disabling:
         */
@@ -1872,6 +1971,14 @@ static void x86_pmu_disable(struct perf_event *event)
                intel_pmu_drain_bts_buffer(cpuc);
 
        cpuc->events[idx] = NULL;
+}
+
+static void x86_pmu_disable(struct perf_event *event)
+{
+       struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+       int i;
+
+       x86_pmu_stop(event);
 
        for (i = 0; i < cpuc->n_events; i++) {
                if (event == cpuc->event_list[i]) {
@@ -1883,6 +1990,7 @@ static void x86_pmu_disable(struct perf_event *event)
                                cpuc->event_list[i-1] = cpuc->event_list[i];
 
                        --cpuc->n_events;
+                       break;
                }
        }
        perf_event_update_userpage(event);
@@ -1933,50 +2041,6 @@ static void intel_pmu_reset(void)
        local_irq_restore(flags);
 }
 
-static int p6_pmu_handle_irq(struct pt_regs *regs)
-{
-       struct perf_sample_data data;
-       struct cpu_hw_events *cpuc;
-       struct perf_event *event;
-       struct hw_perf_event *hwc;
-       int idx, handled = 0;
-       u64 val;
-
-       data.addr = 0;
-       data.raw = NULL;
-
-       cpuc = &__get_cpu_var(cpu_hw_events);
-
-       for (idx = 0; idx < x86_pmu.num_events; idx++) {
-               if (!test_bit(idx, cpuc->active_mask))
-                       continue;
-
-               event = cpuc->events[idx];
-               hwc = &event->hw;
-
-               val = x86_perf_event_update(event, hwc, idx);
-               if (val & (1ULL << (x86_pmu.event_bits - 1)))
-                       continue;
-
-               /*
-                * event overflow
-                */
-               handled         = 1;
-               data.period     = event->hw.last_period;
-
-               if (!x86_perf_event_set_period(event, hwc, idx))
-                       continue;
-
-               if (perf_event_overflow(event, 1, &data, regs))
-                       p6_pmu_disable_event(hwc, idx);
-       }
-
-       if (handled)
-               inc_irq_stat(apic_perf_irqs);
-
-       return handled;
-}
-
 /*
  * This handler is triggered by the local APIC, so the APIC IRQ handling
  * rules apply:
@@ -2043,7 +2107,7 @@ again:
        return 1;
 }
 
-static int amd_pmu_handle_irq(struct pt_regs *regs)
+static int x86_pmu_handle_irq(struct pt_regs *regs)
 {
        struct perf_sample_data data;
        struct cpu_hw_events *cpuc;
@@ -2078,7 +2142,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
                        continue;
 
                if (perf_event_overflow(event, 1, &data, regs))
-                       amd_pmu_disable_event(hwc, idx);
+                       x86_pmu.disable(hwc, idx);
        }
 
        if (handled)
@@ -2156,6 +2220,7 @@ perf_event_nmi_handler(struct notifier_block *self,
 }
 
 static struct event_constraint unconstrained;
+static struct event_constraint emptyconstraint;
 
 static struct event_constraint bts_constraint =
        EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
@@ -2195,10 +2260,146 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event
        return &unconstrained;
 }
 
+/*
+ * AMD64 events are detected based on their event codes.
+ */
+static inline int amd_is_nb_event(struct hw_perf_event *hwc)
+{
+       return (hwc->config & 0xe0) == 0xe0;
+}
+
+static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
+                                     struct perf_event *event)
+{
+       struct hw_perf_event *hwc = &event->hw;
+       struct amd_nb *nb = cpuc->amd_nb;
+       int i;
+
+       /*
+        * only care about NB events
+        */
+       if (!(nb && amd_is_nb_event(hwc)))
+               return;
+
+       /*
+        * need to scan whole list because event may not have
+        * been assigned during scheduling
+        *
+        * no race condition possible because event can only
+        * be removed on one CPU at a time AND PMU is disabled
+        * when we come here
+        */
+       for (i = 0; i < x86_pmu.num_events; i++) {
+               if (nb->owners[i] == event) {
+                       cmpxchg(nb->owners+i, event, NULL);
+                       break;
+               }
+       }
+}
+
+ /*
+  * AMD64 NorthBridge events need special treatment because
+  * counter access needs to be synchronized across all cores
+  * of a package. Refer to BKDG section 3.12
+  *
+  * NB events are events measuring L3 cache, Hypertransport
+  * traffic. They are identified by an event code >= 0xe00.
+  * They measure events on the NorthBride which is shared
+  * by all cores on a package. NB events are counted on a
+  * shared set of counters. When a NB event is programmed
+  * in a counter, the data actually comes from a shared
+  * counter. Thus, access to those counters needs to be
+  * synchronized.
+  *
+  * We implement the synchronization such that no two cores
+  * can be measuring NB events using the same counters. Thus,
+  * we maintain a per-NB allocation table. The available slot
+  * is propagated using the event_constraint structure.
+  *
+  * We provide only one choice for each NB event based on
+  * the fact that only NB events have restrictions. Consequently,
+  * if a counter is available, there is a guarantee the NB event
+  * will be assigned to it. If no slot is available, an empty
+  * constraint is returned and scheduling will eventually fail
+  * for this event.
+  *
+  * Note that all cores attached the same NB compete for the same
+  * counters to host NB events, this is why we use atomic ops. Some
+  * multi-chip CPUs may have more than one NB.
+  *
+  * Given that resources are allocated (cmpxchg), they must be
+  * eventually freed for others to use. This is accomplished by
+  * calling amd_put_event_constraints().
+  *
+  * Non NB events are not impacted by this restriction.
+  */
 static struct event_constraint *
 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
-       return &unconstrained;
+       struct hw_perf_event *hwc = &event->hw;
+       struct amd_nb *nb = cpuc->amd_nb;
+       struct perf_event *old = NULL;
+       int max = x86_pmu.num_events;
+       int i, j, k = -1;
+
+       /*
+        * if not NB event or no NB, then no constraints
+        */
+       if (!(nb && amd_is_nb_event(hwc)))
+               return &unconstrained;
+
+       /*
+        * detect if already present, if so reuse
+        *
+        * cannot merge with actual allocation
+        * because of possible holes
+        *
+        * event can already be present yet not assigned (in hwc->idx)
+        * because of successive calls to x86_schedule_events() from
+        * hw_perf_group_sched_in() without hw_perf_enable()
+        */
+       for (i = 0; i < max; i++) {
+               /*
+                * keep track of first free slot
+                */
+               if (k == -1 && !nb->owners[i])
+                       k = i;
+
+               /* already present, reuse */
+               if (nb->owners[i] == event)
+                       goto done;
+       }
+       /*
+        * not present, so grab a new slot
+        * starting either at:
+        */
+       if (hwc->idx != -1) {
+               /* previous assignment */
+               i = hwc->idx;
+       } else if (k != -1) {
+               /* start from free slot found */
+               i = k;
+       } else {
+               /*
+                * event not found, no slot found in
+                * first pass, try again from the
+                * beginning
+                */
+               i = 0;
+       }
+       j = i;
+       do {
+               old = cmpxchg(nb->owners+i, NULL, event);
+               if (!old)
+                       break;
+               if (++i == max)
+                       i = 0;
+       } while (i != j);
+done:
+       if (!old)
+               return &nb->event_constraints[i];
+
+       return &emptyconstraint;
 }
 
 static int x86_event_sched_in(struct perf_event *event,
@@ -2319,7 +2520,7 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = {
 
 static __initconst struct x86_pmu p6_pmu = {
        .name                   = "p6",
-       .handle_irq             = p6_pmu_handle_irq,
+       .handle_irq             = x86_pmu_handle_irq,
        .disable_all            = p6_pmu_disable_all,
        .enable_all             = p6_pmu_enable_all,
        .enable                 = p6_pmu_enable_event,
@@ -2346,6 +2547,29 @@ static __initconst struct x86_pmu p6_pmu = {
        .event_constraints      = intel_p6_event_constraints
 };
 
+static __initconst struct x86_pmu core_pmu = {
+       .name                   = "core",
+       .handle_irq             = x86_pmu_handle_irq,
+       .disable_all            = x86_pmu_disable_all,
+       .enable_all             = x86_pmu_enable_all,
+       .enable                 = x86_pmu_enable_event,
+       .disable                = x86_pmu_disable_event,
+       .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
+       .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
+       .event_map              = intel_pmu_event_map,
+       .raw_event              = intel_pmu_raw_event,
+       .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
+       .apic                   = 1,
+       /*
+        * Intel PMCs cannot be accessed sanely above 32 bit width,
+        * so we install an artificial 1<<31 period regardless of
+        * the generic event period:
+        */
+       .max_period             = (1ULL << 31) - 1,
+       .get_event_constraints  = intel_get_event_constraints,
+       .event_constraints      = intel_core_event_constraints,
+};
+
 static __initconst struct x86_pmu intel_pmu = {
        .name                   = "Intel",
        .handle_irq             = intel_pmu_handle_irq,
@@ -2372,11 +2596,11 @@ static __initconst struct x86_pmu intel_pmu = {
 
 static __initconst struct x86_pmu amd_pmu = {
        .name                   = "AMD",
-       .handle_irq             = amd_pmu_handle_irq,
-       .disable_all            = amd_pmu_disable_all,
-       .enable_all             = amd_pmu_enable_all,
-       .enable                 = amd_pmu_enable_event,
-       .disable                = amd_pmu_disable_event,
+       .handle_irq             = x86_pmu_handle_irq,
+       .disable_all            = x86_pmu_disable_all,
+       .enable_all             = x86_pmu_enable_all,
+       .enable                 = x86_pmu_enable_event,
+       .disable                = x86_pmu_disable_event,
        .eventsel               = MSR_K7_EVNTSEL0,
        .perfctr                = MSR_K7_PERFCTR0,
        .event_map              = amd_pmu_event_map,
@@ -2388,7 +2612,8 @@ static __initconst struct x86_pmu amd_pmu = {
        .apic                   = 1,
        /* use highest bit to detect overflow */
        .max_period             = (1ULL << 47) - 1,
-       .get_event_constraints  = amd_get_event_constraints
+       .get_event_constraints  = amd_get_event_constraints,
+       .put_event_constraints  = amd_put_event_constraints
 };
 
 static __init int p6_pmu_init(void)
@@ -2443,9 +2668,10 @@ static __init int intel_pmu_init(void)
 
        version = eax.split.version_id;
        if (version < 2)
-               return -ENODEV;
+               x86_pmu = core_pmu;
+       else
+               x86_pmu = intel_pmu;
 
-       x86_pmu                         = intel_pmu;
        x86_pmu.version                 = version;
        x86_pmu.num_events              = eax.split.num_events;
        x86_pmu.event_bits              = eax.split.bit_width;
@@ -2455,12 +2681,17 @@ static __init int intel_pmu_init(void)
         * Quirk: v2 perfmon does not report fixed-purpose events, so
         * assume at least 3 events:
         */
-       x86_pmu.num_events_fixed        = max((int)edx.split.num_events_fixed, 3);
+       if (version > 1)
+               x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
 
        /*
         * Install the hw-cache-events table:
         */
        switch (boot_cpu_data.x86_model) {
+       case 14: /* 65 nm core solo/duo, "Yonah" */
+               pr_cont("Core events, ");
+               break;
+
        case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
        case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
        case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
@@ -2468,10 +2699,12 @@ static __init int intel_pmu_init(void)
                memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
 
-               x86_pmu.event_constraints = intel_core_event_constraints;
+               x86_pmu.event_constraints = intel_core2_event_constraints;
                pr_cont("Core2 events, ");
                break;
-       case 26:
+
+       case 26: /* 45 nm nehalem, "Bloomfield" */
+       case 30: /* 45 nm nehalem, "Lynnfield" */
                memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
                       sizeof(hw_cache_event_ids));
 
@@ -2485,6 +2718,15 @@ static __init int intel_pmu_init(void)
                x86_pmu.event_constraints = intel_gen_event_constraints;
                pr_cont("Atom events, ");
                break;
+
+       case 37: /* 32 nm nehalem, "Clarkdale" */
+       case 44: /* 32 nm nehalem, "Gulftown" */
+               memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
+                      sizeof(hw_cache_event_ids));
+
+               x86_pmu.event_constraints = intel_westmere_event_constraints;
+               pr_cont("Westmere events, ");
+               break;
        default:
                /*
                 * default constraints for v2 and up
@@ -2495,6 +2737,91 @@ static __init int intel_pmu_init(void)
        return 0;
 }
 
+static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
+{
+       struct amd_nb *nb;
+       int i;
+
+       nb = kmalloc(sizeof(struct amd_nb), GFP_KERNEL);
+       if (!nb)
+               return NULL;
+
+       memset(nb, 0, sizeof(*nb));
+       nb->nb_id = nb_id;
+
+       /*
+        * initialize all possible NB constraints
+        */
+       for (i = 0; i < x86_pmu.num_events; i++) {
+               set_bit(i, nb->event_constraints[i].idxmsk);
+               nb->event_constraints[i].weight = 1;
+       }
+       return nb;
+}
+
+static void amd_pmu_cpu_online(int cpu)
+{
+       struct cpu_hw_events *cpu1, *cpu2;
+       struct amd_nb *nb = NULL;
+       int i, nb_id;
+
+       if (boot_cpu_data.x86_max_cores < 2)
+               return;
+
+       /*
+        * function may be called too early in the
+        * boot process, in which case nb_id is bogus
+        */
+       nb_id = amd_get_nb_id(cpu);
+       if (nb_id == BAD_APICID)
+               return;
+
+       cpu1 = &per_cpu(cpu_hw_events, cpu);
+       cpu1->amd_nb = NULL;
+
+       raw_spin_lock(&amd_nb_lock);
+
+       for_each_online_cpu(i) {
+               cpu2 = &per_cpu(cpu_hw_events, i);
+               nb = cpu2->amd_nb;
+               if (!nb)
+                       continue;
+               if (nb->nb_id == nb_id)
+                       goto found;
+       }
+
+       nb = amd_alloc_nb(cpu, nb_id);
+       if (!nb) {
+               pr_err("perf_events: failed NB allocation for CPU%d\n", cpu);
+               raw_spin_unlock(&amd_nb_lock);
+               return;
+       }
+found:
+       nb->refcnt++;
+       cpu1->amd_nb = nb;
+
+       raw_spin_unlock(&amd_nb_lock);
+}
+
+static void amd_pmu_cpu_offline(int cpu)
+{
+       struct cpu_hw_events *cpuhw;
+
+       if (boot_cpu_data.x86_max_cores < 2)
+               return;
+
+       cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+       raw_spin_lock(&amd_nb_lock);
+
+       if (--cpuhw->amd_nb->refcnt == 0)
+               kfree(cpuhw->amd_nb);
+
+       cpuhw->amd_nb = NULL;
+
+       raw_spin_unlock(&amd_nb_lock);
+}
+
 static __init int amd_pmu_init(void)
 {
        /* Performance-monitoring supported from K7 and later: */
@@ -2507,6 +2834,11 @@ static __init int amd_pmu_init(void)
        memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
               sizeof(hw_cache_event_ids));
 
+       /*
+        * explicitly initialize the boot cpu, other cpus will get
+        * the cpu hotplug callbacks from smp_init()
+        */
+       amd_pmu_cpu_online(smp_processor_id());
        return 0;
 }
 
@@ -2567,7 +2899,8 @@ void __init init_hw_perf_events(void)
        register_die_notifier(&perf_event_nmi_notifier);
 
        unconstrained = (struct event_constraint)
-               EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, 0);
+               __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
+                                  0, x86_pmu.num_events);
 
        pr_info("... version:                %d\n",     x86_pmu.version);
        pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
@@ -2586,6 +2919,8 @@ static inline void x86_pmu_read(struct perf_event *event)
 static const struct pmu pmu = {
        .enable         = x86_pmu_enable,
        .disable        = x86_pmu_disable,
+       .start          = x86_pmu_start,
+       .stop           = x86_pmu_stop,
        .read           = x86_pmu_read,
        .unthrottle     = x86_pmu_unthrottle,
 };
@@ -2594,9 +2929,9 @@ static const struct pmu pmu = {
  * validate a single event group
  *
  * validation include:
- *     - check events are compatible which each other
- *     - events do not compete for the same counter
- *     - number of events <= number of counters
+ *     - check events are compatible which each other
+ *     - events do not compete for the same counter
+ *     - number of events <= number of counters
  *
  * validation ensures the group can be loaded onto the
  * PMU if it was the only group available.
@@ -2837,4 +3172,25 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
 void hw_perf_event_setup_online(int cpu)
 {
        init_debug_store_on_cpu(cpu);
+
+       switch (boot_cpu_data.x86_vendor) {
+       case X86_VENDOR_AMD:
+               amd_pmu_cpu_online(cpu);
+               break;
+       default:
+               return;
+       }
+}
+
+void hw_perf_event_setup_offline(int cpu)
+{
+       init_debug_store_on_cpu(cpu);
+
+       switch (boot_cpu_data.x86_vendor) {
+       case X86_VENDOR_AMD:
+               amd_pmu_cpu_offline(cpu);
+               break;
+       default:
+               return;
+       }
 }