powerpc: Fix page fault with lockdep regression
[linux-2.6.git] / arch / powerpc / kernel / entry_32.S
index 1175a85..ba3aeb4 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
+#include <asm/ptrace.h>
 
 #undef SHOW_SYSCALLS
 #undef SHOW_SYSCALLS_TASK
@@ -205,25 +206,43 @@ reenable_mmu:                             /* re-enable mmu so we can */
        andi.   r10,r10,MSR_EE          /* Did EE change? */
        beq     1f
 
-       /* Save handler and return address into the 2 unused words
-        * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything
-        * else can be recovered from the pt_regs except r3 which for
-        * normal interrupts has been set to pt_regs and for syscalls
-        * is an argument, so we temporarily use ORIG_GPR3 to save it
+       /*
+        * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
+        * If from user mode there is only one stack frame on the stack, and
+        * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
+        * stack frame to make trace_hardirqs_off happy.
+        *
+        * This is handy because we also need to save a bunch of GPRs,
+        * r3 can be different from GPR3(r1) at this point, r9 and r11
+        * contains the old MSR and handler address respectively,
+        * r4 & r5 can contain page fault arguments that need to be passed
+        * along as well. r12, CCR, CTR, XER etc... are left clobbered as
+        * they aren't useful past this point (aren't syscall arguments),
+        * the rest is restored from the exception frame.
         */
+       stwu    r1,-32(r1)
        stw     r9,8(r1)
        stw     r11,12(r1)
-       stw     r3,ORIG_GPR3(r1)
+       stw     r3,16(r1)
+       stw     r4,20(r1)
+       stw     r5,24(r1)
+       andi.   r12,r12,MSR_PR
+       b       11f
+       bl      trace_hardirqs_off
+       b       12f
+11:
        bl      trace_hardirqs_off
+12:
+       lwz     r5,24(r1)
+       lwz     r4,20(r1)
+       lwz     r3,16(r1)
+       lwz     r11,12(r1)
+       lwz     r9,8(r1)
+       addi    r1,r1,32
        lwz     r0,GPR0(r1)
-       lwz     r3,ORIG_GPR3(r1)
-       lwz     r4,GPR4(r1)
-       lwz     r5,GPR5(r1)
        lwz     r6,GPR6(r1)
        lwz     r7,GPR7(r1)
        lwz     r8,GPR8(r1)
-       lwz     r9,8(r1)
-       lwz     r11,12(r1)
 1:     mtctr   r11
        mtlr    r9
        bctr                            /* jump to handler */
@@ -373,11 +392,13 @@ syscall_exit_cont:
        bnel-   load_dbcr0
 #endif
 #ifdef CONFIG_44x
+BEGIN_MMU_FTR_SECTION
        lis     r4,icache_44x_need_flush@ha
        lwz     r5,icache_44x_need_flush@l(r4)
        cmplwi  cr0,r5,0
        bne-    2f
 1:
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
 #endif /* CONFIG_44x */
 BEGIN_FTR_SECTION
        lwarx   r7,0,r1
@@ -848,6 +869,9 @@ resume_kernel:
        /* interrupts are hard-disabled at this point */
 restore:
 #ifdef CONFIG_44x
+BEGIN_MMU_FTR_SECTION
+       b       1f
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
        lis     r4,icache_44x_need_flush@ha
        lwz     r5,icache_44x_need_flush@l(r4)
        cmplwi  cr0,r5,0
@@ -874,7 +898,18 @@ restore:
         */
        andi.   r10,r9,MSR_EE
        beq     1f
+       /*
+        * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
+        * which is the stack frame here, we need to force a stack frame
+        * in case we came from user space.
+        */
+       stwu    r1,-32(r1)
+       mflr    r0
+       stw     r0,4(r1)
+       stwu    r1,-32(r1)
        bl      trace_hardirqs_on
+       lwz     r1,0(r1)
+       lwz     r1,0(r1)
        lwz     r9,_MSR(r1)
 1:
 #endif /* CONFIG_TRACE_IRQFLAGS */
@@ -1181,7 +1216,7 @@ do_user_signal:                   /* r10 contains MSR_KERNEL here */
        stw     r3,_TRAP(r1)
 2:     addi    r3,r1,STACK_FRAME_OVERHEAD
        mr      r4,r9
-       bl      do_signal
+       bl      do_notify_resume
        REST_NVGPRS(r1)
        b       recheck