Merge branches 'sched-core-for-linus' and 'sched-urgent-for-linus' of git://git.kerne...
[linux-2.6.git] / arch / mips / mti-malta / malta-int.c
index bc0ba58..1d36c51 100644 (file)
@@ -25,7 +25,6 @@
 #include <linux/irq.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
-#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/kernel_stat.h>
@@ -52,12 +51,11 @@ static unsigned long _msc01_biu_base;
 static unsigned long _gcmp_base;
 static unsigned int ipi_map[NR_CPUS];
 
-static DEFINE_SPINLOCK(mips_irq_lock);
+static DEFINE_RAW_SPINLOCK(mips_irq_lock);
 
 static inline int mips_pcibios_iack(void)
 {
        int irq;
-       u32 dummy;
 
        /*
         * Determine highest priority pending interrupt by performing
@@ -84,10 +82,10 @@ static inline int mips_pcibios_iack(void)
                BONITO_PCIMAP_CFG = 0x20000;
 
                /* Flush Bonito register block */
-               dummy = BONITO_PCIMAP_CFG;
+               (void) BONITO_PCIMAP_CFG;
                iob();    /* sync */
 
-               irq = readl((u32 *)_pcictrl_bonito_pcicfg);
+               irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
                iob();    /* sync */
                irq &= 0xff;
                BONITO_PCIMAP_CFG = 0;
@@ -103,7 +101,7 @@ static inline int get_int(void)
 {
        unsigned long flags;
        int irq;
-       spin_lock_irqsave(&mips_irq_lock, flags);
+       raw_spin_lock_irqsave(&mips_irq_lock, flags);
 
        irq = mips_pcibios_iack();
 
@@ -113,7 +111,7 @@ static inline int get_int(void)
         * on an SMP system,  so leave it up to the generic code...
         */
 
-       spin_unlock_irqrestore(&mips_irq_lock, flags);
+       raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
 
        return irq;
 }
@@ -310,6 +308,8 @@ static void ipi_call_dispatch(void)
 
 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 {
+       scheduler_ipi();
+
        return IRQ_HANDLED;
 }
 
@@ -331,6 +331,7 @@ static struct irqaction irq_call = {
        .flags          = IRQF_DISABLED|IRQF_PERCPU,
        .name           = "IPI_call"
 };
+#endif /* CONFIG_MIPS_MT_SMP */
 
 static int gic_resched_int_base;
 static int gic_call_int_base;
@@ -346,7 +347,6 @@ unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
 {
        return GIC_RESCHED_INT(cpu);
 }
-#endif /* CONFIG_MIPS_MT_SMP */
 
 static struct irqaction i8259irq = {
        .handler = no_action,
@@ -379,38 +379,46 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
 
 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 
-#if defined(CONFIG_MIPS_MT_SMP)
 /*
  * This GIC specific tabular array defines the association between External
  * Interrupts and CPUs/Core Interrupts. The nature of the External
  * Interrupts is also defined here - polarity/trigger.
  */
+
+#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
+#define X GIC_UNUSED
+
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
-       { GIC_EXT_INTR(0),      X,      X,              X,              X,              0 },
-       { GIC_EXT_INTR(1),      X,      X,              X,              X,              0 },
-       { GIC_EXT_INTR(2),      X,      X,              X,              X,              0 },
-       { GIC_EXT_INTR(3),      0,      GIC_CPU_INT0,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(4),      0,      GIC_CPU_INT1,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(5),      0,      GIC_CPU_INT2,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(6),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(7),      0,      GIC_CPU_INT4,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(8),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(9),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(10),     X,      X,              X,              X,              0 },
-       { GIC_EXT_INTR(11),     X,      X,              X,              X,              0 },
-       { GIC_EXT_INTR(12),     0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
-       { GIC_EXT_INTR(13),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
-       { GIC_EXT_INTR(14),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
-       { GIC_EXT_INTR(15),     X,      X,              X,              X,              0 },
-/* This is the end of the general interrupts now we do IPI ones */
+       { X, X,            X,           X,              0 },
+       { X, X,            X,           X,              0 },
+       { X, X,            X,           X,              0 },
+       { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { X, X,            X,           X,              0 },
+       { X, X,            X,           X,              0 },
+       { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+       { X, X,            X,           X,              0 },
+       /* The remainder of this table is initialised by fill_ipi_map */
 };
-#endif
+#undef X
 
 /*
  * GCMP needs to be detected before any SMP initialisation
  */
-static int __init gcmp_probe(unsigned long addr, unsigned long size)
+int __init gcmp_probe(unsigned long addr, unsigned long size)
 {
+       if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
+               gcmp_present = 0;
+               return gcmp_present;
+       }
+
        if (gcmp_present >= 0)
                return gcmp_present;
 
@@ -419,20 +427,35 @@ static int __init gcmp_probe(unsigned long addr, unsigned long size)
        gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
 
        if (gcmp_present)
-               printk(KERN_DEBUG "GCMP present\n");
+               pr_debug("GCMP present\n");
        return gcmp_present;
 }
 
+/* Return the number of IOCU's present */
+int __init gcmp_niocu(void)
+{
+  return gcmp_present ?
+    (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
+    0;
+}
+
+/* Set GCMP region attributes */
+void __init gcmp_setregion(int region, unsigned long base,
+                          unsigned long mask, int type)
+{
+       GCMPGCBn(CMxBASE, region) = base;
+       GCMPGCBn(CMxMASK, region) = mask | type;
+}
+
 #if defined(CONFIG_MIPS_MT_SMP)
 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
 {
        int intr = baseintr + cpu;
-       gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
        gic_intr_map[intr].cpunum = cpu;
        gic_intr_map[intr].pin = cpupin;
        gic_intr_map[intr].polarity = GIC_POL_POS;
        gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
-       gic_intr_map[intr].ipiflag = 1;
+       gic_intr_map[intr].flags = GIC_FLAG_IPI;
        ipi_map[cpu] |= (1 << (cpupin + 2));
 }
 
@@ -447,26 +470,34 @@ static void __init fill_ipi_map(void)
 }
 #endif
 
-void __init arch_init_irq(void)
+void __init arch_init_ipiirq(int irq, struct irqaction *action)
 {
-       int gic_present, gcmp_present;
+       setup_irq(irq, action);
+       irq_set_handler(irq, handle_percpu_irq);
+}
 
+void __init arch_init_irq(void)
+{
        init_i8259_irqs();
 
        if (!cpu_has_veic)
                mips_cpu_irq_init();
 
-       gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
        if (gcmp_present)  {
                GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
                gic_present = 1;
        } else {
-               _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
-               gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
-               MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
+               if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
+                       _msc01_biu_base = (unsigned long)
+                                       ioremap_nocache(MSC01_BIU_REG_BASE,
+                                               MSC01_BIU_ADDRSPACE_SZ);
+                       gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
+                                       MSC01_SC_CFG_GICPRES_MSK) >>
+                                       MSC01_SC_CFG_GICPRES_SHF;
+               }
        }
        if (gic_present)
-               printk(KERN_DEBUG "GIC present\n");
+               pr_debug("GIC present\n");
 
        switch (mips_revision_sconid) {
        case MIPS_REVISION_SCON_SOCIT:
@@ -529,16 +560,16 @@ void __init arch_init_irq(void)
                                                &corehi_irqaction);
        }
 
-#if defined(CONFIG_MIPS_MT_SMP)
        if (gic_present) {
                /* FIXME */
                int i;
-
+#if defined(CONFIG_MIPS_MT_SMP)
                gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
                gic_resched_int_base = gic_call_int_base - NR_CPUS;
-
                fill_ipi_map();
-               gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
+#endif
+               gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
+                               ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
                if (!gcmp_present) {
                        /* Enable the GIC */
                        i = REG(_msc01_biu_base, MSC01_SC_CFG);
@@ -546,7 +577,7 @@ void __init arch_init_irq(void)
                                (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
                        pr_debug("GIC Enabled\n");
                }
-
+#if defined(CONFIG_MIPS_MT_SMP)
                /* set up ipi interrupts */
                if (cpu_has_vint) {
                        set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
@@ -559,16 +590,14 @@ void __init arch_init_irq(void)
                write_c0_status(0x1100dc00);
                printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
                for (i = 0; i < NR_CPUS; i++) {
-                       setup_irq(MIPS_GIC_IRQ_BASE +
-                                       GIC_RESCHED_INT(i), &irq_resched);
-                       setup_irq(MIPS_GIC_IRQ_BASE +
-                                       GIC_CALL_INT(i), &irq_call);
-                       set_irq_handler(MIPS_GIC_IRQ_BASE +
-                                       GIC_RESCHED_INT(i), handle_percpu_irq);
-                       set_irq_handler(MIPS_GIC_IRQ_BASE +
-                                       GIC_CALL_INT(i), handle_percpu_irq);
+                       arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
+                                        GIC_RESCHED_INT(i), &irq_resched);
+                       arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
+                                        GIC_CALL_INT(i), &irq_call);
                }
+#endif
        } else {
+#if defined(CONFIG_MIPS_MT_SMP)
                /* set up ipi interrupts */
                if (cpu_has_veic) {
                        set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
@@ -583,14 +612,10 @@ void __init arch_init_irq(void)
                        cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
                        cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
                }
-
-               setup_irq(cpu_ipi_resched_irq, &irq_resched);
-               setup_irq(cpu_ipi_call_irq, &irq_call);
-
-               set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
-               set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
-       }
+               arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
+               arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
 #endif
+       }
 }
 
 void malta_be_init(void)