include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6.git] / arch / avr32 / mach-at32ap / clock.c
index 49e7b12..442f08c 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2006 Atmel Corporation
  *
- * Based on arch/arm/mach-at91rm9200/clock.c
+ * Based on arch/arm/mach-at91/clock.c
  *   Copyright (C) 2005 David Brownell
  *   Copyright (C) 2005 Ivan Kokshaysky
  *
 #include <linux/err.h>
 #include <linux/device.h>
 #include <linux/string.h>
+#include <linux/list.h>
+
+#include <mach/chip.h>
 
 #include "clock.h"
 
-static spinlock_t clk_lock = SPIN_LOCK_UNLOCKED;
+/* at32 clock list */
+static LIST_HEAD(at32_clock_list);
+
+static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(clk_list_lock);
+
+void at32_clk_register(struct clk *clk)
+{
+       spin_lock(&clk_list_lock);
+       /* add the new item to the end of the list */
+       list_add_tail(&clk->list, &at32_clock_list);
+       spin_unlock(&clk_list_lock);
+}
 
 struct clk *clk_get(struct device *dev, const char *id)
 {
-       int i;
+       struct clk *clk;
 
-       for (i = 0; i < at32_nr_clocks; i++) {
-               struct clk *clk = at32_clock_list[i];
+       spin_lock(&clk_list_lock);
 
-               if (clk->dev == dev && strcmp(id, clk->name) == 0)
+       list_for_each_entry(clk, &at32_clock_list, list) {
+               if (clk->dev == dev && strcmp(id, clk->name) == 0) {
+                       spin_unlock(&clk_list_lock);
                        return clk;
+               }
        }
 
+       spin_unlock(&clk_list_lock);
        return ERR_PTR(-ENOENT);
 }
 EXPORT_SYMBOL(clk_get);
@@ -150,3 +168,131 @@ struct clk *clk_get_parent(struct clk *clk)
        return clk->parent;
 }
 EXPORT_SYMBOL(clk_get_parent);
+
+
+
+#ifdef CONFIG_DEBUG_FS
+
+/* /sys/kernel/debug/at32ap_clk */
+
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include "pm.h"
+
+
+#define        NEST_DELTA      2
+#define        NEST_MAX        6
+
+struct clkinf {
+       struct seq_file *s;
+       unsigned        nest;
+};
+
+static void
+dump_clock(struct clk *parent, struct clkinf *r)
+{
+       unsigned        nest = r->nest;
+       char            buf[16 + NEST_MAX];
+       struct clk      *clk;
+       unsigned        i;
+
+       /* skip clocks coupled to devices that aren't registered */
+       if (parent->dev && !dev_name(parent->dev) && !parent->users)
+               return;
+
+       /* <nest spaces> name <pad to end> */
+       memset(buf, ' ', sizeof(buf) - 1);
+       buf[sizeof(buf) - 1] = 0;
+       i = strlen(parent->name);
+       memcpy(buf + nest, parent->name,
+                       min(i, (unsigned)(sizeof(buf) - 1 - nest)));
+
+       seq_printf(r->s, "%s%c users=%2d %-3s %9ld Hz",
+               buf, parent->set_parent ? '*' : ' ',
+               parent->users,
+               parent->users ? "on" : "off",   /* NOTE: not-paranoid!! */
+               clk_get_rate(parent));
+       if (parent->dev)
+               seq_printf(r->s, ", for %s", dev_name(parent->dev));
+       seq_printf(r->s, "\n");
+
+       /* cost of this scan is small, but not linear... */
+       r->nest = nest + NEST_DELTA;
+
+       list_for_each_entry(clk, &at32_clock_list, list) {
+               if (clk->parent == parent)
+                       dump_clock(clk, r);
+       }
+       r->nest = nest;
+}
+
+static int clk_show(struct seq_file *s, void *unused)
+{
+       struct clkinf   r;
+       int             i;
+       struct clk      *clk;
+
+       /* show all the power manager registers */
+       seq_printf(s, "MCCTRL  = %8x\n", pm_readl(MCCTRL));
+       seq_printf(s, "CKSEL   = %8x\n", pm_readl(CKSEL));
+       seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
+       seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
+       seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
+       seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
+       seq_printf(s, "PLL0    = %8x\n", pm_readl(PLL0));
+       seq_printf(s, "PLL1    = %8x\n", pm_readl(PLL1));
+       seq_printf(s, "IMR     = %8x\n", pm_readl(IMR));
+       for (i = 0; i < 8; i++) {
+               if (i == 5)
+                       continue;
+               seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
+       }
+
+       seq_printf(s, "\n");
+
+       r.s = s;
+       r.nest = 0;
+       /* protected from changes on the list while dumping */
+       spin_lock(&clk_list_lock);
+
+       /* show clock tree as derived from the three oscillators */
+       clk = clk_get(NULL, "osc32k");
+       dump_clock(clk, &r);
+       clk_put(clk);
+
+       clk = clk_get(NULL, "osc0");
+       dump_clock(clk, &r);
+       clk_put(clk);
+
+       clk = clk_get(NULL, "osc1");
+       dump_clock(clk, &r);
+       clk_put(clk);
+
+       spin_unlock(&clk_list_lock);
+
+       return 0;
+}
+
+static int clk_open(struct inode *inode, struct file *file)
+{
+       return single_open(file, clk_show, NULL);
+}
+
+static const struct file_operations clk_operations = {
+       .open           = clk_open,
+       .read           = seq_read,
+       .llseek         = seq_lseek,
+       .release        = single_release,
+};
+
+static int __init clk_debugfs_init(void)
+{
+       (void) debugfs_create_file("at32ap_clk", S_IFREG | S_IRUGO,
+                       NULL, NULL, &clk_operations);
+
+       return 0;
+}
+postcore_initcall(clk_debugfs_init);
+
+#endif