Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / arm / mm / proc-xscale.S
index d29fe92..f056c28 100644 (file)
  *
  * 2001 Sep 08:
  *     Completely revisited, many important fixes
- *     Nicolas Pitre <nico@cam.org>
+ *     Nicolas Pitre <nico@fluxnic.net>
  */
 
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/elf.h>
+#include <asm/hwcap.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
@@ -114,6 +114,10 @@ clean_addr:        .word   CLEAN_ADDR
  * Nothing too exciting at the moment
  */
 ENTRY(cpu_xscale_proc_init)
+       @ enable write buffer coalescing. Some bootloader disable it
+       mrc     p15, 0, r1, c1, c0, 1
+       bic     r1, r1, #1
+       mcr     p15, 0, r1, c1, c0, 1
        mov     pc, lr
 
 /*
@@ -402,8 +406,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
 
 /* =============================== PageTable ============================== */
 
-#define PTE_CACHE_WRITE_ALLOCATE 0
-
 /*
  * cpu_xscale_switch_mm(pgd)
  *
@@ -427,56 +429,42 @@ ENTRY(cpu_xscale_switch_mm)
  *
  * Errata 40: must set memory to write-through for user read-only pages.
  */
+cpu_xscale_mt_table:
+       .long   0x00                                            @ L_PTE_MT_UNCACHED
+       .long   PTE_BUFFERABLE                                  @ L_PTE_MT_BUFFERABLE
+       .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
+       .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
+       .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
+       .long   0x00                                            @ unused
+       .long   PTE_EXT_TEX(1) | PTE_CACHEABLE                  @ L_PTE_MT_MINICACHE
+       .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
+       .long   0x00                                            @ unused
+       .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_WC
+       .long   0x00                                            @ unused
+       .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
+       .long   0x00                                            @ L_PTE_MT_DEV_NONSHARED
+       .long   0x00                                            @ unused
+       .long   0x00                                            @ unused
+       .long   0x00                                            @ unused
+
        .align  5
 ENTRY(cpu_xscale_set_pte_ext)
-       str     r1, [r0], #-2048                @ linux version
-
-       bic     r2, r1, #0xff0
-       orr     r2, r2, #PTE_TYPE_EXT           @ extended page
-
-       eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
-
-       tst     r3, #L_PTE_USER                 @ User?
-       orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
-
-       tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
-       orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
-                                               @ combined with user -> user r/w
+       xscale_set_pte_ext_prologue
 
        @
-       @ Handle the X bit.  We want to set this bit for the minicache
-       @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
-       @ and we have a writeable, cacheable region.  If we ignore the
-       @ U and E bits, we can allow user space to use the minicache as
-       @ well.
+       @ Erratum 40: must set memory to write-through for user read-only pages
        @
-       @  X = (C & ~W & ~B) | (C & W & B & write_allocate)
-       @
-       eor     ip, r1, #L_PTE_CACHEABLE
-       tst     ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-#if PTE_CACHE_WRITE_ALLOCATE
-       eorne   ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-       tstne   ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
-#endif
-       orreq   r2, r2, #PTE_EXT_TEX(1)
+       and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
+       teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
 
-       @
-       @ Erratum 40: The B bit must be cleared for a user read-only
-       @ cacheable page.
-       @
-       @  B = B & ~(U & C & ~W)
-       @
-       and     ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
-       teq     ip, #L_PTE_USER | L_PTE_CACHEABLE
-       biceq   r2, r2, #PTE_BUFFERABLE
+       moveq   r1, #L_PTE_MT_WRITETHROUGH
+       and     r1, r1, #L_PTE_MT_MASK
+       adr     ip, cpu_xscale_mt_table
+       ldr     ip, [ip, r1]
+       bic     r2, r2, #0x0c
+       orr     r2, r2, ip
 
-       tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
-       movne   r2, #0                          @ no -> fault
-
-       str     r2, [r0]                        @ hardware version
-       mov     ip, #0
-       mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
-       mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
+       xscale_set_pte_ext_epilogue
        mov     pc, lr
 
 
@@ -523,6 +511,7 @@ xscale_crval:
        .type   xscale_processor_functions, #object
 ENTRY(xscale_processor_functions)
        .word   v5t_early_abort
+       .word   legacy_pabort
        .word   cpu_xscale_proc_init
        .word   cpu_xscale_proc_fin
        .word   cpu_xscale_reset
@@ -584,6 +573,11 @@ cpu_ixp42x_name:
        .asciz  "XScale-IXP42x Family"
        .size   cpu_ixp42x_name, . - cpu_ixp42x_name
 
+       .type   cpu_ixp43x_name, #object
+cpu_ixp43x_name:
+       .asciz  "XScale-IXP43x Family"
+       .size   cpu_ixp43x_name, . - cpu_ixp43x_name
+
        .type   cpu_ixp46x_name, #object
 cpu_ixp46x_name:
        .asciz  "XScale-IXP46x Family"
@@ -843,6 +837,29 @@ __ixp42x_proc_info:
        .long   xscale_cache_fns
        .size   __ixp42x_proc_info, . - __ixp42x_proc_info                
 
+       .type   __ixp43x_proc_info, #object
+__ixp43x_proc_info:
+       .long   0x69054040
+       .long   0xfffffff0
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       b       __xscale_setup
+       .long   cpu_arch_name
+       .long   cpu_elf_name
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   cpu_ixp43x_name
+       .long   xscale_processor_functions
+       .long   v4wbi_tlb_fns
+       .long   xscale_mc_user_fns
+       .long   xscale_cache_fns
+       .size   __ixp43x_proc_info, . - __ixp43x_proc_info
+
        .type   __ixp46x_proc_info, #object
 __ixp46x_proc_info:
        .long   0x69054200