#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/syscore_ops.h>
+#include <linux/platform_device.h>
#include <asm/clkdev.h>
#include "dvfs.h"
#include "pm.h"
#include "sleep.h"
+#include "devices.h"
#include "tegra11_emc.h"
#include "tegra_cl_dvfs.h"
#define PLL_FIXED_MDIV(c, ref) ((ref) > (c)->u.pll.cf_max ? 2 : 1)
/* PLLU */
+#define PLLU_BASE_OVERRIDE (1<<24)
#define PLLU_BASE_POST_DIV (1<<20)
/* PLLD */
#define PLLCX_MISC_KOEF_LOW_RANGE \
((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
-#define PLLCX_MISC_KOEF_HIGH_RANGE \
- ((0x10 << PLLCX_MISC_KA_SHIFT) | (0xA0 << PLLCX_MISC_KB_SHIFT))
+
+#define PLLCX_MISC_DIV_LOW_RANGE \
+ ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE \
+ ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
#define PLLCX_MISC_DEFAULT_VALUE ((0x0 << PLLCX_MISC_VCO_GAIN_SHIFT) | \
PLLCX_MISC_KOEF_LOW_RANGE | \
(0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
- (0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
- (0x2 << PLLCX_MISC_FILT_DIV_SHIFT) | \
+ PLLCX_MISC_DIV_LOW_RANGE | \
PLLCX_MISC_RESET)
-#define PLLCX_MISC1_DEFAULT_VALUE 0x00132308
-#define PLLCX_MISC2_DEFAULT_VALUE 0x11111100
-#define PLLCX_MISC3_DEFAULT_VALUE 0x0
+#define PLLCX_MISC1_DEFAULT_VALUE 0x000d2308
+#define PLLCX_MISC2_DEFAULT_VALUE 0x30211200
+#define PLLCX_MISC3_DEFAULT_VALUE 0x200
/* PLLX and PLLC (PLLXC)*/
#define PLLXC_USE_DYN_RAMP 0
#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
#define UTMIP_PLL_CFG1 0x484
#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
-#define PLLE_BASE_CML_ENABLE (1<<31)
-#define PLLE_BASE_ENABLE (1<<30)
+/* PLLE */
+#define PLLE_BASE_LOCK_OVERRIDE (0x1 << 29)
#define PLLE_BASE_DIVCML_SHIFT 24
#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
-#define PLLE_BASE_DIVP_SHIFT 16
-#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
-#define PLLE_BASE_DIVN_SHIFT 8
-#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
-#define PLLE_BASE_DIVM_SHIFT 0
-#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
-#define PLLE_BASE_DIV_MASK \
- (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
- PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
-#define PLLE_BASE_DIV(m, n, p, cml) \
- (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
- ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
-
-#define PLLE_MISC_SETUP_BASE_SHIFT 16
-#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
+#define PLLE_BASE_DIVN_MASK (0xFF<<PLL_BASE_DIVN_SHIFT)
+#define PLLE_BASE_DIVM_MASK (0xFF<<PLL_BASE_DIVM_SHIFT)
+
+/* PLLE has 4-bit CMLDIV, but entry 15 is not allowed in h/w */
+#define PLLE_CMLDIV_MAX 14
+
#define PLLE_MISC_READY (1<<15)
+#define PLLE_MISC_IDDQ_SW_CTRL (1<<14)
+#define PLLE_MISC_IDDQ_SW_VALUE (1<<13)
#define PLLE_MISC_LOCK (1<<11)
#define PLLE_MISC_LOCK_ENABLE (1<<9)
-#define PLLE_MISC_SETUP_EX_SHIFT 2
-#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
-#define PLLE_MISC_SETUP_MASK \
- (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
-#define PLLE_MISC_SETUP_VALUE \
- ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
+#define PLLE_MISC_PLLE_PTS (1<<8)
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
+#define PLLE_MISC_VREG_BG_CTRL_MASK (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT 2
+#define PLLE_MISC_VREG_CTRL_MASK (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
#define PLLE_SS_CTRL 0x68
#define PLLE_SS_INCINTRV_SHIFT 24
#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
#define PLLE_SS_INC_SHIFT 16
#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_CNTL_SSC_BYP (0x1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (0x1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (0x1 << 10)
#define PLLE_SS_MAX_SHIFT 0
#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
#define PLLE_SS_COEFFICIENTS_MASK \
(PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
-#define PLLE_SS_COEFFICIENTS_12MHZ \
- ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
- (0x24<<PLLE_SS_MAX_SHIFT))
-#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
+#define PLLE_SS_COEFFICIENTS_VAL \
+ ((0x20<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+ (0x25<<PLLE_SS_MAX_SHIFT))
+#define PLLE_SS_DISABLE (PLLE_SS_CNTL_SSC_BYP |\
+ PLLE_SS_CNTL_INTERP_RESET | PLLE_SS_CNTL_BYPASS_SS)
#define PLLE_AUX 0x48c
+#define PLLE_AUX_PLLRE_SEL (1<<28)
+#define PLLE_AUX_SEQ_STATE_SHIFT 26
+#define PLLE_AUX_SEQ_STATE_MASK (0x3<<PLLE_AUX_SEQ_STATE_SHIFT)
+#define PLLE_AUX_SEQ_START_STATE (1<<25)
+#define PLLE_AUX_SEQ_ENABLE (1<<24)
+#define PLLE_AUX_SS_SWCTL (1<<6)
+#define PLLE_AUX_ENABLE_SWCTL (1<<4)
+#define PLLE_AUX_USE_LOCKDET (1<<3)
#define PLLE_AUX_PLLP_SEL (1<<2)
-#define PMC_SATA_PWRGT 0x1ac
-#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
-#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
+/* USB PLLs PD HW controls */
+#define XUSBIO_PLL_CFG0 0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1<<25)
+#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1<<24)
+#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1<<6)
+#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1<<0)
+
+/* XUSB PLL PAD controls */
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1 0x30
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD (1<<3)
+#define XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ (1<<0)
+
+#define UTMIPLL_HW_PWRDN_CFG0 0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
+#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1<<5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1<<4)
+#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1<<1)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1<<0)
+
+#define PLLU_HW_PWRDN_CFG0 0x530
+#define PLLU_HW_PWRDN_CFG0_SEQ_START_STATE (1<<25)
+#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1<<24)
+#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1<<6)
+#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1<<2)
+#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1<<0)
+
+#define USB_PLLS_SEQ_START_STATE (1<<25)
+#define USB_PLLS_SEQ_ENABLE (1<<24)
+#define USB_PLLS_USE_LOCKDET (1<<6)
+#define USB_PLLS_ENABLE_SWCTL ((1<<2) | (1<<0))
+
+/* DFLL */
+#define DFLL_BASE 0x2f4
+#define DFLL_BASE_RESET (1<<0)
+
+#define LVL2_CLK_GATE_OVRE 0x554
#define ROUND_DIVIDER_UP 0
#define ROUND_DIVIDER_DOWN 1
+#define DIVIDER_1_5_ALLOWED 0
/* PLLP default fixed rate in h/w controlled mode */
#define PLLP_DEFAULT_FIXED_RATE 216000000
+/* Use PLL_RE as PLLE input (default - OSC via pll reference divider) */
+#define USE_PLLE_INPUT_PLLRE 0
+
static bool tegra11_is_dyn_ramp(struct clk *c,
unsigned long rate, bool from_vco_min);
static void tegra11_pllp_init_dependencies(unsigned long pllp_rate);
static bool detach_shared_bus;
module_param(detach_shared_bus, bool, 0644);
-static bool use_dfll;
-module_param(use_dfll, bool, 0644);
+static int use_dfll;
/**
* Structure defining the fields for USB UTMI clocks Parameters.
static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
static void __iomem *misc_gp_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+static void __iomem *reg_xusb_padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE);
#define MISC_GP_HIDREV 0x804
#define MISC_GP_TRANSACTOR_SCRATCH_0 0x864
__raw_readl((u32)reg_pmc_base + (reg))
#define chipid_readl() \
__raw_readl((u32)misc_gp_base + MISC_GP_HIDREV)
+#define xusb_padctl_writel(value, reg) \
+ __raw_writel(value, (u32)reg_xusb_padctl_base + (reg))
+#define xusb_padctl_readl(reg) \
+ __raw_readl((u32)reg_xusb_padctl_base + (reg))
#define clk_writel_delay(value, reg) \
do { \
if (divider_ux1 - 2 > max_x)
return -EINVAL;
+#if !DIVIDER_1_5_ALLOWED
+ if (divider_ux1 == 3)
+ divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
+#endif
return divider_ux1 - 2;
}
return divider_u16 - 1;
}
+static inline bool bus_user_is_slower(struct clk *a, struct clk *b)
+{
+ return a->u.shared_bus_user.client->max_rate * a->div <
+ b->u.shared_bus_user.client->max_rate * b->div;
+}
+
+static inline bool bus_user_request_is_lower(struct clk *a, struct clk *b)
+{
+ return a->u.shared_bus_user.rate * a->div <
+ b->u.shared_bus_user.rate * b->div;
+}
+
/* clk_m functions */
static unsigned long tegra11_clk_m_autodetect_rate(struct clk *c)
{
val |= SUPER_LP_DIV2_BYPASS;
clk_writel_delay(val, c->reg);
}
- if (c->flags & DIV_2)
- source |= val & SUPER_LP_DIV2_BYPASS;
for (sel = c->inputs; sel->input != NULL; sel++) {
if (sel->value == source)
BUG_ON(sel->input == NULL);
c->parent = sel->input;
+ /* Update parent in case when LP CPU PLLX DIV2 bypassed */
+ if ((c->flags & DIV_2) && (c->parent->flags & PLLX) &&
+ (val & SUPER_LP_DIV2_BYPASS))
+ c->parent = c->parent->parent;
+
if (c->flags & DIV_U71) {
c->mul = 2;
c->div = 2;
if (dramp)
goto out;
} else if (old_rate > vco_min) {
+#if PLLXC_USE_DYN_RAMP
pr_warn("No dynamic ramp down: %s: %lu to %lu\n",
c->u.cpu.main->name, old_rate, vco_min);
+#endif
}
}
if (rate > vco_min) {
if (tegra11_is_dyn_ramp(c->u.cpu.main, rate, true))
main_rate = vco_min;
+#if PLLXC_USE_DYN_RAMP
else
pr_warn("No dynamic ramp up: %s: %lu to %lu\n",
c->u.cpu.main->name, vco_min, rate);
+#endif
}
ret = clk_set_rate(c->u.cpu.main, main_rate);
{
int ret;
struct clk *dfll = c->u.cpu.dynamic;
+ unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
/* dfll rate request */
ret = clk_set_rate(dfll, rate);
/* 1st time - switch to dfll */
if (c->parent->parent != dfll) {
+ if (max(old_rate, rate) < dfll_rate_min) {
+ /* set interim cpu dvfs rate at dfll_rate_min to
+ prevent voltage drop below dfll Vmin */
+ ret = tegra_dvfs_set_rate(c, dfll_rate_min);
+ if (ret) {
+ pr_err("Failed to set cpu dvfs rate %lu\n",
+ dfll_rate_min);
+ return ret;
+ }
+ }
+
ret = clk_set_parent(c->parent, dfll);
if (ret) {
pr_err("Failed to switch cpu to %s\n", dfll->name);
return ret;
}
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
- if (ret) {
- pr_err("Failed to lock %s\n", dfll->name);
- return ret;
- }
+ WARN(ret, "Failed to lock %s at rate %lu\n", dfll->name, rate);
+
/* prevent legacy dvfs voltage scaling */
- if (c->dvfs && c->dvfs->dvfs_rail)
- c->dvfs->dvfs_rail->dfll_mode = true;
+ tegra_dvfs_dfll_mode_set(c->dvfs, rate);
}
return 0;
}
unsigned long old_rate)
{
int ret;
+ struct clk *pll;
struct clk *dfll = c->u.cpu.dynamic;
- struct clk *pll = (old_rate <= c->u.cpu.backup_rate) ?
- c->u.cpu.backup : c->u.cpu.main;
+ unsigned long dfll_rate_min = c->dvfs->dfll_data.use_dfll_rate_min;
+
+ rate = min(rate, c->max_rate - c->dvfs->dfll_data.max_rate_boost);
+ pll = (rate <= c->u.cpu.backup_rate) ? c->u.cpu.backup : c->u.cpu.main;
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
if (ret) {
pr_err("Failed to unlock %s\n", dfll->name);
- return ret;
+ goto back_to_dfll;
}
/* restore legacy dvfs operations and set appropriate voltage */
- if (c->dvfs && c->dvfs->dvfs_rail)
- c->dvfs->dvfs_rail->dfll_mode = false;
-
- rate = max(rate, old_rate);
- ret = tegra_dvfs_set_rate(c, rate);
+ ret = tegra_dvfs_dfll_mode_clear(c->dvfs, max(rate, dfll_rate_min));
if (ret) {
pr_err("Failed to set cpu rail for rate %lu\n", rate);
- return ret;
+ goto back_to_dfll;
}
- /* set pll rate same as dfll old rate, and return to pll source */
- ret = clk_set_rate(pll, old_rate);
+ /* set pll to target rate and return to pll source */
+ ret = clk_set_rate(pll, rate);
if (ret) {
pr_err("Failed to set cpu rate %lu on source"
- " %s\n", old_rate, pll->name);
- return ret;
+ " %s\n", rate, pll->name);
+ goto back_to_dfll;
}
ret = clk_set_parent(c->parent, pll);
if (ret) {
pr_err("Failed to switch cpu to %s\n", pll->name);
- return ret;
+ goto back_to_dfll;
}
+
+ /* If going up, adjust voltage here (down path is taken care of by the
+ framework after set rate exit) */
+ if (old_rate <= rate)
+ tegra_dvfs_set_rate(c, rate);
+
return 0;
+
+back_to_dfll:
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ tegra_dvfs_dfll_mode_set(c->dvfs, old_rate);
+ return ret;
}
static int tegra11_cpu_clk_set_rate(struct clk *c, unsigned long rate)
}
}
#endif
- if (has_dfll) {
- if (use_dfll)
+ if (has_dfll && c->dvfs && c->dvfs->dvfs_rail) {
+ if (tegra_dvfs_is_dfll_range(c->dvfs, rate))
return tegra11_cpu_clk_dfll_on(c, rate, old_rate);
- else if (is_dfll) {
- int ret = tegra11_cpu_clk_dfll_off(c, rate, old_rate);
- if (ret)
- return ret;
- }
+ else if (is_dfll)
+ return tegra11_cpu_clk_dfll_off(c, rate, old_rate);
}
return tegra11_cpu_clk_set_plls(c, rate, old_rate);
}
+static long tegra11_cpu_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long max_rate = c->max_rate;
+
+ /* Remove dfll boost to maximum rate when running on PLL */
+ if (!c->dvfs || !tegra_dvfs_is_dfll_scale(c->dvfs, rate))
+ max_rate -= c->dvfs->dfll_data.max_rate_boost;
+
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < c->min_rate)
+ rate = c->min_rate;
+ return rate;
+}
+
static struct clk_ops tegra_cpu_ops = {
.init = tegra11_cpu_clk_init,
.enable = tegra11_cpu_clk_enable,
.disable = tegra11_cpu_clk_disable,
.set_rate = tegra11_cpu_clk_set_rate,
+ .round_rate = tegra11_cpu_clk_round_rate,
};
spin_unlock(¶meters_lock);
if (flags) {
- /* over-clocking after the switch - allow, but lower rate */
- if (rate > p->max_rate) {
- rate = p->max_rate;
+ /* over/under-clocking after switch - allow, but update rate */
+ if ((rate > p->max_rate) || (rate < p->min_rate)) {
+ rate = rate > p->max_rate ? p->max_rate : p->min_rate;
ret = clk_set_rate(c->parent, rate);
if (ret) {
pr_err("%s: Failed to set rate %lu for %s\n",
} else
#endif
{
- if (p == c->parent) /* already switched - exit*/
- return 0;
-
if (rate > p->max_rate) { /* over-clocking - no switch */
pr_warn("%s: No %s mode switch to %s at rate %lu\n",
__func__, c->name, p->name, rate);
flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP :
TEGRA_POWER_CLUSTER_G;
+ if (p == c->parent) {
+ if (flags & TEGRA_POWER_CLUSTER_FORCE) {
+ /* Allow parameterized switch to the same mode */
+ ret = tegra_cluster_control(delay, flags);
+ if (ret)
+ pr_err("%s: Failed to force %s mode to %s\n",
+ __func__, c->name, p->name);
+ return ret;
+ }
+ return 0; /* already switched - exit */
+ }
+
if (c->parent->parent->parent == dfll) {
/* G (DFLL selected as clock source) => LP switch:
* turn DFLL into open loop mode ("release" VDD_CPU rail)
*/
ret = tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 0);
if (ret)
- return ret;
+ goto abort;
p_source = rate <= p->u.cpu.backup_rate ?
p->u.cpu.backup : p->u.cpu.main;
ret = clk_set_rate(p_source, rate);
if (ret)
- return ret;
+ goto abort;
} else if (p->parent->parent == dfll) {
/* LP => G (DFLL selected as clock source) switch:
* set DFLL rate ready (DFLL is still disabled)
p_source = dfll;
ret = clk_set_rate(p_source, rate);
if (ret)
- return ret;
+ goto abort;
} else
/* DFLL is not selcted on either side of the switch:
* set target p_source equal to current clock source
if (ret) {
pr_err("%s: Failed to set parent %s for %s\n",
__func__, p_source->name, p->name);
- return ret;
+ goto abort;
}
}
clk_disable(p);
pr_err("%s: Failed to switch %s mode to %s\n",
__func__, c->name, p->name);
- return ret;
+ goto abort;
}
/* Disabling old parent scales old mode voltage rail */
tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
return 0;
+
+abort:
+ /* Re-lock DFLL if necessary after aborted switch */
+ if (c->parent->parent->parent == dfll)
+ tegra_clk_cfg_ex(dfll, TEGRA_CLK_DFLL_LOCK, 1);
+ return ret;
}
static long tegra11_cpu_cmplx_round_rate(struct clk *c,
unsigned long rate)
{
- if (rate > c->parent->max_rate)
- rate = c->parent->max_rate;
- else if (rate < c->parent->min_rate)
- rate = c->parent->min_rate;
- return rate;
+ return clk_round_rate(c->parent, rate);
}
static struct clk_ops tegra_cpu_cmplx_ops = {
/* This special sbus round function is implemented because:
*
- * (a) fractional 1 : 1.5 divider can not be used to derive system bus clock
+ * (a) sbus complex clock source is selected automatically based on rate
*
* (b) since sbus is a shared bus, and its frequency is set to the highest
* enabled shared_bus_user clock, the target rate should be rounded up divider
round_rate = source_rate * 2 / (divider + 2);
if (round_rate > c->max_rate) {
- divider = max(2, (divider + 1));
+ divider += new_parent->flags & DIV_U71_INT ? 2 : 1;
+#if !DIVIDER_1_5_ALLOWED
+ divider = max(2, divider);
+#endif
round_rate = source_rate * 2 / (divider + 2);
}
return 0;
}
+static void usb_plls_hw_control_enable(u32 reg)
+{
+ u32 val = clk_readl(reg);
+ val |= USB_PLLS_USE_LOCKDET | USB_PLLS_SEQ_START_STATE;
+ val &= ~USB_PLLS_ENABLE_SWCTL;
+ val |= USB_PLLS_SEQ_START_STATE;
+ pll_writel_delay(val, reg);
+
+ val |= USB_PLLS_SEQ_ENABLE;
+ pll_writel_delay(val, reg);
+}
static void tegra11_utmi_param_configure(struct clk *c)
{
utmi_parameters[i].active_delay_count);
/* Remove power downs from UTMIP PLL control bits */
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
clk_writel(reg, UTMIP_PLL_CFG2);
/* Remove power downs from UTMIP PLL control bits */
reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+ clk_writel(reg, UTMIP_PLL_CFG1);
+
+ /* Setup HW control of UTMIPLL */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+ reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+ reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+ reg = clk_readl(UTMIP_PLL_CFG1);
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
clk_writel(reg, UTMIP_PLL_CFG1);
+
+ udelay(1);
+
+ /* Setup SW override of UTMIPLL assuming USB2.0
+ ports are assigned to USB2 */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+ reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
+
+ udelay(1);
+
+ /* Enable HW control UTMIPLL */
+ reg = clk_readl(UTMIPLL_HW_PWRDN_CFG0);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+ clk_writel(reg, UTMIPLL_HW_PWRDN_CFG0);
}
static void tegra11_pll_clk_init(struct clk *c)
}
if (c->flags & PLLU) {
+ /* Configure UTMI PLL power management */
tegra11_utmi_param_configure(c);
+
+ /* Put PLLU under h/w control */
+ usb_plls_hw_control_enable(PLLU_HW_PWRDN_CFG0);
+
+ val = clk_readl(c->reg + PLL_BASE);
+ val &= ~PLLU_BASE_OVERRIDE;
+ clk_writel(val, c->reg + PLL_BASE);
+
+ /* Set XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+ val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+ val |= XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
}
}
pr_debug("%s on clock %s\n", __func__, c->name);
#if USE_PLL_LOCK_BITS
+ /* toggle lock enable bit to reset lock detection circuit (couple
+ register reads provide enough duration for reset pulse) */
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLL_MISC_LOCK_ENABLE(c);
+ clk_writel(val, c->reg + PLL_MISC(c));
+ val = clk_readl(c->reg + PLL_MISC(c));
val = clk_readl(c->reg + PLL_MISC(c));
val |= PLL_MISC_LOCK_ENABLE(c);
clk_writel(val, c->reg + PLL_MISC(c));
clk_writel(val, c->reg);
}
+static u8 get_pll_cpcon(struct clk *c, u16 n)
+{
+ if (c->flags & PLLD) {
+ if (n >= 600)
+ return 12;
+ else if (n >= 300)
+ return 8;
+ else if (n >= 50)
+ return 3;
+ else
+ return 2;
+ }
+ return c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+}
+
static int tegra11_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
u32 val, p_div, old_base;
cfg.p = 0x1 << p_div;
cfg.m = input_rate / cfreq;
cfg.n = cfg.output_rate / cfreq;
- cfg.cpcon = c->u.pll.cpcon_default ? : OUT_OF_TABLE_CPCON;
+ cfg.cpcon = get_pll_cpcon(c, cfg.n);
if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
(cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
if (sel->input_rate == input_rate && sel->output_rate == rate) {
u32 p = c->u.pll.round_p_to_pdiv(sel->p, pdiv);
BUG_ON(IS_ERR_VALUE(p));
- if (rate >= c->u.pll.vco_min)
- BUG_ON(sel->p != 1);
BUG_ON(sel->m != PLL_FIXED_MDIV(c, input_rate));
*cfg = *sel;
return 0;
if (p) {
for (i = 0; i <= PLLCX_PDIV_MAX; i++) {
+ /* Do not use DIV3 p values - mapped to even PDIV */
+ if (i && ((i & 0x1) == 0))
+ continue;
+
if (p <= pllcx_p[i]) {
if (pdiv)
*pdiv = i;
switch (input_rate) {
case 12000000:
- n_threshold = 77;
+ n_threshold = 70;
break;
case 13000000:
case 26000000:
}
val = clk_readl(c->reg + PLL_MISC(c));
- val &= ~(PLLCX_MISC_KA_MASK | PLLCX_MISC_KB_MASK);
+ val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
val |= n <= n_threshold ?
- PLLCX_MISC_KOEF_LOW_RANGE : PLLCX_MISC_KOEF_HIGH_RANGE;
+ PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
clk_writel(val, c->reg + PLL_MISC(c));
}
};
-/* FIXME: pllre suspend/resume */
/* non-monotonic mapping below is not a typo */
static u8 pllre_p[PLLRE_PDIV_MAX + 1] = {
/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
.set_rate = tegra11_pllre_out_clk_set_rate,
};
+#ifdef CONFIG_PM_SLEEP
+/* Resume both pllre_vco and pllre_out */
+static void tegra11_pllre_clk_resume_enable(struct clk *c)
+{
+ u32 pdiv;
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ unsigned long rate = clk_get_rate_all_locked(c->parent->parent);
+ enum clk_state state = c->parent->state;
+
+ if (val & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* temporarily sync h/w and s/w states, final sync happens
+ in tegra_clk_resume later */
+ c->parent->state = OFF;
+ pllre_set_defaults(c->parent, rate);
+
+ /* restore PLLRE VCO feedback loop (m, n) */
+ rate = clk_get_rate_all_locked(c->parent) + 1;
+ tegra11_pllre_clk_set_rate(c->parent, rate);
+
+ /* restore PLLRE post-divider */
+ c->parent->u.pll.round_p_to_pdiv(c->div, &pdiv);
+ val = clk_readl(c->reg);
+ val &= ~PLLRE_BASE_DIVP_MASK;
+ val |= pdiv << PLLRE_BASE_DIVP_SHIFT;
+ clk_writel(val, c->reg);
+
+ tegra11_pllre_clk_enable(c->parent);
+ c->parent->state = state;
+}
+#endif
+
+/* non-monotonic mapping below is not a typo */
+static u8 plle_p[PLLE_CMLDIV_MAX + 1] = {
+/* CMLDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
+/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32 };
+
+static inline void select_pll_e_input(u32 aux_reg)
+{
+#if USE_PLLE_INPUT_PLLRE
+ aux_reg |= PLLE_AUX_PLLRE_SEL;
+#else
+ aux_reg &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
+#endif
+ clk_writel(aux_reg, PLLE_AUX);
+}
static void tegra11_plle_clk_init(struct clk *c)
{
- u32 val;
+ u32 val, p;
+ struct clk *pll_ref = tegra_get_clock_by_name("pll_ref");
+ struct clk *re_vco = tegra_get_clock_by_name("pll_re_vco");
+ struct clk *pllp = tegra_get_clock_by_name("pllp");
+#if USE_PLLE_INPUT_PLLRE
+ struct clk *ref = re_vco;
+#else
+ struct clk *ref = pll_ref;
+#endif
- val = clk_readl(PLLE_AUX);
- c->parent = (val & PLLE_AUX_PLLP_SEL) ?
- tegra_get_clock_by_name("pll_p") :
- tegra_get_clock_by_name("pll_ref");
val = clk_readl(c->reg + PLL_BASE);
- c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
- c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
- c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
- c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+ c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+ c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ c->div = (val & PLLE_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+ p = (val & PLLE_BASE_DIVCML_MASK) >> PLLE_BASE_DIVCML_SHIFT;
+ c->div *= plle_p[p];
+
+ val = clk_readl(PLLE_AUX);
+ c->parent = (val & PLLE_AUX_PLLRE_SEL) ? re_vco :
+ (val & PLLE_AUX_PLLP_SEL) ? pllp : pll_ref;
+ if (c->parent != ref) {
+ if (c->state == ON) {
+ WARN(1, "%s: pll_e is left enabled with %s input\n",
+ __func__, c->parent->name);
+ } else {
+ c->parent = ref;
+ select_pll_e_input(val);
+ }
+ }
}
static void tegra11_plle_clk_disable(struct clk *c)
u32 val;
pr_debug("%s on clock %s\n", __func__, c->name);
+ /* FIXME: do we need to restore other s/w controls ? */
val = clk_readl(c->reg + PLL_BASE);
- val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+ val &= ~PLL_BASE_ENABLE;
clk_writel(val, c->reg + PLL_BASE);
-}
-
-static void tegra11_plle_training(struct clk *c)
-{
- u32 val;
-
- /* PLLE is already disabled, and setup cleared;
- * create falling edge on PLLE IDDQ input */
- val = pmc_readl(PMC_SATA_PWRGT);
- val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
- pmc_writel(val, PMC_SATA_PWRGT);
-
- val = pmc_readl(PMC_SATA_PWRGT);
- val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
- pmc_writel(val, PMC_SATA_PWRGT);
- val = pmc_readl(PMC_SATA_PWRGT);
- val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
- pmc_writel(val, PMC_SATA_PWRGT);
-
- do {
- val = clk_readl(c->reg + PLL_MISC(c));
- } while (!(val & PLLE_MISC_READY));
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
+ pll_writel_delay(val, c->reg + PLL_MISC(c));
}
-static int tegra11_plle_configure(struct clk *c, bool force_training)
+static int tegra11_plle_clk_enable(struct clk *c)
{
u32 val;
const struct clk_pll_freq_table *sel;
unsigned long rate = c->u.pll.fixed_rate;
unsigned long input_rate = clk_get_rate(c->parent);
+ if (c->state == ON) {
+ /* BL left plle enabled - don't change configuartion */
+ pr_warn("%s: pll_e is already enabled\n", __func__);
+ return 0;
+ }
+
for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
if (sel->input_rate == input_rate && sel->output_rate == rate)
break;
}
- if (sel->input_rate == 0)
- return -ENOSYS;
-
- /* disable PLLE, clear setup fiels */
- tegra11_plle_clk_disable(c);
-
- val = clk_readl(c->reg + PLL_MISC(c));
- val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
- clk_writel(val, c->reg + PLL_MISC(c));
-
- /* training */
- val = clk_readl(c->reg + PLL_MISC(c));
- if (force_training || (!(val & PLLE_MISC_READY)))
- tegra11_plle_training(c);
+ if (sel->input_rate == 0) {
+ pr_err("%s: %s input rate %lu is out-of-table\n",
+ __func__, c->name, input_rate);
+ return -EINVAL;
+ }
- /* configure dividers, setup, disable SS */
+ /* setup locking configuration, s/w control of IDDQ and enable modes,
+ take pll out of IDDQ via s/w control, setup VREG */
val = clk_readl(c->reg + PLL_BASE);
- val &= ~PLLE_BASE_DIV_MASK;
- val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
+ val &= ~PLLE_BASE_LOCK_OVERRIDE;
clk_writel(val, c->reg + PLL_BASE);
- c->mul = sel->n;
- c->div = sel->m * sel->p;
val = clk_readl(c->reg + PLL_MISC(c));
- val |= PLLE_MISC_SETUP_VALUE;
val |= PLLE_MISC_LOCK_ENABLE;
+ val |= PLLE_MISC_IDDQ_SW_CTRL;
+ val &= ~PLLE_MISC_IDDQ_SW_VALUE;
+ val |= PLLE_MISC_PLLE_PTS;
+ val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
clk_writel(val, c->reg + PLL_MISC(c));
+ udelay(5);
+ /* configure dividers, disable SS */
val = clk_readl(PLLE_SS_CTRL);
val |= PLLE_SS_DISABLE;
clk_writel(val, PLLE_SS_CTRL);
- /* enable and lock PLLE*/
val = clk_readl(c->reg + PLL_BASE);
- val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
- clk_writel(val, c->reg + PLL_BASE);
-
- tegra11_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
+ val &= ~(PLLE_BASE_DIVM_MASK | PLLE_BASE_DIVN_MASK |
+ PLLE_BASE_DIVCML_MASK);
+ val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+ (sel->n << PLL_BASE_DIVN_SHIFT) |
+ (sel->cpcon << PLLE_BASE_DIVCML_SHIFT);
+ pll_writel_delay(val, c->reg + PLL_BASE);
+ c->mul = sel->n;
+ c->div = sel->m * sel->p;
+ /* enable and lock pll */
+ val |= PLL_BASE_ENABLE;
+ clk_writel(val, c->reg + PLL_BASE);
+ tegra11_pll_clk_wait_for_lock(
+ c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
#if USE_PLLE_SS
- /* configure spread spectrum coefficients */
- /* FIXME: coefficients for 216MHZ input? */
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
- if (input_rate == 12000000)
+ val = clk_readl(PLLE_SS_CTRL);
+ val &= ~PLLE_SS_COEFFICIENTS_MASK;
+ val |= PLLE_SS_COEFFICIENTS_VAL;
+ clk_writel(val, PLLE_SS_CTRL);
+ val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
+ pll_writel_delay(val, PLLE_SS_CTRL);
+ val &= ~PLLE_SS_CNTL_INTERP_RESET;
+ pll_writel_delay(val, PLLE_SS_CTRL);
#endif
- {
- val = clk_readl(PLLE_SS_CTRL);
- val &= ~(PLLE_SS_COEFFICIENTS_MASK | PLLE_SS_DISABLE);
- val |= PLLE_SS_COEFFICIENTS_12MHZ;
- clk_writel(val, PLLE_SS_CTRL);
- }
+#if !USE_PLLE_SWCTL
+ /* switch pll under h/w control */
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLLE_MISC_IDDQ_SW_CTRL;
+ clk_writel(val, c->reg + PLL_MISC(c));
+
+ val = clk_readl(PLLE_AUX);
+ val |= PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE;
+ val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
+ pll_writel_delay(val, PLLE_AUX);
+ val |= PLLE_AUX_SEQ_ENABLE;
+ pll_writel_delay(val, PLLE_AUX);
#endif
+ /* clear XUSB PLL pad pwr override and iddq */
+ val = xusb_padctl_readl(XUSB_PADCTL_IOPHY_PLL0_CTL1);
+ val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_PWR_OVRD;
+ val &= ~XUSB_PADCTL_IOPHY_PLL0_CTL1_PLL_IDDQ;
+ xusb_padctl_writel(val, XUSB_PADCTL_IOPHY_PLL0_CTL1);
+
+ /* enable hw control of xusb brick pll */
+ usb_plls_hw_control_enable(XUSBIO_PLL_CFG0);
+
return 0;
}
-static int tegra11_plle_clk_enable(struct clk *c)
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_plle_clk_resume(struct clk *c)
{
- pr_debug("%s on clock %s\n", __func__, c->name);
- return tegra11_plle_configure(c, !c->set);
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ if (val & PLL_BASE_ENABLE)
+ return; /* already resumed */
+
+ /* Restore parent */
+ val = clk_readl(PLLE_AUX);
+ select_pll_e_input(val);
}
+#endif
static struct clk_ops tegra_plle_ops = {
.init = tegra11_plle_clk_init,
*/
/* DFLL operations */
-static void tegra11_dfll_cpu_late_init(struct clk *c)
+static void __init tegra11_dfll_cpu_late_init(struct clk *c)
{
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
int ret;
- struct clk *cpu_clk;
- struct tegra_cl_dvfs *cld = c->u.dfll.cl_dvfs;
+ struct clk *cpu = tegra_get_clock_by_name("cpu");
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
+#ifdef CONFIG_TEGRA_FPGA_PLATFORM
u32 netlist, patchid;
tegra_get_netlist_revision(&netlist, &patchid);
if (netlist < 12) {
return;
}
#endif
-
- cpu_clk = tegra_get_clock_by_name("cpu_g");
- BUG_ON(!cpu_clk);
-
- cld->safe_dvfs = cpu_clk->dvfs;
- cld->ref_clk = clk_get_sys("dfll_cpu", "ref");
- cld->soc_clk = clk_get_sys("dfll_cpu", "soc");
- cld->i2c_clk = clk_get_sys("dfll_cpu", "i2c");
- cld->i2c_fast = clk_get_sys("dfll_cpu", "i2c_fast");
- if (IS_ERR_OR_NULL(cld->ref_clk) || IS_ERR_OR_NULL(cld->soc_clk) ||
- IS_ERR_OR_NULL(cld->i2c_clk) || IS_ERR_OR_NULL(cld->i2c_fast))
- {
- WARN(1, "%s: could not find CPU DFLL control clocks\n",
- __func__);
- return;
- }
-
/* release dfll clock source reset, init cl_dvfs control logic, and
move dfll to initialized state, so it can be used as CPU source */
tegra_periph_reset_deassert(c);
- ret = tegra_init_cl_dvfs(cld);
+ ret = tegra_init_cl_dvfs();
if (!ret) {
c->state = OFF;
+ c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
+
+ use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
+ tegra_dvfs_set_dfll_range(cpu->parent->dvfs, use_dfll);
pr_info("Tegra CPU DFLL is initialized\n");
}
+#endif
}
static int tegra11_dfll_clk_enable(struct clk *c)
static void tegra11_dfll_clk_reset(struct clk *c, bool assert)
{
- u32 val = assert ? 1 : 0;
+ u32 val = assert ? DFLL_BASE_RESET : 0;
clk_writel_delay(val, c->reg);
}
return -EINVAL;
}
+#ifdef CONFIG_PM_SLEEP
+static void tegra11_dfll_clk_resume(struct clk *c)
+{
+ if (!(clk_readl(c->reg) & DFLL_BASE_RESET))
+ return; /* already resumed */
+
+ tegra_periph_reset_deassert(c);
+ tegra_cl_dvfs_resume(c->u.dfll.cl_dvfs);
+}
+#endif
+
static struct clk_ops tegra_dfll_ops = {
.enable = tegra11_dfll_clk_enable,
.disable = tegra11_dfll_clk_disable,
.clk_cfg_ex = tegra11_dfll_clk_cfg_ex,
};
+/* DFLL sysfs interface */
+static int tegra11_use_dfll_cb(const char *arg, const struct kernel_param *kp)
+{
+ int ret = 0;
+ unsigned long c_flags, p_flags;
+ unsigned int old_use_dfll;
+ struct clk *c = tegra_get_clock_by_name("cpu");
+
+ if (!c->parent || !c->parent->dvfs)
+ return -ENOSYS;
+
+ clk_lock_save(c, &c_flags);
+ if (c->parent->u.cpu.mode == MODE_LP) {
+ pr_err("%s: DFLL is not used on LP CPU\n", __func__);
+ clk_unlock_restore(c, &c_flags);
+ return -ENOSYS;
+ }
+
+ clk_lock_save(c->parent, &p_flags);
+ old_use_dfll = use_dfll;
+ param_set_int(arg, kp);
+
+ if (use_dfll != old_use_dfll) {
+ ret = tegra_dvfs_set_dfll_range(c->parent->dvfs, use_dfll);
+ if (ret) {
+ use_dfll = old_use_dfll;
+ } else {
+ ret = clk_set_rate_locked(c->parent,
+ clk_get_rate_locked(c->parent));
+ if (ret) {
+ use_dfll = old_use_dfll;
+ tegra_dvfs_set_dfll_range(
+ c->parent->dvfs, use_dfll);
+ }
+ }
+ }
+ clk_unlock_restore(c->parent, &p_flags);
+ clk_unlock_restore(c, &c_flags);
+ tegra_recalculate_cpu_edp_limits();
+ return ret;
+}
+
+static struct kernel_param_ops tegra11_use_dfll_ops = {
+ .set = tegra11_use_dfll_cb,
+ .get = param_get_int,
+};
+module_param_cb(use_dfll, &tegra11_use_dfll_ops, &use_dfll, 0644);
+
+
/* Clock divider ops (non-atomic shared register access) */
static DEFINE_SPINLOCK(pll_div_lock);
} else {
if (c->flags & PLLU) {
/* for xusb_hs clock enforce PLLU source during init */
- val &= periph_clk_source_mask(c);
+ val &= ~periph_clk_source_mask(c);
val |= c->inputs[0].value << periph_clk_source_shift(c);
clk_writel_delay(val, c->reg);
}
};
+#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM)
+/* msenc clock propagation WAR for bug 1005168 */
+static int tegra11_msenc_clk_enable(struct clk *c)
+{
+ int ret = tegra11_periph_clk_enable(c);
+ if (ret)
+ return ret;
+
+ clk_writel(0, LVL2_CLK_GATE_OVRE);
+ clk_writel(0x00400000, LVL2_CLK_GATE_OVRE);
+ udelay(1);
+ clk_writel(0, LVL2_CLK_GATE_OVRE);
+ return 0;
+}
+
+static struct clk_ops tegra_msenc_clk_ops = {
+ .init = &tegra11_periph_clk_init,
+ .enable = &tegra11_msenc_clk_enable,
+ .disable = &tegra11_periph_clk_disable,
+ .set_parent = &tegra11_periph_clk_set_parent,
+ .set_rate = &tegra11_periph_clk_set_rate,
+ .round_rate = &tegra11_periph_clk_round_rate,
+ .reset = &tegra11_periph_clk_reset,
+};
+#endif
/* Periph extended clock configuration ops */
static int
tegra11_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
{
tegra11_periph_clk_init(c);
tegra_emc_dram_type_init(c);
- c->max_rate = clk_get_rate(c->parent);
}
static long tegra11_emc_clk_round_rate(struct clk *c, unsigned long rate)
static int tegra11_clk_emc_bus_update(struct clk *bus)
{
struct clk *p = NULL;
- unsigned long rate, parent_rate, backup_rate;
+ unsigned long rate, old_rate, parent_rate, backup_rate;
if (detach_shared_bus)
return 0;
rate = tegra11_clk_shared_bus_update(bus, NULL, NULL);
rate = clk_round_rate_locked(bus, rate);
- if (rate == clk_get_rate_locked(bus))
+ old_rate = clk_get_rate_locked(bus);
+ if (rate == old_rate)
return 0;
if (!tegra_emc_is_parent_ready(rate, &p, &parent_rate, &backup_rate)) {
if (bus->parent == p) {
/* need backup to re-lock current parent */
- if (IS_ERR_VALUE(backup_rate) ||
- clk_set_rate_locked(bus, backup_rate)) {
- pr_err("%s: Failed to backup %s for rate %lu\n",
+ int ret;
+ if (IS_ERR_VALUE(backup_rate)) {
+ pr_err("%s: No backup for %s rate %lu\n",
__func__, bus->name, rate);
return -EINVAL;
}
- if (p->refcnt) {
- pr_err("%s: %s has other than emc child\n",
- __func__, p->name);
+ if (backup_rate < old_rate) /* skip lowering voltage */
+ bus->auto_dvfs = false;
+ ret = clk_set_rate_locked(bus, backup_rate);
+ bus->auto_dvfs = true;
+ if (ret) {
+ pr_err("%s: Failed to backup %s for rate %lu\n",
+ __func__, bus->name, rate);
return -EINVAL;
}
}
+ if (p->refcnt) {
+ pr_err("%s: %s has other than emc child\n",
+ __func__, p->name);
+ return -EINVAL;
+ }
+
if (clk_set_rate(p, parent_rate)) {
pr_err("%s: Failed to set %s rate %lu\n",
__func__, p->name, parent_rate);
return ret;
}
-static inline bool cbus_user_is_slower(struct clk *a, struct clk *b)
-{
- return a->u.shared_bus_user.client->max_rate * a->div <
- b->u.shared_bus_user.client->max_rate * b->div;
-}
-
-static inline bool cbus_user_request_is_lower(struct clk *a, struct clk *b)
-{
- return a->u.shared_bus_user.rate * a->div <
- b->u.shared_bus_user.rate * b->div;
-}
-
static inline void cbus_move_enabled_user(
struct clk *user, struct clk *dst, struct clk *src)
{
struct clk *slow = NULL;
struct clk *top = NULL;
unsigned long rate;
+ unsigned long old_rate;
if (detach_shared_bus)
return 0;
}
}
- ret = bus->ops->set_rate(bus, rate);
- if (ret)
- return ret;
+ old_rate = clk_get_rate_locked(bus);
+ if (IS_ENABLED(CONFIG_TEGRA_MIGRATE_CBUS_USERS) || (old_rate != rate)) {
+ ret = bus->ops->set_rate(bus, rate);
+ if (ret)
+ return ret;
+ }
if (bus->dvfs) {
if (bus->refcnt && (mv <= 0)) {
}
}
+ clk_rate_change_notify(bus, rate);
return 0;
};
#else
/* Make sure top user on the source bus is requesting highest rate */
if (!src_bus->u.cbus.top_user || (dst_bus->u.cbus.top_user &&
- cbus_user_request_is_lower(src_bus->u.cbus.top_user,
+ bus_user_request_is_lower(src_bus->u.cbus.top_user,
dst_bus->u.cbus.top_user)))
swap(src_bus, dst_bus);
/* If top user is the slow one on its own (source) bus, do nothing */
top_user = src_bus->u.cbus.top_user;
BUG_ON(!top_user->u.shared_bus_user.client);
- if (!cbus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
+ if (!bus_user_is_slower(src_bus->u.cbus.slow_user, top_user))
return 0;
/* If source bus top user is slower than all users on destination bus,
move top user; otherwise move all users slower than the top one */
if (!dst_bus->u.cbus.slow_user ||
- !cbus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
+ !bus_user_is_slower(dst_bus->u.cbus.slow_user, top_user)) {
cbus_move_enabled_user(top_user, dst_bus, src_bus);
} else {
list_for_each_safe(pos, n, &src_bus->shared_bus_list) {
c = list_entry(pos, struct clk, u.shared_bus_user.node);
if (c->u.shared_bus_user.enabled &&
c->u.shared_bus_user.client &&
- cbus_user_is_slower(c, top_user))
+ bus_user_is_slower(c, top_user))
cbus_move_enabled_user(c, dst_bus, src_bus);
}
}
* clock to each user. The frequency of the bus is set to the highest
* enabled shared_bus_user clock, with a minimum value set by the
* shared bus.
+ *
+ * Optionally shared bus may support users migration. Since shared bus and
+ * its * children (users) have reversed rate relations: user rates determine
+ * bus rate, * switching user from one parent/bus to another may change rates
+ * of both parents. Therefore we need a cross-bus lock on top of individual
+ * user and bus locks. For now, limit bus switch support to cbus only if
+ * CONFIG_TEGRA_MIGRATE_CBUS_USERS is set.
*/
static unsigned long tegra11_clk_shared_bus_update(
struct clk *slow = NULL;
struct clk *top = NULL;
+ unsigned long override_rate = 0;
unsigned long top_rate = 0;
unsigned long rate = bus->min_rate;
unsigned long bw = 0;
case SHARED_CEILING:
ceiling = min(request_rate, ceiling);
break;
+ case SHARED_OVERRIDE:
+ if (override_rate == 0)
+ override_rate = request_rate;
+ break;
case SHARED_AUTO:
break;
case SHARED_FLOOR:
top_rate = request_rate;
top = c;
} else if ((top_rate == request_rate) &&
- cbus_user_is_slower(c, top)) {
+ bus_user_is_slower(c, top)) {
top = c;
}
}
}
if (c->u.shared_bus_user.client &&
- (!slow || cbus_user_is_slower(c, slow)))
+ (!slow || bus_user_is_slower(c, slow)))
slow = c;
}
}
bw = (bw < bus->max_rate / 100) ? (bw * 100) : bus->max_rate;
}
- rate = min(max(rate, bw), ceiling);
+ rate = override_rate ? : min(max(rate, bw), ceiling);
if (bus_top)
*bus_top = top;
return -ENOSYS;
}
-static void tegra_clk_shared_bus_init(struct clk *c)
+static void tegra_clk_shared_bus_user_init(struct clk *c)
{
c->max_rate = c->parent->max_rate;
-
- /* EMC BW requets are normilized by the clients to 32 bit bus,
- hence, max limits should be scaled up to actual bus width */
- if ((c->parent->flags & PERIPH_EMC_ENB) &&
- (c->u.shared_bus_user.mode == SHARED_BW)) {
- c->max_rate *= tegra_mc_get_effective_bytes_width() / 4;
- }
-
c->u.shared_bus_user.rate = c->parent->max_rate;
c->state = OFF;
c->set = true;
+ if (c->u.shared_bus_user.mode == SHARED_CEILING) {
+ c->state = ON;
+ c->refcnt++;
+ }
+
if (c->u.shared_bus_user.client_id) {
c->u.shared_bus_user.client =
tegra_get_clock_by_name(c->u.shared_bus_user.client_id);
&c->parent->shared_bus_list);
}
-/*
- * Shared bus and its children/users have reversed rate relations - user rates
- * determine bus rate. Hence switching user from one parent/bus to another may
- * change rates of both parents. Therefore we need a cross-bus lock on top of
- * individual user and bus locks. For now limit bus switch support to cansleep
- * users with cross-clock mutex only.
- */
-static int tegra_clk_shared_bus_set_parent(struct clk *c, struct clk *p)
+static int tegra_clk_shared_bus_user_set_parent(struct clk *c, struct clk *p)
{
+ int ret;
const struct clk_mux_sel *sel;
if (detach_shared_bus)
clk_enable(p);
list_move_tail(&c->u.shared_bus_user.node, &p->shared_bus_list);
- tegra_clk_shared_bus_update(p);
+ ret = tegra_clk_shared_bus_update(p);
+ if (ret) {
+ list_move_tail(&c->u.shared_bus_user.node,
+ &c->parent->shared_bus_list);
+ tegra_clk_shared_bus_update(c->parent);
+ clk_disable(p);
+ return ret;
+ }
+
tegra_clk_shared_bus_update(c->parent);
if (c->refcnt && c->parent)
return 0;
}
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
+static int tegra_clk_shared_bus_user_set_rate(struct clk *c, unsigned long rate)
{
+ int ret;
+
c->u.shared_bus_user.rate = rate;
- tegra_clk_shared_bus_update(c->parent);
+ ret = tegra_clk_shared_bus_update(c->parent);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
- return 0;
+ return ret;
}
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
+static long tegra_clk_shared_bus_user_round_rate(
+ struct clk *c, unsigned long rate)
{
/* Defer rounding requests until aggregated. BW users must not be
rounded at all, others just clipped to bus range (some clients
if (c->div > 1)
rate /= c->div;
- } else if (c->parent->flags & PERIPH_EMC_ENB) {
- /* EMC BW requets are normilized by the clients to 32 bit bus,
- and should be scaled down to actual bus width */
- rate /= tegra_mc_get_effective_bytes_width() / 4;
}
return rate;
}
-static int tegra_clk_shared_bus_enable(struct clk *c)
+static int tegra_clk_shared_bus_user_enable(struct clk *c)
{
- int ret = 0;
+ int ret;
c->u.shared_bus_user.enabled = true;
- tegra_clk_shared_bus_update(c->parent);
- if (c->u.shared_bus_user.client)
+ ret = tegra_clk_shared_bus_update(c->parent);
+ if (!ret && c->u.shared_bus_user.client)
ret = clk_enable(c->u.shared_bus_user.client);
- if (c->cross_clk_mutex && clk_cansleep(c))
+ if (!ret && c->cross_clk_mutex && clk_cansleep(c))
tegra_clk_shared_bus_migrate_users(c);
return ret;
}
-static void tegra_clk_shared_bus_disable(struct clk *c)
+static void tegra_clk_shared_bus_user_disable(struct clk *c)
{
if (c->u.shared_bus_user.client)
clk_disable(c->u.shared_bus_user.client);
tegra_clk_shared_bus_migrate_users(c);
}
-static void tegra_clk_shared_bus_reset(struct clk *c, bool assert)
+static void tegra_clk_shared_bus_user_reset(struct clk *c, bool assert)
{
if (c->u.shared_bus_user.client) {
if (c->u.shared_bus_user.client->ops &&
}
}
-static struct clk_ops tegra_clk_shared_bus_ops = {
- .init = tegra_clk_shared_bus_init,
- .enable = tegra_clk_shared_bus_enable,
- .disable = tegra_clk_shared_bus_disable,
- .set_parent = tegra_clk_shared_bus_set_parent,
- .set_rate = tegra_clk_shared_bus_set_rate,
- .round_rate = tegra_clk_shared_bus_round_rate,
- .reset = tegra_clk_shared_bus_reset,
+static struct clk_ops tegra_clk_shared_bus_user_ops = {
+ .init = tegra_clk_shared_bus_user_init,
+ .enable = tegra_clk_shared_bus_user_enable,
+ .disable = tegra_clk_shared_bus_user_disable,
+ .set_parent = tegra_clk_shared_bus_user_set_parent,
+ .set_rate = tegra_clk_shared_bus_user_set_rate,
+ .round_rate = tegra_clk_shared_bus_user_round_rate,
+ .reset = tegra_clk_shared_bus_user_reset,
};
/* coupled gate ops */
};
static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+ { 12000000, 624000000, 104, 1, 2},
{ 12000000, 600000000, 100, 1, 2},
{ 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
{ 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
static struct clk tegra_pll_c_out1 = {
.name = "pll_c_out1",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71 | PERIPH_ON_CBUS,
+#ifdef CONFIG_TEGRA_DUAL_CBUS
+ .flags = DIV_U71 | DIV_U71_INT,
+#else
+ .flags = DIV_U71 | DIV_U71_INT | PERIPH_ON_CBUS,
+#endif
.parent = &tegra_pll_c,
.reg = 0x84,
.reg_shift = 0,
.input_max = 48000000,
.cf_min = 12000000,
.cf_max = 19200000,
- .vco_min = 739000000,
- .vco_max = 1200000000,
+ .vco_min = 624000000,
+ .vco_max = 1248000000,
.freq_table = tegra_pll_cx_freq_table,
.lock_delay = 300,
.misc1 = 0x4f0 - 0x4e8,
.input_max = 48000000,
.cf_min = 12000000,
.cf_max = 19200000,
- .vco_min = 739000000,
- .vco_max = 1200000000,
+ .vco_min = 624000000,
+ .vco_max = 1248000000,
.freq_table = tegra_pll_cx_freq_table,
.lock_delay = 300,
.misc1 = 0x504 - 0x4fc,
.ops = &tegra_pllm_ops,
.reg = 0x90,
.parent = &tegra_pll_ref,
- .max_rate = 800000000,
+ .max_rate = 1066000000,
.u.pll = {
.input_min = 12000000,
.input_max = 500000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 400000000,
- .vco_max = 800000000,
+ .vco_max = 1066000000,
.freq_table = tegra_pll_m_freq_table,
.lock_delay = 300,
.misc1 = 0x98 - 0x90,
static struct clk tegra_pll_m_out1 = {
.name = "pll_m_out1",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
+ .flags = DIV_U71 | DIV_U71_INT,
.parent = &tegra_pll_m,
.reg = 0x94,
.reg_shift = 0,
static struct clk tegra_pll_p_out2 = {
.name = "pll_p_out2",
.ops = &tegra_pll_div_ops,
- .flags = DIV_U71 | DIV_U71_FIXED,
+ .flags = DIV_U71 | DIV_U71_FIXED | DIV_U71_INT,
.parent = &tegra_pll_p,
.reg = 0xa4,
.reg_shift = 16,
{ 19200000, 216000000, 720, 16, 4, 12},
{ 26000000, 216000000, 864, 26, 4, 12},
- { 12000000, 594000000, 594, 12, 1, 12},
+ { 12000000, 594000000, 99, 2, 1, 8},
{ 13000000, 594000000, 594, 13, 1, 12},
{ 16800000, 594000000, 495, 14, 1, 12},
{ 19200000, 594000000, 495, 16, 1, 12},
.vco_max = 1000000000,
.freq_table = tegra_pll_d_freq_table,
.lock_delay = 1000,
- .cpcon_default = 12,
},
};
.vco_max = 1000000000,
.freq_table = tegra_pll_d_freq_table,
.lock_delay = 1000,
- .cpcon_default = 12,
},
};
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
.vco_min = 700000000,
- .vco_max = 1800000000,
+ .vco_max = 2400000000U,
.freq_table = tegra_pll_x_freq_table,
.lock_delay = 300,
.misc1 = 0x510 - 0xe0,
/* FIXME: remove; for now, should be always checked-in as "0" */
#define USE_LP_CPU_TO_TEST_DFLL 0
-static struct tegra_cl_dvfs cpu_cl_dvfs = {
- .cl_base = (u32)IO_ADDRESS(TEGRA_CL_DVFS_BASE),
-};
-
static struct clk tegra_dfll_cpu = {
.name = "dfll_cpu",
.flags = DFLL,
.ops = &tegra_dfll_ops,
.reg = 0x2f4,
.max_rate = 2000000000,
- .u.dfll = {
- .cl_dvfs = &cpu_cl_dvfs,
- },
};
static struct clk tegra_pll_re_vco = {
.ops = &tegra_pllre_ops,
.reg = 0x4c4,
.parent = &tegra_pll_ref,
- .max_rate = 600000000,
+ .max_rate = 672000000,
.u.pll = {
.input_min = 12000000,
.input_max = 1000000000,
.cf_min = 12000000,
.cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
.vco_min = 300000000,
- .vco_max = 600000000,
+ .vco_max = 672000000,
.lock_delay = 300,
.round_p_to_pdiv = pllre_round_p_to_pdiv,
},
.ops = &tegra_pllre_out_ops,
.parent = &tegra_pll_re_vco,
.reg = 0x4c4,
- .max_rate = 600000000,
+ .max_rate = 672000000,
};
static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
/* PLLE special case: use cpcon field to store cml divider value */
- { 12000000, 100000000, 150, 1, 18, 11},
- { 216000000, 100000000, 200, 18, 24, 13},
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
- { 13000000, 100000000, 200, 1, 26, 13},
-#endif
+ { 336000000, 100000000, 100, 21, 16, 11},
+ { 312000000, 100000000, 200, 26, 24, 13},
+ { 12000000, 100000000, 200, 1, 24, 13},
{ 0, 0, 0, 0, 0, 0 },
};
.max_rate = 100000000,
.u.pll = {
.input_min = 12000000,
- .input_max = 216000000,
+ .input_max = 1000000000,
.cf_min = 12000000,
- .cf_max = 12000000,
- .vco_min = 1200000000,
+ .cf_max = 75000000,
+ .vco_min = 1600000000,
.vco_max = 2400000000U,
.freq_table = tegra_pll_e_freq_table,
.lock_delay = 300,
};
/* Audio sync clocks */
-#define SYNC_SOURCE(_id) \
+#define SYNC_SOURCE(_id, _dev) \
{ \
.name = #_id "_sync", \
+ .lookup = { \
+ .dev_id = #_dev , \
+ .con_id = "ext_audio_sync", \
+ }, \
.rate = 24000000, \
.max_rate = 24000000, \
.ops = &tegra_sync_source_ops \
}
static struct clk tegra_sync_source_list[] = {
- SYNC_SOURCE(spdif_in),
- SYNC_SOURCE(i2s0),
- SYNC_SOURCE(i2s1),
- SYNC_SOURCE(i2s2),
- SYNC_SOURCE(i2s3),
- SYNC_SOURCE(i2s4),
- SYNC_SOURCE(vimclk),
+ SYNC_SOURCE(spdif_in, tegra30-spdif),
+ SYNC_SOURCE(i2s0, tegra30-i2s.0),
+ SYNC_SOURCE(i2s1, tegra30-i2s.1),
+ SYNC_SOURCE(i2s2, tegra30-i2s.2),
+ SYNC_SOURCE(i2s3, tegra30-i2s.3),
+ SYNC_SOURCE(i2s4, tegra30-i2s.4),
+ SYNC_SOURCE(vimclk, vimclk),
};
static struct clk_mux_sel mux_d_audio_clk[] = {
{ 0, 0 }
};
-#define AUDIO_SYNC_CLK(_id, _index) \
+#define AUDIO_SYNC_CLK(_id, _dev, _index) \
{ \
.name = #_id, \
+ .lookup = { \
+ .dev_id = #_dev, \
+ .con_id = "audio_sync", \
+ }, \
.inputs = mux_audio_sync_clk, \
.reg = 0x4A0 + (_index) * 4, \
.max_rate = 24000000, \
.ops = &tegra_audio_sync_clk_ops \
}
static struct clk tegra_clk_audio_list[] = {
- AUDIO_SYNC_CLK(audio0, 0),
- AUDIO_SYNC_CLK(audio1, 1),
- AUDIO_SYNC_CLK(audio2, 2),
- AUDIO_SYNC_CLK(audio3, 3),
- AUDIO_SYNC_CLK(audio4, 4),
- AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
+ AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0),
+ AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1),
+ AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2),
+ AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3),
+ AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4),
+ AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), /* SPDIF */
};
-#define AUDIO_SYNC_2X_CLK(_id, _index) \
+#define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \
{ \
.name = #_id "_2x", \
+ .lookup = { \
+ .dev_id = #_dev, \
+ .con_id = "audio_sync_2x" \
+ }, \
.flags = PERIPH_NO_RESET, \
.max_rate = 48000000, \
.ops = &tegra_clk_double_ops, \
}, \
}
static struct clk tegra_clk_audio_2x_list[] = {
- AUDIO_SYNC_2X_CLK(audio0, 0),
- AUDIO_SYNC_2X_CLK(audio1, 1),
- AUDIO_SYNC_2X_CLK(audio2, 2),
- AUDIO_SYNC_2X_CLK(audio3, 3),
- AUDIO_SYNC_2X_CLK(audio4, 4),
- AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
+ AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0),
+ AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1),
+ AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2),
+ AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3),
+ AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4),
+ AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), /* SPDIF */
};
#define MUX_I2S_SPDIF(_id, _index) \
}
static struct clk tegra_clk_out_list[] = {
CLK_OUT_CLK(1, 12288000),
- CLK_OUT_CLK(2, 25500000),
+ CLK_OUT_CLK(2, 40800000),
CLK_OUT_CLK(3, 12288000),
};
{ .input = &tegra_clk_m, .value = 0},
{ .input = &tegra_pll_c_out1, .value = 1},
{ .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
+ { .input = &tegra_pll_p, .value = 3},
{ .input = &tegra_pll_p_out2, .value = 4},
/* { .input = &tegra_clk_d, .value = 5}, - no use on tegra11x */
{ .input = &tegra_clk_32k, .value = 6},
.inputs = mux_cclk_lp,
.reg = 0x370,
.ops = &tegra_super_ops,
- .max_rate = 700000000,
+ .max_rate = 816000000,
};
static struct clk tegra_clk_sclk = {
.inputs = mux_sclk,
.reg = 0x28,
.ops = &tegra_super_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
+ .max_rate = 384000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_virtual_cpu_g = {
.name = "cpu_lp",
.parent = &tegra_clk_cclk_lp,
.ops = &tegra_cpu_ops,
- .max_rate = 700000000,
+ .max_rate = 816000000,
.u.cpu = {
.main = &tegra_pll_x,
.backup = &tegra_pll_p_out4,
.name = "cop",
.parent = &tegra_clk_sclk,
.ops = &tegra_cop_ops,
- .max_rate = 334000000,
+ .max_rate = 384000000,
};
static struct clk tegra_clk_hclk = {
.reg = 0x30,
.reg_shift = 4,
.ops = &tegra_bus_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
+ .max_rate = 384000000,
+ .min_rate = 12000000,
};
static struct clk tegra_clk_pclk = {
.reg = 0x30,
.reg_shift = 0,
.ops = &tegra_bus_ops,
- .max_rate = 167000000,
- .min_rate = 40000000,
+ .max_rate = 192000000,
+ .min_rate = 12000000,
};
static struct raw_notifier_head sbus_rate_change_nh;
.pclk = &tegra_clk_pclk,
.hclk = &tegra_clk_hclk,
.sclk_low = &tegra_pll_p_out2,
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ .sclk_high = &tegra_pll_c_out1,
+#else
.sclk_high = &tegra_pll_m_out1,
+#endif
},
.rate_change_nh = &sbus_rate_change_nh,
};
{ .input = &tegra_clk_m, .value = 0},
{ .input = &tegra_pll_p, .value = 1},
{ .input = &tegra_pll_c, .value = 3},
- { .input = &tegra_pll_re_out, .value = 5},
+ { .input = &tegra_pll_re_vco, .value = 5},
{ 0, 0},
};
static struct clk_mux_sel mux_clkm_pllre_clk32_480M_pllc_ref[] = {
{ .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_re_out, .value = 1},
+ { .input = &tegra_pll_re_vco, .value = 1},
{ .input = &tegra_clk_32k, .value = 2},
{ .input = &tegra_pll_u_480M, .value = 3},
{ .input = &tegra_pll_c, .value = 4},
.name = "emc",
.ops = &tegra_emc_clk_ops,
.reg = 0x19c,
- .max_rate = 800000000,
- .min_rate = 25000000,
+ .max_rate = 1066000000,
+ .min_rate = 12750000,
.inputs = mux_pllm_pllc_pllp_clkm,
.flags = MUX | MUX8 | DIV_U71 | PERIPH_EMC_ENB,
.u.periph = {
};
#ifdef CONFIG_TEGRA_DUAL_CBUS
+
+static struct raw_notifier_head c2bus_rate_change_nh;
+static struct raw_notifier_head c3bus_rate_change_nh;
+
static struct clk tegra_clk_c2bus = {
.name = "c2bus",
.parent = &tegra_pll_c2,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &c2bus_rate_change_nh,
};
static struct clk tegra_clk_c3bus = {
.name = "c3bus",
.parent = &tegra_pll_c3,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 1,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &c3bus_rate_change_nh,
};
+#ifdef CONFIG_TEGRA_MIGRATE_CBUS_USERS
static DEFINE_MUTEX(cbus_mutex);
+#define CROSS_CBUS_MUTEX (&cbus_mutex)
+#else
+#define CROSS_CBUS_MUTEX NULL
+#endif
+
static struct clk_mux_sel mux_clk_cbus[] = {
{ .input = &tegra_clk_c2bus, .value = 0},
.dev_id = _dev, \
.con_id = _con, \
}, \
- .ops = &tegra_clk_shared_bus_ops, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
.parent = _parent, \
.inputs = mux_clk_cbus, \
.flags = MUX, \
.client_div = _div, \
.mode = _mode, \
}, \
- .cross_clk_mutex = &cbus_mutex, \
+ .cross_clk_mutex = CROSS_CBUS_MUTEX, \
}
#else
+
+static struct raw_notifier_head cbus_rate_change_nh;
+
static struct clk tegra_clk_cbus = {
.name = "cbus",
.parent = &tegra_pll_c,
.ops = &tegra_clk_cbus_ops,
- .max_rate = 600000000,
+ .max_rate = 700000000,
.mul = 1,
.div = 2,
.flags = PERIPH_ON_CBUS,
.shared_bus_backup = {
.input = &tegra_pll_p,
- }
+ },
+ .rate_change_nh = &cbus_rate_change_nh,
};
#endif
.dev_id = _dev, \
.con_id = _con, \
}, \
- .ops = &tegra_clk_shared_bus_ops, \
+ .ops = &tegra_clk_shared_bus_user_ops, \
.parent = _parent, \
.u.shared_bus_user = { \
.client_id = _id, \
PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("sbc1", "tegra11-spi.0", NULL, 41, 0x134, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc2", "tegra11-spi.1", NULL, 44, 0x118, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc3", "tegra11-spi.2", NULL, 46, 0x11c, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc4", "tegra11-spi.3", NULL, 68, 0x1b4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc5", "tegra11-spi.4", NULL, 104, 0x3c8, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc6", "tegra11-spi.5", NULL, 105, 0x3cc, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc1", "tegra11-spi.0", NULL, 41, 0x134, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc2", "tegra11-spi.1", NULL, 44, 0x118, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc3", "tegra11-spi.2", NULL, 46, 0x11c, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc4", "tegra11-spi.3", NULL, 68, 0x1b4, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc5", "tegra11-spi.4", NULL, 104, 0x3c8, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("sbc6", "tegra11-spi.5", NULL, 105, 0x3cc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB),
PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
+ PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 200000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("trace", "trace", NULL, 77, 0x634, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 12000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("i2c1", "tegra11-i2c.0", "div-clk", 12, 0x124, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c3", "tegra11-i2c.2", "div-clk", 67, 0x1b8, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 58300000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c1-fast", "tegra11-i2c.0", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c2-fast", "tegra11-i2c.1", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c3-fast", "tegra11-i2c.2", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c4-fast", "tegra11-i2c.3", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("i2c5-fast", "tegra11-i2c.4", "fast-clk", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
+ PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0),
PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 408000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
- PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71, &tegra_vi_clk_ops),
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+ PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+ PERIPH_CLK_EX("vi", "vi", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+ PERIPH_CLK("vi_sensor", "vi", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
+ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 700000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
PERIPH_CLK("msenc", "msenc", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
#else
- PERIPH_CLK("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK_EX("msenc", "msenc", NULL, 91, 0x1f0, 600000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
#endif
PERIPH_CLK("tsec", "tsec", NULL, 83, 0x1f4, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71),
+ PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 384000000, mux_pllm_pllc2_c_c3_pllp_plla, MUX | MUX8 | DIV_U71 | DIV_U71_INT),
PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops),
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 198000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
+ PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0),
PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0x4b8, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsi_clk_ops),
PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB),
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
- PERIPH_CLK("cilab", "tegra_camera", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cilcd", "tegra_camera", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("cile", "tegra_camera", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
- PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 156000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
-
- PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
+ PERIPH_CLK("csi", "vi", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
+ PERIPH_CLK("isp", "vi", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
+ PERIPH_CLK("csus", "vi", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
+ PERIPH_CLK("cilab", "vi", "cilab", 144, 0x614, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cilcd", "vi", "cilcd", 145, 0x618, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("cile", "vi", "cile", 146, 0x61c, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("dsialp", "tegradc.0", "dsialp", 147, 0x620, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+ PERIPH_CLK("dsiblp", "tegradc.1", "dsiblp", 148, 0x624, 102000000, mux_pllp_pllc_clkm, MUX | DIV_U71),
+
+ PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 12000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
PERIPH_CLK("se", "se", NULL, 127, 0x42c, 600000000, mux_pllp_pllc2_c_c3_pllm_clkm, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("cl_dvfs_ref", "dfll_cpu", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
- PERIPH_CLK("cl_dvfs_soc", "dfll_cpu", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+ PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 102000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT),
+ PERIPH_CLK("cl_dvfs_ref", "tegra_cl_dvfs", "ref", 155, 0x62c, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+ PERIPH_CLK("cl_dvfs_soc", "tegra_cl_dvfs", "soc", 155, 0x630, 54000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
PERIPH_CLK("soc_therm", "soc_therm", NULL, 78, 0x644, 136000000, mux_pllm_pllc_pllp_plla, MUX | MUX8 | DIV_U71 | PERIPH_ON_APB),
PERIPH_CLK("dds", "dds", NULL, 150, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0),
+ SHARED_CLK("override.sclk", "override_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_OVERRIDE),
SHARED_CLK("sbc1.sclk", "tegra11-spi.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("sbc2.sclk", "tegra11-spi.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("sbc3.sclk", "tegra11-spi.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("msenc.emc", "tegra_msenc", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("tsec.emc", "tegra_tsec", "emc", &tegra_clk_emc, NULL, 0, 0),
SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0),
- SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
+ SHARED_CLK("camera.emc", "vi", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("iso.emc", "iso", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW),
SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0),
+ SHARED_CLK("override.emc", "override.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.emc", "edp.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING),
#ifdef CONFIG_TEGRA_DUAL_CBUS
DUAL_CBUS_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_c2bus, "3d", 0, 0),
DUAL_CBUS_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_c2bus, "2d", 0, 0),
+ DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c2bus, "epp", 0, 0),
SHARED_CLK("cap.c2bus", "cap.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.c2bus", "floor.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, 0),
+ SHARED_CLK("override.c2bus", "override.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.c2bus", "edp.c2bus", NULL, &tegra_clk_c2bus, NULL, 0, SHARED_CEILING),
- DUAL_CBUS_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_c3bus, "epp", 0, 0),
DUAL_CBUS_CLK("msenc.cbus", "tegra_msenc", "msenc", &tegra_clk_c3bus, "msenc", 0, 0),
DUAL_CBUS_CLK("tsec.cbus", "tegra_tsec", "tsec", &tegra_clk_c3bus, "tsec", 0, 0),
DUAL_CBUS_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_c3bus, "vde", 0, 0),
DUAL_CBUS_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_c3bus, "se", 0, 0),
SHARED_CLK("cap.c3bus", "cap.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.c3bus", "floor.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, 0),
+ SHARED_CLK("override.c3bus", "override.c3bus", NULL, &tegra_clk_c3bus, NULL, 0, SHARED_OVERRIDE),
#else
SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0),
SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0),
SHARED_CLK("se.cbus", "tegra11-se", NULL, &tegra_clk_cbus, "se", 0, 0),
SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0),
+ SHARED_CLK("override.cbus", "override.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_OVERRIDE),
+ SHARED_CLK("edp.cbus", "edp.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING),
#endif
};
#define XUSB_ID "tegra_xhci"
static struct clk tegra_xusb_source_clks[] = {
- PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | PERIPH_NO_RESET | PERIPH_ON_APB),
+ PERIPH_CLK("xusb_host_src", XUSB_ID, "host_src", 143, 0x600, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
+ PERIPH_CLK("xusb_falcon_src", XUSB_ID, "falcon_src", 143, 0x604, 350000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_fs_src", XUSB_ID, "fs_src", 143, 0x608, 48000000, mux_clkm_48M_pllp_480M, MUX | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_ss_src", XUSB_ID, "ss_src", 143, 0x610, 120000000, mux_clkm_pllre_clk32_480M_pllc_ref, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET),
+ PERIPH_CLK("xusb_dev_src", XUSB_ID, "dev_src", 95, 0x60c, 120000000, mux_clkm_pllp_pllc_pllre, MUX | MUX8 | DIV_U71 | DIV_U71_INT | PERIPH_NO_RESET | PERIPH_ON_APB),
{
.name = "xusb_hs_src",
.lookup = {
.flags = PLLU | PERIPH_NO_ENB,
.max_rate = 60000000,
.u.periph = {
- .src_mask = 0x1,
+ .src_mask = 0x1 << 25,
.src_shift = 25,
},
},
CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"),
CLK_DUPLICATE("avp.emc", "nvavp", "emc"),
CLK_DUPLICATE("vde.cbus", "nvavp", "vde"),
- CLK_DUPLICATE("i2c5", "dfll_cpu", "i2c"),
- CLK_DUPLICATE("i2c5-fast", "dfll_cpu", "i2c_fast"),
+ CLK_DUPLICATE("i2c5", "tegra_cl_dvfs", "i2c"),
+ CLK_DUPLICATE("cpu_g", "tegra_cl_dvfs", "safe_dvfs"),
CLK_DUPLICATE("host1x", "tegra_host1x", "host1x"),
CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"),
};
clkdev_add(&c->lookup);
}
+int tegra11_cpu_backup_rate_exchange(unsigned long *rate)
+{
+ struct clk *backup = tegra_clk_cpu_cmplx.parent->u.cpu.backup;
+ unsigned long old_rate = clk_get_rate(backup);
+ unsigned long new_rate = min(
+ *rate, tegra_clk_cpu_cmplx.parent->u.cpu.backup_rate);
+ *rate = old_rate;
+ if (new_rate != old_rate)
+ return clk_set_rate(backup, new_rate);
+ return 0;
+}
+
+void tegra_edp_throttle_cpu_now(u8 factor)
+{
+ /* empty definition for tegra11 */
+ return;
+}
+
bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
{
/*
* respective muxes statically.
*/
- /* pll_c can be used as a clock source for EMC only on configuration
- with dual cbus, or as a clock source for single cbus */
- if (p == &tegra_pll_c) {
+ /*
+ * In configuration with dual cbus pll_c can be used as a scaled clock
+ * source for EMC only when pll_m is fixed, or as a general fixed rate
+ * clock source for EMC and other peripherals is pll_m is scaled. In
+ * configuration with single cbus pll_c can be used as a scaled cbus
+ * clock source only.
+ */
+ if ((p == &tegra_pll_c) && (c != &tegra_pll_c_out1)) {
#ifdef CONFIG_TEGRA_DUAL_CBUS
+#ifndef CONFIG_TEGRA_PLLM_SCALED
return c->flags & PERIPH_EMC_ENB;
+#endif
#else
return c->flags & PERIPH_ON_CBUS;
#endif
}
+
+ /*
+ * In any configuration pll_m must not be used as a clock source for
+ * cbus modules. If pll_m is scaled it can be used as EMC source only.
+ * Otherwise fixed rate pll_m can be used as clock source for EMC and
+ * other peripherals.
+ */
+ if ((p == &tegra_pll_m) && (c != &tegra_pll_m_out1)) {
+ if (c->flags & PERIPH_ON_CBUS)
+ return false;
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ return c->flags & PERIPH_EMC_ENB;
+#endif
+ }
return true;
}
* Frequency table index must be sequential starting at 0 and frequencies
* must be ascending.
*/
-#define CPU_FREQ_STEP 100000 /* 100MHz */
+#define CPU_FREQ_STEP 102000 /* 102MHz cpu_g table step */
#define CPU_FREQ_TABLE_MAX_SIZE (2 * MAX_DVFS_FREQS + 1)
static struct cpufreq_frequency_table freq_table[CPU_FREQ_TABLE_MAX_SIZE];
struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
{
int i, j;
+ bool g_vmin_done = false;
unsigned int freq, lp_backup_freq, g_vmin_freq, g_start_freq, max_freq;
struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g");
struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp");
if (freq <= lp_backup_freq)
continue;
- if (freq >= g_vmin_freq) {
- freq_table[i++].frequency = g_vmin_freq;
- if (freq == g_vmin_freq)
- continue;
+ if (!g_vmin_done && (freq >= g_vmin_freq)) {
+ g_vmin_done = true;
+ if (freq > g_vmin_freq)
+ freq_table[i++].frequency = g_vmin_freq;
}
freq_table[i++].frequency = freq;
/* Vote on memory bus frequency based on cpu frequency;
cpu rate is in kHz, emc rate is in Hz */
- if (cpu_rate >= 750000)
- return emc_max_rate; /* cpu >= 750 MHz, emc max */
- else if (cpu_rate >= 450000)
- return emc_max_rate/2; /* cpu >= 500 MHz, emc max/2 */
- else if (cpu_rate >= 250000)
- return 100000000; /* cpu >= 250 MHz, emc 100 MHz */
+ if (cpu_rate >= 1300000)
+ return emc_max_rate; /* cpu >= 1.3GHz, emc max */
+ else if (cpu_rate >= 975000)
+ return 400000000; /* cpu >= 975 MHz, emc 400 MHz */
+ else if (cpu_rate >= 725000)
+ return 200000000; /* cpu >= 725 MHz, emc 200 MHz */
+ else if (cpu_rate >= 500000)
+ return 100000000; /* cpu >= 500 MHz, emc 100 MHz */
+ else if (cpu_rate >= 275000)
+ return 50000000; /* cpu >= 275 MHz, emc 50 MHz */
else
return 0; /* emc min */
}
*ctx++ = clk_readl(tegra_pll_a_out0.reg);
*ctx++ = clk_readl(tegra_pll_c_out1.reg);
- *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
- *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
*ctx++ = clk_readl(tegra_clk_cclk_lp.reg);
*ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER);
*ctx++ = clk_readl(CLK_OUT_ENB_W);
*ctx++ = clk_readl(CLK_OUT_ENB_X);
+ *ctx++ = clk_readl(tegra_clk_cclk_g.reg);
+ *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
+
*ctx++ = clk_readl(SPARE_REG);
*ctx++ = clk_readl(MISC_CLK_ENB);
*ctx++ = clk_readl(CLK_MASK_ARM);
tegra11_pllcx_clk_resume_enable(&tegra_pll_c3);
tegra11_pllxc_clk_resume_enable(&tegra_pll_c);
tegra11_pllxc_clk_resume_enable(&tegra_pll_x);
+ tegra11_pllre_clk_resume_enable(&tegra_pll_re_out);
plla_base = *ctx++;
clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
pll_c_out1 = *ctx++;
clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg);
- clk_writel(*ctx++, tegra_clk_cclk_g.reg);
- clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
-
val = *ctx++;
tegra11_super_clk_resume(&tegra_clk_cclk_lp,
tegra_clk_virtual_cpu_lp.u.cpu.backup, val);
clk_writel(*ctx++, CLK_OUT_ENB_X);
wmb();
+ /* DFLL resume after cl_dvfs and i2c5 clocks are resumed */
+ tegra11_dfll_clk_resume(&tegra_dfll_cpu);
+
+ /* CPU G clock restored after DFLL and PLLs */
+ clk_writel(*ctx++, tegra_clk_cclk_g.reg);
+ clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER);
+
clk_writel(*ctx++, SPARE_REG);
clk_writel(*ctx++, MISC_CLK_ENB);
clk_writel(*ctx++, CLK_MASK_ARM);
p = &tegra_pll_x;
if (p->state == OFF)
tegra11_pllxc_clk_disable(p);
+ p = &tegra_pll_re_vco;
+ if (p->state == OFF)
+ tegra11_pllre_clk_disable(p);
clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE);
clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE);
tegra_emc_timing_invalidate();
tegra11_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */
+ tegra11_plle_clk_resume(&tegra_pll_e); /* Restore plle parent as pll_re_vco */
tegra11_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */
}