* arch/arm/mach-tegra/common.c
*
* Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010-2012 NVIDIA Corporation. All rights reserved.
+ * Copyright (C) 2010-2012 NVIDIA Corporation
*
* Author:
* Colin Cross <ccross@android.com>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
+#include <trace/events/nvsecurity.h>
+
#include <asm/soc.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#define AHB_ARBITRATION_PRIORITY_CTRL 0x4
#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
#define PRIORITY_SELECT_USB BIT(6)
+#define PRIORITY_SELECT_SDMMC4 BIT(12)
#define PRIORITY_SELECT_USB2 BIT(18)
#define PRIORITY_SELECT_USB3 BIT(17)
+#define PRIORITY_SELECT_SE BIT(14)
#define AHB_GIZMO_AHB_MEM 0xc
#define ENB_FAST_REARBITRATE BIT(2)
#define FORCED_RECOVERY_MODE BIT(1)
#define AHB_GIZMO_USB 0x1c
+#define AHB_GIZMO_SDMMC4 0x44
#define AHB_GIZMO_USB2 0x78
#define AHB_GIZMO_USB3 0x7c
+#define AHB_GIZMO_SE 0x4c
#define IMMEDIATE BIT(18)
+#define AHB_MEM_PREFETCH_CFG5 0xc4
#define AHB_MEM_PREFETCH_CFG3 0xe0
#define AHB_MEM_PREFETCH_CFG4 0xe4
#define AHB_MEM_PREFETCH_CFG1 0xec
#define AHB_MEM_PREFETCH_CFG2 0xf0
+#define AHB_MEM_PREFETCH_CFG6 0xcc
#define PREFETCH_ENB BIT(31)
#define MST_ID(x) (((x) & 0x1f) << 26)
#define AHBDMA_MST_ID MST_ID(5)
#define USB_MST_ID MST_ID(6)
+#define SDMMC4_MST_ID MST_ID(12)
#define USB2_MST_ID MST_ID(18)
#define USB3_MST_ID MST_ID(17)
+#define SE_MST_ID MST_ID(14)
#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
unsigned long tegra_avp_kernel_size;
unsigned long tegra_bootloader_fb_start;
unsigned long tegra_bootloader_fb_size;
+unsigned long tegra_bootloader_fb2_start;
+unsigned long tegra_bootloader_fb2_size;
unsigned long tegra_fb_start;
unsigned long tegra_fb_size;
unsigned long tegra_fb2_start;
unsigned long tegra_tsec_size;
unsigned long tegra_lp0_vec_start;
unsigned long tegra_lp0_vec_size;
+#ifdef CONFIG_TEGRA_NVDUMPER
+unsigned long nvdumper_reserved;
+#endif
bool tegra_lp0_vec_relocate;
unsigned long tegra_grhost_aperture = ~0ul;
static bool is_tegra_debug_uart_hsport;
static struct board_info pmu_board_info;
static struct board_info display_board_info;
+static int panel_id;
static struct board_info camera_board_info;
+static struct board_info io_board_info;
+static struct board_info button_board_info;
+static struct board_info joystick_board_info;
+static struct board_info rightspeaker_board_info;
+static struct board_info leftspeaker_board_info;
-static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
+static int pmu_core_edp;
static int board_panel_type;
static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
-
+static int pwr_i2c_clk = 400;
/*
* Storage for debug-macro.S's state.
*
static enum audio_codec_type audio_codec_name;
static enum image_type board_image_type = system_image;
static int max_cpu_current;
+static int max_core_current;
+static int emc_max_dvfs;
+static int usb_port_owner_info;
/* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
* and so this clock (pllp_out3) should never be disabled.
{ "sclk", NULL, 0, true },
{ "pll_p", NULL, 0, true },
{ "pll_p_out1", "pll_p", 0, false },
- { "pll_p_out3", "pll_p", 0, true },
+ { "pll_p_out3", "pll_p", 0, false },
#ifdef CONFIG_TEGRA_SILICON_PLATFORM
{ "pll_m_out1", "pll_m", 275000000, false },
{ "pll_p_out2", "pll_p", 102000000, false },
{ "csite", NULL, 0, true },
#endif
{ "pll_u", NULL, 480000000, true },
- { "pll_u_12M", NULL, 0, true },
- { "pll_u_48M", NULL, 0, true },
- { "pll_u_60M", NULL, 0, true },
- { "pll_u_480M", NULL, 0, true },
+ { "pll_re_vco", NULL, 312000000, false },
{ "sdmmc1", "pll_p", 48000000, false},
- { "sdmmc3", "pll_p", 48000000, true},
+ { "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ "sbc1.sclk", NULL, 40000000, false},
{ "sbc2.sclk", NULL, 40000000, false},
{ "sbc5.sclk", NULL, 40000000, false},
{ "sbc6.sclk", NULL, 40000000, false},
#ifdef CONFIG_TEGRA_DUAL_CBUS
- { "c2bus", "pll_c2", 300000000, false },
- { "c3bus", "pll_c3", 300000000, false },
+ { "c2bus", "pll_c2", 250000000, false },
+ { "c3bus", "pll_c3", 250000000, false },
+ { "pll_c", NULL, 624000000, false },
#else
- { "cbus", "pll_c", 416000000, false },
- { "pll_c_out1", "pll_c", 208000000, false },
+ { "cbus", "pll_c", 250000000, false },
+#endif
+ { "pll_c_out1", "pll_c", 150000000, false },
+#ifdef CONFIG_TEGRA_PLLM_SCALED
+ { "vi", "pll_p", 0, false},
#endif
{ NULL, NULL, 0, 0},
};
#endif
+#ifdef CONFIG_CACHE_L2X0
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_2x_SOC)
#ifdef CONFIG_TRUSTED_FOUNDATIONS
-#define CACHE_LINE_SIZE 32
-static inline void tegra_l2x0_disable_tz(void)
+static void tegra_cache_smc(bool enable, u32 arg)
{
- static u32 l2x0_way_mask;
+ void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+ bool need_affinity_switch;
+ bool can_switch_affinity;
+ bool l2x0_enabled;
+ cpumask_t local_cpu_mask;
+ cpumask_t saved_cpu_mask;
+ unsigned long flags;
+ long ret;
- BUG_ON(smp_processor_id() != 0);
+ /*
+ * ISSUE : Some registers of PL310 controler must be written
+ * from Secure context (and from CPU0)!
+ *
+ * When called form Normal we obtain an abort or do nothing.
+ * Instructions that must be called in Secure:
+ * - Write to Control register (L2X0_CTRL==0x100)
+ * - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
+ * - Invalidate all entries (L2X0_INV_WAY==0x77C),
+ * mandatory at boot time.
+ * - Tag and Data RAM Latency Control Registers
+ * (0x108 & 0x10C) must be written in Secure.
+ */
+ need_affinity_switch = (smp_processor_id() != 0);
+ can_switch_affinity = !irqs_disabled();
+
+ WARN_ON(need_affinity_switch && !can_switch_affinity);
+ if (need_affinity_switch && can_switch_affinity) {
+ cpu_set(0, local_cpu_mask);
+ sched_getaffinity(0, &saved_cpu_mask);
+ ret = sched_setaffinity(0, &local_cpu_mask);
+ WARN_ON(ret != 0);
+ }
+
+ local_irq_save(flags);
+ l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
+ if (enable && !l2x0_enabled)
+ tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
+ else if (!enable && l2x0_enabled)
+ tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
+ local_irq_restore(flags);
+
+ if (need_affinity_switch && can_switch_affinity) {
+ ret = sched_setaffinity(0, &saved_cpu_mask);
+ WARN_ON(ret != 0);
+ }
+}
+
+static void tegra_l2x0_disable(void)
+{
+ unsigned long flags;
+ static u32 l2x0_way_mask;
if (!l2x0_way_mask) {
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
l2x0_way_mask = (1 << ways) - 1;
}
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- /* flush all ways on disable */
- tegra_generic_smc_uncached(0xFFFFF100, 0x00000002, l2x0_way_mask);
-#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
- if (tegra_is_cpu_in_lp2(0)) {
- register unsigned long sp asm ("sp");
- /* flush only the stack, if entering LP2 */
- __cpuc_flush_dcache_area((void *)sp, (CACHE_LINE_SIZE * 2));
- outer_flush_range(__pa(sp), __pa(sp) + (CACHE_LINE_SIZE * 2));
-
- /* pass zero arg, so secureos flushes only its workspace */
- tegra_generic_smc_uncached(0xFFFFF100, 0x00000002,
- l2x0_way_mask);
- } else {
- /* flush all ways on disable, if entering LP0/LP1 */
- tegra_generic_smc_uncached(0xFFFFF100, 0x00000002,
- l2x0_way_mask);
- }
-#endif
+ local_irq_save(flags);
+ tegra_cache_smc(false, l2x0_way_mask);
+ local_irq_restore(flags);
}
+#endif /* CONFIG_TRUSTED_FOUNDATIONS */
-static inline void tegra_init_cache_tz(bool init)
+void tegra_init_cache(bool init)
{
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl;
-
- BUG_ON(smp_processor_id() != 0);
-
- if (init) {
- /* init L2 from secureos */
- tegra_generic_smc(0xFFFFF100, 0x00000001, 0x0);
-
- /* common init called for outer call hookup */
- aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
- l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
-
-#ifdef CONFIG_OUTER_CACHE
- /* use our outer_disable() routine */
- outer_cache.disable = tegra_l2x0_disable_tz;
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
+ u32 cache_type;
+ u32 tag_latency, data_latency;
#endif
- } else {
- /* reenable L2 in secureos */
- aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
- tegra_generic_smc_uncached(0xFFFFF100, 0x00000004, aux_ctrl);
- }
-}
-#endif /* CONFIG_TRUSTED_FOUNDATIONS */
-#ifdef CONFIG_CACHE_L2X0
-void tegra_init_cache(bool init)
-{
#ifdef CONFIG_TRUSTED_FOUNDATIONS
- /* enable/re-enable of L2 handled by secureos */
- tegra_init_cache_tz(init);
+ /* issue the SMC to enable the L2 */
+ aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
+ trace_smc_init_cache(NVSEC_SMC_START);
+ tegra_cache_smc(true, aux_ctrl);
+ trace_smc_init_cache(NVSEC_SMC_DONE);
+
+ /* after init, reread aux_ctrl and register handlers */
+ aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
+ l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
+
+ /* override outer_disable() with our disable */
+ outer_cache.disable = tegra_l2x0_disable;
#else
- void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
- u32 aux_ctrl;
- u32 cache_type;
- u32 tag_latency = 0x770, data_latency = 0x770;
#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
tag_latency = 0x331;
data_latency = 0x441;
data_latency = 0x551;
}
}
+#else
+ tag_latency = 0x770;
+ data_latency = 0x770;
#endif
#endif
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
writel(aux_ctrl, p + L2X0_AUX_CTRL);
}
l2x0_enable();
-#endif /* CONFIG_TRUSTED_FOUNDATIONS */
+#endif
+}
+#else
+void tegra_init_cache(bool init)
+{
+}
+#endif
+#endif
+
+static void __init tegra_perf_init(void)
+{
+ u32 reg;
+
+ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(reg));
+ reg >>= 11;
+ reg = (1 << (reg & 0x1f))-1;
+ reg |= 0x80000000;
+ asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r"(reg));
+ reg = 1;
+ asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(reg));
}
-#endif /* CONFIG_CACHE_L2X0 */
static void __init tegra_init_power(void)
{
#ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
#endif
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+ /* some partitions need to be powergated by default for t11x */
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBA);
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBB);
+ tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_XUSBC);
+#endif
}
static inline unsigned long gizmo_readl(unsigned long offset)
val |= IMMEDIATE;
gizmo_writel(val, AHB_GIZMO_USB3);
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+ val = gizmo_readl(AHB_GIZMO_SDMMC4);
+ val |= IMMEDIATE;
+ gizmo_writel(val, AHB_GIZMO_SDMMC4);
+
+ val = gizmo_readl(AHB_GIZMO_SE);
+ val |= IMMEDIATE;
+ gizmo_writel(val, AHB_GIZMO_SE);
+#endif
+
val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
| AHB_PRIORITY_WEIGHT(7);
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+ val |= PRIORITY_SELECT_SE | PRIORITY_SELECT_SDMMC4;
+#endif
gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) |
INACTIVITY_TIMEOUT(0x1000);
gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
+
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG5);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | SDMMC4_MST_ID | ADDR_BNDRY(0xc) |
+ INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG5);
+
+ val = gizmo_readl(AHB_MEM_PREFETCH_CFG6);
+ val &= ~MST_ID(~0);
+ val |= PREFETCH_ENB | SE_MST_ID | ADDR_BNDRY(0xc) |
+ INACTIVITY_TIMEOUT(0x1000);
+ gizmo_writel(val, AHB_MEM_PREFETCH_CFG6);
+#endif
}
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
handler initializer is not called, so do it here for non-SMP. */
tegra_cpu_reset_handler_init();
#endif
+ tegra_perf_init();
tegra_init_fuse();
tegra2_init_clocks();
tegra2_init_dvfs();
handler initializer is not called, so do it here for non-SMP. */
tegra_cpu_reset_handler_init();
#endif
+ tegra_perf_init();
tegra_init_fuse();
tegra30_init_clocks();
tegra3_init_dvfs();
handler initializer is not called, so do it here for non-SMP. */
tegra_cpu_reset_handler_init();
#endif
+ tegra_perf_init();
tegra_init_fuse();
tegra11x_init_clocks();
tegra11x_init_dvfs();
}
early_param("lp0_vec", tegra_lp0_vec_arg);
+#ifdef CONFIG_TEGRA_NVDUMPER
+static int __init tegra_nvdumper_arg(char *options)
+{
+ char *p = options;
+
+ nvdumper_reserved = memparse(p, &p);
+ return 0;
+}
+early_param("nvdumper_reserved", tegra_nvdumper_arg);
+#endif
+
static int __init tegra_bootloader_fb_arg(char *options)
{
char *p = options;
}
early_param("tegra_fbmem", tegra_bootloader_fb_arg);
+static int __init tegra_bootloader_fb2_arg(char *options)
+{
+ char *p = options;
+
+ tegra_bootloader_fb2_size = memparse(p, &p);
+ if (*p == '@')
+ tegra_bootloader_fb2_start = memparse(p+1, &p);
+
+ pr_info("Found tegra_fbmem2: %08lx@%08lx\n",
+ tegra_bootloader_fb2_size, tegra_bootloader_fb2_start);
+
+ return 0;
+}
+early_param("tegra_fbmem2", tegra_bootloader_fb2_arg);
+
static int __init tegra_sku_override(char *id)
{
char *p = id;
}
__setup("panel=", tegra_board_panel_type);
+int tegra_get_board_panel_id(void)
+{
+ return panel_id;
+}
+static int __init tegra_board_panel_id(char *options)
+{
+ char *p = options;
+ panel_id = memparse(p, &p);
+ return panel_id;
+}
+__setup("display_panel=", tegra_board_panel_id);
+
enum power_supply_type get_power_supply_type(void)
{
return pow_supply_type;
}
__setup("max_cpu_cur_ma=", tegra_max_cpu_current);
+int get_maximum_core_current_supported(void)
+{
+ return max_core_current;
+}
+static int __init tegra_max_core_current(char *options)
+{
+ char *p = options;
+ max_core_current = memparse(p, &p);
+ return 1;
+}
+__setup("core_edp_ma=", tegra_max_core_current);
+
+int get_emc_max_dvfs(void)
+{
+ return emc_max_dvfs;
+}
+static int __init tegra_emc_max_dvfs(char *options)
+{
+ char *p = options;
+ emc_max_dvfs = memparse(p, &p);
+ return 1;
+}
+__setup("emc_max_dvfs", tegra_emc_max_dvfs);
+
static int __init tegra_debug_uartport(char *info)
{
char *p = info;
}
__setup("audio_codec=", tegra_audio_codec_type);
+static int tegra_get_pwr_i2c_clk_rate(char *options)
+{
+ int clk = simple_strtol(options, NULL, 16);
+ if (clk != 0)
+ pwr_i2c_clk = clk;
+ return 0;
+}
+
+int get_pwr_i2c_clk_rate(void)
+{
+ return pwr_i2c_clk;
+}
+__setup("pwr_i2c=", tegra_get_pwr_i2c_clk_rate);
void tegra_get_board_info(struct board_info *bi)
{
__setup("cameraboard=", tegra_camera_board_info);
+static int __init tegra_leftspeaker_board_info(char *info)
+{
+ char *p = info;
+ leftspeaker_board_info.board_id = memparse(p, &p);
+ leftspeaker_board_info.sku = memparse(p+1, &p);
+ leftspeaker_board_info.fab = memparse(p+1, &p);
+ leftspeaker_board_info.major_revision = memparse(p+1, &p);
+ leftspeaker_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_leftspeaker_board_info(struct board_info *bi)
+{
+ memcpy(bi, &leftspeaker_board_info, sizeof(struct board_info));
+}
+
+__setup("leftspeakerboard=", tegra_leftspeaker_board_info);
+
+static int __init tegra_rightspeaker_board_info(char *info)
+{
+ char *p = info;
+ rightspeaker_board_info.board_id = memparse(p, &p);
+ rightspeaker_board_info.sku = memparse(p+1, &p);
+ rightspeaker_board_info.fab = memparse(p+1, &p);
+ rightspeaker_board_info.major_revision = memparse(p+1, &p);
+ rightspeaker_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_rightspeaker_board_info(struct board_info *bi)
+{
+ memcpy(bi, &rightspeaker_board_info, sizeof(struct board_info));
+}
+
+__setup("rightspeakerboard=", tegra_rightspeaker_board_info);
+
+static int __init tegra_joystick_board_info(char *info)
+{
+ char *p = info;
+ joystick_board_info.board_id = memparse(p, &p);
+ joystick_board_info.sku = memparse(p+1, &p);
+ joystick_board_info.fab = memparse(p+1, &p);
+ joystick_board_info.major_revision = memparse(p+1, &p);
+ joystick_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_joystick_board_info(struct board_info *bi)
+{
+ memcpy(bi, &joystick_board_info, sizeof(struct board_info));
+}
+
+__setup("joystickboard=", tegra_joystick_board_info);
+
+static int __init tegra_button_board_info(char *info)
+{
+ char *p = info;
+ button_board_info.board_id = memparse(p, &p);
+ button_board_info.sku = memparse(p+1, &p);
+ button_board_info.fab = memparse(p+1, &p);
+ button_board_info.major_revision = memparse(p+1, &p);
+ button_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_button_board_info(struct board_info *bi)
+{
+ memcpy(bi, &button_board_info, sizeof(struct board_info));
+}
+
+__setup("buttonboard=", tegra_button_board_info);
+
+static int __init tegra_io_board_info(char *info)
+{
+ char *p = info;
+ io_board_info.board_id = memparse(p, &p);
+ io_board_info.sku = memparse(p+1, &p);
+ io_board_info.fab = memparse(p+1, &p);
+ io_board_info.major_revision = memparse(p+1, &p);
+ io_board_info.minor_revision = memparse(p+1, &p);
+ return 1;
+}
+
+void tegra_get_io_board_info(struct board_info *bi)
+{
+ memcpy(bi, &io_board_info, sizeof(struct board_info));
+}
+
+__setup("ioboard=", tegra_io_board_info);
+
static int __init tegra_modem_id(char *id)
{
char *p = id;
__setup("modem_id=", tegra_modem_id);
+static int __init tegra_usb_port_owner_info(char *id)
+{
+ char *p = id;
+
+ usb_port_owner_info = memparse(p, &p);
+ return 1;
+}
+
+int tegra_get_usb_port_owner_info(void)
+{
+ return usb_port_owner_info;
+}
+
+__setup("usb_port_owner_info=", tegra_usb_port_owner_info);
+
static int __init tegra_commchip_id(char *id)
{
char *p = id;
* highmem, or outside the memory map) to a physical address that is outside
* the memory map.
*/
-void tegra_move_framebuffer(unsigned long to, unsigned long from,
+void __tegra_move_framebuffer(struct platform_device *pdev,
+ unsigned long to, unsigned long from,
unsigned long size)
{
struct page *page;
iounmap(to_io);
}
+void __tegra_clear_framebuffer(struct platform_device *pdev,
+ unsigned long to, unsigned long size)
+{
+ void __iomem *to_io;
+ unsigned long i;
+
+ BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
+ BUG_ON(PAGE_ALIGN(size) != size);
+
+ to_io = ioremap(to, size);
+ if (!to_io) {
+ pr_err("%s: Failed to map target framebuffer\n", __func__);
+ return;
+ }
+
+ if (pfn_valid(page_to_pfn(phys_to_page(to)))) {
+ for (i = 0 ; i < size; i += PAGE_SIZE)
+ memset(to_io + i, 0, PAGE_SIZE);
+ } else {
+ for (i = 0; i < size; i += 4)
+ writel(0, to_io + i);
+ }
+ iounmap(to_io);
+}
+
void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
unsigned long fb2_size)
{
} else
tegra_lp0_vec_relocate = true;
+#ifdef CONFIG_TEGRA_NVDUMPER
+ if (nvdumper_reserved) {
+ if (memblock_reserve(nvdumper_reserved, NVDUMPER_RESERVED_SIZE)) {
+ pr_err("Failed to reserve nvdumper page %08lx@%08lx\n",
+ nvdumper_reserved, NVDUMPER_RESERVED_SIZE);
+ nvdumper_reserved = 0;
+ }
+ }
+#endif
+
/*
* We copy the bootloader's framebuffer to the framebuffer allocated
* above, and then free this one.
}
}
+ if (tegra_bootloader_fb2_size) {
+ tegra_bootloader_fb2_size =
+ PAGE_ALIGN(tegra_bootloader_fb2_size);
+ if (memblock_reserve(tegra_bootloader_fb2_start,
+ tegra_bootloader_fb2_size)) {
+ pr_err("Failed to reserve bootloader fb2 %08lx@%08lx\n",
+ tegra_bootloader_fb2_size,
+ tegra_bootloader_fb2_start);
+ tegra_bootloader_fb2_start = 0;
+ tegra_bootloader_fb2_size = 0;
+ }
+ }
+
pr_info("Tegra reserved memory:\n"
"LP0: %08lx - %08lx\n"
"Bootloader framebuffer: %08lx - %08lx\n"
+ "Bootloader framebuffer2: %08lx - %08lx\n"
"Framebuffer: %08lx - %08lx\n"
"2nd Framebuffer: %08lx - %08lx\n"
"Carveout: %08lx - %08lx\n"
tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
tegra_bootloader_fb_start,
tegra_bootloader_fb_size ?
- tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1
- : 0,
+ tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
+ tegra_bootloader_fb2_start,
+ tegra_bootloader_fb2_size ?
+ tegra_bootloader_fb2_start + tegra_bootloader_fb2_size - 1 : 0,
tegra_fb_start,
tegra_fb_size ?
tegra_fb_start + tegra_fb_size - 1 : 0,
tegra_avp_kernel_start,
tegra_avp_kernel_start + tegra_avp_kernel_size - 1);
}
+
+#ifdef CONFIG_TEGRA_NVDUMPER
+ if (nvdumper_reserved) {
+ pr_info("Nvdumper: %08lx - %08lx\n",
+ nvdumper_reserved,
+ nvdumper_reserved + NVDUMPER_RESERVED_SIZE - 1);
+ }
+#endif
}
#ifdef CONFIG_ANDROID_RAM_CONSOLE
if (memblock_free(tegra_bootloader_fb_start,
tegra_bootloader_fb_size))
pr_err("Failed to free bootloader fb.\n");
+ if (tegra_bootloader_fb2_size)
+ if (memblock_free(tegra_bootloader_fb2_start,
+ tegra_bootloader_fb2_size))
+ pr_err("Failed to free bootloader fb2.\n");
}
static struct platform_device *pinmux_devices[] = {