/*
* arch/arm/mach-tegra/board-cardhu-panel.c
*
- * Copyright (c) 2010, NVIDIA Corporation.
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <asm/mach-types.h>
#include <linux/platform_device.h>
#include <linux/pwm_backlight.h>
-#include <mach/nvhost.h>
+#include <asm/atomic.h>
+#include <linux/nvhost.h>
#include <mach/nvmap.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include "devices.h"
#include "gpio-names.h"
-#ifdef CONFIG_TEGRA_CARDHU_DSI
/* Select panel to be used. */
#define DSI_PANEL_219 0
#define DSI_PANEL_218 1
#define AVDD_LCD PMU_TCA6416_GPIO_PORT17
-#endif
+#define DSI_PANEL_RESET 0
+#define pm269_lvds_shutdown TEGRA_GPIO_PN6
#define cardhu_lvds_shutdown TEGRA_GPIO_PL2
#define cardhu_bl_enb TEGRA_GPIO_PH2
#define cardhu_bl_pwm TEGRA_GPIO_PH0
#define cardhu_hdmi_hpd TEGRA_GPIO_PN7
-#ifdef DSI_PANEL_219
+#if defined(DSI_PANEL_219) || defined(DSI_PANEL_218)
#define cardhu_dsia_bl_enb TEGRA_GPIO_PW1
#define cardhu_dsib_bl_enb TEGRA_GPIO_PW0
#define cardhu_dsi_panel_reset TEGRA_GPIO_PD2
static struct regulator *cardhu_hdmi_pll = NULL;
static struct regulator *cardhu_hdmi_vddio = NULL;
+static atomic_t sd_brightness = ATOMIC_INIT(255);
+
+#ifdef CONFIG_TEGRA_CARDHU_DSI
+static struct regulator *cardhu_dsi_reg = NULL;
+#else
+static struct regulator *cardhu_lvds_reg = NULL;
+static struct regulator *cardhu_lvds_vdd_bl = NULL;
+static struct regulator *cardhu_lvds_vdd_panel = NULL;
+#endif
+
+static struct board_info board_info;
+
+static tegra_dc_bl_output cardhu_bl_output_measured = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62,
+ 63, 64, 65, 66, 67, 68, 69, 70,
+ 70, 72, 73, 74, 75, 76, 77, 78,
+ 79, 80, 81, 82, 83, 84, 85, 86,
+ 87, 88, 89, 90, 91, 92, 93, 94,
+ 95, 96, 97, 98, 99, 100, 101, 102,
+ 103, 104, 105, 106, 107, 108, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 124, 125, 126,
+ 127, 128, 129, 130, 131, 132, 133, 133,
+ 134, 135, 136, 137, 138, 139, 140, 141,
+ 142, 143, 144, 145, 146, 147, 148, 148,
+ 149, 150, 151, 152, 153, 154, 155, 156,
+ 157, 158, 159, 160, 161, 162, 163, 164,
+ 165, 166, 167, 168, 169, 170, 171, 172,
+ 173, 174, 175, 176, 177, 179, 180, 181,
+ 182, 184, 185, 186, 187, 188, 189, 190,
+ 191, 192, 193, 194, 195, 196, 197, 198,
+ 199, 200, 201, 202, 203, 204, 205, 206,
+ 207, 208, 209, 211, 212, 213, 214, 215,
+ 216, 217, 218, 219, 220, 221, 222, 223,
+ 224, 225, 226, 227, 228, 229, 230, 231,
+ 232, 233, 234, 235, 236, 237, 238, 239,
+ 240, 241, 242, 243, 244, 245, 246, 247,
+ 248, 249, 250, 251, 252, 253, 254, 255
+};
+
+static p_tegra_dc_bl_output bl_output;
+
static int cardhu_backlight_init(struct device *dev) {
int ret;
+ bl_output = cardhu_bl_output_measured;
+
+ if (WARN_ON(ARRAY_SIZE(cardhu_bl_output_measured) != 256))
+ pr_err("bl_output array does not have 256 elements\n");
+
#ifndef CONFIG_TEGRA_CARDHU_DSI
tegra_gpio_disable(cardhu_bl_pwm);
gpio_free(cardhu_bl_enb);
else
tegra_gpio_enable(cardhu_bl_enb);
-#else
- #if DSI_PANEL_219
+
+ return ret;
+#endif
+
+#if DSI_PANEL_219 || DSI_PANEL_218
/* Enable back light for DSIa panel */
printk("cardhu_dsi_backlight_init\n");
ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
gpio_free(cardhu_dsib_bl_enb);
else
tegra_gpio_enable(cardhu_dsib_bl_enb);
- #endif
-
#endif
+
return ret;
};
static void cardhu_backlight_exit(struct device *dev) {
#ifndef CONFIG_TEGRA_CARDHU_DSI
- int ret;
- ret = gpio_request(cardhu_bl_enb, "backlight_enb");
+ /* int ret; */
+ /*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
gpio_set_value(cardhu_bl_enb, 0);
gpio_free(cardhu_bl_enb);
tegra_gpio_disable(cardhu_bl_enb);
-#else
- #if DSI_PANEL_219
+ return;
+#endif
+#if DSI_PANEL_219 || DSI_PANEL_218
/* Disable back light for DSIa panel */
gpio_set_value(cardhu_dsia_bl_enb, 0);
gpio_free(cardhu_dsia_bl_enb);
gpio_free(cardhu_dsib_bl_enb);
tegra_gpio_disable(cardhu_dsib_bl_enb);
- gpio_set_value(TEGRA_GPIO_PL2, 1);
+ gpio_set_value(cardhu_lvds_shutdown, 1);
mdelay(20);
- #endif
#endif
}
static int cardhu_backlight_notify(struct device *unused, int brightness)
{
+ int cur_sd_brightness = atomic_read(&sd_brightness);
+ int orig_brightness = brightness;
+
#ifndef CONFIG_TEGRA_CARDHU_DSI
- int ret;
- ret = gpio_request(cardhu_bl_enb, "backlight_enb");
+ /* Set the backlight GPIO pin mode to 'backlight_enable' */
+ gpio_request(cardhu_bl_enb, "backlight_enb");
gpio_set_value(cardhu_bl_enb, !!brightness);
-#else
- #if DSI_PANEL_219
+#elif DSI_PANEL_219 || DSI_PANEL_218
/* DSIa */
gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
/* DSIb */
gpio_set_value(cardhu_dsib_bl_enb, !!brightness);
- #endif
#endif
+
+ /* SD brightness is a percentage, 8-bit value. */
+ brightness = (brightness * cur_sd_brightness) / 255;
+
+ /* Apply any backlight response curve */
+ if (brightness > 255) {
+ pr_info("Error: Brightness > 255!\n");
+ } else {
+ brightness = bl_output[brightness];
+ }
+
return brightness;
}
.pwm_id = 0,
.max_brightness = 255,
.dft_brightness = 224,
- .pwm_period_ns = 5000000,
+ .pwm_period_ns = 1000000,
.init = cardhu_backlight_init,
.exit = cardhu_backlight_exit,
.notify = cardhu_backlight_notify,
},
};
+#ifndef CONFIG_TEGRA_CARDHU_DSI
static int cardhu_panel_enable(void)
{
- static struct regulator *reg = NULL;
+ if (cardhu_lvds_reg == NULL) {
+ cardhu_lvds_reg = regulator_get(NULL, "vdd_lvds");
+ if (WARN_ON(IS_ERR(cardhu_lvds_reg)))
+ pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
+ __func__, PTR_ERR(cardhu_lvds_reg));
+ else
+ regulator_enable(cardhu_lvds_reg);
+ }
- if (reg == NULL) {
- reg = regulator_get(NULL, "avdd_lvds");
- if (WARN_ON(IS_ERR(reg)))
- pr_err("%s: couldn't get regulator avdd_lvds: %ld\n",
- __func__, PTR_ERR(reg));
+ if (cardhu_lvds_vdd_bl == NULL) {
+ cardhu_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
+ if (WARN_ON(IS_ERR(cardhu_lvds_vdd_bl)))
+ pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
+ __func__, PTR_ERR(cardhu_lvds_vdd_bl));
else
- regulator_enable(reg);
+ regulator_enable(cardhu_lvds_vdd_bl);
}
- gpio_set_value(cardhu_lvds_shutdown, 1);
+ if (cardhu_lvds_vdd_panel == NULL) {
+ cardhu_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
+ if (WARN_ON(IS_ERR(cardhu_lvds_vdd_panel)))
+ pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
+ __func__, PTR_ERR(cardhu_lvds_vdd_panel));
+ else
+ regulator_enable(cardhu_lvds_vdd_panel);
+ }
+ if (board_info.board_id == BOARD_PM269)
+ gpio_set_value(pm269_lvds_shutdown, 1);
+ else
+ gpio_set_value(cardhu_lvds_shutdown, 1);
+
return 0;
}
static int cardhu_panel_disable(void)
{
- gpio_set_value(cardhu_lvds_shutdown, 0);
+ regulator_disable(cardhu_lvds_reg);
+ regulator_put(cardhu_lvds_reg);
+ cardhu_lvds_reg = NULL;
+
+ regulator_disable(cardhu_lvds_vdd_bl);
+ regulator_put(cardhu_lvds_vdd_bl);
+ cardhu_lvds_vdd_bl = NULL;
+
+ regulator_disable(cardhu_lvds_vdd_panel);
+ regulator_put(cardhu_lvds_vdd_panel);
+ cardhu_lvds_vdd_panel= NULL;
+ if (board_info.board_id == BOARD_PM269)
+ gpio_set_value(pm269_lvds_shutdown, 0);
+ else
+ gpio_set_value(cardhu_lvds_shutdown, 0);
+ return 0;
+}
+#endif
+
+static int cardhu_hdmi_vddio_enable(void)
+{
+ int ret;
+ if (!cardhu_hdmi_vddio) {
+ cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
+ if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
+ ret = PTR_ERR(cardhu_hdmi_vddio);
+ pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
+ cardhu_hdmi_vddio = NULL;
+ return ret;
+ }
+ }
+ ret = regulator_enable(cardhu_hdmi_vddio);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
+ regulator_put(cardhu_hdmi_vddio);
+ cardhu_hdmi_vddio = NULL;
+ return ret;
+ }
+ return ret;
+}
+
+static int cardhu_hdmi_vddio_disable(void)
+{
+ if (cardhu_hdmi_vddio) {
+ regulator_disable(cardhu_hdmi_vddio);
+ regulator_put(cardhu_hdmi_vddio);
+ cardhu_hdmi_vddio = NULL;
+ }
return 0;
}
pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
return ret;
}
- if (!cardhu_hdmi_vddio) {
- cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
- if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
- pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
- cardhu_hdmi_vddio = NULL;
- regulator_put(cardhu_hdmi_pll);
- cardhu_hdmi_pll = NULL;
- regulator_put(cardhu_hdmi_reg);
- cardhu_hdmi_reg = NULL;
-
- return PTR_ERR(cardhu_hdmi_vddio);
- }
- }
- ret = regulator_enable(cardhu_hdmi_vddio);
- if (ret < 0) {
- pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
- return ret;
- }
return 0;
}
static int cardhu_hdmi_disable(void)
{
-
regulator_disable(cardhu_hdmi_reg);
regulator_put(cardhu_hdmi_reg);
cardhu_hdmi_reg = NULL;
regulator_disable(cardhu_hdmi_pll);
regulator_put(cardhu_hdmi_pll);
cardhu_hdmi_pll = NULL;
-
- regulator_disable(cardhu_hdmi_vddio);
- regulator_put(cardhu_hdmi_vddio);
- cardhu_hdmi_vddio = NULL;
return 0;
}
static struct resource cardhu_disp1_resources[] = {
.end = 0, /* Filled in by cardhu_panel_init() */
.flags = IORESOURCE_MEM,
},
-#ifdef CONFIG_TEGRA_CARDHU_DSI
+#ifdef CONFIG_TEGRA_DSI_INSTANCE_1
+ {
+ .name = "dsi_regs",
+ .start = TEGRA_DSIB_BASE,
+ .end = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+#else
{
.name = "dsi_regs",
.start = TEGRA_DSI_BASE,
},
};
+#ifndef CONFIG_TEGRA_CARDHU_DSI
static struct tegra_dc_mode cardhu_panel_modes[] = {
{
- /* 1366x768@62.3Hz */
- .pclk = 72000000,
- .h_ref_to_sync = 4,
- .v_ref_to_sync = 2,
- .h_sync_width = 32,
+ /* 1366x768@60Hz */
+ .pclk = 74180000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 30,
.v_sync_width = 5,
- .h_back_porch = 20,
- .v_back_porch = 12,
+ .h_back_porch = 52,
+ .v_back_porch = 20,
.h_active = 1366,
.v_active = 768,
- .h_front_porch = 48,
- .v_front_porch = 3,
+ .h_front_porch = 64,
+ .v_front_porch = 25,
},
};
+static struct tegra_dc_mode cardhu_panel_modes_55hz[] = {
+ {
+ /* 1366x768p 55Hz */
+ .pclk = 68000000,
+ .h_ref_to_sync = 0,
+ .v_ref_to_sync = 12,
+ .h_sync_width = 30,
+ .v_sync_width = 5,
+ .h_back_porch = 52,
+ .v_back_porch = 20,
+ .h_active = 1366,
+ .v_active = 768,
+ .h_front_porch = 64,
+ .v_front_porch = 25,
+ },
+};
+#endif
+
+static struct tegra_dc_sd_settings cardhu_sd_settings = {
+ .enable = 1, /* enabled by default. */
+ .use_auto_pwm = false,
+ .hw_update_delay = 0,
+ .bin_width = -1,
+ .aggressiveness = 1,
+ .use_vid_luma = false,
+ /* Default video coefficients */
+ .coeff = {5, 9, 2},
+ .fc = {0, 0},
+ /* Immediate backlight changes */
+ .blp = {1024, 255},
+ /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+ /* Default BL TF */
+ .bltf = {
+ {
+ {57, 65, 74, 83},
+ {93, 103, 114, 126},
+ {138, 151, 165, 179},
+ {194, 209, 225, 242},
+ },
+ {
+ {58, 66, 75, 84},
+ {94, 105, 116, 127},
+ {140, 153, 166, 181},
+ {196, 211, 227, 244},
+ },
+ {
+ {60, 68, 77, 87},
+ {97, 107, 119, 130},
+ {143, 156, 170, 184},
+ {199, 215, 231, 248},
+ },
+ {
+ {64, 73, 82, 91},
+ {102, 113, 124, 137},
+ {149, 163, 177, 192},
+ {207, 223, 240, 255},
+ },
+ },
+ /* Default LUT */
+ .lut = {
+ {
+ {250, 250, 250},
+ {194, 194, 194},
+ {149, 149, 149},
+ {113, 113, 113},
+ {82, 82, 82},
+ {56, 56, 56},
+ {34, 34, 34},
+ {15, 15, 15},
+ {0, 0, 0},
+ },
+ {
+ {246, 246, 246},
+ {191, 191, 191},
+ {147, 147, 147},
+ {111, 111, 111},
+ {80, 80, 80},
+ {55, 55, 55},
+ {33, 33, 33},
+ {14, 14, 14},
+ {0, 0, 0},
+ },
+ {
+ {239, 239, 239},
+ {185, 185, 185},
+ {142, 142, 142},
+ {107, 107, 107},
+ {77, 77, 77},
+ {52, 52, 52},
+ {30, 30, 30},
+ {12, 12, 12},
+ {0, 0, 0},
+ },
+ {
+ {224, 224, 224},
+ {173, 173, 173},
+ {133, 133, 133},
+ {99, 99, 99},
+ {70, 70, 70},
+ {46, 46, 46},
+ {25, 25, 25},
+ {7, 7, 7},
+ {0, 0, 0},
+ },
+ },
+ .sd_brightness = &sd_brightness,
+ .bl_device = &cardhu_backlight_device,
+};
+
+#ifndef CONFIG_TEGRA_CARDHU_DSI
static struct tegra_fb_data cardhu_fb_data = {
.win = 0,
.xres = 1366,
.yres = 768,
- .bits_per_pixel = 16,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
};
+#endif
static struct tegra_fb_data cardhu_hdmi_fb_data = {
.win = 0,
.xres = 1366,
.yres = 768,
- .bits_per_pixel = 16,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
};
static struct tegra_dc_out cardhu_disp2_out = {
.dcc_bus = 3,
.hotplug_gpio = cardhu_hdmi_hpd,
+ .max_pixclock = KHZ2PICOS(148500),
+
.align = TEGRA_DC_ALIGN_MSB,
.order = TEGRA_DC_ORDER_RED_BLUE,
.enable = cardhu_hdmi_enable,
.disable = cardhu_hdmi_disable,
+
+ .postsuspend = cardhu_hdmi_vddio_disable,
+ .hotplug_init = cardhu_hdmi_vddio_enable,
};
static struct tegra_dc_platform_data cardhu_disp2_pdata = {
.flags = 0,
.default_out = &cardhu_disp2_out,
.fb = &cardhu_hdmi_fb_data,
+ .emc_clk_rate = 300000000,
};
#ifdef CONFIG_TEGRA_CARDHU_DSI
static int cardhu_dsi_panel_enable(void)
{
- static struct regulator *reg = NULL;
int ret;
- if (reg == NULL) {
- reg = regulator_get(NULL, "avdd_dsi_csi");
- if (IS_ERR_OR_NULL(reg)) {
+ if (cardhu_dsi_reg == NULL) {
+ cardhu_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
+ if (IS_ERR_OR_NULL(cardhu_dsi_reg)) {
pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
- reg = NULL;
- return PTR_ERR(reg);
+ cardhu_dsi_reg = NULL;
+ return PTR_ERR(cardhu_dsi_reg);
}
}
- regulator_enable(reg);
+ regulator_enable(cardhu_dsi_reg);
-#if DSI_PANEL_219
- ret = gpio_request(TEGRA_GPIO_PL2, "pl2");
+ ret = gpio_request(TEGRA_GPIO_PJ1, "DSI TE");
if (ret < 0)
return ret;
- ret = gpio_direction_output(TEGRA_GPIO_PL2, 0);
+
+ ret = gpio_direction_input(TEGRA_GPIO_PJ1);
if (ret < 0) {
- gpio_free(TEGRA_GPIO_PL2);
+ gpio_free(TEGRA_GPIO_PJ1);
return ret;
}
- else
- tegra_gpio_enable(TEGRA_GPIO_PL2);
+ tegra_gpio_enable(TEGRA_GPIO_PJ1);
+
+#if DSI_PANEL_219
ret = gpio_request(TEGRA_GPIO_PH0, "ph0");
if (ret < 0)
else
tegra_gpio_enable(TEGRA_GPIO_PU2);
- gpio_set_value(TEGRA_GPIO_PL2, 1);
+ gpio_set_value(cardhu_lvds_shutdown, 1);
mdelay(20);
gpio_set_value(TEGRA_GPIO_PH0, 1);
mdelay(10);
#if DSI_PANEL_218
printk("DSI_PANEL_218 is enabled\n");
- ret = gpio_request(AVDD_LCD, 1);
+ ret = gpio_request(AVDD_LCD, "avdd_lcd");
if(ret < 0)
gpio_free(AVDD_LCD);
ret = gpio_direction_output(AVDD_LCD, 1);
else
tegra_gpio_enable(AVDD_LCD);
+#if DSI_PANEL_RESET
ret = gpio_request(TEGRA_GPIO_PD2, "pd2");
if (ret < 0){
return ret;
mdelay(2);
gpio_set_value(TEGRA_GPIO_PD2, 1);
mdelay(2);
+#endif
#endif
return 0;
static int cardhu_dsi_panel_disable(void)
{
- return 0;
+ int err;
+
+ err = 0;
+ printk(KERN_INFO "DSI panel disable\n");
+
+#if DSI_PANEL_219
+ tegra_gpio_disable(TEGRA_GPIO_PU2);
+ gpio_free(TEGRA_GPIO_PU2);
+ tegra_gpio_disable(TEGRA_GPIO_PH2);
+ gpio_free(TEGRA_GPIO_PH2);
+ tegra_gpio_disable(TEGRA_GPIO_PH0);
+ gpio_free(TEGRA_GPIO_PH0);
+ tegra_gpio_disable(TEGRA_GPIO_PL2);
+ gpio_free(TEGRA_GPIO_PL2);
+#endif
+
+#if DSI_PANEL_218
+ tegra_gpio_disable(TEGRA_GPIO_PD2);
+ gpio_free(TEGRA_GPIO_PD2);
+#endif
+
+ return err;
+}
+
+static int cardhu_dsi_panel_postsuspend(void)
+{
+ int err;
+
+ err = 0;
+ printk(KERN_INFO "DSI panel postsuspend\n");
+
+ if (cardhu_dsi_reg) {
+ err = regulator_disable(cardhu_dsi_reg);
+ if (err < 0)
+ printk(KERN_ERR
+ "DSI regulator avdd_dsi_csi disable failed\n");
+ regulator_put(cardhu_dsi_reg);
+ cardhu_dsi_reg = NULL;
+ }
+
+#if DSI_PANEL_218
+ tegra_gpio_disable(AVDD_LCD);
+ gpio_free(AVDD_LCD);
+#endif
+
+ return err;
}
static struct tegra_dsi_cmd dsi_init_cmd[]= {
DSI_DLY_MS(20),
};
+static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
+ DSI_CMD_SHORT(0x05, 0x28, 0x00),
+ DSI_DLY_MS(20),
+ DSI_CMD_SHORT(0x05, 0x10, 0x00),
+ DSI_DLY_MS(5),
+};
+
struct tegra_dsi_out cardhu_dsi = {
.n_data_lanes = 2,
.pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
.virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
.panel_has_frame_buffer = true,
+#ifdef CONFIG_TEGRA_DSI_INSTANCE_1
+ .dsi_instance = 1,
+#else
+ .dsi_instance = 0,
+#endif
+ .panel_reset = DSI_PANEL_RESET,
.n_init_cmd = ARRAY_SIZE(dsi_init_cmd),
.dsi_init_cmd = dsi_init_cmd,
+ .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
+ .dsi_suspend_cmd = dsi_suspend_cmd,
+
.video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
+ .lp_cmd_mode_freq_khz = 430000,
};
static struct tegra_dc_mode cardhu_dsi_modes[] = {
#if DSI_PANEL_218
{
- .pclk = 48000000,
+ .pclk = 323000000,
.h_ref_to_sync = 11,
.v_ref_to_sync = 1,
.h_sync_width = 16,
.yres = 480,
.bits_per_pixel = 32,
#endif
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
};
#endif
static struct tegra_dc_out cardhu_disp1_out = {
.align = TEGRA_DC_ALIGN_MSB,
.order = TEGRA_DC_ORDER_RED_BLUE,
+ .sd_settings = &cardhu_sd_settings,
+ .parent_clk = "pll_p",
+
#ifndef CONFIG_TEGRA_CARDHU_DSI
.type = TEGRA_DC_OUT_RGB,
.enable = cardhu_dsi_panel_enable,
.disable = cardhu_dsi_panel_disable,
+ .postsuspend = cardhu_dsi_panel_postsuspend,
#endif
};
static struct tegra_dc_platform_data cardhu_disp1_pdata = {
.flags = TEGRA_DC_FLAG_ENABLED,
.default_out = &cardhu_disp1_out,
+ .emc_clk_rate = 300000000,
#ifndef CONFIG_TEGRA_CARDHU_DSI
.fb = &cardhu_fb_data,
#else
};
static struct nvmap_platform_carveout cardhu_carveouts[] = {
- [0] = {
- .name = "iram",
- .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM,
- .base = TEGRA_IRAM_BASE,
- .size = TEGRA_IRAM_SIZE,
- .buddy_size = 0, /* no buddy allocation for IRAM */
- },
+ [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
[1] = {
.name = "generic-0",
.usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC,
},
};
+
+#if defined(CONFIG_TEGRA_NVAVP)
+static struct resource tegra_nvavp_resources[] = {
+ [0] = {
+ .start = INT_SHR_SEM_INBOX_IBF,
+ .end = INT_SHR_SEM_INBOX_IBF,
+ .flags = IORESOURCE_IRQ,
+ .name = "mbox_from_avp_pending",
+ },
+};
+
+static struct nvhost_device cardhu_nvavp_device = {
+ .name = "tegra-avp",
+ .id = -1,
+ .resource = tegra_nvavp_resources,
+ .num_resources = ARRAY_SIZE(tegra_nvavp_resources),
+};
+#endif
+
static struct platform_device *cardhu_gfx_devices[] __initdata = {
&cardhu_nvmap_device,
&tegra_grhost_device,
int err;
struct resource *res;
+ tegra_get_board_info(&board_info);
+
cardhu_carveouts[1].base = tegra_carveout_start;
cardhu_carveouts[1].size = tegra_carveout_size;
+ if (board_info.board_id == BOARD_E1291 &&
+ ((board_info.sku & SKU_TOUCHSCREEN_MECH_FIX) == 0)) {
+ /* use 55Hz panel timings to reduce noise on sensitive touch */
+ printk("Using cardhu_panel_modes_55hz\n");
+ cardhu_disp1_out.modes = cardhu_panel_modes_55hz;
+ cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes_55hz);
+ }
+
+ if (board_info.board_id == BOARD_PM269) {
+ gpio_request(pm269_lvds_shutdown, "lvds_shutdown");
+ gpio_direction_output(pm269_lvds_shutdown, 1);
+ tegra_gpio_enable(pm269_lvds_shutdown);
+ } else {
+ gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
+ gpio_direction_output(cardhu_lvds_shutdown, 1);
+ tegra_gpio_enable(cardhu_lvds_shutdown);
+ }
+
tegra_gpio_enable(cardhu_hdmi_hpd);
gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
gpio_direction_input(cardhu_hdmi_hpd);
res->start = tegra_fb_start;
res->end = tegra_fb_start + tegra_fb_size - 1;
+ /* Copy the bootloader fb to the fb. */
+ tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
+ min(tegra_fb_size, tegra_bootloader_fb_size));
+
if (!err)
err = nvhost_device_register(&cardhu_disp1_device);
res->end = tegra_fb2_start + tegra_fb2_size - 1;
if (!err)
err = nvhost_device_register(&cardhu_disp2_device);
+
+#if defined(CONFIG_TEGRA_NVAVP)
+ if (!err)
+ err = nvhost_device_register(&cardhu_nvavp_device);
+#endif
return err;
}