arm: tegra: cardhu: add support for PM315
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-memory.c
index ca9178b..7e73292 100644 (file)
 #include "fuse.h"
 #include "devices.h"
 
+static const struct tegra30_emc_table cardhu_emc_tables_h5tc4g83mfr[] = {
+       {
+               0x32,       /* Rev 3.2 */
+               51000,      /* SDRAM frequency */
+               {
+                       0x00000002, /* EMC_RC */
+                       0x0000000d, /* EMC_RFC */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000181, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000000e, /* EMC_TXSR */
+                       0x0000000e, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000002, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000018e, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x007800a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000040, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00010003, /* MC_EMEM_ARB_CFG */
+                       0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74630303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               102000,     /* SDRAM frequency */
+               {
+                       0x00000004, /* EMC_RC */
+                       0x0000001a, /* EMC_RFC */
+                       0x00000003, /* EMC_RAS */
+                       0x00000001, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000001, /* EMC_RD_RCD */
+                       0x00000001, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000001c, /* EMC_TXSR */
+                       0x0000001c, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000004, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000031c, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x007800a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000040, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73c30504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               204000,     /* SDRAM frequency */
+               {
+                       0x00000009, /* EMC_RC */
+                       0x00000035, /* EMC_RFC */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000038, /* EMC_TXSR */
+                       0x00000038, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000007, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x004400a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00080000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000003, /* MC_EMEM_ARB_CFG */
+                       0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
+                       0x73840a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               400000,     /* SDRAM frequency */
+               {
+                       0x00000012, /* EMC_RC */
+                       0x00000066, /* EMC_RFC */
+                       0x0000000c, /* EMC_RAS */
+                       0x00000004, /* EMC_RP */
+                       0x00000003, /* EMC_R2W */
+                       0x00000008, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x0000000a, /* EMC_W2P */
+                       0x00000004, /* EMC_RD_RCD */
+                       0x00000004, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x0000000d, /* EMC_RDV */
+                       0x00000bf0, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000008, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000006c, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x0000000c, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000c30, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00007088, /* EMC_FBIO_CFG5 */
+                       0x001d0084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00038000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00038000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00030000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f508, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x080001e8, /* EMC_XM2QUSEPADCTRL */
+                       0x08000021, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x0158000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000006, /* MC_EMEM_ARB_CFG */
+                       0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7086120a, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff89, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000000, /* EMC_CFG.PERIODIC_QRST */
+               0x80000521, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200000, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               800000,     /* SDRAM frequency */
+               {
+                       0x00000025, /* EMC_RC */
+                       0x000000ee, /* EMC_RFC */
+                       0x0000001a, /* EMC_RAS */
+                       0x00000009, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x0000000d, /* EMC_W2R */
+                       0x00000004, /* EMC_R2P */
+                       0x00000013, /* EMC_W2P */
+                       0x00000009, /* EMC_RD_RCD */
+                       0x00000009, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000007, /* EMC_WDV */
+                       0x0000000b, /* EMC_QUSE */
+                       0x00000009, /* EMC_QRST */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00000012, /* EMC_RDV */
+                       0x00001820, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000012, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000000f, /* EMC_AR2PDEN */
+                       0x00000018, /* EMC_RW2PDEN */
+                       0x000000f8, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x00000018, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000007, /* EMC_TCLKSTABLE */
+                       0x00000008, /* EMC_TCLKSTOP */
+                       0x00001860, /* EMC_TREFBW */
+                       0x0000000c, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00005088, /* EMC_FBIO_CFG5 */
+                       0xf0070191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0000c00a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x22220000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f501, /* EMC_XM2COMPPADCTRL */
+                       0x07077404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x080001e8, /* EMC_XM2QUSEPADCTRL */
+                       0x06000021, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x00d0000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x0000000c, /* MC_EMEM_ARB_CFG */
+                       0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
+                       0x712c2414, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff49, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80000d71, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200018, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       }
+};
+
 static const struct tegra30_emc_table cardhu_emc_tables_h5tc2g[] = {
        {
                0x30,           /* Rev 3.0 */
@@ -7083,13 +7686,18 @@ static struct tegra30_emc_pdata cardhu_emc_chip_h5tc2g_a2_2g2r = {
        .num_tables = ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2_2g2r)
 };
 
+static struct tegra30_emc_pdata cardhu_emc_chip_h5tc4g = {
+       .description = "h5tc4g",
+       .tables = (struct tegra30_emc_table *)cardhu_emc_tables_h5tc4g83mfr,
+       .num_tables = ARRAY_SIZE(cardhu_emc_tables_h5tc4g83mfr)
+};
+
 int cardhu_emc_init(void)
 {
        struct board_info board;
        struct tegra30_emc_pdata *emc_platdata = NULL;
 
        tegra_get_board_info(&board);
-
        switch (board.board_id) {
        case BOARD_PM269:
                tegra_init_dram_bit_map(pm269_bit_swap_map,
@@ -7107,6 +7715,9 @@ int cardhu_emc_init(void)
        case BOARD_PM311:
                emc_platdata = &cardhu_emc_chip_h5tc2g_pm311;
                break;
+       case BOARD_PM315:
+               emc_platdata = &cardhu_emc_chip_h5tc4g;
+               break;
        default:
                if (tegra_revision == TEGRA_REVISION_A01)
                        emc_platdata = &cardhu_emc_chip_h5tc2g;