config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
+ depends on !ARCH_TEGRA_3x_SOC
+ select ARM_CPU_SUSPEND if PM
+ select ARCH_TEGRA_HAS_PCIE
select CPU_V7
select ARM_GIC
+ select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select ARCH_REQUIRE_GPIOLIB
+ select PINCTRL
+ select PINCTRL_TEGRA20
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB_SUPPORT
+ select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT
- select ARM_ERRATA_742230
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_754327
+ select ARM_ERRATA_764369
+ select ARM_ERRATA_742230 if SMP
+ select PL310_ERRATA_727915 if CACHE_L2X0
+ select PL310_ERRATA_769419 if CACHE_L2X0
+ select CPU_FREQ_TABLE if CPU_FREQ
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
+ select ARCH_SUPPORTS_MSI if TEGRA_PCI
+ select PCI_MSI if TEGRA_PCI
+ select CPA
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
+ select ARM_CPU_SUSPEND if PM
+ select ARCH_TEGRA_HAS_PCIE
+ select ARCH_TEGRA_HAS_SATA
+ select ARCH_TEGRA_HAS_DUAL_3D
+ select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
select CPU_V7
select ARM_GIC
+ select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
+ select GIC_SET_MULTIPLE_CPUS if SMP
select ARCH_REQUIRE_GPIOLIB
- select TEGRA_IOVMM
+ select PINCTRL
+ select PINCTRL_TEGRA30
select USB_ARCH_HAS_EHCI if USB_SUPPORT
- select USB_ULPI if USB_SUPPORT
+ select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
+ select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
+ select ARCH_SUPPORTS_MSI if TEGRA_PCI
+ select PCI_MSI if TEGRA_PCI
+ select ARM_ERRATA_743622
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369
+ select PL310_ERRATA_769419 if CACHE_L2X0
+ select CPU_FREQ_TABLE if CPU_FREQ
+ select TEGRA_LP2_ARM_TWD if HAVE_ARM_TWD && !TEGRA_RAIL_OFF_MULTIPLE_CPUS
+ select CPA
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+config ARCH_TEGRA_HAS_DUAL_3D
+ bool
+
+config ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
+ bool
+
+config ARCH_TEGRA_HAS_PCIE
+ bool
+
+config ARCH_TEGRA_HAS_SATA
+ bool
+
config TEGRA_PCI
- bool "PCI Express support"
- depends on ARCH_TEGRA_2x_SOC
+ bool "PCIe host controller driver"
select PCI
+ depends on ARCH_TEGRA_HAS_PCIE
+ help
+ Adds PCIe Host controller driver for tegra based systems
comment "Tegra board type"
config MACH_VENTANA
bool "Ventana board"
depends on ARCH_TEGRA_2x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
help
Support for NVIDIA Ventana development platform
help
Support for the nVidia Ventana development platform
-# Whistler
+config MACH_WHISTLER
+ bool "Whistler board"
+ depends on ARCH_TEGRA_2x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_WM8753 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
+ help
+ Support for NVIDIA Whistler development platform
-# Aruba
+config MACH_ARUBA
+ bool "Aruba board"
+ depends on ARCH_TEGRA_3x_SOC
+ select TEGRA_FPGA_PLATFORM
+ help
+ Support for NVIDIA Aruba2 FPGA development platform
-# Cardhu
+config MACH_CARDHU
+ bool "Cardhu board"
+ depends on ARCH_TEGRA_3x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_MAX98095 if SND_SOC
+ help
+ Support for NVIDIA Cardhu development platform
-# Enterprise
+config MACH_P1852
+ bool "P1852 board"
+ depends on ARCH_TEGRA_3x_SOC
+ help
+ Support for NVIDIA P1852 development platform
+
+config MACH_TEGRA_ENTERPRISE
+ bool "Enterprise board"
+ depends on ARCH_TEGRA_3x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_MAX98088 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_TLV320AIC326X if SND_SOC
+ select TEGRA_SLOW_CSITE
+ help
+ Support for NVIDIA Enterprise development platform
-config TEGRA_FPGA_PLATFORM
- bool "Support for NVIDIA Tegra FPGA platform"
- default n
+config MACH_KAI
+ bool "Kai board"
+ depends on ARCH_TEGRA_3x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
+ select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
help
- This enables the NVIDIA Tegra FPGA platform support.
- Select this only if you are an NVIDIA developer working on
- an FPGA platforms. All others must leave this unselected.
+ Support for NVIDIA KAI development platform
+
+choice
+ prompt "Tegra platform type"
+ default TEGRA_SILICON_PLATFORM
+
+config TEGRA_SILICON_PLATFORM
+ bool "Silicon"
+ help
+ This enables support for a Tegra silicon platform.
+
+config TEGRA_SIMULATION_PLATFORM
+ bool "Simulation"
+ help
+ This enables support for a Tegra simulation platform.
+ Select this only if you are an NVIDIA developer working
+ on a simulation platform.
+
+config TEGRA_FPGA_PLATFORM
+ bool "FPGA"
+ help
+ This enables support for a Tegra FPGA platform.
+ Select this only if you are an NVIDIA developer working
+ on a FPGA platform.
+endchoice
+
+source "arch/arm/mach-tegra/p852/Kconfig"
choice
prompt "Low-level debug console UART"
config TEGRA_DEBUG_UARTA
bool "UART-A"
+ depends on DEBUG_LL
config TEGRA_DEBUG_UARTB
bool "UART-B"
+ depends on DEBUG_LL
config TEGRA_DEBUG_UARTC
bool "UART-C"
+ depends on DEBUG_LL
config TEGRA_DEBUG_UARTD
bool "UART-D"
+ depends on DEBUG_LL
config TEGRA_DEBUG_UARTE
bool "UART-E"
-
+ depends on DEBUG_LL
endchoice
config TEGRA_SYSTEM_DMA
Adds system DMA functionality for NVIDIA Tegra SoCs, used by
several Tegra device drivers
-config TEGRA_SPI_SLAVE
- tristate "Nvidia Tegra SPI slave driver"
- depends on ARCH_TEGRA
- select TEGRA_SYSTEM_DMA
- help
- SPI slave driver for NVIDIA Tegra SoCs
-
config TEGRA_PWM
tristate "Enable PWM driver"
select HAVE_PWM
help
Enable support for the Tegra PWM controller(s).
+config TEGRA_FIQ_DEBUGGER
+ bool "Enable the FIQ serial debugger on Tegra"
+ default n
+ select FIQ_DEBUGGER
+ help
+ Enables the FIQ serial debugger on Tegra
+
+config TEGRA_CARDHU_DSI
+ bool "Support DSI panel on Cardhu"
+ depends on MACH_CARDHU
+ select TEGRA_DSI
+ help
+ Support for DSI Panel on Nvidia Cardhu
+
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
+ depends on TEGRA_SILICON_PLATFORM
+ default n
config TEGRA_CPU_DVFS
bool "Enable voltage scaling on Tegra CPU"
+ depends on TEGRA_SILICON_PLATFORM
default y
config TEGRA_CORE_DVFS
bool "Enable voltage scaling on Tegra core"
+ depends on TEGRA_SILICON_PLATFORM
depends on TEGRA_CPU_DVFS
default y
help
Enables support for remapping discontiguous physical memory
shared with the operating system into contiguous I/O virtual
- space through the GART hardware included on Tegra SoCs
+ space through the GART (Graphics Address Relocation Table)
+ hardware included on Tegra SoCs.
config TEGRA_IOVMM_SMMU
bool "Enable I/O virtual memory manager for SMMU"
help
Enables support for remapping discontiguous physical memory
shared with the operating system into contiguous I/O virtual
- space through the SMMU hardware included on Tegra SoCs
+ space through the SMMU (System Memory Management Unit)
+ hardware included on Tegra SoCs.
+
+config TEGRA_IOVMM_SMMU_SYSFS
+ bool "Enable SMMU register access for debugging"
+ depends on TEGRA_IOVMM_SMMU
+ default n
+ help
+ Enables SMMU register access through /sys/devices/smmu/* files.
config TEGRA_IOVMM
bool
config TEGRA_AVP_KERNEL_ON_SMMU
bool "Use SMMU to relocate AVP kernel"
depends on TEGRA_IOVMM_SMMU
- default n
+ default y
help
Use SMMU to relocate AVP kernel (nvrm_avp.bin).
- This option is not implemented yet.
config TEGRA_ARB_SEMAPHORE
bool
config TEGRA_THERMAL_THROTTLE
- bool "Enable throttling of CPU speed on overtemp"
- depends on CPU_FREQ
- default y
- help
- Also requires enabling a temperature sensor such as NCT1008.
+ bool "Enable throttling of CPU speed on overtemp"
+ depends on TEGRA_SILICON_PLATFORM
+ depends on CPU_FREQ
+ default y
+ help
+ Also requires enabling a temperature sensor such as NCT1008.
config WIFI_CONTROL_FUNC
bool "Enable WiFi control function abstraction"
depends on DEBUG_FS
default n
+config TEGRA_CLUSTER_CONTROL
+ bool
+ depends on ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
+ default y if PM_SLEEP
+
config TEGRA_AUTO_HOTPLUG
bool "Enable automatic CPU hot-plugging"
- depends on HOTPLUG_CPU && CPU_FREQ && !ARCH_CPU_PROBE_RELEASE
+ depends on HOTPLUG_CPU && CPU_FREQ && !ARCH_CPU_PROBE_RELEASE && !ARCH_TEGRA_2x_SOC
default y
help
This option enables turning CPUs off/on and switching tegra
high/low power CPU clusters automatically, corresponding to
CPU frequency scaling.
+config TEGRA_MC_EARLY_ACK
+ bool "Enable early acknowledgement from mermory controller"
+ depends on ARCH_TEGRA_3x_SOC
+ default y
+ help
+ This option enables early acknowledgement from memory
+ controller. This feature is used to improve CPU memory
+ write performance.
+
config TEGRA_MC_PROFILE
tristate "Enable profiling memory controller utilization"
- depends on ARCH_TEGRA_2x_SOC
- default n
+ default y
help
When enabled, provides a mechanism to perform statistical
sampling of the memory controller usage on a client-by-client
config TEGRA_EDP_LIMITS
bool "Enforce electrical design limits"
+ depends on TEGRA_SILICON_PLATFORM
depends on CPU_FREQ
+ default y if ARCH_TEGRA_3x_SOC
default n
help
Limit maximum CPU frequency based on temperature and number
of on-line CPUs to keep CPU rail current within power supply
capabilities.
+config TEGRA_EMC_TO_DDR_CLOCK
+ int "EMC to DDR clocks ratio"
+ default "2" if ARCH_TEGRA_2x_SOC
+ default "1"
+
+config TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
+ bool "Use conservative cpu frequency governor when device enters early suspend"
+ depends on HAS_EARLYSUSPEND && CPU_FREQ
+ default n
+ help
+ Also will restore to original cpu frequency governor when device is resumed
+
+config TEGRA_STAT_MON
+ bool "Enable H/W statistics monitor"
+ depends on ARCH_TEGRA_2x_SOC
+ default n
+ help
+ Enables support for hardware statistics monitor for AVP.
+
+config USB_HOTPLUG
+ bool "Enabling the USB hotplug"
+ default n
+
+config TEGRA_DYNAMIC_PWRDET
+ bool "Enable dynamic activation of IO level auto-detection"
+ depends on TEGRA_SILICON_PLATFORM
+ default n
+ help
+ This option allows turning off tegra IO level auto-detection
+ when IO power is stable. If set auto-detection cells are active
+ only during power transitions, otherwise, the cells are active
+ always
+
+config TEGRA_EDP_EXACT_FREQ
+ bool "Use maximum possible cpu frequency when EDP capping"
+ depends on TEGRA_EDP_LIMITS
+ default y
+ help
+ When enabled the cpu will run at the exact frequency
+ specified in the EDP table when EDP capping is applied; when
+ disabled the next lower cpufreq frequency will be used.
+
+config TEGRA_USB_MODEM_POWER
+ bool "Enable tegra usb modem power management"
+ default n
+ help
+ This option enables support for out-of_band remote wakeup, selective
+ suspend and system suspend/resume.
+
+config TEGRA_BB_XMM_POWER
+ bool "Enable power driver for XMM modem"
+ default n
+ help
+ Enables power driver which controls gpio signals to XMM modem.
+
+config TEGRA_BB_XMM_POWER2
+ tristate "Enable power driver for XMM modem (flashless)"
+ default n
+ help
+ Enables power driver which controls gpio signals to XMM modem
+ (in flashless configuration). User-mode application must
+ insert this LKM to initiate 2nd USB enumeration power sequence
+ - after modem software has been downloaded to flashless device.
+
+config TEGRA_THERMAL_SYSFS
+ bool "Enable Thermal driver to use Thermal Sysfs infrastructure"
+ depends on THERMAL
+ default y
+
+config TEGRA_PLLM_RESTRICTED
+ bool "Restrict PLLM usage as module clock source"
+ depends on !ARCH_TEGRA_2x_SOC
+ default n
+ help
+ When enabled, PLLM usage may be restricted to modules with dividers
+ capable of dividing maximum PLLM frequency at minimum voltage. When
+ disabled, PLLM is used as a clock source with no restrictions (which
+ may effectively increase lower limit for core voltage).
+
+config TEGRA_WDT_RECOVERY
+ bool "Enable suspend/resume watchdog recovery mechanism"
+ default n
+ help
+ Enables watchdog recovery mechanism to protect against
+ suspend/resume hangs.
+
+config TEGRA_LP2_ARM_TWD
+ bool
+
+config TEGRA_RAIL_OFF_MULTIPLE_CPUS
+ bool
+
+config TEGRA_SLOW_CSITE
+ bool "lower csite clock to 1 Mhz to reduce its power consumption"
+ default n
+ help
+ When enabled, csite will be running at 1 Mhz and the performance of
+ jtag, lauterbach and other debugger will be extremely slow.
+
+config TEGRA_PREINIT_CLOCKS
+ bool "Preinitialize Tegra clocks to known states"
+ default n
+ help
+ Preinitialize Tegra clocks to known states before actual full-
+ scale clock initialization starts.
endif