Merge branch 'next/fixes-non-critical' into next/drivers
[linux-2.6.git] / arch / arm / mach-lpc32xx / clock.c
index 0e01bf4..f55c772 100644 (file)
@@ -721,6 +721,41 @@ static struct clk clk_tsc = {
        .get_rate       = local_return_parent_rate,
 };
 
+static int adc_onoff_enable(struct clk *clk, int enable)
+{
+       u32 tmp;
+       u32 divider;
+
+       /* Use PERIPH_CLOCK */
+       tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+       tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+       /*
+        * Set clock divider so that we have equal to or less than
+        * 4.5MHz clock at ADC
+        */
+       divider = clk->get_rate(clk) / 4500000 + 1;
+       tmp |= divider;
+       __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+       /* synchronize rate of this clock w/ actual HW setting */
+       clk->rate = clk->get_rate(clk->parent) / divider;
+
+       if (enable == 0)
+               __raw_writel(0, clk->enable_reg);
+       else
+               __raw_writel(clk->enable_mask, clk->enable_reg);
+
+       return 0;
+}
+
+static struct clk clk_adc = {
+       .parent         = &clk_pclk,
+       .enable         = adc_onoff_enable,
+       .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+       .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+       .get_rate       = local_return_parent_rate,
+};
+
 static int mmc_onoff_enable(struct clk *clk, int enable)
 {
        u32 tmp;
@@ -1055,6 +1090,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
+       _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
        _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
        _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
        _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)