Merge branch 'next/soc-exynos5250-arch' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / arm / include / asm / hardware / cache-l2x0.h
index 99a6ed7..7df239b 100644 (file)
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARM_HARDWARE_L2X0_H
 #define __ASM_ARM_HARDWARE_L2X0_H
 
+#include <linux/errno.h>
+
 #define L2X0_CACHE_ID                  0x000
 #define L2X0_CACHE_TYPE                        0x004
 #define L2X0_CTRL                      0x100
@@ -52,6 +54,8 @@
 #define L2X0_LOCKDOWN_WAY_D_BASE       0x900
 #define L2X0_LOCKDOWN_WAY_I_BASE       0x904
 #define L2X0_LOCKDOWN_STRIDE           0x08
+#define L2X0_ADDR_FILTER_START         0xC00
+#define L2X0_ADDR_FILTER_END           0xC04
 #define L2X0_TEST_OPERATION            0xF00
 #define L2X0_LINE_DATA                 0xF10
 #define L2X0_LINE_TAG                  0xF30
 #define L2X0_CACHE_ID_PART_MASK                (0xf << 6)
 #define L2X0_CACHE_ID_PART_L210                (1 << 6)
 #define L2X0_CACHE_ID_PART_L310                (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK          0x3f
+#define L2X0_CACHE_ID_RTL_R0P0          0x0
+#define L2X0_CACHE_ID_RTL_R1P0          0x2
+#define L2X0_CACHE_ID_RTL_R2P0          0x4
+#define L2X0_CACHE_ID_RTL_R3P0          0x5
+#define L2X0_CACHE_ID_RTL_R3P1          0x6
+#define L2X0_CACHE_ID_RTL_R3P2          0x8
 
 #define L2X0_AUX_CTRL_MASK                     0xc0000fff
+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT    0
+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK     0x7
+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT    3
+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK     (0x7 << 3)
+#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT                6
+#define L2X0_AUX_CTRL_TAG_LATENCY_MASK         (0x7 << 6)
+#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT      9
+#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK       (0x7 << 9)
 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT      16
 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT           17
 #define L2X0_AUX_CTRL_WAY_SIZE_MASK            (0x7 << 17)
 #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT     29
 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT                30
 
+#define L2X0_LATENCY_CTRL_SETUP_SHIFT  0
+#define L2X0_LATENCY_CTRL_RD_SHIFT     4
+#define L2X0_LATENCY_CTRL_WR_SHIFT     8
+
+#define L2X0_ADDR_FILTER_EN            1
+
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
+extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
+#else
+static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask)
+{
+       return -ENODEV;
+}
 #endif
 
+struct l2x0_regs {
+       unsigned long phy_base;
+       unsigned long aux_ctrl;
+       /*
+        * Whether the following registers need to be saved/restored
+        * depends on platform
+        */
+       unsigned long tag_latency;
+       unsigned long data_latency;
+       unsigned long filter_start;
+       unsigned long filter_end;
+       unsigned long prefetch_ctrl;
+       unsigned long pwr_ctrl;
+};
+
+extern struct l2x0_regs l2x0_saved_regs;
+
+#endif /* __ASSEMBLY__ */
+
 #endif