KVM: Unify the delivery of IOAPIC and MSI interrupts
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
146                            struct kvm_vcpu *vcpu,
147                            u8 vector, u8 trig_mode, u8 delivery_mode)
148 {
149         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
150                      delivery_mode);
151
152         ASSERT((delivery_mode == IOAPIC_FIXED) ||
153                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
154
155         return kvm_apic_set_irq(vcpu, vector, trig_mode);
156 }
157
158 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
159 {
160         kvm_inject_nmi(vcpu);
161         kvm_vcpu_kick(vcpu);
162 }
163
164 u32 kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
165                                     u8 dest_mode)
166 {
167         u32 mask = 0;
168         int i;
169         struct kvm *kvm = ioapic->kvm;
170         struct kvm_vcpu *vcpu;
171
172         ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
173
174         if (dest_mode == 0) {   /* Physical mode. */
175                 if (dest == 0xFF) {     /* Broadcast. */
176                         for (i = 0; i < KVM_MAX_VCPUS; ++i)
177                                 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
178                                         mask |= 1 << i;
179                         return mask;
180                 }
181                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
182                         vcpu = kvm->vcpus[i];
183                         if (!vcpu)
184                                 continue;
185                         if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
186                                 if (vcpu->arch.apic)
187                                         mask = 1 << i;
188                                 break;
189                         }
190                 }
191         } else if (dest != 0)   /* Logical mode, MDA non-zero. */
192                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
193                         vcpu = kvm->vcpus[i];
194                         if (!vcpu)
195                                 continue;
196                         if (vcpu->arch.apic &&
197                             kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
198                                 mask |= 1 << vcpu->vcpu_id;
199                 }
200         ioapic_debug("mask %x\n", mask);
201         return mask;
202 }
203
204 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
205 {
206         union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
207         unsigned long deliver_bitmask;
208         struct kvm_vcpu *vcpu;
209         int vcpu_id, r = -1;
210
211         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
212                      "vector=%x trig_mode=%x\n",
213                      entry.fields.dest, entry.fields.dest_mode,
214                      entry.fields.delivery_mode, entry.fields.vector,
215                      entry.fields.trig_mode);
216
217         kvm_get_intr_delivery_bitmask(ioapic, &entry, &deliver_bitmask);
218         if (!deliver_bitmask) {
219                 ioapic_debug("no target on destination\n");
220                 return 0;
221         }
222
223         /* Always delivery PIT interrupt to vcpu 0 */
224 #ifdef CONFIG_X86
225         if (irq == 0)
226                 deliver_bitmask = 1;
227 #endif
228
229         for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
230                 if (!(deliver_bitmask & (1 << vcpu_id)))
231                         continue;
232                 deliver_bitmask &= ~(1 << vcpu_id);
233                 vcpu = ioapic->kvm->vcpus[vcpu_id];
234                 if (vcpu) {
235                         if (entry.fields.delivery_mode ==
236                                         IOAPIC_LOWEST_PRIORITY ||
237                             entry.fields.delivery_mode == IOAPIC_FIXED) {
238                                 if (r < 0)
239                                         r = 0;
240                                 r += ioapic_inj_irq(ioapic, vcpu,
241                                                     entry.fields.vector,
242                                                     entry.fields.trig_mode,
243                                                     entry.fields.delivery_mode);
244                         } else if (entry.fields.delivery_mode == IOAPIC_NMI) {
245                                 r = 1;
246                                 ioapic_inj_nmi(vcpu);
247                         } else
248                                 ioapic_debug("unsupported delivery mode %x!\n",
249                                              entry.fields.delivery_mode);
250                 } else
251                         ioapic_debug("null destination vcpu: "
252                                      "mask=%x vector=%x delivery_mode=%x\n",
253                                      entry.fields.deliver_bitmask,
254                                      entry.fields.vector,
255                                      entry.fields.delivery_mode);
256         }
257         return r;
258 }
259
260 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
261 {
262         u32 old_irr = ioapic->irr;
263         u32 mask = 1 << irq;
264         union kvm_ioapic_redirect_entry entry;
265         int ret = 1;
266
267         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
268                 entry = ioapic->redirtbl[irq];
269                 level ^= entry.fields.polarity;
270                 if (!level)
271                         ioapic->irr &= ~mask;
272                 else {
273                         ioapic->irr |= mask;
274                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
275                             || !entry.fields.remote_irr)
276                                 ret = ioapic_service(ioapic, irq);
277                 }
278         }
279         return ret;
280 }
281
282 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
283                                     int trigger_mode)
284 {
285         union kvm_ioapic_redirect_entry *ent;
286
287         ent = &ioapic->redirtbl[pin];
288
289         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
290
291         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
292                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
293                 ent->fields.remote_irr = 0;
294                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
295                         ioapic_service(ioapic, pin);
296         }
297 }
298
299 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
300 {
301         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
302         int i;
303
304         for (i = 0; i < IOAPIC_NUM_PINS; i++)
305                 if (ioapic->redirtbl[i].fields.vector == vector)
306                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
307 }
308
309 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
310                            int len, int is_write)
311 {
312         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
313
314         return ((addr >= ioapic->base_address &&
315                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
316 }
317
318 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
319                              void *val)
320 {
321         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
322         u32 result;
323
324         ioapic_debug("addr %lx\n", (unsigned long)addr);
325         ASSERT(!(addr & 0xf));  /* check alignment */
326
327         addr &= 0xff;
328         switch (addr) {
329         case IOAPIC_REG_SELECT:
330                 result = ioapic->ioregsel;
331                 break;
332
333         case IOAPIC_REG_WINDOW:
334                 result = ioapic_read_indirect(ioapic, addr, len);
335                 break;
336
337         default:
338                 result = 0;
339                 break;
340         }
341         switch (len) {
342         case 8:
343                 *(u64 *) val = result;
344                 break;
345         case 1:
346         case 2:
347         case 4:
348                 memcpy(val, (char *)&result, len);
349                 break;
350         default:
351                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
352         }
353 }
354
355 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
356                               const void *val)
357 {
358         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
359         u32 data;
360
361         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
362                      (void*)addr, len, val);
363         ASSERT(!(addr & 0xf));  /* check alignment */
364         if (len == 4 || len == 8)
365                 data = *(u32 *) val;
366         else {
367                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
368                 return;
369         }
370
371         addr &= 0xff;
372         switch (addr) {
373         case IOAPIC_REG_SELECT:
374                 ioapic->ioregsel = data;
375                 break;
376
377         case IOAPIC_REG_WINDOW:
378                 ioapic_write_indirect(ioapic, data);
379                 break;
380 #ifdef  CONFIG_IA64
381         case IOAPIC_REG_EOI:
382                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
383                 break;
384 #endif
385
386         default:
387                 break;
388         }
389 }
390
391 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
392 {
393         int i;
394
395         for (i = 0; i < IOAPIC_NUM_PINS; i++)
396                 ioapic->redirtbl[i].fields.mask = 1;
397         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
398         ioapic->ioregsel = 0;
399         ioapic->irr = 0;
400         ioapic->id = 0;
401 }
402
403 int kvm_ioapic_init(struct kvm *kvm)
404 {
405         struct kvm_ioapic *ioapic;
406
407         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
408         if (!ioapic)
409                 return -ENOMEM;
410         kvm->arch.vioapic = ioapic;
411         kvm_ioapic_reset(ioapic);
412         ioapic->dev.read = ioapic_mmio_read;
413         ioapic->dev.write = ioapic_mmio_write;
414         ioapic->dev.in_range = ioapic_in_range;
415         ioapic->dev.private = ioapic;
416         ioapic->kvm = kvm;
417         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
418         return 0;
419 }
420