812801317e362920d842e3373b9cf139a5e793cf
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
146                            struct kvm_vcpu *vcpu,
147                            u8 vector, u8 trig_mode, u8 delivery_mode)
148 {
149         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
150                      delivery_mode);
151
152         ASSERT((delivery_mode == IOAPIC_FIXED) ||
153                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
154
155         return kvm_apic_set_irq(vcpu, vector, trig_mode);
156 }
157
158 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
159 {
160         kvm_inject_nmi(vcpu);
161         kvm_vcpu_kick(vcpu);
162 }
163
164 u32 kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
165                                     u8 dest_mode)
166 {
167         u32 mask = 0;
168         int i;
169         struct kvm *kvm = ioapic->kvm;
170         struct kvm_vcpu *vcpu;
171
172         ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
173
174         if (dest_mode == 0) {   /* Physical mode. */
175                 if (dest == 0xFF) {     /* Broadcast. */
176                         for (i = 0; i < KVM_MAX_VCPUS; ++i)
177                                 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
178                                         mask |= 1 << i;
179                         return mask;
180                 }
181                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
182                         vcpu = kvm->vcpus[i];
183                         if (!vcpu)
184                                 continue;
185                         if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
186                                 if (vcpu->arch.apic)
187                                         mask = 1 << i;
188                                 break;
189                         }
190                 }
191         } else if (dest != 0)   /* Logical mode, MDA non-zero. */
192                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
193                         vcpu = kvm->vcpus[i];
194                         if (!vcpu)
195                                 continue;
196                         if (vcpu->arch.apic &&
197                             kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
198                                 mask |= 1 << vcpu->vcpu_id;
199                 }
200         ioapic_debug("mask %x\n", mask);
201         return mask;
202 }
203
204 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
205 {
206         u8 dest = ioapic->redirtbl[irq].fields.dest_id;
207         u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
208         u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
209         u8 vector = ioapic->redirtbl[irq].fields.vector;
210         u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
211         u32 deliver_bitmask;
212         struct kvm_vcpu *vcpu;
213         int vcpu_id, r = -1;
214
215         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
216                      "vector=%x trig_mode=%x\n",
217                      dest, dest_mode, delivery_mode, vector, trig_mode);
218
219         deliver_bitmask = kvm_ioapic_get_delivery_bitmask(ioapic, dest,
220                                                           dest_mode);
221         if (!deliver_bitmask) {
222                 ioapic_debug("no target on destination\n");
223                 return 0;
224         }
225
226         switch (delivery_mode) {
227         case IOAPIC_LOWEST_PRIORITY:
228                 vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
229                                 deliver_bitmask);
230 #ifdef CONFIG_X86
231                 if (irq == 0)
232                         vcpu = ioapic->kvm->vcpus[0];
233 #endif
234                 if (vcpu != NULL)
235                         r = ioapic_inj_irq(ioapic, vcpu, vector,
236                                        trig_mode, delivery_mode);
237                 else
238                         ioapic_debug("null lowest prio vcpu: "
239                                      "mask=%x vector=%x delivery_mode=%x\n",
240                                      deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
241                 break;
242         case IOAPIC_FIXED:
243 #ifdef CONFIG_X86
244                 if (irq == 0)
245                         deliver_bitmask = 1;
246 #endif
247                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
248                         if (!(deliver_bitmask & (1 << vcpu_id)))
249                                 continue;
250                         deliver_bitmask &= ~(1 << vcpu_id);
251                         vcpu = ioapic->kvm->vcpus[vcpu_id];
252                         if (vcpu) {
253                                 if (r < 0)
254                                         r = 0;
255                                 r += ioapic_inj_irq(ioapic, vcpu, vector,
256                                                trig_mode, delivery_mode);
257                         }
258                 }
259                 break;
260         case IOAPIC_NMI:
261                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
262                         if (!(deliver_bitmask & (1 << vcpu_id)))
263                                 continue;
264                         deliver_bitmask &= ~(1 << vcpu_id);
265                         vcpu = ioapic->kvm->vcpus[vcpu_id];
266                         if (vcpu) {
267                                 ioapic_inj_nmi(vcpu);
268                                 r = 1;
269                         }
270                         else
271                                 ioapic_debug("NMI to vcpu %d failed\n",
272                                                 vcpu->vcpu_id);
273                 }
274                 break;
275         default:
276                 printk(KERN_WARNING "Unsupported delivery mode %d\n",
277                        delivery_mode);
278                 break;
279         }
280         return r;
281 }
282
283 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
284 {
285         u32 old_irr = ioapic->irr;
286         u32 mask = 1 << irq;
287         union kvm_ioapic_redirect_entry entry;
288         int ret = 1;
289
290         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
291                 entry = ioapic->redirtbl[irq];
292                 level ^= entry.fields.polarity;
293                 if (!level)
294                         ioapic->irr &= ~mask;
295                 else {
296                         ioapic->irr |= mask;
297                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
298                             || !entry.fields.remote_irr)
299                                 ret = ioapic_service(ioapic, irq);
300                 }
301         }
302         return ret;
303 }
304
305 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
306                                     int trigger_mode)
307 {
308         union kvm_ioapic_redirect_entry *ent;
309
310         ent = &ioapic->redirtbl[pin];
311
312         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
313
314         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
315                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
316                 ent->fields.remote_irr = 0;
317                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
318                         ioapic_service(ioapic, pin);
319         }
320 }
321
322 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
323 {
324         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
325         int i;
326
327         for (i = 0; i < IOAPIC_NUM_PINS; i++)
328                 if (ioapic->redirtbl[i].fields.vector == vector)
329                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
330 }
331
332 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
333                            int len, int is_write)
334 {
335         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
336
337         return ((addr >= ioapic->base_address &&
338                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
339 }
340
341 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
342                              void *val)
343 {
344         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
345         u32 result;
346
347         ioapic_debug("addr %lx\n", (unsigned long)addr);
348         ASSERT(!(addr & 0xf));  /* check alignment */
349
350         addr &= 0xff;
351         switch (addr) {
352         case IOAPIC_REG_SELECT:
353                 result = ioapic->ioregsel;
354                 break;
355
356         case IOAPIC_REG_WINDOW:
357                 result = ioapic_read_indirect(ioapic, addr, len);
358                 break;
359
360         default:
361                 result = 0;
362                 break;
363         }
364         switch (len) {
365         case 8:
366                 *(u64 *) val = result;
367                 break;
368         case 1:
369         case 2:
370         case 4:
371                 memcpy(val, (char *)&result, len);
372                 break;
373         default:
374                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
375         }
376 }
377
378 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
379                               const void *val)
380 {
381         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
382         u32 data;
383
384         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
385                      (void*)addr, len, val);
386         ASSERT(!(addr & 0xf));  /* check alignment */
387         if (len == 4 || len == 8)
388                 data = *(u32 *) val;
389         else {
390                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
391                 return;
392         }
393
394         addr &= 0xff;
395         switch (addr) {
396         case IOAPIC_REG_SELECT:
397                 ioapic->ioregsel = data;
398                 break;
399
400         case IOAPIC_REG_WINDOW:
401                 ioapic_write_indirect(ioapic, data);
402                 break;
403 #ifdef  CONFIG_IA64
404         case IOAPIC_REG_EOI:
405                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
406                 break;
407 #endif
408
409         default:
410                 break;
411         }
412 }
413
414 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
415 {
416         int i;
417
418         for (i = 0; i < IOAPIC_NUM_PINS; i++)
419                 ioapic->redirtbl[i].fields.mask = 1;
420         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
421         ioapic->ioregsel = 0;
422         ioapic->irr = 0;
423         ioapic->id = 0;
424 }
425
426 int kvm_ioapic_init(struct kvm *kvm)
427 {
428         struct kvm_ioapic *ioapic;
429
430         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
431         if (!ioapic)
432                 return -ENOMEM;
433         kvm->arch.vioapic = ioapic;
434         kvm_ioapic_reset(ioapic);
435         ioapic->dev.read = ioapic_mmio_read;
436         ioapic->dev.write = ioapic_mmio_write;
437         ioapic->dev.in_range = ioapic_in_range;
438         ioapic->dev.private = ioapic;
439         ioapic->kvm = kvm;
440         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
441         return 0;
442 }
443