UBI: document UBI ioctls
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union ioapic_redir_entry *pent;
89
90         pent = &ioapic->redirtbl[idx];
91
92         if (!pent->fields.mask) {
93                 int injected = ioapic_deliver(ioapic, idx);
94                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
95                         pent->fields.remote_irr = 1;
96         }
97         if (!pent->fields.trig_mode)
98                 ioapic->irr &= ~(1 << idx);
99 }
100
101 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
102 {
103         unsigned index;
104
105         switch (ioapic->ioregsel) {
106         case IOAPIC_REG_VERSION:
107                 /* Writes are ignored. */
108                 break;
109
110         case IOAPIC_REG_APIC_ID:
111                 ioapic->id = (val >> 24) & 0xf;
112                 break;
113
114         case IOAPIC_REG_ARB_ID:
115                 break;
116
117         default:
118                 index = (ioapic->ioregsel - 0x10) >> 1;
119
120                 ioapic_debug("change redir index %x val %x\n", index, val);
121                 if (index >= IOAPIC_NUM_PINS)
122                         return;
123                 if (ioapic->ioregsel & 1) {
124                         ioapic->redirtbl[index].bits &= 0xffffffff;
125                         ioapic->redirtbl[index].bits |= (u64) val << 32;
126                 } else {
127                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
128                         ioapic->redirtbl[index].bits |= (u32) val;
129                         ioapic->redirtbl[index].fields.remote_irr = 0;
130                 }
131                 if (ioapic->irr & (1 << index))
132                         ioapic_service(ioapic, index);
133                 break;
134         }
135 }
136
137 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
138                            struct kvm_vcpu *vcpu,
139                            u8 vector, u8 trig_mode, u8 delivery_mode)
140 {
141         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
142                      delivery_mode);
143
144         ASSERT((delivery_mode == IOAPIC_FIXED) ||
145                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
146
147         return kvm_apic_set_irq(vcpu, vector, trig_mode);
148 }
149
150 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
151 {
152         kvm_inject_nmi(vcpu);
153 }
154
155 static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
156                                        u8 dest_mode)
157 {
158         u32 mask = 0;
159         int i;
160         struct kvm *kvm = ioapic->kvm;
161         struct kvm_vcpu *vcpu;
162
163         ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
164
165         if (dest_mode == 0) {   /* Physical mode. */
166                 if (dest == 0xFF) {     /* Broadcast. */
167                         for (i = 0; i < KVM_MAX_VCPUS; ++i)
168                                 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
169                                         mask |= 1 << i;
170                         return mask;
171                 }
172                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
173                         vcpu = kvm->vcpus[i];
174                         if (!vcpu)
175                                 continue;
176                         if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
177                                 if (vcpu->arch.apic)
178                                         mask = 1 << i;
179                                 break;
180                         }
181                 }
182         } else if (dest != 0)   /* Logical mode, MDA non-zero. */
183                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
184                         vcpu = kvm->vcpus[i];
185                         if (!vcpu)
186                                 continue;
187                         if (vcpu->arch.apic &&
188                             kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
189                                 mask |= 1 << vcpu->vcpu_id;
190                 }
191         ioapic_debug("mask %x\n", mask);
192         return mask;
193 }
194
195 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
196 {
197         u8 dest = ioapic->redirtbl[irq].fields.dest_id;
198         u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
199         u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
200         u8 vector = ioapic->redirtbl[irq].fields.vector;
201         u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
202         u32 deliver_bitmask;
203         struct kvm_vcpu *vcpu;
204         int vcpu_id, r = 0;
205
206         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
207                      "vector=%x trig_mode=%x\n",
208                      dest, dest_mode, delivery_mode, vector, trig_mode);
209
210         deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode);
211         if (!deliver_bitmask) {
212                 ioapic_debug("no target on destination\n");
213                 return 0;
214         }
215
216         switch (delivery_mode) {
217         case IOAPIC_LOWEST_PRIORITY:
218                 vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
219                                 deliver_bitmask);
220 #ifdef CONFIG_X86
221                 if (irq == 0)
222                         vcpu = ioapic->kvm->vcpus[0];
223 #endif
224                 if (vcpu != NULL)
225                         r = ioapic_inj_irq(ioapic, vcpu, vector,
226                                        trig_mode, delivery_mode);
227                 else
228                         ioapic_debug("null lowest prio vcpu: "
229                                      "mask=%x vector=%x delivery_mode=%x\n",
230                                      deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
231                 break;
232         case IOAPIC_FIXED:
233 #ifdef CONFIG_X86
234                 if (irq == 0)
235                         deliver_bitmask = 1;
236 #endif
237                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
238                         if (!(deliver_bitmask & (1 << vcpu_id)))
239                                 continue;
240                         deliver_bitmask &= ~(1 << vcpu_id);
241                         vcpu = ioapic->kvm->vcpus[vcpu_id];
242                         if (vcpu) {
243                                 r = ioapic_inj_irq(ioapic, vcpu, vector,
244                                                trig_mode, delivery_mode);
245                         }
246                 }
247                 break;
248         case IOAPIC_NMI:
249                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
250                         if (!(deliver_bitmask & (1 << vcpu_id)))
251                                 continue;
252                         deliver_bitmask &= ~(1 << vcpu_id);
253                         vcpu = ioapic->kvm->vcpus[vcpu_id];
254                         if (vcpu)
255                                 ioapic_inj_nmi(vcpu);
256                         else
257                                 ioapic_debug("NMI to vcpu %d failed\n",
258                                                 vcpu->vcpu_id);
259                 }
260                 break;
261         default:
262                 printk(KERN_WARNING "Unsupported delivery mode %d\n",
263                        delivery_mode);
264                 break;
265         }
266         return r;
267 }
268
269 void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
270 {
271         u32 old_irr = ioapic->irr;
272         u32 mask = 1 << irq;
273         union ioapic_redir_entry entry;
274
275         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
276                 entry = ioapic->redirtbl[irq];
277                 level ^= entry.fields.polarity;
278                 if (!level)
279                         ioapic->irr &= ~mask;
280                 else {
281                         ioapic->irr |= mask;
282                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
283                             || !entry.fields.remote_irr)
284                                 ioapic_service(ioapic, irq);
285                 }
286         }
287 }
288
289 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int gsi,
290                                     int trigger_mode)
291 {
292         union ioapic_redir_entry *ent;
293
294         ent = &ioapic->redirtbl[gsi];
295
296         kvm_notify_acked_irq(ioapic->kvm, gsi);
297
298         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
299                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
300                 ent->fields.remote_irr = 0;
301                 if (!ent->fields.mask && (ioapic->irr & (1 << gsi)))
302                         ioapic_service(ioapic, gsi);
303         }
304 }
305
306 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
307 {
308         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
309         int i;
310
311         for (i = 0; i < IOAPIC_NUM_PINS; i++)
312                 if (ioapic->redirtbl[i].fields.vector == vector)
313                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
314 }
315
316 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
317                            int len, int is_write)
318 {
319         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
320
321         return ((addr >= ioapic->base_address &&
322                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
323 }
324
325 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
326                              void *val)
327 {
328         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
329         u32 result;
330
331         ioapic_debug("addr %lx\n", (unsigned long)addr);
332         ASSERT(!(addr & 0xf));  /* check alignment */
333
334         addr &= 0xff;
335         switch (addr) {
336         case IOAPIC_REG_SELECT:
337                 result = ioapic->ioregsel;
338                 break;
339
340         case IOAPIC_REG_WINDOW:
341                 result = ioapic_read_indirect(ioapic, addr, len);
342                 break;
343
344         default:
345                 result = 0;
346                 break;
347         }
348         switch (len) {
349         case 8:
350                 *(u64 *) val = result;
351                 break;
352         case 1:
353         case 2:
354         case 4:
355                 memcpy(val, (char *)&result, len);
356                 break;
357         default:
358                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
359         }
360 }
361
362 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
363                               const void *val)
364 {
365         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
366         u32 data;
367
368         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
369                      (void*)addr, len, val);
370         ASSERT(!(addr & 0xf));  /* check alignment */
371         if (len == 4 || len == 8)
372                 data = *(u32 *) val;
373         else {
374                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
375                 return;
376         }
377
378         addr &= 0xff;
379         switch (addr) {
380         case IOAPIC_REG_SELECT:
381                 ioapic->ioregsel = data;
382                 break;
383
384         case IOAPIC_REG_WINDOW:
385                 ioapic_write_indirect(ioapic, data);
386                 break;
387 #ifdef  CONFIG_IA64
388         case IOAPIC_REG_EOI:
389                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
390                 break;
391 #endif
392
393         default:
394                 break;
395         }
396 }
397
398 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
399 {
400         int i;
401
402         for (i = 0; i < IOAPIC_NUM_PINS; i++)
403                 ioapic->redirtbl[i].fields.mask = 1;
404         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
405         ioapic->ioregsel = 0;
406         ioapic->irr = 0;
407         ioapic->id = 0;
408 }
409
410 int kvm_ioapic_init(struct kvm *kvm)
411 {
412         struct kvm_ioapic *ioapic;
413
414         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
415         if (!ioapic)
416                 return -ENOMEM;
417         kvm->arch.vioapic = ioapic;
418         kvm_ioapic_reset(ioapic);
419         ioapic->dev.read = ioapic_mmio_read;
420         ioapic->dev.write = ioapic_mmio_write;
421         ioapic->dev.in_range = ioapic_in_range;
422         ioapic->dev.private = ioapic;
423         ioapic->kvm = kvm;
424         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
425         return 0;
426 }