KVM: make irq ack notifications aware of routing table
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union ioapic_redir_entry *pent;
89
90         pent = &ioapic->redirtbl[idx];
91
92         if (!pent->fields.mask) {
93                 int injected = ioapic_deliver(ioapic, idx);
94                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
95                         pent->fields.remote_irr = 1;
96         }
97         if (!pent->fields.trig_mode)
98                 ioapic->irr &= ~(1 << idx);
99 }
100
101 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
102 {
103         unsigned index;
104         bool mask_before, mask_after;
105
106         switch (ioapic->ioregsel) {
107         case IOAPIC_REG_VERSION:
108                 /* Writes are ignored. */
109                 break;
110
111         case IOAPIC_REG_APIC_ID:
112                 ioapic->id = (val >> 24) & 0xf;
113                 break;
114
115         case IOAPIC_REG_ARB_ID:
116                 break;
117
118         default:
119                 index = (ioapic->ioregsel - 0x10) >> 1;
120
121                 ioapic_debug("change redir index %x val %x\n", index, val);
122                 if (index >= IOAPIC_NUM_PINS)
123                         return;
124                 mask_before = ioapic->redirtbl[index].fields.mask;
125                 if (ioapic->ioregsel & 1) {
126                         ioapic->redirtbl[index].bits &= 0xffffffff;
127                         ioapic->redirtbl[index].bits |= (u64) val << 32;
128                 } else {
129                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
130                         ioapic->redirtbl[index].bits |= (u32) val;
131                         ioapic->redirtbl[index].fields.remote_irr = 0;
132                 }
133                 mask_after = ioapic->redirtbl[index].fields.mask;
134                 if (mask_before != mask_after)
135                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
136                 if (ioapic->irr & (1 << index))
137                         ioapic_service(ioapic, index);
138                 break;
139         }
140 }
141
142 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
143                            struct kvm_vcpu *vcpu,
144                            u8 vector, u8 trig_mode, u8 delivery_mode)
145 {
146         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
147                      delivery_mode);
148
149         ASSERT((delivery_mode == IOAPIC_FIXED) ||
150                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
151
152         return kvm_apic_set_irq(vcpu, vector, trig_mode);
153 }
154
155 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
156 {
157         kvm_inject_nmi(vcpu);
158         kvm_vcpu_kick(vcpu);
159 }
160
161 u32 kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
162                                     u8 dest_mode)
163 {
164         u32 mask = 0;
165         int i;
166         struct kvm *kvm = ioapic->kvm;
167         struct kvm_vcpu *vcpu;
168
169         ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
170
171         if (dest_mode == 0) {   /* Physical mode. */
172                 if (dest == 0xFF) {     /* Broadcast. */
173                         for (i = 0; i < KVM_MAX_VCPUS; ++i)
174                                 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
175                                         mask |= 1 << i;
176                         return mask;
177                 }
178                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
179                         vcpu = kvm->vcpus[i];
180                         if (!vcpu)
181                                 continue;
182                         if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
183                                 if (vcpu->arch.apic)
184                                         mask = 1 << i;
185                                 break;
186                         }
187                 }
188         } else if (dest != 0)   /* Logical mode, MDA non-zero. */
189                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
190                         vcpu = kvm->vcpus[i];
191                         if (!vcpu)
192                                 continue;
193                         if (vcpu->arch.apic &&
194                             kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
195                                 mask |= 1 << vcpu->vcpu_id;
196                 }
197         ioapic_debug("mask %x\n", mask);
198         return mask;
199 }
200
201 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
202 {
203         u8 dest = ioapic->redirtbl[irq].fields.dest_id;
204         u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
205         u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
206         u8 vector = ioapic->redirtbl[irq].fields.vector;
207         u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
208         u32 deliver_bitmask;
209         struct kvm_vcpu *vcpu;
210         int vcpu_id, r = 0;
211
212         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
213                      "vector=%x trig_mode=%x\n",
214                      dest, dest_mode, delivery_mode, vector, trig_mode);
215
216         deliver_bitmask = kvm_ioapic_get_delivery_bitmask(ioapic, dest,
217                                                           dest_mode);
218         if (!deliver_bitmask) {
219                 ioapic_debug("no target on destination\n");
220                 return 0;
221         }
222
223         switch (delivery_mode) {
224         case IOAPIC_LOWEST_PRIORITY:
225                 vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
226                                 deliver_bitmask);
227 #ifdef CONFIG_X86
228                 if (irq == 0)
229                         vcpu = ioapic->kvm->vcpus[0];
230 #endif
231                 if (vcpu != NULL)
232                         r = ioapic_inj_irq(ioapic, vcpu, vector,
233                                        trig_mode, delivery_mode);
234                 else
235                         ioapic_debug("null lowest prio vcpu: "
236                                      "mask=%x vector=%x delivery_mode=%x\n",
237                                      deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
238                 break;
239         case IOAPIC_FIXED:
240 #ifdef CONFIG_X86
241                 if (irq == 0)
242                         deliver_bitmask = 1;
243 #endif
244                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
245                         if (!(deliver_bitmask & (1 << vcpu_id)))
246                                 continue;
247                         deliver_bitmask &= ~(1 << vcpu_id);
248                         vcpu = ioapic->kvm->vcpus[vcpu_id];
249                         if (vcpu) {
250                                 r = ioapic_inj_irq(ioapic, vcpu, vector,
251                                                trig_mode, delivery_mode);
252                         }
253                 }
254                 break;
255         case IOAPIC_NMI:
256                 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
257                         if (!(deliver_bitmask & (1 << vcpu_id)))
258                                 continue;
259                         deliver_bitmask &= ~(1 << vcpu_id);
260                         vcpu = ioapic->kvm->vcpus[vcpu_id];
261                         if (vcpu)
262                                 ioapic_inj_nmi(vcpu);
263                         else
264                                 ioapic_debug("NMI to vcpu %d failed\n",
265                                                 vcpu->vcpu_id);
266                 }
267                 break;
268         default:
269                 printk(KERN_WARNING "Unsupported delivery mode %d\n",
270                        delivery_mode);
271                 break;
272         }
273         return r;
274 }
275
276 void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
277 {
278         u32 old_irr = ioapic->irr;
279         u32 mask = 1 << irq;
280         union ioapic_redir_entry entry;
281
282         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
283                 entry = ioapic->redirtbl[irq];
284                 level ^= entry.fields.polarity;
285                 if (!level)
286                         ioapic->irr &= ~mask;
287                 else {
288                         ioapic->irr |= mask;
289                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
290                             || !entry.fields.remote_irr)
291                                 ioapic_service(ioapic, irq);
292                 }
293         }
294 }
295
296 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
297                                     int trigger_mode)
298 {
299         union ioapic_redir_entry *ent;
300
301         ent = &ioapic->redirtbl[pin];
302
303         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
304
305         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
306                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
307                 ent->fields.remote_irr = 0;
308                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
309                         ioapic_service(ioapic, pin);
310         }
311 }
312
313 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
314 {
315         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
316         int i;
317
318         for (i = 0; i < IOAPIC_NUM_PINS; i++)
319                 if (ioapic->redirtbl[i].fields.vector == vector)
320                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
321 }
322
323 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
324                            int len, int is_write)
325 {
326         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
327
328         return ((addr >= ioapic->base_address &&
329                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
330 }
331
332 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
333                              void *val)
334 {
335         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
336         u32 result;
337
338         ioapic_debug("addr %lx\n", (unsigned long)addr);
339         ASSERT(!(addr & 0xf));  /* check alignment */
340
341         addr &= 0xff;
342         switch (addr) {
343         case IOAPIC_REG_SELECT:
344                 result = ioapic->ioregsel;
345                 break;
346
347         case IOAPIC_REG_WINDOW:
348                 result = ioapic_read_indirect(ioapic, addr, len);
349                 break;
350
351         default:
352                 result = 0;
353                 break;
354         }
355         switch (len) {
356         case 8:
357                 *(u64 *) val = result;
358                 break;
359         case 1:
360         case 2:
361         case 4:
362                 memcpy(val, (char *)&result, len);
363                 break;
364         default:
365                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
366         }
367 }
368
369 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
370                               const void *val)
371 {
372         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
373         u32 data;
374
375         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
376                      (void*)addr, len, val);
377         ASSERT(!(addr & 0xf));  /* check alignment */
378         if (len == 4 || len == 8)
379                 data = *(u32 *) val;
380         else {
381                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
382                 return;
383         }
384
385         addr &= 0xff;
386         switch (addr) {
387         case IOAPIC_REG_SELECT:
388                 ioapic->ioregsel = data;
389                 break;
390
391         case IOAPIC_REG_WINDOW:
392                 ioapic_write_indirect(ioapic, data);
393                 break;
394 #ifdef  CONFIG_IA64
395         case IOAPIC_REG_EOI:
396                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
397                 break;
398 #endif
399
400         default:
401                 break;
402         }
403 }
404
405 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
406 {
407         int i;
408
409         for (i = 0; i < IOAPIC_NUM_PINS; i++)
410                 ioapic->redirtbl[i].fields.mask = 1;
411         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
412         ioapic->ioregsel = 0;
413         ioapic->irr = 0;
414         ioapic->id = 0;
415 }
416
417 int kvm_ioapic_init(struct kvm *kvm)
418 {
419         struct kvm_ioapic *ioapic;
420
421         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
422         if (!ioapic)
423                 return -ENOMEM;
424         kvm->arch.vioapic = ioapic;
425         kvm_ioapic_reset(ioapic);
426         ioapic->dev.read = ioapic_mmio_read;
427         ioapic->dev.write = ioapic_mmio_write;
428         ioapic->dev.in_range = ioapic_in_range;
429         ioapic->dev.private = ioapic;
430         ioapic->kvm = kvm;
431         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
432         return 0;
433 }
434