0fa482c9110b582607b5a575816a5daaec80e6b6
[linux-2.6.git] / sound / sparc / cs4231.c
1 /*
2  * Driver for CS4231 sound chips found on Sparcs.
3  * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4  *
5  * Based entirely upon drivers/sbus/audio/cs4231.c which is:
6  * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
7  * and also sound/isa/cs423x/cs4231_lib.c which is:
8  * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
9  */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/moduleparam.h>
19
20 #include <sound/driver.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/info.h>
24 #include <sound/control.h>
25 #include <sound/timer.h>
26 #include <sound/initval.h>
27 #include <sound/pcm_params.h>
28
29 #include <asm/io.h>
30 #include <asm/irq.h>
31
32 #ifdef CONFIG_SBUS
33 #define SBUS_SUPPORT
34 #endif
35
36 #ifdef SBUS_SUPPORT
37 #include <asm/sbus.h>
38 #endif
39
40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
41 #define EBUS_SUPPORT
42 #endif
43
44 #ifdef EBUS_SUPPORT
45 #include <linux/pci.h>
46 #include <asm/ebus.h>
47 #endif
48
49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
52
53 module_param_array(index, int, NULL, 0444);
54 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
55 module_param_array(id, charp, NULL, 0444);
56 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
57 module_param_array(enable, bool, NULL, 0444);
58 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
59 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
60 MODULE_DESCRIPTION("Sun CS4231");
61 MODULE_LICENSE("GPL");
62 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
63
64 #ifdef SBUS_SUPPORT
65 typedef struct sbus_dma_info {
66        spinlock_t      lock;
67        int             dir;
68        void __iomem    *regs;
69 } sbus_dma_info_t;
70 #endif
71
72 typedef struct snd_cs4231 cs4231_t;
73
74 typedef struct cs4231_dma_control {
75         void            (*prepare)(struct cs4231_dma_control *dma_cont, int dir);
76         void            (*enable)(struct cs4231_dma_control *dma_cont, int on);
77         int             (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len);
78         unsigned int    (*address)(struct cs4231_dma_control *dma_cont);
79         void            (*reset)(cs4231_t *chip); 
80         void            (*preallocate)(cs4231_t *chip, snd_pcm_t *pcm); 
81 #ifdef EBUS_SUPPORT
82         struct          ebus_dma_info   ebus_info;
83 #endif
84 #ifdef SBUS_SUPPORT
85         struct          sbus_dma_info   sbus_info;
86 #endif
87 } cs4231_dma_control_t;
88
89 struct snd_cs4231 {
90         spinlock_t              lock;
91         void __iomem            *port;
92
93         cs4231_dma_control_t    p_dma;
94         cs4231_dma_control_t    c_dma;
95
96         u32                     flags;
97 #define CS4231_FLAG_EBUS        0x00000001
98 #define CS4231_FLAG_PLAYBACK    0x00000002
99 #define CS4231_FLAG_CAPTURE     0x00000004
100
101         snd_card_t              *card;
102         snd_pcm_t               *pcm;
103         snd_pcm_substream_t     *playback_substream;
104         unsigned int            p_periods_sent;
105         snd_pcm_substream_t     *capture_substream;
106         unsigned int            c_periods_sent;
107         snd_timer_t             *timer;
108
109         unsigned short mode;
110 #define CS4231_MODE_NONE        0x0000
111 #define CS4231_MODE_PLAY        0x0001
112 #define CS4231_MODE_RECORD      0x0002
113 #define CS4231_MODE_TIMER       0x0004
114 #define CS4231_MODE_OPEN        (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
115
116         unsigned char           image[32];      /* registers image */
117         int                     mce_bit;
118         int                     calibrate_mute;
119         struct semaphore        mce_mutex;
120         struct semaphore        open_mutex;
121
122         union {
123 #ifdef SBUS_SUPPORT
124                 struct sbus_dev         *sdev;
125 #endif
126 #ifdef EBUS_SUPPORT
127                 struct pci_dev          *pdev;
128 #endif
129         } dev_u;
130         unsigned int            irq[2];
131         unsigned int            regs_size;
132         struct snd_cs4231       *next;
133 };
134
135 static cs4231_t *cs4231_list;
136
137 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
138  * now....  -DaveM
139  */
140
141 /* IO ports */
142
143 #define CS4231P(chip, x)        ((chip)->port + c_d_c_CS4231##x)
144
145 /* XXX offsets are different than PC ISA chips... */
146 #define c_d_c_CS4231REGSEL      0x0
147 #define c_d_c_CS4231REG         0x4
148 #define c_d_c_CS4231STATUS      0x8
149 #define c_d_c_CS4231PIO         0xc
150
151 /* codec registers */
152
153 #define CS4231_LEFT_INPUT       0x00    /* left input control */
154 #define CS4231_RIGHT_INPUT      0x01    /* right input control */
155 #define CS4231_AUX1_LEFT_INPUT  0x02    /* left AUX1 input control */
156 #define CS4231_AUX1_RIGHT_INPUT 0x03    /* right AUX1 input control */
157 #define CS4231_AUX2_LEFT_INPUT  0x04    /* left AUX2 input control */
158 #define CS4231_AUX2_RIGHT_INPUT 0x05    /* right AUX2 input control */
159 #define CS4231_LEFT_OUTPUT      0x06    /* left output control register */
160 #define CS4231_RIGHT_OUTPUT     0x07    /* right output control register */
161 #define CS4231_PLAYBK_FORMAT    0x08    /* clock and data format - playback - bits 7-0 MCE */
162 #define CS4231_IFACE_CTRL       0x09    /* interface control - bits 7-2 MCE */
163 #define CS4231_PIN_CTRL         0x0a    /* pin control */
164 #define CS4231_TEST_INIT        0x0b    /* test and initialization */
165 #define CS4231_MISC_INFO        0x0c    /* miscellaneaous information */
166 #define CS4231_LOOPBACK         0x0d    /* loopback control */
167 #define CS4231_PLY_UPR_CNT      0x0e    /* playback upper base count */
168 #define CS4231_PLY_LWR_CNT      0x0f    /* playback lower base count */
169 #define CS4231_ALT_FEATURE_1    0x10    /* alternate #1 feature enable */
170 #define CS4231_ALT_FEATURE_2    0x11    /* alternate #2 feature enable */
171 #define CS4231_LEFT_LINE_IN     0x12    /* left line input control */
172 #define CS4231_RIGHT_LINE_IN    0x13    /* right line input control */
173 #define CS4231_TIMER_LOW        0x14    /* timer low byte */
174 #define CS4231_TIMER_HIGH       0x15    /* timer high byte */
175 #define CS4231_LEFT_MIC_INPUT   0x16    /* left MIC input control register (InterWave only) */
176 #define CS4231_RIGHT_MIC_INPUT  0x17    /* right MIC input control register (InterWave only) */
177 #define CS4236_EXT_REG          0x17    /* extended register access */
178 #define CS4231_IRQ_STATUS       0x18    /* irq status register */
179 #define CS4231_LINE_LEFT_OUTPUT 0x19    /* left line output control register (InterWave only) */
180 #define CS4231_VERSION          0x19    /* CS4231(A) - version values */
181 #define CS4231_MONO_CTRL        0x1a    /* mono input/output control */
182 #define CS4231_LINE_RIGHT_OUTPUT 0x1b   /* right line output control register (InterWave only) */
183 #define CS4235_LEFT_MASTER      0x1b    /* left master output control */
184 #define CS4231_REC_FORMAT       0x1c    /* clock and data format - record - bits 7-0 MCE */
185 #define CS4231_PLY_VAR_FREQ     0x1d    /* playback variable frequency */
186 #define CS4235_RIGHT_MASTER     0x1d    /* right master output control */
187 #define CS4231_REC_UPR_CNT      0x1e    /* record upper count */
188 #define CS4231_REC_LWR_CNT      0x1f    /* record lower count */
189
190 /* definitions for codec register select port - CODECP( REGSEL ) */
191
192 #define CS4231_INIT             0x80    /* CODEC is initializing */
193 #define CS4231_MCE              0x40    /* mode change enable */
194 #define CS4231_TRD              0x20    /* transfer request disable */
195
196 /* definitions for codec status register - CODECP( STATUS ) */
197
198 #define CS4231_GLOBALIRQ        0x01    /* IRQ is active */
199
200 /* definitions for codec irq status - CS4231_IRQ_STATUS */
201
202 #define CS4231_PLAYBACK_IRQ     0x10
203 #define CS4231_RECORD_IRQ       0x20
204 #define CS4231_TIMER_IRQ        0x40
205 #define CS4231_ALL_IRQS         0x70
206 #define CS4231_REC_UNDERRUN     0x08
207 #define CS4231_REC_OVERRUN      0x04
208 #define CS4231_PLY_OVERRUN      0x02
209 #define CS4231_PLY_UNDERRUN     0x01
210
211 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
212
213 #define CS4231_ENABLE_MIC_GAIN  0x20
214
215 #define CS4231_MIXS_LINE        0x00
216 #define CS4231_MIXS_AUX1        0x40
217 #define CS4231_MIXS_MIC         0x80
218 #define CS4231_MIXS_ALL         0xc0
219
220 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
221
222 #define CS4231_LINEAR_8         0x00    /* 8-bit unsigned data */
223 #define CS4231_ALAW_8           0x60    /* 8-bit A-law companded */
224 #define CS4231_ULAW_8           0x20    /* 8-bit U-law companded */
225 #define CS4231_LINEAR_16        0x40    /* 16-bit twos complement data - little endian */
226 #define CS4231_LINEAR_16_BIG    0xc0    /* 16-bit twos complement data - big endian */
227 #define CS4231_ADPCM_16         0xa0    /* 16-bit ADPCM */
228 #define CS4231_STEREO           0x10    /* stereo mode */
229 /* bits 3-1 define frequency divisor */
230 #define CS4231_XTAL1            0x00    /* 24.576 crystal */
231 #define CS4231_XTAL2            0x01    /* 16.9344 crystal */
232
233 /* definitions for interface control register - CS4231_IFACE_CTRL */
234
235 #define CS4231_RECORD_PIO       0x80    /* record PIO enable */
236 #define CS4231_PLAYBACK_PIO     0x40    /* playback PIO enable */
237 #define CS4231_CALIB_MODE       0x18    /* calibration mode bits */
238 #define CS4231_AUTOCALIB        0x08    /* auto calibrate */
239 #define CS4231_SINGLE_DMA       0x04    /* use single DMA channel */
240 #define CS4231_RECORD_ENABLE    0x02    /* record enable */
241 #define CS4231_PLAYBACK_ENABLE  0x01    /* playback enable */
242
243 /* definitions for pin control register - CS4231_PIN_CTRL */
244
245 #define CS4231_IRQ_ENABLE       0x02    /* enable IRQ */
246 #define CS4231_XCTL1            0x40    /* external control #1 */
247 #define CS4231_XCTL0            0x80    /* external control #0 */
248
249 /* definitions for test and init register - CS4231_TEST_INIT */
250
251 #define CS4231_CALIB_IN_PROGRESS 0x20   /* auto calibrate in progress */
252 #define CS4231_DMA_REQUEST      0x10    /* DMA request in progress */
253
254 /* definitions for misc control register - CS4231_MISC_INFO */
255
256 #define CS4231_MODE2            0x40    /* MODE 2 */
257 #define CS4231_IW_MODE3         0x6c    /* MODE 3 - InterWave enhanced mode */
258 #define CS4231_4236_MODE3       0xe0    /* MODE 3 - CS4236+ enhanced mode */
259
260 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
261
262 #define CS4231_DACZ             0x01    /* zero DAC when underrun */
263 #define CS4231_TIMER_ENABLE     0x40    /* codec timer enable */
264 #define CS4231_OLB              0x80    /* output level bit */
265
266 /* SBUS DMA register defines.  */
267
268 #define APCCSR  0x10UL  /* APC DMA CSR */
269 #define APCCVA  0x20UL  /* APC Capture DMA Address */
270 #define APCCC   0x24UL  /* APC Capture Count */
271 #define APCCNVA 0x28UL  /* APC Capture DMA Next Address */
272 #define APCCNC  0x2cUL  /* APC Capture Next Count */
273 #define APCPVA  0x30UL  /* APC Play DMA Address */
274 #define APCPC   0x34UL  /* APC Play Count */
275 #define APCPNVA 0x38UL  /* APC Play DMA Next Address */
276 #define APCPNC  0x3cUL  /* APC Play Next Count */
277
278 /* Defines for SBUS DMA-routines */
279
280 #define APCVA  0x0UL    /* APC DMA Address */
281 #define APCC   0x4UL    /* APC Count */
282 #define APCNVA 0x8UL    /* APC DMA Next Address */
283 #define APCNC  0xcUL    /* APC Next Count */
284 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
285 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
286
287 /* APCCSR bits */
288
289 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
290 #define APC_PLAY_INT    0x400000 /* Playback interrupt */
291 #define APC_CAPT_INT    0x200000 /* Capture interrupt */
292 #define APC_GENL_INT    0x100000 /* General interrupt */
293 #define APC_XINT_ENA    0x80000  /* General ext int. enable */
294 #define APC_XINT_PLAY   0x40000  /* Playback ext intr */
295 #define APC_XINT_CAPT   0x20000  /* Capture ext intr */
296 #define APC_XINT_GENL   0x10000  /* Error ext intr */
297 #define APC_XINT_EMPT   0x8000   /* Pipe empty interrupt (0 write to pva) */
298 #define APC_XINT_PEMP   0x4000   /* Play pipe empty (pva and pnva not set) */
299 #define APC_XINT_PNVA   0x2000   /* Playback NVA dirty */
300 #define APC_XINT_PENA   0x1000   /* play pipe empty Int enable */
301 #define APC_XINT_COVF   0x800    /* Cap data dropped on floor */
302 #define APC_XINT_CNVA   0x400    /* Capture NVA dirty */
303 #define APC_XINT_CEMP   0x200    /* Capture pipe empty (cva and cnva not set) */
304 #define APC_XINT_CENA   0x100    /* Cap. pipe empty int enable */
305 #define APC_PPAUSE      0x80     /* Pause the play DMA */
306 #define APC_CPAUSE      0x40     /* Pause the capture DMA */
307 #define APC_CDC_RESET   0x20     /* CODEC RESET */
308 #define APC_PDMA_READY  0x08     /* Play DMA Go */
309 #define APC_CDMA_READY  0x04     /* Capture DMA Go */
310 #define APC_CHIP_RESET  0x01     /* Reset the chip */
311
312 /* EBUS DMA register offsets  */
313
314 #define EBDMA_CSR       0x00UL  /* Control/Status */
315 #define EBDMA_ADDR      0x04UL  /* DMA Address */
316 #define EBDMA_COUNT     0x08UL  /* DMA Count */
317
318 /*
319  *  Some variables
320  */
321
322 static unsigned char freq_bits[14] = {
323         /* 5510 */      0x00 | CS4231_XTAL2,
324         /* 6620 */      0x0E | CS4231_XTAL2,
325         /* 8000 */      0x00 | CS4231_XTAL1,
326         /* 9600 */      0x0E | CS4231_XTAL1,
327         /* 11025 */     0x02 | CS4231_XTAL2,
328         /* 16000 */     0x02 | CS4231_XTAL1,
329         /* 18900 */     0x04 | CS4231_XTAL2,
330         /* 22050 */     0x06 | CS4231_XTAL2,
331         /* 27042 */     0x04 | CS4231_XTAL1,
332         /* 32000 */     0x06 | CS4231_XTAL1,
333         /* 33075 */     0x0C | CS4231_XTAL2,
334         /* 37800 */     0x08 | CS4231_XTAL2,
335         /* 44100 */     0x0A | CS4231_XTAL2,
336         /* 48000 */     0x0C | CS4231_XTAL1
337 };
338
339 static unsigned int rates[14] = {
340         5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
341         27042, 32000, 33075, 37800, 44100, 48000
342 };
343
344 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
345         .count  = 14,
346         .list   = rates,
347 };
348
349 static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime)
350 {
351         return snd_pcm_hw_constraint_list(runtime, 0,
352                                           SNDRV_PCM_HW_PARAM_RATE,
353                                           &hw_constraints_rates);
354 }
355
356 static unsigned char snd_cs4231_original_image[32] =
357 {
358         0x00,                   /* 00/00 - lic */
359         0x00,                   /* 01/01 - ric */
360         0x9f,                   /* 02/02 - la1ic */
361         0x9f,                   /* 03/03 - ra1ic */
362         0x9f,                   /* 04/04 - la2ic */
363         0x9f,                   /* 05/05 - ra2ic */
364         0xbf,                   /* 06/06 - loc */
365         0xbf,                   /* 07/07 - roc */
366         0x20,                   /* 08/08 - pdfr */
367         CS4231_AUTOCALIB,       /* 09/09 - ic */
368         0x00,                   /* 0a/10 - pc */
369         0x00,                   /* 0b/11 - ti */
370         CS4231_MODE2,           /* 0c/12 - mi */
371         0x00,                   /* 0d/13 - lbc */
372         0x00,                   /* 0e/14 - pbru */
373         0x00,                   /* 0f/15 - pbrl */
374         0x80,                   /* 10/16 - afei */
375         0x01,                   /* 11/17 - afeii */
376         0x9f,                   /* 12/18 - llic */
377         0x9f,                   /* 13/19 - rlic */
378         0x00,                   /* 14/20 - tlb */
379         0x00,                   /* 15/21 - thb */
380         0x00,                   /* 16/22 - la3mic/reserved */
381         0x00,                   /* 17/23 - ra3mic/reserved */
382         0x00,                   /* 18/24 - afs */
383         0x00,                   /* 19/25 - lamoc/version */
384         0x00,                   /* 1a/26 - mioc */
385         0x00,                   /* 1b/27 - ramoc/reserved */
386         0x20,                   /* 1c/28 - cdfr */
387         0x00,                   /* 1d/29 - res4 */
388         0x00,                   /* 1e/30 - cbru */
389         0x00,                   /* 1f/31 - cbrl */
390 };
391
392 static u8 __cs4231_readb(cs4231_t *cp, void __iomem *reg_addr)
393 {
394 #ifdef EBUS_SUPPORT
395         if (cp->flags & CS4231_FLAG_EBUS) {
396                 return readb(reg_addr);
397         } else {
398 #endif
399 #ifdef SBUS_SUPPORT
400                 return sbus_readb(reg_addr);
401 #endif
402 #ifdef EBUS_SUPPORT
403         }
404 #endif
405 }
406
407 static void __cs4231_writeb(cs4231_t *cp, u8 val, void __iomem *reg_addr)
408 {
409 #ifdef EBUS_SUPPORT
410         if (cp->flags & CS4231_FLAG_EBUS) {
411                 return writeb(val, reg_addr);
412         } else {
413 #endif
414 #ifdef SBUS_SUPPORT
415                 return sbus_writeb(val, reg_addr);
416 #endif
417 #ifdef EBUS_SUPPORT
418         }
419 #endif
420 }
421
422 /*
423  *  Basic I/O functions
424  */
425
426 static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg,
427                      unsigned char mask, unsigned char value)
428 {
429         int timeout;
430         unsigned char tmp;
431
432         for (timeout = 250;
433              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
434              timeout--)
435                 udelay(100);
436 #ifdef CONFIG_SND_DEBUG
437         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
438                 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
439 #endif
440         if (chip->calibrate_mute) {
441                 chip->image[reg] &= mask;
442                 chip->image[reg] |= value;
443         } else {
444                 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
445                 mb();
446                 tmp = (chip->image[reg] & mask) | value;
447                 __cs4231_writeb(chip, tmp, CS4231P(chip, REG));
448                 chip->image[reg] = tmp;
449                 mb();
450         }
451 }
452
453 static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value)
454 {
455         int timeout;
456
457         for (timeout = 250;
458              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
459              timeout--)
460                 udelay(100);
461 #ifdef CONFIG_SND_DEBUG
462         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
463                 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
464 #endif
465         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
466         __cs4231_writeb(chip, value, CS4231P(chip, REG));
467         mb();
468 }
469
470 static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value)
471 {
472         int timeout;
473
474         for (timeout = 250;
475              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
476              timeout--)
477                 udelay(100);
478 #ifdef CONFIG_SND_DEBUG
479         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
480                 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
481 #endif
482         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
483         __cs4231_writeb(chip, value, CS4231P(chip, REG));
484         chip->image[reg] = value;
485         mb();
486 }
487
488 static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg)
489 {
490         int timeout;
491         unsigned char ret;
492
493         for (timeout = 250;
494              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
495              timeout--)
496                 udelay(100);
497 #ifdef CONFIG_SND_DEBUG
498         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
499                 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg);
500 #endif
501         __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
502         mb();
503         ret = __cs4231_readb(chip, CS4231P(chip, REG));
504         return ret;
505 }
506
507 /*
508  *  CS4231 detection / MCE routines
509  */
510
511 static void snd_cs4231_busy_wait(cs4231_t *chip)
512 {
513         int timeout;
514
515         /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
516         for (timeout = 5; timeout > 0; timeout--)
517                 __cs4231_readb(chip, CS4231P(chip, REGSEL));
518
519         /* end of cleanup sequence */
520         for (timeout = 500;
521              timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
522              timeout--)
523                 udelay(1000);
524 }
525
526 static void snd_cs4231_mce_up(cs4231_t *chip)
527 {
528         unsigned long flags;
529         int timeout;
530
531         spin_lock_irqsave(&chip->lock, flags);
532         for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--)
533                 udelay(100);
534 #ifdef CONFIG_SND_DEBUG
535         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
536                 snd_printdd("mce_up - auto calibration time out (0)\n");
537 #endif
538         chip->mce_bit |= CS4231_MCE;
539         timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
540         if (timeout == 0x80)
541                 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
542         if (!(timeout & CS4231_MCE))
543                 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
544         spin_unlock_irqrestore(&chip->lock, flags);
545 }
546
547 static void snd_cs4231_mce_down(cs4231_t *chip)
548 {
549         unsigned long flags;
550         int timeout;
551
552         spin_lock_irqsave(&chip->lock, flags);
553         snd_cs4231_busy_wait(chip);
554 #ifdef CONFIG_SND_DEBUG
555         if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
556                 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
557 #endif
558         chip->mce_bit &= ~CS4231_MCE;
559         timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
560         __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
561         if (timeout == 0x80)
562                 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
563         if ((timeout & CS4231_MCE) == 0) {
564                 spin_unlock_irqrestore(&chip->lock, flags);
565                 return;
566         }
567         snd_cs4231_busy_wait(chip);
568
569         /* calibration process */
570
571         for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--)
572                 udelay(100);
573         if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
574                 snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
575                 spin_unlock_irqrestore(&chip->lock, flags);
576                 return;
577         }
578
579         /* in 10ms increments, check condition, up to 250ms */
580         timeout = 25;
581         while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
582                 spin_unlock_irqrestore(&chip->lock, flags);
583                 if (--timeout < 0) {
584                         snd_printk("mce_down - auto calibration time out (2)\n");
585                         return;
586                 }
587                 msleep(10);
588                 spin_lock_irqsave(&chip->lock, flags);
589         }
590
591         /* in 10ms increments, check condition, up to 100ms */
592         timeout = 10;
593         while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
594                 spin_unlock_irqrestore(&chip->lock, flags);
595                 if (--timeout < 0) {
596                         snd_printk("mce_down - auto calibration time out (3)\n");
597                         return;
598                 }
599                 msleep(10);
600                 spin_lock_irqsave(&chip->lock, flags);
601         }
602         spin_unlock_irqrestore(&chip->lock, flags);
603 }
604
605 static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont, snd_pcm_substream_t *substream, unsigned int *periods_sent)
606 {
607         snd_pcm_runtime_t *runtime = substream->runtime;
608
609         while (1) {
610                 unsigned int period_size = snd_pcm_lib_period_bytes(substream);
611                 unsigned int offset = period_size * (*periods_sent);
612
613                 if (period_size >= (1 << 24))
614                         BUG();
615
616                 if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size))
617                         return;
618                 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
619         }
620 }
621
622 static void cs4231_dma_trigger(snd_pcm_substream_t *substream, unsigned int what, int on)
623 {
624         cs4231_t *chip = snd_pcm_substream_chip(substream);
625         cs4231_dma_control_t *dma_cont;
626
627         if (what & CS4231_PLAYBACK_ENABLE) {
628                 dma_cont = &chip->p_dma;
629                 if (on) {
630                         dma_cont->prepare(dma_cont, 0);
631                         dma_cont->enable(dma_cont, 1);
632                         snd_cs4231_advance_dma(dma_cont,
633                                 chip->playback_substream,
634                                 &chip->p_periods_sent);
635                 } else {
636                         dma_cont->enable(dma_cont, 0);
637                 }
638         }
639         if (what & CS4231_RECORD_ENABLE) {
640                 dma_cont = &chip->c_dma;
641                 if (on) {
642                         dma_cont->prepare(dma_cont, 1);
643                         dma_cont->enable(dma_cont, 1);
644                         snd_cs4231_advance_dma(dma_cont,
645                                 chip->capture_substream,
646                                 &chip->c_periods_sent);
647                 } else {
648                         dma_cont->enable(dma_cont, 0);
649                 }
650         }
651 }
652
653 static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd)
654 {
655         cs4231_t *chip = snd_pcm_substream_chip(substream);
656         int result = 0;
657
658         switch (cmd) {
659         case SNDRV_PCM_TRIGGER_START:
660         case SNDRV_PCM_TRIGGER_STOP:
661         {
662                 unsigned int what = 0;
663                 snd_pcm_substream_t *s;
664                 struct list_head *pos;
665                 unsigned long flags;
666
667                 snd_pcm_group_for_each(pos, substream) {
668                         s = snd_pcm_group_substream_entry(pos);
669                         if (s == chip->playback_substream) {
670                                 what |= CS4231_PLAYBACK_ENABLE;
671                                 snd_pcm_trigger_done(s, substream);
672                         } else if (s == chip->capture_substream) {
673                                 what |= CS4231_RECORD_ENABLE;
674                                 snd_pcm_trigger_done(s, substream);
675                         }
676                 }
677
678                 spin_lock_irqsave(&chip->lock, flags);
679                 if (cmd == SNDRV_PCM_TRIGGER_START) {
680                         cs4231_dma_trigger(substream, what, 1);
681                         chip->image[CS4231_IFACE_CTRL] |= what;
682                 } else {
683                         cs4231_dma_trigger(substream, what, 0);
684                         chip->image[CS4231_IFACE_CTRL] &= ~what;
685                 }
686                 snd_cs4231_out(chip, CS4231_IFACE_CTRL,
687                                chip->image[CS4231_IFACE_CTRL]);
688                 spin_unlock_irqrestore(&chip->lock, flags);
689                 break;
690         }
691         default:
692                 result = -EINVAL;
693                 break;
694         }
695
696         return result;
697 }
698
699 /*
700  *  CODEC I/O
701  */
702
703 static unsigned char snd_cs4231_get_rate(unsigned int rate)
704 {
705         int i;
706
707         for (i = 0; i < 14; i++)
708                 if (rate == rates[i])
709                         return freq_bits[i];
710         // snd_BUG();
711         return freq_bits[13];
712 }
713
714 static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int channels)
715 {
716         unsigned char rformat;
717
718         rformat = CS4231_LINEAR_8;
719         switch (format) {
720         case SNDRV_PCM_FORMAT_MU_LAW:   rformat = CS4231_ULAW_8; break;
721         case SNDRV_PCM_FORMAT_A_LAW:    rformat = CS4231_ALAW_8; break;
722         case SNDRV_PCM_FORMAT_S16_LE:   rformat = CS4231_LINEAR_16; break;
723         case SNDRV_PCM_FORMAT_S16_BE:   rformat = CS4231_LINEAR_16_BIG; break;
724         case SNDRV_PCM_FORMAT_IMA_ADPCM:        rformat = CS4231_ADPCM_16; break;
725         }
726         if (channels > 1)
727                 rformat |= CS4231_STEREO;
728         return rformat;
729 }
730
731 static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute)
732 {
733         unsigned long flags;
734
735         mute = mute ? 1 : 0;
736         spin_lock_irqsave(&chip->lock, flags);
737         if (chip->calibrate_mute == mute) {
738                 spin_unlock_irqrestore(&chip->lock, flags);
739                 return;
740         }
741         if (!mute) {
742                 snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
743                                 chip->image[CS4231_LEFT_INPUT]);
744                 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
745                                 chip->image[CS4231_RIGHT_INPUT]);
746                 snd_cs4231_dout(chip, CS4231_LOOPBACK,
747                                 chip->image[CS4231_LOOPBACK]);
748         }
749         snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
750                         mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
751         snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
752                         mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
753         snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
754                         mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
755         snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
756                         mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
757         snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
758                         mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
759         snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
760                         mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
761         snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
762                         mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
763         snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
764                         mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
765         snd_cs4231_dout(chip, CS4231_MONO_CTRL,
766                         mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
767         chip->calibrate_mute = mute;
768         spin_unlock_irqrestore(&chip->lock, flags);
769 }
770
771 static void snd_cs4231_playback_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
772                                        unsigned char pdfr)
773 {
774         unsigned long flags;
775
776         down(&chip->mce_mutex);
777         snd_cs4231_calibrate_mute(chip, 1);
778
779         snd_cs4231_mce_up(chip);
780
781         spin_lock_irqsave(&chip->lock, flags);
782         snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
783                        (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
784                        (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
785                        pdfr);
786         spin_unlock_irqrestore(&chip->lock, flags);
787
788         snd_cs4231_mce_down(chip);
789
790         snd_cs4231_calibrate_mute(chip, 0);
791         up(&chip->mce_mutex);
792 }
793
794 static void snd_cs4231_capture_format(cs4231_t *chip, snd_pcm_hw_params_t *params,
795                                       unsigned char cdfr)
796 {
797         unsigned long flags;
798
799         down(&chip->mce_mutex);
800         snd_cs4231_calibrate_mute(chip, 1);
801
802         snd_cs4231_mce_up(chip);
803
804         spin_lock_irqsave(&chip->lock, flags);
805         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
806                 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
807                                ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
808                                (cdfr & 0x0f));
809                 spin_unlock_irqrestore(&chip->lock, flags);
810                 snd_cs4231_mce_down(chip);
811                 snd_cs4231_mce_up(chip);
812                 spin_lock_irqsave(&chip->lock, flags);
813         }
814         snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
815         spin_unlock_irqrestore(&chip->lock, flags);
816
817         snd_cs4231_mce_down(chip);
818
819         snd_cs4231_calibrate_mute(chip, 0);
820         up(&chip->mce_mutex);
821 }
822
823 /*
824  *  Timer interface
825  */
826
827 static unsigned long snd_cs4231_timer_resolution(snd_timer_t *timer)
828 {
829         cs4231_t *chip = snd_timer_chip(timer);
830
831         return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
832 }
833
834 static int snd_cs4231_timer_start(snd_timer_t *timer)
835 {
836         unsigned long flags;
837         unsigned int ticks;
838         cs4231_t *chip = snd_timer_chip(timer);
839
840         spin_lock_irqsave(&chip->lock, flags);
841         ticks = timer->sticks;
842         if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
843             (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
844             (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
845                 snd_cs4231_out(chip, CS4231_TIMER_HIGH,
846                                chip->image[CS4231_TIMER_HIGH] =
847                                (unsigned char) (ticks >> 8));
848                 snd_cs4231_out(chip, CS4231_TIMER_LOW,
849                                chip->image[CS4231_TIMER_LOW] =
850                                (unsigned char) ticks);
851                 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
852                                chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
853         }
854         spin_unlock_irqrestore(&chip->lock, flags);
855
856         return 0;
857 }
858
859 static int snd_cs4231_timer_stop(snd_timer_t *timer)
860 {
861         unsigned long flags;
862         cs4231_t *chip = snd_timer_chip(timer);
863
864         spin_lock_irqsave(&chip->lock, flags);
865         snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
866                        chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
867         spin_unlock_irqrestore(&chip->lock, flags);
868
869         return 0;
870 }
871
872 static void snd_cs4231_init(cs4231_t *chip)
873 {
874         unsigned long flags;
875
876         snd_cs4231_mce_down(chip);
877
878 #ifdef SNDRV_DEBUG_MCE
879         snd_printdd("init: (1)\n");
880 #endif
881         snd_cs4231_mce_up(chip);
882         spin_lock_irqsave(&chip->lock, flags);
883         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
884                                             CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
885                                             CS4231_CALIB_MODE);
886         chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
887         snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
888         spin_unlock_irqrestore(&chip->lock, flags);
889         snd_cs4231_mce_down(chip);
890
891 #ifdef SNDRV_DEBUG_MCE
892         snd_printdd("init: (2)\n");
893 #endif
894
895         snd_cs4231_mce_up(chip);
896         spin_lock_irqsave(&chip->lock, flags);
897         snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
898         spin_unlock_irqrestore(&chip->lock, flags);
899         snd_cs4231_mce_down(chip);
900
901 #ifdef SNDRV_DEBUG_MCE
902         snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
903 #endif
904
905         spin_lock_irqsave(&chip->lock, flags);
906         snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
907         spin_unlock_irqrestore(&chip->lock, flags);
908
909         snd_cs4231_mce_up(chip);
910         spin_lock_irqsave(&chip->lock, flags);
911         snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
912         spin_unlock_irqrestore(&chip->lock, flags);
913         snd_cs4231_mce_down(chip);
914
915 #ifdef SNDRV_DEBUG_MCE
916         snd_printdd("init: (4)\n");
917 #endif
918
919         snd_cs4231_mce_up(chip);
920         spin_lock_irqsave(&chip->lock, flags);
921         snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
922         spin_unlock_irqrestore(&chip->lock, flags);
923         snd_cs4231_mce_down(chip);
924
925 #ifdef SNDRV_DEBUG_MCE
926         snd_printdd("init: (5)\n");
927 #endif
928 }
929
930 static int snd_cs4231_open(cs4231_t *chip, unsigned int mode)
931 {
932         unsigned long flags;
933
934         down(&chip->open_mutex);
935         if ((chip->mode & mode)) {
936                 up(&chip->open_mutex);
937                 return -EAGAIN;
938         }
939         if (chip->mode & CS4231_MODE_OPEN) {
940                 chip->mode |= mode;
941                 up(&chip->open_mutex);
942                 return 0;
943         }
944         /* ok. now enable and ack CODEC IRQ */
945         spin_lock_irqsave(&chip->lock, flags);
946         snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
947                        CS4231_RECORD_IRQ |
948                        CS4231_TIMER_IRQ);
949         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
950         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
951         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
952
953         snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
954                        CS4231_RECORD_IRQ |
955                        CS4231_TIMER_IRQ);
956         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
957
958         spin_unlock_irqrestore(&chip->lock, flags);
959
960         chip->mode = mode;
961         up(&chip->open_mutex);
962         return 0;
963 }
964
965 static void snd_cs4231_close(cs4231_t *chip, unsigned int mode)
966 {
967         unsigned long flags;
968
969         down(&chip->open_mutex);
970         chip->mode &= ~mode;
971         if (chip->mode & CS4231_MODE_OPEN) {
972                 up(&chip->open_mutex);
973                 return;
974         }
975         snd_cs4231_calibrate_mute(chip, 1);
976
977         /* disable IRQ */
978         spin_lock_irqsave(&chip->lock, flags);
979         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
980         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
981         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
982
983         /* now disable record & playback */
984
985         if (chip->image[CS4231_IFACE_CTRL] &
986             (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
987              CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
988                 spin_unlock_irqrestore(&chip->lock, flags);
989                 snd_cs4231_mce_up(chip);
990                 spin_lock_irqsave(&chip->lock, flags);
991                 chip->image[CS4231_IFACE_CTRL] &=
992                         ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
993                           CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
994                 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
995                 spin_unlock_irqrestore(&chip->lock, flags);
996                 snd_cs4231_mce_down(chip);
997                 spin_lock_irqsave(&chip->lock, flags);
998         }
999
1000         /* clear IRQ again */
1001         snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
1002         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1003         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));        /* clear IRQ */
1004         spin_unlock_irqrestore(&chip->lock, flags);
1005
1006         snd_cs4231_calibrate_mute(chip, 0);
1007
1008         chip->mode = 0;
1009         up(&chip->open_mutex);
1010 }
1011
1012 /*
1013  *  timer open/close
1014  */
1015
1016 static int snd_cs4231_timer_open(snd_timer_t *timer)
1017 {
1018         cs4231_t *chip = snd_timer_chip(timer);
1019         snd_cs4231_open(chip, CS4231_MODE_TIMER);
1020         return 0;
1021 }
1022
1023 static int snd_cs4231_timer_close(snd_timer_t * timer)
1024 {
1025         cs4231_t *chip = snd_timer_chip(timer);
1026         snd_cs4231_close(chip, CS4231_MODE_TIMER);
1027         return 0;
1028 }
1029
1030 static struct _snd_timer_hardware snd_cs4231_timer_table =
1031 {
1032         .flags          =       SNDRV_TIMER_HW_AUTO,
1033         .resolution     =       9945,
1034         .ticks          =       65535,
1035         .open           =       snd_cs4231_timer_open,
1036         .close          =       snd_cs4231_timer_close,
1037         .c_resolution   =       snd_cs4231_timer_resolution,
1038         .start          =       snd_cs4231_timer_start,
1039         .stop           =       snd_cs4231_timer_stop,
1040 };
1041
1042 /*
1043  *  ok.. exported functions..
1044  */
1045
1046 static int snd_cs4231_playback_hw_params(snd_pcm_substream_t *substream,
1047                                          snd_pcm_hw_params_t *hw_params)
1048 {
1049         cs4231_t *chip = snd_pcm_substream_chip(substream);
1050         unsigned char new_pdfr;
1051         int err;
1052
1053         if ((err = snd_pcm_lib_malloc_pages(substream,
1054                                             params_buffer_bytes(hw_params))) < 0)
1055                 return err;
1056         new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1057                                          params_channels(hw_params)) |
1058                 snd_cs4231_get_rate(params_rate(hw_params));
1059         snd_cs4231_playback_format(chip, hw_params, new_pdfr);
1060
1061         return 0;
1062 }
1063
1064 static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream)
1065 {
1066         return snd_pcm_lib_free_pages(substream);
1067 }
1068
1069 static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream)
1070 {
1071         cs4231_t *chip = snd_pcm_substream_chip(substream);
1072         snd_pcm_runtime_t *runtime = substream->runtime;
1073         unsigned long flags;
1074
1075         spin_lock_irqsave(&chip->lock, flags);
1076
1077         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
1078                                             CS4231_PLAYBACK_PIO);
1079
1080         if (runtime->period_size > 0xffff + 1)
1081                 BUG();
1082
1083         chip->p_periods_sent = 0;
1084         spin_unlock_irqrestore(&chip->lock, flags);
1085
1086         return 0;
1087 }
1088
1089 static int snd_cs4231_capture_hw_params(snd_pcm_substream_t *substream,
1090                                         snd_pcm_hw_params_t *hw_params)
1091 {
1092         cs4231_t *chip = snd_pcm_substream_chip(substream);
1093         unsigned char new_cdfr;
1094         int err;
1095
1096         if ((err = snd_pcm_lib_malloc_pages(substream,
1097                                             params_buffer_bytes(hw_params))) < 0)
1098                 return err;
1099         new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
1100                                          params_channels(hw_params)) |
1101                 snd_cs4231_get_rate(params_rate(hw_params));
1102         snd_cs4231_capture_format(chip, hw_params, new_cdfr);
1103
1104         return 0;
1105 }
1106
1107 static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream)
1108 {
1109         return snd_pcm_lib_free_pages(substream);
1110 }
1111
1112 static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream)
1113 {
1114         cs4231_t *chip = snd_pcm_substream_chip(substream);
1115         unsigned long flags;
1116
1117         spin_lock_irqsave(&chip->lock, flags);
1118         chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
1119                                             CS4231_RECORD_PIO);
1120
1121
1122         chip->c_periods_sent = 0;
1123         spin_unlock_irqrestore(&chip->lock, flags);
1124
1125         return 0;
1126 }
1127
1128 static void snd_cs4231_overrange(cs4231_t *chip)
1129 {
1130         unsigned long flags;
1131         unsigned char res;
1132
1133         spin_lock_irqsave(&chip->lock, flags);
1134         res = snd_cs4231_in(chip, CS4231_TEST_INIT);
1135         spin_unlock_irqrestore(&chip->lock, flags);
1136
1137         if (res & (0x08 | 0x02))        /* detect overrange only above 0dB; may be user selectable? */
1138                 chip->capture_substream->runtime->overrange++;
1139 }
1140
1141 static void snd_cs4231_play_callback(cs4231_t *cookie)
1142 {
1143         cs4231_t *chip = cookie;
1144
1145         if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
1146                 snd_pcm_period_elapsed(chip->playback_substream);
1147                 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
1148                                             &chip->p_periods_sent);
1149         }
1150 }
1151
1152 static void snd_cs4231_capture_callback(cs4231_t *cookie)
1153 {
1154         cs4231_t *chip = cookie;
1155
1156         if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
1157                 snd_pcm_period_elapsed(chip->capture_substream);
1158                 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
1159                                             &chip->c_periods_sent);
1160         }
1161 }
1162
1163 static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream)
1164 {
1165         cs4231_t *chip = snd_pcm_substream_chip(substream);
1166         cs4231_dma_control_t *dma_cont = &chip->p_dma;
1167         size_t ptr;
1168         
1169         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1170                 return 0;
1171         ptr = dma_cont->address(dma_cont);
1172         if (ptr != 0)
1173                 ptr -= substream->runtime->dma_addr;
1174         
1175         return bytes_to_frames(substream->runtime, ptr);
1176 }
1177
1178 static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream)
1179 {
1180         cs4231_t *chip = snd_pcm_substream_chip(substream);
1181         cs4231_dma_control_t *dma_cont = &chip->c_dma;
1182         size_t ptr;
1183         
1184         if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1185                 return 0;
1186         ptr = dma_cont->address(dma_cont);
1187         if (ptr != 0)
1188                 ptr -= substream->runtime->dma_addr;
1189         
1190         return bytes_to_frames(substream->runtime, ptr);
1191 }
1192
1193 /*
1194
1195  */
1196
1197 static int snd_cs4231_probe(cs4231_t *chip)
1198 {
1199         unsigned long flags;
1200         int i, id, vers;
1201         unsigned char *ptr;
1202
1203         id = vers = 0;
1204         for (i = 0; i < 50; i++) {
1205                 mb();
1206                 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
1207                         udelay(2000);
1208                 else {
1209                         spin_lock_irqsave(&chip->lock, flags);
1210                         snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
1211                         id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
1212                         vers = snd_cs4231_in(chip, CS4231_VERSION);
1213                         spin_unlock_irqrestore(&chip->lock, flags);
1214                         if (id == 0x0a)
1215                                 break;  /* this is valid value */
1216                 }
1217         }
1218         snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
1219         if (id != 0x0a)
1220                 return -ENODEV; /* no valid device found */
1221
1222         spin_lock_irqsave(&chip->lock, flags);
1223
1224
1225         /* Reset DMA engine (sbus only).  */
1226         chip->p_dma.reset(chip);
1227
1228         __cs4231_readb(chip, CS4231P(chip, STATUS));    /* clear any pendings IRQ */
1229         __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
1230         mb();
1231
1232         spin_unlock_irqrestore(&chip->lock, flags);
1233
1234         chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1235         chip->image[CS4231_IFACE_CTRL] =
1236                 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
1237         chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1238         chip->image[CS4231_ALT_FEATURE_2] = 0x01;
1239         if (vers & 0x20)
1240                 chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
1241
1242         ptr = (unsigned char *) &chip->image;
1243
1244         snd_cs4231_mce_down(chip);
1245
1246         spin_lock_irqsave(&chip->lock, flags);
1247
1248         for (i = 0; i < 32; i++)        /* ok.. fill all CS4231 registers */
1249                 snd_cs4231_out(chip, i, *ptr++);
1250
1251         spin_unlock_irqrestore(&chip->lock, flags);
1252
1253         snd_cs4231_mce_up(chip);
1254
1255         snd_cs4231_mce_down(chip);
1256
1257         mdelay(2);
1258
1259         return 0;               /* all things are ok.. */
1260 }
1261
1262 static snd_pcm_hardware_t snd_cs4231_playback =
1263 {
1264         .info                   = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1265                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1266         .formats                = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1267                                  SNDRV_PCM_FMTBIT_IMA_ADPCM |
1268                                  SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1269                                  SNDRV_PCM_FMTBIT_S16_BE),
1270         .rates                  = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1271         .rate_min               = 5510,
1272         .rate_max               = 48000,
1273         .channels_min           = 1,
1274         .channels_max           = 2,
1275         .buffer_bytes_max       = (32*1024),
1276         .period_bytes_min       = 4096,
1277         .period_bytes_max       = (32*1024),
1278         .periods_min            = 1,
1279         .periods_max            = 1024,
1280 };
1281
1282 static snd_pcm_hardware_t snd_cs4231_capture =
1283 {
1284         .info                   = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1285                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1286         .formats                = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
1287                                  SNDRV_PCM_FMTBIT_IMA_ADPCM |
1288                                  SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
1289                                  SNDRV_PCM_FMTBIT_S16_BE),
1290         .rates                  = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1291         .rate_min               = 5510,
1292         .rate_max               = 48000,
1293         .channels_min           = 1,
1294         .channels_max           = 2,
1295         .buffer_bytes_max       = (32*1024),
1296         .period_bytes_min       = 4096,
1297         .period_bytes_max       = (32*1024),
1298         .periods_min            = 1,
1299         .periods_max            = 1024,
1300 };
1301
1302 static int snd_cs4231_playback_open(snd_pcm_substream_t *substream)
1303 {
1304         cs4231_t *chip = snd_pcm_substream_chip(substream);
1305         snd_pcm_runtime_t *runtime = substream->runtime;
1306         int err;
1307
1308         runtime->hw = snd_cs4231_playback;
1309
1310         if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
1311                 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1312                 return err;
1313         }
1314         chip->playback_substream = substream;
1315         chip->p_periods_sent = 0;
1316         snd_pcm_set_sync(substream);
1317         snd_cs4231_xrate(runtime);
1318
1319         return 0;
1320 }
1321
1322 static int snd_cs4231_capture_open(snd_pcm_substream_t *substream)
1323 {
1324         cs4231_t *chip = snd_pcm_substream_chip(substream);
1325         snd_pcm_runtime_t *runtime = substream->runtime;
1326         int err;
1327
1328         runtime->hw = snd_cs4231_capture;
1329
1330         if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
1331                 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1332                 return err;
1333         }
1334         chip->capture_substream = substream;
1335         chip->c_periods_sent = 0;
1336         snd_pcm_set_sync(substream);
1337         snd_cs4231_xrate(runtime);
1338
1339         return 0;
1340 }
1341
1342 static int snd_cs4231_playback_close(snd_pcm_substream_t *substream)
1343 {
1344         cs4231_t *chip = snd_pcm_substream_chip(substream);
1345
1346         snd_cs4231_close(chip, CS4231_MODE_PLAY);
1347         chip->playback_substream = NULL;
1348
1349         return 0;
1350 }
1351
1352 static int snd_cs4231_capture_close(snd_pcm_substream_t *substream)
1353 {
1354         cs4231_t *chip = snd_pcm_substream_chip(substream);
1355
1356         snd_cs4231_close(chip, CS4231_MODE_RECORD);
1357         chip->capture_substream = NULL;
1358
1359         return 0;
1360 }
1361
1362 /* XXX We can do some power-management, in particular on EBUS using
1363  * XXX the audio AUXIO register...
1364  */
1365
1366 static snd_pcm_ops_t snd_cs4231_playback_ops = {
1367         .open           =       snd_cs4231_playback_open,
1368         .close          =       snd_cs4231_playback_close,
1369         .ioctl          =       snd_pcm_lib_ioctl,
1370         .hw_params      =       snd_cs4231_playback_hw_params,
1371         .hw_free        =       snd_cs4231_playback_hw_free,
1372         .prepare        =       snd_cs4231_playback_prepare,
1373         .trigger        =       snd_cs4231_trigger,
1374         .pointer        =       snd_cs4231_playback_pointer,
1375 };
1376
1377 static snd_pcm_ops_t snd_cs4231_capture_ops = {
1378         .open           =       snd_cs4231_capture_open,
1379         .close          =       snd_cs4231_capture_close,
1380         .ioctl          =       snd_pcm_lib_ioctl,
1381         .hw_params      =       snd_cs4231_capture_hw_params,
1382         .hw_free        =       snd_cs4231_capture_hw_free,
1383         .prepare        =       snd_cs4231_capture_prepare,
1384         .trigger        =       snd_cs4231_trigger,
1385         .pointer        =       snd_cs4231_capture_pointer,
1386 };
1387
1388 int snd_cs4231_pcm(cs4231_t *chip)
1389 {
1390         snd_pcm_t *pcm;
1391         int err;
1392
1393         if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0)
1394                 return err;
1395
1396         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
1397         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
1398         
1399         /* global setup */
1400         pcm->private_data = chip;
1401         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1402         strcpy(pcm->name, "CS4231");
1403
1404         chip->p_dma.preallocate(chip, pcm);
1405
1406         chip->pcm = pcm;
1407
1408         return 0;
1409 }
1410
1411 static void snd_cs4231_timer_free(snd_timer_t *timer)
1412 {
1413         cs4231_t *chip = timer->private_data;
1414         chip->timer = NULL;
1415 }
1416
1417 int snd_cs4231_timer(cs4231_t *chip)
1418 {
1419         snd_timer_t *timer;
1420         snd_timer_id_t tid;
1421         int err;
1422
1423         /* Timer initialization */
1424         tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1425         tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1426         tid.card = chip->card->number;
1427         tid.device = 0;
1428         tid.subdevice = 0;
1429         if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1430                 return err;
1431         strcpy(timer->name, "CS4231");
1432         timer->private_data = chip;
1433         timer->private_free = snd_cs4231_timer_free;
1434         timer->hw = snd_cs4231_timer_table;
1435         chip->timer = timer;
1436
1437         return 0;
1438 }
1439         
1440 /*
1441  *  MIXER part
1442  */
1443
1444 static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1445 {
1446         static char *texts[4] = {
1447                 "Line", "CD", "Mic", "Mix"
1448         };
1449         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1450
1451         snd_assert(chip->card != NULL, return -EINVAL);
1452         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1453         uinfo->count = 2;
1454         uinfo->value.enumerated.items = 4;
1455         if (uinfo->value.enumerated.item > 3)
1456                 uinfo->value.enumerated.item = 3;
1457         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1458
1459         return 0;
1460 }
1461
1462 static int snd_cs4231_get_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1463 {
1464         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1465         unsigned long flags;
1466         
1467         spin_lock_irqsave(&chip->lock, flags);
1468         ucontrol->value.enumerated.item[0] =
1469                 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
1470         ucontrol->value.enumerated.item[1] =
1471                 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
1472         spin_unlock_irqrestore(&chip->lock, flags);
1473
1474         return 0;
1475 }
1476
1477 static int snd_cs4231_put_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1478 {
1479         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1480         unsigned long flags;
1481         unsigned short left, right;
1482         int change;
1483         
1484         if (ucontrol->value.enumerated.item[0] > 3 ||
1485             ucontrol->value.enumerated.item[1] > 3)
1486                 return -EINVAL;
1487         left = ucontrol->value.enumerated.item[0] << 6;
1488         right = ucontrol->value.enumerated.item[1] << 6;
1489
1490         spin_lock_irqsave(&chip->lock, flags);
1491
1492         left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
1493         right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
1494         change = left != chip->image[CS4231_LEFT_INPUT] ||
1495                  right != chip->image[CS4231_RIGHT_INPUT];
1496         snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
1497         snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
1498
1499         spin_unlock_irqrestore(&chip->lock, flags);
1500
1501         return change;
1502 }
1503
1504 int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1505 {
1506         int mask = (kcontrol->private_value >> 16) & 0xff;
1507
1508         uinfo->type = (mask == 1) ?
1509                 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1510         uinfo->count = 1;
1511         uinfo->value.integer.min = 0;
1512         uinfo->value.integer.max = mask;
1513
1514         return 0;
1515 }
1516
1517 int snd_cs4231_get_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1518 {
1519         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1520         unsigned long flags;
1521         int reg = kcontrol->private_value & 0xff;
1522         int shift = (kcontrol->private_value >> 8) & 0xff;
1523         int mask = (kcontrol->private_value >> 16) & 0xff;
1524         int invert = (kcontrol->private_value >> 24) & 0xff;
1525         
1526         spin_lock_irqsave(&chip->lock, flags);
1527
1528         ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
1529
1530         spin_unlock_irqrestore(&chip->lock, flags);
1531
1532         if (invert)
1533                 ucontrol->value.integer.value[0] =
1534                         (mask - ucontrol->value.integer.value[0]);
1535
1536         return 0;
1537 }
1538
1539 int snd_cs4231_put_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1540 {
1541         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1542         unsigned long flags;
1543         int reg = kcontrol->private_value & 0xff;
1544         int shift = (kcontrol->private_value >> 8) & 0xff;
1545         int mask = (kcontrol->private_value >> 16) & 0xff;
1546         int invert = (kcontrol->private_value >> 24) & 0xff;
1547         int change;
1548         unsigned short val;
1549         
1550         val = (ucontrol->value.integer.value[0] & mask);
1551         if (invert)
1552                 val = mask - val;
1553         val <<= shift;
1554
1555         spin_lock_irqsave(&chip->lock, flags);
1556
1557         val = (chip->image[reg] & ~(mask << shift)) | val;
1558         change = val != chip->image[reg];
1559         snd_cs4231_out(chip, reg, val);
1560
1561         spin_unlock_irqrestore(&chip->lock, flags);
1562
1563         return change;
1564 }
1565
1566 int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1567 {
1568         int mask = (kcontrol->private_value >> 24) & 0xff;
1569
1570         uinfo->type = mask == 1 ?
1571                 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1572         uinfo->count = 2;
1573         uinfo->value.integer.min = 0;
1574         uinfo->value.integer.max = mask;
1575
1576         return 0;
1577 }
1578
1579 int snd_cs4231_get_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1580 {
1581         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1582         unsigned long flags;
1583         int left_reg = kcontrol->private_value & 0xff;
1584         int right_reg = (kcontrol->private_value >> 8) & 0xff;
1585         int shift_left = (kcontrol->private_value >> 16) & 0x07;
1586         int shift_right = (kcontrol->private_value >> 19) & 0x07;
1587         int mask = (kcontrol->private_value >> 24) & 0xff;
1588         int invert = (kcontrol->private_value >> 22) & 1;
1589         
1590         spin_lock_irqsave(&chip->lock, flags);
1591
1592         ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
1593         ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
1594
1595         spin_unlock_irqrestore(&chip->lock, flags);
1596
1597         if (invert) {
1598                 ucontrol->value.integer.value[0] =
1599                         (mask - ucontrol->value.integer.value[0]);
1600                 ucontrol->value.integer.value[1] =
1601                         (mask - ucontrol->value.integer.value[1]);
1602         }
1603
1604         return 0;
1605 }
1606
1607 int snd_cs4231_put_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1608 {
1609         cs4231_t *chip = snd_kcontrol_chip(kcontrol);
1610         unsigned long flags;
1611         int left_reg = kcontrol->private_value & 0xff;
1612         int right_reg = (kcontrol->private_value >> 8) & 0xff;
1613         int shift_left = (kcontrol->private_value >> 16) & 0x07;
1614         int shift_right = (kcontrol->private_value >> 19) & 0x07;
1615         int mask = (kcontrol->private_value >> 24) & 0xff;
1616         int invert = (kcontrol->private_value >> 22) & 1;
1617         int change;
1618         unsigned short val1, val2;
1619         
1620         val1 = ucontrol->value.integer.value[0] & mask;
1621         val2 = ucontrol->value.integer.value[1] & mask;
1622         if (invert) {
1623                 val1 = mask - val1;
1624                 val2 = mask - val2;
1625         }
1626         val1 <<= shift_left;
1627         val2 <<= shift_right;
1628
1629         spin_lock_irqsave(&chip->lock, flags);
1630
1631         val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
1632         val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
1633         change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
1634         snd_cs4231_out(chip, left_reg, val1);
1635         snd_cs4231_out(chip, right_reg, val2);
1636
1637         spin_unlock_irqrestore(&chip->lock, flags);
1638
1639         return change;
1640 }
1641
1642 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
1643 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1644   .info = snd_cs4231_info_single, \
1645   .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
1646   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
1647
1648 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
1649 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1650   .info = snd_cs4231_info_double, \
1651   .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
1652   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
1653
1654 static snd_kcontrol_new_t snd_cs4231_controls[] = {
1655 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
1656 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
1657 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
1658 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
1659 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
1660 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
1661 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
1662 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
1663 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
1664 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
1665 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
1666 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
1667 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
1668 {
1669         .iface  = SNDRV_CTL_ELEM_IFACE_MIXER,
1670         .name   = "Capture Source",
1671         .info   = snd_cs4231_info_mux,
1672         .get    = snd_cs4231_get_mux,
1673         .put    = snd_cs4231_put_mux,
1674 },
1675 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
1676 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
1677 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
1678 /* SPARC specific uses of XCTL{0,1} general purpose outputs.  */
1679 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
1680 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
1681 };
1682                                         
1683 int snd_cs4231_mixer(cs4231_t *chip)
1684 {
1685         snd_card_t *card;
1686         int err, idx;
1687
1688         snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
1689
1690         card = chip->card;
1691
1692         strcpy(card->mixername, chip->pcm->name);
1693
1694         for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
1695                 if ((err = snd_ctl_add(card,
1696                                        snd_ctl_new1(&snd_cs4231_controls[idx],
1697                                                     chip))) < 0)
1698                         return err;
1699         }
1700         return 0;
1701 }
1702
1703 static int dev;
1704
1705 static int cs4231_attach_begin(snd_card_t **rcard)
1706 {
1707         snd_card_t *card;
1708
1709         *rcard = NULL;
1710
1711         if (dev >= SNDRV_CARDS)
1712                 return -ENODEV;
1713
1714         if (!enable[dev]) {
1715                 dev++;
1716                 return -ENOENT;
1717         }
1718
1719         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1720         if (card == NULL)
1721                 return -ENOMEM;
1722
1723         strcpy(card->driver, "CS4231");
1724         strcpy(card->shortname, "Sun CS4231");
1725
1726         *rcard = card;
1727         return 0;
1728 }
1729
1730 static int cs4231_attach_finish(snd_card_t *card, cs4231_t *chip)
1731 {
1732         int err;
1733
1734         if ((err = snd_cs4231_pcm(chip)) < 0)
1735                 goto out_err;
1736
1737         if ((err = snd_cs4231_mixer(chip)) < 0)
1738                 goto out_err;
1739
1740         if ((err = snd_cs4231_timer(chip)) < 0)
1741                 goto out_err;
1742
1743         if ((err = snd_card_set_generic_dev(card)) < 0)
1744                 goto out_err;
1745
1746         if ((err = snd_card_register(card)) < 0)
1747                 goto out_err;
1748
1749         chip->next = cs4231_list;
1750         cs4231_list = chip;
1751
1752         dev++;
1753         return 0;
1754
1755 out_err:
1756         snd_card_free(card);
1757         return err;
1758 }
1759
1760 #ifdef SBUS_SUPPORT
1761
1762 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1763 {
1764         unsigned long flags;
1765         unsigned char status;
1766         u32 csr;
1767         cs4231_t *chip = dev_id;
1768
1769         /*This is IRQ is not raised by the cs4231*/
1770         if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
1771                 return IRQ_NONE;
1772
1773         /* ACK the APC interrupt. */
1774         csr = sbus_readl(chip->port + APCCSR);
1775
1776         sbus_writel(csr, chip->port + APCCSR);
1777
1778         if ((csr & APC_PDMA_READY) && 
1779             (csr & APC_PLAY_INT) &&
1780             (csr & APC_XINT_PNVA) &&
1781             !(csr & APC_XINT_EMPT))
1782                         snd_cs4231_play_callback(chip);
1783
1784         if ((csr & APC_CDMA_READY) && 
1785             (csr & APC_CAPT_INT) &&
1786             (csr & APC_XINT_CNVA) &&
1787             !(csr & APC_XINT_EMPT))
1788                         snd_cs4231_capture_callback(chip);
1789         
1790         status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
1791
1792         if (status & CS4231_TIMER_IRQ) {
1793                 if (chip->timer)
1794                         snd_timer_interrupt(chip->timer, chip->timer->sticks);
1795         }               
1796
1797         if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
1798                 snd_cs4231_overrange(chip);
1799
1800         /* ACK the CS4231 interrupt. */
1801         spin_lock_irqsave(&chip->lock, flags);
1802         snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
1803         spin_unlock_irqrestore(&chip->lock, flags);
1804
1805         return 0;
1806 }
1807
1808 /*
1809  * SBUS DMA routines
1810  */
1811
1812 int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
1813 {
1814         unsigned long flags;
1815         u32 test, csr;
1816         int err;
1817         sbus_dma_info_t *base = &dma_cont->sbus_info;
1818         
1819         if (len >= (1 << 24))
1820                 return -EINVAL;
1821         spin_lock_irqsave(&base->lock, flags);
1822         csr = sbus_readl(base->regs + APCCSR);
1823         err = -EINVAL;
1824         test = APC_CDMA_READY;
1825         if ( base->dir == APC_PLAY )
1826                 test = APC_PDMA_READY;
1827         if (!(csr & test))
1828                 goto out;
1829         err = -EBUSY;
1830         csr = sbus_readl(base->regs + APCCSR);
1831         test = APC_XINT_CNVA;
1832         if ( base->dir == APC_PLAY )
1833                 test = APC_XINT_PNVA;
1834         if (!(csr & test))
1835                 goto out;
1836         err = 0;
1837         sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
1838         sbus_writel(len, base->regs + base->dir + APCNC);
1839 out:
1840         spin_unlock_irqrestore(&base->lock, flags);
1841         return err;
1842 }
1843
1844 void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
1845 {
1846         unsigned long flags;
1847         u32 csr, test;
1848         sbus_dma_info_t *base = &dma_cont->sbus_info;
1849
1850         spin_lock_irqsave(&base->lock, flags);
1851         csr = sbus_readl(base->regs + APCCSR);
1852         test =  APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
1853                 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
1854                  APC_XINT_PENA;
1855         if ( base->dir == APC_RECORD )
1856                 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
1857                         APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
1858         csr |= test;
1859         sbus_writel(csr, base->regs + APCCSR);
1860         spin_unlock_irqrestore(&base->lock, flags);
1861 }
1862
1863 void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
1864 {
1865         unsigned long flags;
1866         u32 csr, shift;
1867         sbus_dma_info_t *base = &dma_cont->sbus_info;
1868
1869         spin_lock_irqsave(&base->lock, flags);
1870         if (!on) {
1871                 if (base->dir == APC_PLAY) { 
1872                         sbus_writel(0, base->regs + base->dir + APCNVA); 
1873                         sbus_writel(1, base->regs + base->dir + APCC); 
1874                 }
1875                 else
1876                 {
1877                         sbus_writel(0, base->regs + base->dir + APCNC); 
1878                         sbus_writel(0, base->regs + base->dir + APCVA); 
1879                 } 
1880         } 
1881         udelay(600); 
1882         csr = sbus_readl(base->regs + APCCSR);
1883         shift = 0;
1884         if ( base->dir == APC_PLAY )
1885                 shift = 1;
1886         if (on)
1887                 csr &= ~(APC_CPAUSE << shift);
1888         else
1889                 csr |= (APC_CPAUSE << shift); 
1890         sbus_writel(csr, base->regs + APCCSR);
1891         if (on)
1892                 csr |= (APC_CDMA_READY << shift);
1893         else
1894                 csr &= ~(APC_CDMA_READY << shift);
1895         sbus_writel(csr, base->regs + APCCSR);
1896         
1897         spin_unlock_irqrestore(&base->lock, flags);
1898 }
1899
1900 unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
1901 {
1902         sbus_dma_info_t *base = &dma_cont->sbus_info;
1903
1904         return sbus_readl(base->regs + base->dir + APCVA);
1905 }
1906
1907 void sbus_dma_reset(cs4231_t *chip)
1908 {
1909         sbus_writel(APC_CHIP_RESET, chip->port + APCCSR);
1910         sbus_writel(0x00, chip->port + APCCSR);
1911         sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET,
1912                     chip->port + APCCSR);
1913   
1914         udelay(20);
1915   
1916         sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET,
1917                     chip->port + APCCSR);
1918         sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA |
1919                        APC_XINT_PENA |
1920                        APC_XINT_CENA),
1921                        chip->port + APCCSR);
1922 }
1923
1924 void sbus_dma_preallocate(cs4231_t *chip, snd_pcm_t *pcm)
1925 {
1926         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
1927                                               snd_dma_sbus_data(chip->dev_u.sdev),
1928                                               64*1024, 128*1024);
1929 }
1930
1931 /*
1932  * Init and exit routines
1933  */
1934
1935 static int snd_cs4231_sbus_free(cs4231_t *chip)
1936 {
1937         if (chip->irq[0])
1938                 free_irq(chip->irq[0], chip);
1939
1940         if (chip->port)
1941                 sbus_iounmap(chip->port, chip->regs_size);
1942
1943         if (chip->timer)
1944                 snd_device_free(chip->card, chip->timer);
1945
1946         kfree(chip);
1947
1948         return 0;
1949 }
1950
1951 static int snd_cs4231_sbus_dev_free(snd_device_t *device)
1952 {
1953         cs4231_t *cp = device->device_data;
1954
1955         return snd_cs4231_sbus_free(cp);
1956 }
1957
1958 static snd_device_ops_t snd_cs4231_sbus_dev_ops = {
1959         .dev_free       =       snd_cs4231_sbus_dev_free,
1960 };
1961
1962 static int __init snd_cs4231_sbus_create(snd_card_t *card,
1963                                          struct sbus_dev *sdev,
1964                                          int dev,
1965                                          cs4231_t **rchip)
1966 {
1967         cs4231_t *chip;
1968         int err;
1969
1970         *rchip = NULL;
1971         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1972         if (chip == NULL)
1973                 return -ENOMEM;
1974
1975         spin_lock_init(&chip->lock);
1976         spin_lock_init(&chip->c_dma.sbus_info.lock);
1977         spin_lock_init(&chip->p_dma.sbus_info.lock);
1978         init_MUTEX(&chip->mce_mutex);
1979         init_MUTEX(&chip->open_mutex);
1980         chip->card = card;
1981         chip->dev_u.sdev = sdev;
1982         chip->regs_size = sdev->reg_addrs[0].reg_size;
1983         memcpy(&chip->image, &snd_cs4231_original_image,
1984                sizeof(snd_cs4231_original_image));
1985
1986         chip->port = sbus_ioremap(&sdev->resource[0], 0,
1987                                   chip->regs_size, "cs4231");
1988         if (!chip->port) {
1989                 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
1990                 return -EIO;
1991         }
1992
1993         chip->c_dma.sbus_info.regs = chip->port;
1994         chip->p_dma.sbus_info.regs = chip->port;
1995         chip->c_dma.sbus_info.dir = APC_RECORD;
1996         chip->p_dma.sbus_info.dir = APC_PLAY;
1997
1998         chip->p_dma.prepare = sbus_dma_prepare;
1999         chip->p_dma.enable = sbus_dma_enable;
2000         chip->p_dma.request = sbus_dma_request;
2001         chip->p_dma.address = sbus_dma_addr;
2002         chip->p_dma.reset = sbus_dma_reset;
2003         chip->p_dma.preallocate = sbus_dma_preallocate;
2004
2005         chip->c_dma.prepare = sbus_dma_prepare;
2006         chip->c_dma.enable = sbus_dma_enable;
2007         chip->c_dma.request = sbus_dma_request;
2008         chip->c_dma.address = sbus_dma_addr;
2009         chip->c_dma.reset = sbus_dma_reset;
2010         chip->c_dma.preallocate = sbus_dma_preallocate;
2011
2012         if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
2013                         SA_SHIRQ, "cs4231", chip)) {
2014                 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n",
2015                            dev,
2016                            __irq_itoa(sdev->irqs[0]));
2017                 snd_cs4231_sbus_free(chip);
2018                 return -EBUSY;
2019         }
2020         chip->irq[0] = sdev->irqs[0];
2021
2022         if (snd_cs4231_probe(chip) < 0) {
2023                 snd_cs4231_sbus_free(chip);
2024                 return -ENODEV;
2025         }
2026         snd_cs4231_init(chip);
2027
2028         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2029                                   chip, &snd_cs4231_sbus_dev_ops)) < 0) {
2030                 snd_cs4231_sbus_free(chip);
2031                 return err;
2032         }
2033
2034         *rchip = chip;
2035         return 0;
2036 }
2037
2038 static int cs4231_sbus_attach(struct sbus_dev *sdev)
2039 {
2040         struct resource *rp = &sdev->resource[0];
2041         cs4231_t *cp;
2042         snd_card_t *card;
2043         int err;
2044
2045         err = cs4231_attach_begin(&card);
2046         if (err)
2047                 return err;
2048
2049         sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
2050                 card->shortname,
2051                 rp->flags & 0xffL,
2052                 rp->start,
2053                 __irq_itoa(sdev->irqs[0]));
2054
2055         if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) {
2056                 snd_card_free(card);
2057                 return err;
2058         }
2059
2060         return cs4231_attach_finish(card, cp);
2061 }
2062 #endif
2063
2064 #ifdef EBUS_SUPPORT
2065
2066 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
2067 {
2068         cs4231_t *chip = cookie;
2069         
2070         snd_cs4231_play_callback(chip);
2071 }
2072
2073 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
2074 {
2075         cs4231_t *chip = cookie;
2076
2077         snd_cs4231_capture_callback(chip);
2078 }
2079
2080 /*
2081  * EBUS DMA wrappers
2082  */
2083
2084 int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
2085 {
2086         return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
2087 }
2088
2089 void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
2090 {
2091         ebus_dma_enable(&dma_cont->ebus_info, on);
2092 }
2093
2094 void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
2095 {
2096         ebus_dma_prepare(&dma_cont->ebus_info, dir);
2097 }
2098
2099 unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
2100 {
2101         return ebus_dma_addr(&dma_cont->ebus_info);
2102 }
2103
2104 void _ebus_dma_reset(cs4231_t *chip)
2105 {
2106         return;
2107 }
2108
2109 void _ebus_dma_preallocate(cs4231_t *chip, snd_pcm_t *pcm)
2110 {
2111         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2112                                       snd_dma_pci_data(chip->dev_u.pdev),
2113                                       64*1024, 128*1024);
2114 }
2115
2116 /*
2117  * Init and exit routines
2118  */
2119
2120 static int snd_cs4231_ebus_free(cs4231_t *chip)
2121 {
2122         if (chip->c_dma.ebus_info.regs) {
2123                 ebus_dma_unregister(&chip->c_dma.ebus_info);
2124                 iounmap(chip->c_dma.ebus_info.regs);
2125         }
2126         if (chip->p_dma.ebus_info.regs) {
2127                 ebus_dma_unregister(&chip->p_dma.ebus_info);
2128                 iounmap(chip->p_dma.ebus_info.regs);
2129         }
2130
2131         if (chip->port)
2132                 iounmap(chip->port);
2133         if (chip->timer)
2134                 snd_device_free(chip->card, chip->timer);
2135
2136         kfree(chip);
2137
2138         return 0;
2139 }
2140
2141 static int snd_cs4231_ebus_dev_free(snd_device_t *device)
2142 {
2143         cs4231_t *cp = device->device_data;
2144
2145         return snd_cs4231_ebus_free(cp);
2146 }
2147
2148 static snd_device_ops_t snd_cs4231_ebus_dev_ops = {
2149         .dev_free       =       snd_cs4231_ebus_dev_free,
2150 };
2151
2152 static int __init snd_cs4231_ebus_create(snd_card_t *card,
2153                                          struct linux_ebus_device *edev,
2154                                          int dev,
2155                                          cs4231_t **rchip)
2156 {
2157         cs4231_t *chip;
2158         int err;
2159
2160         *rchip = NULL;
2161         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2162         if (chip == NULL)
2163                 return -ENOMEM;
2164
2165         spin_lock_init(&chip->lock);
2166         spin_lock_init(&chip->c_dma.ebus_info.lock);
2167         spin_lock_init(&chip->p_dma.ebus_info.lock);
2168         init_MUTEX(&chip->mce_mutex);
2169         init_MUTEX(&chip->open_mutex);
2170         chip->flags |= CS4231_FLAG_EBUS;
2171         chip->card = card;
2172         chip->dev_u.pdev = edev->bus->self;
2173         memcpy(&chip->image, &snd_cs4231_original_image,
2174                sizeof(snd_cs4231_original_image));
2175         strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
2176         chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2177         chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
2178         chip->c_dma.ebus_info.client_cookie = chip;
2179         chip->c_dma.ebus_info.irq = edev->irqs[0];
2180         strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
2181         chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
2182         chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
2183         chip->p_dma.ebus_info.client_cookie = chip;
2184         chip->p_dma.ebus_info.irq = edev->irqs[1];
2185
2186         chip->p_dma.prepare = _ebus_dma_prepare;
2187         chip->p_dma.enable = _ebus_dma_enable;
2188         chip->p_dma.request = _ebus_dma_request;
2189         chip->p_dma.address = _ebus_dma_addr;
2190         chip->p_dma.reset = _ebus_dma_reset;
2191         chip->p_dma.preallocate = _ebus_dma_preallocate;
2192
2193         chip->c_dma.prepare = _ebus_dma_prepare;
2194         chip->c_dma.enable = _ebus_dma_enable;
2195         chip->c_dma.request = _ebus_dma_request;
2196         chip->c_dma.address = _ebus_dma_addr;
2197         chip->c_dma.reset = _ebus_dma_reset;
2198         chip->c_dma.preallocate = _ebus_dma_preallocate;
2199
2200         chip->port = ioremap(edev->resource[0].start, 0x10);
2201         chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
2202         chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
2203         if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) {
2204                 snd_cs4231_ebus_free(chip);
2205                 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
2206                 return -EIO;
2207         }
2208
2209         if (ebus_dma_register(&chip->c_dma.ebus_info)) {
2210                 snd_cs4231_ebus_free(chip);
2211                 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
2212                 return -EBUSY;
2213         }
2214         if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
2215                 snd_cs4231_ebus_free(chip);
2216                 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
2217                 return -EBUSY;
2218         }
2219
2220         if (ebus_dma_register(&chip->p_dma.ebus_info)) {
2221                 snd_cs4231_ebus_free(chip);
2222                 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
2223                 return -EBUSY;
2224         }
2225         if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
2226                 snd_cs4231_ebus_free(chip);
2227                 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
2228                 return -EBUSY;
2229         }
2230
2231         if (snd_cs4231_probe(chip) < 0) {
2232                 snd_cs4231_ebus_free(chip);
2233                 return -ENODEV;
2234         }
2235         snd_cs4231_init(chip);
2236
2237         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
2238                                   chip, &snd_cs4231_ebus_dev_ops)) < 0) {
2239                 snd_cs4231_ebus_free(chip);
2240                 return err;
2241         }
2242
2243         *rchip = chip;
2244         return 0;
2245 }
2246
2247 static int cs4231_ebus_attach(struct linux_ebus_device *edev)
2248 {
2249         snd_card_t *card;
2250         cs4231_t *chip;
2251         int err;
2252
2253         err = cs4231_attach_begin(&card);
2254         if (err)
2255                 return err;
2256
2257         sprintf(card->longname, "%s at 0x%lx, irq %s",
2258                 card->shortname,
2259                 edev->resource[0].start,
2260                 __irq_itoa(edev->irqs[0]));
2261
2262         if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) {
2263                 snd_card_free(card);
2264                 return err;
2265         }
2266
2267         return cs4231_attach_finish(card, chip);
2268 }
2269 #endif
2270
2271 static int __init cs4231_init(void)
2272 {
2273 #ifdef SBUS_SUPPORT
2274         struct sbus_bus *sbus;
2275         struct sbus_dev *sdev;
2276 #endif
2277 #ifdef EBUS_SUPPORT
2278         struct linux_ebus *ebus;
2279         struct linux_ebus_device *edev;
2280 #endif
2281         int found;
2282
2283         found = 0;
2284
2285 #ifdef SBUS_SUPPORT
2286         for_all_sbusdev(sdev, sbus) {
2287                 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
2288                         if (cs4231_sbus_attach(sdev) == 0)
2289                                 found++;
2290                 }
2291         }
2292 #endif
2293 #ifdef EBUS_SUPPORT
2294         for_each_ebus(ebus) {
2295                 for_each_ebusdev(edev, ebus) {
2296                         int match = 0;
2297
2298                         if (!strcmp(edev->prom_name, "SUNW,CS4231")) {
2299                                 match = 1;
2300                         } else if (!strcmp(edev->prom_name, "audio")) {
2301                                 char compat[16];
2302
2303                                 prom_getstring(edev->prom_node, "compatible",
2304                                                compat, sizeof(compat));
2305                                 compat[15] = '\0';
2306                                 if (!strcmp(compat, "SUNW,CS4231"))
2307                                         match = 1;
2308                         }
2309
2310                         if (match &&
2311                             cs4231_ebus_attach(edev) == 0)
2312                                 found++;
2313                 }
2314         }
2315 #endif
2316
2317
2318         return (found > 0) ? 0 : -EIO;
2319 }
2320
2321 static void __exit cs4231_exit(void)
2322 {
2323         cs4231_t *p = cs4231_list;
2324
2325         while (p != NULL) {
2326                 cs4231_t *next = p->next;
2327
2328                 snd_card_free(p->card);
2329
2330                 p = next;
2331         }
2332
2333         cs4231_list = NULL;
2334 }
2335
2336 module_init(cs4231_init);
2337 module_exit(cs4231_exit);