[ALSA] Add snd_card_set_generic_dev() call
[linux-2.6.git] / sound / sparc / amd7930.c
1 /*
2  * Driver for AMD7930 sound chips found on Sparcs.
3  * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4  *
5  * Based entirely upon drivers/sbus/audio/amd7930.c which is:
6  * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
7  *
8  * --- Notes from Thomas's original driver ---
9  * This is the lowlevel driver for the AMD7930 audio chip found on all
10  * sun4c machines and some sun4m machines.
11  *
12  * The amd7930 is actually an ISDN chip which has a very simple
13  * integrated audio encoder/decoder. When Sun decided on what chip to
14  * use for audio, they had the brilliant idea of using the amd7930 and
15  * only connecting the audio encoder/decoder pins.
16  *
17  * Thanks to the AMD engineer who was able to get us the AMD79C30
18  * databook which has all the programming information and gain tables.
19  *
20  * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
21  * SparcStation 1+.  The chip provides microphone and speaker interfaces
22  * which provide mono-channel audio at 8K samples per second via either
23  * 8-bit A-law or 8-bit mu-law encoding.  Also, the chip features an
24  * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
25  * which performs basic D channel LAPD processing and provides raw
26  * B channel data.  The digital audio channel, the two ISDN B channels,
27  * and two 64 Kbps channels to the microprocessor are all interconnected
28  * via a multiplexer.
29  * --- End of notes from Thoamas's original driver ---
30  */
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/moduleparam.h>
38
39 #include <sound/driver.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/info.h>
43 #include <sound/control.h>
44 #include <sound/initval.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48 #include <asm/sbus.h>
49
50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
51 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
52 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
53
54 module_param_array(index, int, NULL, 0444);
55 MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
56 module_param_array(id, charp, NULL, 0444);
57 MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
58 module_param_array(enable, bool, NULL, 0444);
59 MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
60 MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
61 MODULE_DESCRIPTION("Sun AMD7930");
62 MODULE_LICENSE("GPL");
63 MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
64
65 /* Device register layout.  */
66
67 /* Register interface presented to the CPU by the amd7930. */
68 #define AMD7930_CR      0x00UL          /* Command Register (W) */
69 #define AMD7930_IR      AMD7930_CR      /* Interrupt Register (R) */
70 #define AMD7930_DR      0x01UL          /* Data Register (R/W) */
71 #define AMD7930_DSR1    0x02UL          /* D-channel Status Register 1 (R) */
72 #define AMD7930_DER     0x03UL          /* D-channel Error Register (R) */
73 #define AMD7930_DCTB    0x04UL          /* D-channel Transmit Buffer (W) */
74 #define AMD7930_DCRB    AMD7930_DCTB    /* D-channel Receive Buffer (R) */
75 #define AMD7930_BBTB    0x05UL          /* Bb-channel Transmit Buffer (W) */
76 #define AMD7930_BBRB    AMD7930_BBTB    /* Bb-channel Receive Buffer (R) */
77 #define AMD7930_BCTB    0x06UL          /* Bc-channel Transmit Buffer (W) */
78 #define AMD7930_BCRB    AMD7930_BCTB    /* Bc-channel Receive Buffer (R) */
79 #define AMD7930_DSR2    0x07UL          /* D-channel Status Register 2 (R) */
80
81 /* Indirect registers in the Main Audio Processor. */
82 struct amd7930_map {
83         __u16   x[8];
84         __u16   r[8];
85         __u16   gx;
86         __u16   gr;
87         __u16   ger;
88         __u16   stgr;
89         __u16   ftgr;
90         __u16   atgr;
91         __u8    mmr1;
92         __u8    mmr2;
93 };
94
95 /* After an amd7930 interrupt, reading the Interrupt Register (ir)
96  * clears the interrupt and returns a bitmask indicating which
97  * interrupt source(s) require service.
98  */
99
100 #define AMR_IR_DTTHRSH                  0x01 /* D-channel xmit threshold */
101 #define AMR_IR_DRTHRSH                  0x02 /* D-channel recv threshold */
102 #define AMR_IR_DSRI                     0x04 /* D-channel packet status */
103 #define AMR_IR_DERI                     0x08 /* D-channel error */
104 #define AMR_IR_BBUF                     0x10 /* B-channel data xfer */
105 #define AMR_IR_LSRI                     0x20 /* LIU status */
106 #define AMR_IR_DSR2I                    0x40 /* D-channel buffer status */
107 #define AMR_IR_MLTFRMI                  0x80 /* multiframe or PP */
108
109 /* The amd7930 has "indirect registers" which are accessed by writing
110  * the register number into the Command Register and then reading or
111  * writing values from the Data Register as appropriate. We define the
112  * AMR_* macros to be the indirect register numbers and AM_* macros to
113  * be bits in whatever register is referred to.
114  */
115
116 /* Initialization */
117 #define AMR_INIT                        0x21
118 #define         AM_INIT_ACTIVE                  0x01
119 #define         AM_INIT_DATAONLY                0x02
120 #define         AM_INIT_POWERDOWN               0x03
121 #define         AM_INIT_DISABLE_INTS            0x04
122 #define AMR_INIT2                       0x20
123 #define         AM_INIT2_ENABLE_POWERDOWN       0x20
124 #define         AM_INIT2_ENABLE_MULTIFRAME      0x10
125
126 /* Line Interface Unit */
127 #define AMR_LIU_LSR                     0xA1
128 #define         AM_LIU_LSR_STATE                0x07
129 #define         AM_LIU_LSR_F3                   0x08
130 #define         AM_LIU_LSR_F7                   0x10
131 #define         AM_LIU_LSR_F8                   0x20
132 #define         AM_LIU_LSR_HSW                  0x40
133 #define         AM_LIU_LSR_HSW_CHG              0x80
134 #define AMR_LIU_LPR                     0xA2
135 #define AMR_LIU_LMR1                    0xA3
136 #define         AM_LIU_LMR1_B1_ENABL            0x01
137 #define         AM_LIU_LMR1_B2_ENABL            0x02
138 #define         AM_LIU_LMR1_F_DISABL            0x04
139 #define         AM_LIU_LMR1_FA_DISABL           0x08
140 #define         AM_LIU_LMR1_REQ_ACTIV           0x10
141 #define         AM_LIU_LMR1_F8_F3               0x20
142 #define         AM_LIU_LMR1_LIU_ENABL           0x40
143 #define AMR_LIU_LMR2                    0xA4
144 #define         AM_LIU_LMR2_DECHO               0x01
145 #define         AM_LIU_LMR2_DLOOP               0x02
146 #define         AM_LIU_LMR2_DBACKOFF            0x04
147 #define         AM_LIU_LMR2_EN_F3_INT           0x08
148 #define         AM_LIU_LMR2_EN_F8_INT           0x10
149 #define         AM_LIU_LMR2_EN_HSW_INT          0x20
150 #define         AM_LIU_LMR2_EN_F7_INT           0x40
151 #define AMR_LIU_2_4                     0xA5
152 #define AMR_LIU_MF                      0xA6
153 #define AMR_LIU_MFSB                    0xA7
154 #define AMR_LIU_MFQB                    0xA8
155
156 /* Multiplexor */
157 #define AMR_MUX_MCR1                    0x41
158 #define AMR_MUX_MCR2                    0x42
159 #define AMR_MUX_MCR3                    0x43
160 #define         AM_MUX_CHANNEL_B1               0x01
161 #define         AM_MUX_CHANNEL_B2               0x02
162 #define         AM_MUX_CHANNEL_Ba               0x03
163 #define         AM_MUX_CHANNEL_Bb               0x04
164 #define         AM_MUX_CHANNEL_Bc               0x05
165 #define         AM_MUX_CHANNEL_Bd               0x06
166 #define         AM_MUX_CHANNEL_Be               0x07
167 #define         AM_MUX_CHANNEL_Bf               0x08
168 #define AMR_MUX_MCR4                    0x44
169 #define         AM_MUX_MCR4_ENABLE_INTS         0x08
170 #define         AM_MUX_MCR4_REVERSE_Bb          0x10
171 #define         AM_MUX_MCR4_REVERSE_Bc          0x20
172 #define AMR_MUX_1_4                     0x45
173
174 /* Main Audio Processor */
175 #define AMR_MAP_X                       0x61
176 #define AMR_MAP_R                       0x62
177 #define AMR_MAP_GX                      0x63
178 #define AMR_MAP_GR                      0x64
179 #define AMR_MAP_GER                     0x65
180 #define AMR_MAP_STGR                    0x66
181 #define AMR_MAP_FTGR_1_2                0x67
182 #define AMR_MAP_ATGR_1_2                0x68
183 #define AMR_MAP_MMR1                    0x69
184 #define         AM_MAP_MMR1_ALAW                0x01
185 #define         AM_MAP_MMR1_GX                  0x02
186 #define         AM_MAP_MMR1_GR                  0x04
187 #define         AM_MAP_MMR1_GER                 0x08
188 #define         AM_MAP_MMR1_X                   0x10
189 #define         AM_MAP_MMR1_R                   0x20
190 #define         AM_MAP_MMR1_STG                 0x40
191 #define         AM_MAP_MMR1_LOOPBACK            0x80
192 #define AMR_MAP_MMR2                    0x6A
193 #define         AM_MAP_MMR2_AINB                0x01
194 #define         AM_MAP_MMR2_LS                  0x02
195 #define         AM_MAP_MMR2_ENABLE_DTMF         0x04
196 #define         AM_MAP_MMR2_ENABLE_TONEGEN      0x08
197 #define         AM_MAP_MMR2_ENABLE_TONERING     0x10
198 #define         AM_MAP_MMR2_DISABLE_HIGHPASS    0x20
199 #define         AM_MAP_MMR2_DISABLE_AUTOZERO    0x40
200 #define AMR_MAP_1_10                    0x6B
201 #define AMR_MAP_MMR3                    0x6C
202 #define AMR_MAP_STRA                    0x6D
203 #define AMR_MAP_STRF                    0x6E
204 #define AMR_MAP_PEAKX                   0x70
205 #define AMR_MAP_PEAKR                   0x71
206 #define AMR_MAP_15_16                   0x72
207
208 /* Data Link Controller */
209 #define AMR_DLC_FRAR_1_2_3              0x81
210 #define AMR_DLC_SRAR_1_2_3              0x82
211 #define AMR_DLC_TAR                     0x83
212 #define AMR_DLC_DRLR                    0x84
213 #define AMR_DLC_DTCR                    0x85
214 #define AMR_DLC_DMR1                    0x86
215 #define         AMR_DLC_DMR1_DTTHRSH_INT        0x01
216 #define         AMR_DLC_DMR1_DRTHRSH_INT        0x02
217 #define         AMR_DLC_DMR1_TAR_ENABL          0x04
218 #define         AMR_DLC_DMR1_EORP_INT           0x08
219 #define         AMR_DLC_DMR1_EN_ADDR1           0x10
220 #define         AMR_DLC_DMR1_EN_ADDR2           0x20
221 #define         AMR_DLC_DMR1_EN_ADDR3           0x40
222 #define         AMR_DLC_DMR1_EN_ADDR4           0x80
223 #define         AMR_DLC_DMR1_EN_ADDRS           0xf0
224 #define AMR_DLC_DMR2                    0x87
225 #define         AMR_DLC_DMR2_RABRT_INT          0x01
226 #define         AMR_DLC_DMR2_RESID_INT          0x02
227 #define         AMR_DLC_DMR2_COLL_INT           0x04
228 #define         AMR_DLC_DMR2_FCS_INT            0x08
229 #define         AMR_DLC_DMR2_OVFL_INT           0x10
230 #define         AMR_DLC_DMR2_UNFL_INT           0x20
231 #define         AMR_DLC_DMR2_OVRN_INT           0x40
232 #define         AMR_DLC_DMR2_UNRN_INT           0x80
233 #define AMR_DLC_1_7                     0x88
234 #define AMR_DLC_DRCR                    0x89
235 #define AMR_DLC_RNGR1                   0x8A
236 #define AMR_DLC_RNGR2                   0x8B
237 #define AMR_DLC_FRAR4                   0x8C
238 #define AMR_DLC_SRAR4                   0x8D
239 #define AMR_DLC_DMR3                    0x8E
240 #define         AMR_DLC_DMR3_VA_INT             0x01
241 #define         AMR_DLC_DMR3_EOTP_INT           0x02
242 #define         AMR_DLC_DMR3_LBRP_INT           0x04
243 #define         AMR_DLC_DMR3_RBA_INT            0x08
244 #define         AMR_DLC_DMR3_LBT_INT            0x10
245 #define         AMR_DLC_DMR3_TBE_INT            0x20
246 #define         AMR_DLC_DMR3_RPLOST_INT         0x40
247 #define         AMR_DLC_DMR3_KEEP_FCS           0x80
248 #define AMR_DLC_DMR4                    0x8F
249 #define         AMR_DLC_DMR4_RCV_1              0x00
250 #define         AMR_DLC_DMR4_RCV_2              0x01
251 #define         AMR_DLC_DMR4_RCV_4              0x02
252 #define         AMR_DLC_DMR4_RCV_8              0x03
253 #define         AMR_DLC_DMR4_RCV_16             0x01
254 #define         AMR_DLC_DMR4_RCV_24             0x02
255 #define         AMR_DLC_DMR4_RCV_30             0x03
256 #define         AMR_DLC_DMR4_XMT_1              0x00
257 #define         AMR_DLC_DMR4_XMT_2              0x04
258 #define         AMR_DLC_DMR4_XMT_4              0x08
259 #define         AMR_DLC_DMR4_XMT_8              0x0c
260 #define         AMR_DLC_DMR4_XMT_10             0x08
261 #define         AMR_DLC_DMR4_XMT_14             0x0c
262 #define         AMR_DLC_DMR4_IDLE_MARK          0x00
263 #define         AMR_DLC_DMR4_IDLE_FLAG          0x10
264 #define         AMR_DLC_DMR4_ADDR_BOTH          0x00
265 #define         AMR_DLC_DMR4_ADDR_1ST           0x20
266 #define         AMR_DLC_DMR4_ADDR_2ND           0xa0
267 #define         AMR_DLC_DMR4_CR_ENABLE          0x40
268 #define AMR_DLC_12_15                   0x90
269 #define AMR_DLC_ASR                     0x91
270 #define AMR_DLC_EFCR                    0x92
271 #define         AMR_DLC_EFCR_EXTEND_FIFO        0x01
272 #define         AMR_DLC_EFCR_SEC_PKT_INT        0x02
273
274 #define AMR_DSR1_VADDR                  0x01
275 #define AMR_DSR1_EORP                   0x02
276 #define AMR_DSR1_PKT_IP                 0x04
277 #define AMR_DSR1_DECHO_ON               0x08
278 #define AMR_DSR1_DLOOP_ON               0x10
279 #define AMR_DSR1_DBACK_OFF              0x20
280 #define AMR_DSR1_EOTP                   0x40
281 #define AMR_DSR1_CXMT_ABRT              0x80
282
283 #define AMR_DSR2_LBRP                   0x01
284 #define AMR_DSR2_RBA                    0x02
285 #define AMR_DSR2_RPLOST                 0x04
286 #define AMR_DSR2_LAST_BYTE              0x08
287 #define AMR_DSR2_TBE                    0x10
288 #define AMR_DSR2_MARK_IDLE              0x20
289 #define AMR_DSR2_FLAG_IDLE              0x40
290 #define AMR_DSR2_SECOND_PKT             0x80
291
292 #define AMR_DER_RABRT                   0x01
293 #define AMR_DER_RFRAME                  0x02
294 #define AMR_DER_COLLISION               0x04
295 #define AMR_DER_FCS                     0x08
296 #define AMR_DER_OVFL                    0x10
297 #define AMR_DER_UNFL                    0x20
298 #define AMR_DER_OVRN                    0x40
299 #define AMR_DER_UNRN                    0x80
300
301 /* Peripheral Port */
302 #define AMR_PP_PPCR1                    0xC0
303 #define AMR_PP_PPSR                     0xC1
304 #define AMR_PP_PPIER                    0xC2
305 #define AMR_PP_MTDR                     0xC3
306 #define AMR_PP_MRDR                     0xC3
307 #define AMR_PP_CITDR0                   0xC4
308 #define AMR_PP_CIRDR0                   0xC4
309 #define AMR_PP_CITDR1                   0xC5
310 #define AMR_PP_CIRDR1                   0xC5
311 #define AMR_PP_PPCR2                    0xC8
312 #define AMR_PP_PPCR3                    0xC9
313
314 typedef struct snd_amd7930 {
315         spinlock_t              lock;
316         void __iomem            *regs;
317         u32                     flags;
318 #define AMD7930_FLAG_PLAYBACK   0x00000001
319 #define AMD7930_FLAG_CAPTURE    0x00000002
320
321         struct amd7930_map      map;
322
323         snd_card_t              *card;
324         snd_pcm_t               *pcm;
325         snd_pcm_substream_t     *playback_substream;
326         snd_pcm_substream_t     *capture_substream;
327
328         /* Playback/Capture buffer state. */
329         unsigned char           *p_orig, *p_cur;
330         int                     p_left;
331         unsigned char           *c_orig, *c_cur;
332         int                     c_left;
333
334         int                     rgain;
335         int                     pgain;
336         int                     mgain;
337
338         struct sbus_dev         *sdev;
339         unsigned int            irq;
340         unsigned int            regs_size;
341         struct snd_amd7930      *next;
342 } amd7930_t;
343
344 static amd7930_t *amd7930_list;
345
346 /* Idle the AMD7930 chip.  The amd->lock is not held.  */
347 static __inline__ void amd7930_idle(amd7930_t *amd)
348 {
349         unsigned long flags;
350
351         spin_lock_irqsave(&amd->lock, flags);
352         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
353         sbus_writeb(0, amd->regs + AMD7930_DR);
354         spin_unlock_irqrestore(&amd->lock, flags);
355 }
356
357 /* Enable chip interrupts.  The amd->lock is not held.  */
358 static __inline__ void amd7930_enable_ints(amd7930_t *amd)
359 {
360         unsigned long flags;
361
362         spin_lock_irqsave(&amd->lock, flags);
363         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
364         sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
365         spin_unlock_irqrestore(&amd->lock, flags);
366 }
367
368 /* Disable chip interrupts.  The amd->lock is not held.  */
369 static __inline__ void amd7930_disable_ints(amd7930_t *amd)
370 {
371         unsigned long flags;
372
373         spin_lock_irqsave(&amd->lock, flags);
374         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
375         sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
376         spin_unlock_irqrestore(&amd->lock, flags);
377 }
378
379 /* Commit amd7930_map settings to the hardware.
380  * The amd->lock is held and local interrupts are disabled.
381  */
382 static void __amd7930_write_map(amd7930_t *amd)
383 {
384         struct amd7930_map *map = &amd->map;
385
386         sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
387         sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
388         sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
389
390         sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
391         sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
392         sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
393
394         sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
395         sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
396         sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
397
398         sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
399         sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
400         sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
401
402         sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
403         sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
404
405         sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
406         sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
407 }
408
409 /* gx, gr & stg gains.  this table must contain 256 elements with
410  * the 0th being "infinity" (the magic value 9008).  The remaining
411  * elements match sun's gain curve (but with higher resolution):
412  * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
413  */
414 static __const__ __u16 gx_coeff[256] = {
415         0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
416         0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
417         0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
418         0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
419         0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
420         0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
421         0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
422         0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
423         0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
424         0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
425         0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
426         0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
427         0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
428         0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
429         0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
430         0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
431         0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
432         0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
433         0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
434         0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
435         0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
436         0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
437         0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
438         0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
439         0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
440         0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
441         0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
442         0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
443         0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
444         0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
445         0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
446         0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
447 };
448
449 static __const__ __u16 ger_coeff[] = {
450         0x431f, /* 5. dB */
451         0x331f, /* 5.5 dB */
452         0x40dd, /* 6. dB */
453         0x11dd, /* 6.5 dB */
454         0x440f, /* 7. dB */
455         0x411f, /* 7.5 dB */
456         0x311f, /* 8. dB */
457         0x5520, /* 8.5 dB */
458         0x10dd, /* 9. dB */
459         0x4211, /* 9.5 dB */
460         0x410f, /* 10. dB */
461         0x111f, /* 10.5 dB */
462         0x600b, /* 11. dB */
463         0x00dd, /* 11.5 dB */
464         0x4210, /* 12. dB */
465         0x110f, /* 13. dB */
466         0x7200, /* 14. dB */
467         0x2110, /* 15. dB */
468         0x2200, /* 15.9 dB */
469         0x000b, /* 16.9 dB */
470         0x000f  /* 18. dB */
471 };
472
473 /* Update amd7930_map settings and program them into the hardware.
474  * The amd->lock is held and local interrupts are disabled.
475  */
476 static void __amd7930_update_map(amd7930_t *amd)
477 {
478         struct amd7930_map *map = &amd->map;
479         int level;
480
481         map->gx = gx_coeff[amd->rgain];
482         map->stgr = gx_coeff[amd->mgain];
483         level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
484         if (level >= 256) {
485                 map->ger = ger_coeff[level - 256];
486                 map->gr = gx_coeff[255];
487         } else {
488                 map->ger = ger_coeff[0];
489                 map->gr = gx_coeff[level];
490         }
491         __amd7930_write_map(amd);
492 }
493
494 static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id, struct pt_regs *regs)
495 {
496         amd7930_t *amd = dev_id;
497         unsigned int elapsed;
498         u8 ir;
499
500         spin_lock(&amd->lock);
501
502         elapsed = 0;
503
504         ir = sbus_readb(amd->regs + AMD7930_IR);
505         if (ir & AMR_IR_BBUF) {
506                 u8 byte;
507
508                 if (amd->flags & AMD7930_FLAG_PLAYBACK) {
509                         if (amd->p_left > 0) {
510                                 byte = *(amd->p_cur++);
511                                 amd->p_left--;
512                                 sbus_writeb(byte, amd->regs + AMD7930_BBTB);
513                                 if (amd->p_left == 0)
514                                         elapsed |= AMD7930_FLAG_PLAYBACK;
515                         } else
516                                 sbus_writeb(0, amd->regs + AMD7930_BBTB);
517                 } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
518                         byte = sbus_readb(amd->regs + AMD7930_BBRB);
519                         if (amd->c_left > 0) {
520                                 *(amd->c_cur++) = byte;
521                                 amd->c_left--;
522                                 if (amd->c_left == 0)
523                                         elapsed |= AMD7930_FLAG_CAPTURE;
524                         }
525                 }
526         }
527         spin_unlock(&amd->lock);
528
529         if (elapsed & AMD7930_FLAG_PLAYBACK)
530                 snd_pcm_period_elapsed(amd->playback_substream);
531         else
532                 snd_pcm_period_elapsed(amd->capture_substream);
533
534         return IRQ_HANDLED;
535 }
536
537 static int snd_amd7930_trigger(amd7930_t *amd, unsigned int flag, int cmd)
538 {
539         unsigned long flags;
540         int result = 0;
541
542         spin_lock_irqsave(&amd->lock, flags);
543         if (cmd == SNDRV_PCM_TRIGGER_START) {
544                 if (!(amd->flags & flag)) {
545                         amd->flags |= flag;
546
547                         /* Enable B channel interrupts.  */
548                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
549                         sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
550                 }
551         } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
552                 if (amd->flags & flag) {
553                         amd->flags &= ~flag;
554
555                         /* Disable B channel interrupts.  */
556                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
557                         sbus_writeb(0, amd->regs + AMD7930_DR);
558                 }
559         } else {
560                 result = -EINVAL;
561         }
562         spin_unlock_irqrestore(&amd->lock, flags);
563
564         return result;
565 }
566
567 static int snd_amd7930_playback_trigger(snd_pcm_substream_t * substream,
568                                         int cmd)
569 {
570         amd7930_t *amd = snd_pcm_substream_chip(substream);
571         return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
572 }
573
574 static int snd_amd7930_capture_trigger(snd_pcm_substream_t * substream,
575                                        int cmd)
576 {
577         amd7930_t *amd = snd_pcm_substream_chip(substream);
578         return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
579 }
580
581 static int snd_amd7930_playback_prepare(snd_pcm_substream_t * substream)
582 {
583         amd7930_t *amd = snd_pcm_substream_chip(substream);
584         snd_pcm_runtime_t *runtime = substream->runtime;
585         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
586         unsigned long flags;
587         u8 new_mmr1;
588
589         spin_lock_irqsave(&amd->lock, flags);
590
591         amd->flags |= AMD7930_FLAG_PLAYBACK;
592
593         /* Setup the pseudo-dma transfer pointers.  */
594         amd->p_orig = amd->p_cur = runtime->dma_area;
595         amd->p_left = size;
596
597         /* Put the chip into the correct encoding format.  */
598         new_mmr1 = amd->map.mmr1;
599         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
600                 new_mmr1 |= AM_MAP_MMR1_ALAW;
601         else
602                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
603         if (new_mmr1 != amd->map.mmr1) {
604                 amd->map.mmr1 = new_mmr1;
605                 __amd7930_update_map(amd);
606         }
607
608         spin_unlock_irqrestore(&amd->lock, flags);
609
610         return 0;
611 }
612
613 static int snd_amd7930_capture_prepare(snd_pcm_substream_t * substream)
614 {
615         amd7930_t *amd = snd_pcm_substream_chip(substream);
616         snd_pcm_runtime_t *runtime = substream->runtime;
617         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
618         unsigned long flags;
619         u8 new_mmr1;
620
621         spin_lock_irqsave(&amd->lock, flags);
622
623         amd->flags |= AMD7930_FLAG_CAPTURE;
624
625         /* Setup the pseudo-dma transfer pointers.  */
626         amd->c_orig = amd->c_cur = runtime->dma_area;
627         amd->c_left = size;
628
629         /* Put the chip into the correct encoding format.  */
630         new_mmr1 = amd->map.mmr1;
631         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
632                 new_mmr1 |= AM_MAP_MMR1_ALAW;
633         else
634                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
635         if (new_mmr1 != amd->map.mmr1) {
636                 amd->map.mmr1 = new_mmr1;
637                 __amd7930_update_map(amd);
638         }
639
640         spin_unlock_irqrestore(&amd->lock, flags);
641
642         return 0;
643 }
644
645 static snd_pcm_uframes_t snd_amd7930_playback_pointer(snd_pcm_substream_t * substream)
646 {
647         amd7930_t *amd = snd_pcm_substream_chip(substream);
648         size_t ptr;
649
650         if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
651                 return 0;
652         ptr = amd->p_cur - amd->p_orig;
653         return bytes_to_frames(substream->runtime, ptr);
654 }
655
656 static snd_pcm_uframes_t snd_amd7930_capture_pointer(snd_pcm_substream_t * substream)
657 {
658         amd7930_t *amd = snd_pcm_substream_chip(substream);
659         size_t ptr;
660
661         if (!(amd->flags & AMD7930_FLAG_CAPTURE))
662                 return 0;
663
664         ptr = amd->c_cur - amd->c_orig;
665         return bytes_to_frames(substream->runtime, ptr);
666 }
667
668 /* Playback and capture have identical properties.  */
669 static snd_pcm_hardware_t snd_amd7930_pcm_hw =
670 {
671         .info                   = (SNDRV_PCM_INFO_MMAP |
672                                    SNDRV_PCM_INFO_MMAP_VALID |
673                                    SNDRV_PCM_INFO_INTERLEAVED |
674                                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
675                                    SNDRV_PCM_INFO_HALF_DUPLEX),
676         .formats                = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
677         .rates                  = SNDRV_PCM_RATE_8000,
678         .rate_min               = 8000,
679         .rate_max               = 8000,
680         .channels_min           = 1,
681         .channels_max           = 1,
682         .buffer_bytes_max       = (64*1024),
683         .period_bytes_min       = 1,
684         .period_bytes_max       = (64*1024),
685         .periods_min            = 1,
686         .periods_max            = 1024,
687 };
688
689 static int snd_amd7930_playback_open(snd_pcm_substream_t * substream)
690 {
691         amd7930_t *amd = snd_pcm_substream_chip(substream);
692         snd_pcm_runtime_t *runtime = substream->runtime;
693
694         amd->playback_substream = substream;
695         runtime->hw = snd_amd7930_pcm_hw;
696         return 0;
697 }
698
699 static int snd_amd7930_capture_open(snd_pcm_substream_t * substream)
700 {
701         amd7930_t *amd = snd_pcm_substream_chip(substream);
702         snd_pcm_runtime_t *runtime = substream->runtime;
703
704         amd->capture_substream = substream;
705         runtime->hw = snd_amd7930_pcm_hw;
706         return 0;
707 }
708
709 static int snd_amd7930_playback_close(snd_pcm_substream_t * substream)
710 {
711         amd7930_t *amd = snd_pcm_substream_chip(substream);
712
713         amd->playback_substream = NULL;
714         return 0;
715 }
716
717 static int snd_amd7930_capture_close(snd_pcm_substream_t * substream)
718 {
719         amd7930_t *amd = snd_pcm_substream_chip(substream);
720
721         amd->capture_substream = NULL;
722         return 0;
723 }
724
725 static int snd_amd7930_hw_params(snd_pcm_substream_t * substream,
726                                     snd_pcm_hw_params_t * hw_params)
727 {
728         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
729 }
730
731 static int snd_amd7930_hw_free(snd_pcm_substream_t * substream)
732 {
733         return snd_pcm_lib_free_pages(substream);
734 }
735
736 static snd_pcm_ops_t snd_amd7930_playback_ops = {
737         .open           =       snd_amd7930_playback_open,
738         .close          =       snd_amd7930_playback_close,
739         .ioctl          =       snd_pcm_lib_ioctl,
740         .hw_params      =       snd_amd7930_hw_params,
741         .hw_free        =       snd_amd7930_hw_free,
742         .prepare        =       snd_amd7930_playback_prepare,
743         .trigger        =       snd_amd7930_playback_trigger,
744         .pointer        =       snd_amd7930_playback_pointer,
745 };
746
747 static snd_pcm_ops_t snd_amd7930_capture_ops = {
748         .open           =       snd_amd7930_capture_open,
749         .close          =       snd_amd7930_capture_close,
750         .ioctl          =       snd_pcm_lib_ioctl,
751         .hw_params      =       snd_amd7930_hw_params,
752         .hw_free        =       snd_amd7930_hw_free,
753         .prepare        =       snd_amd7930_capture_prepare,
754         .trigger        =       snd_amd7930_capture_trigger,
755         .pointer        =       snd_amd7930_capture_pointer,
756 };
757
758 static void snd_amd7930_pcm_free(snd_pcm_t *pcm)
759 {
760         amd7930_t *amd = pcm->private_data;
761
762         amd->pcm = NULL;
763         snd_pcm_lib_preallocate_free_for_all(pcm);
764 }
765
766 static int __init snd_amd7930_pcm(amd7930_t *amd)
767 {
768         snd_pcm_t *pcm;
769         int err;
770
771         if ((err = snd_pcm_new(amd->card,
772                                /* ID */             "sun_amd7930",
773                                /* device */         0,
774                                /* playback count */ 1,
775                                /* capture count */  1, &pcm)) < 0)
776                 return err;
777         snd_assert(pcm != NULL, return -EINVAL);
778
779         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
780         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
781
782         pcm->private_data = amd;
783         pcm->private_free = snd_amd7930_pcm_free;
784         pcm->info_flags = 0;
785         strcpy(pcm->name, amd->card->shortname);
786         amd->pcm = pcm;
787
788         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
789                                               snd_dma_continuous_data(GFP_KERNEL),
790                                               64*1024, 64*1024);
791
792         return 0;
793 }
794
795 #define VOLUME_MONITOR  0
796 #define VOLUME_CAPTURE  1
797 #define VOLUME_PLAYBACK 2
798
799 static int snd_amd7930_info_volume(snd_kcontrol_t *kctl, snd_ctl_elem_info_t *uinfo)
800 {
801         int type = kctl->private_value;
802
803         snd_assert(type == VOLUME_MONITOR ||
804                    type == VOLUME_CAPTURE ||
805                    type == VOLUME_PLAYBACK, return -EINVAL);
806         (void) type;
807
808         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
809         uinfo->count = 1;
810         uinfo->value.integer.min = 0;
811         uinfo->value.integer.max = 255;
812
813         return 0;
814 }
815
816 static int snd_amd7930_get_volume(snd_kcontrol_t *kctl, snd_ctl_elem_value_t *ucontrol)
817 {
818         amd7930_t *amd = snd_kcontrol_chip(kctl);
819         int type = kctl->private_value;
820         int *swval;
821
822         snd_assert(type == VOLUME_MONITOR ||
823                    type == VOLUME_CAPTURE ||
824                    type == VOLUME_PLAYBACK, return -EINVAL);
825
826         switch (type) {
827         case VOLUME_MONITOR:
828                 swval = &amd->mgain;
829                 break;
830         case VOLUME_CAPTURE:
831                 swval = &amd->rgain;
832                 break;
833         case VOLUME_PLAYBACK:
834         default:
835                 swval = &amd->pgain;
836                 break;
837         };
838
839         ucontrol->value.integer.value[0] = *swval;
840
841         return 0;
842 }
843
844 static int snd_amd7930_put_volume(snd_kcontrol_t *kctl, snd_ctl_elem_value_t *ucontrol)
845 {
846         amd7930_t *amd = snd_kcontrol_chip(kctl);
847         unsigned long flags;
848         int type = kctl->private_value;
849         int *swval, change;
850
851         snd_assert(type == VOLUME_MONITOR ||
852                    type == VOLUME_CAPTURE ||
853                    type == VOLUME_PLAYBACK, return -EINVAL);
854
855         switch (type) {
856         case VOLUME_MONITOR:
857                 swval = &amd->mgain;
858                 break;
859         case VOLUME_CAPTURE:
860                 swval = &amd->rgain;
861                 break;
862         case VOLUME_PLAYBACK:
863         default:
864                 swval = &amd->pgain;
865                 break;
866         };
867
868         spin_lock_irqsave(&amd->lock, flags);
869
870         if (*swval != ucontrol->value.integer.value[0]) {
871                 *swval = ucontrol->value.integer.value[0];
872                 __amd7930_update_map(amd);
873                 change = 1;
874         } else
875                 change = 0;
876
877         spin_unlock_irqrestore(&amd->lock, flags);
878
879         return change;
880 }
881
882 static snd_kcontrol_new_t amd7930_controls[] __initdata = {
883         {
884                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
885                 .name           =       "Monitor Volume",
886                 .index          =       0,
887                 .info           =       snd_amd7930_info_volume,
888                 .get            =       snd_amd7930_get_volume,
889                 .put            =       snd_amd7930_put_volume,
890                 .private_value  =       VOLUME_MONITOR,
891         },
892         {
893                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
894                 .name           =       "Capture Volume",
895                 .index          =       0,
896                 .info           =       snd_amd7930_info_volume,
897                 .get            =       snd_amd7930_get_volume,
898                 .put            =       snd_amd7930_put_volume,
899                 .private_value  =       VOLUME_CAPTURE,
900         },
901         {
902                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
903                 .name           =       "Playback Volume",
904                 .index          =       0,
905                 .info           =       snd_amd7930_info_volume,
906                 .get            =       snd_amd7930_get_volume,
907                 .put            =       snd_amd7930_put_volume,
908                 .private_value  =       VOLUME_PLAYBACK,
909         },
910 };
911
912 static int __init snd_amd7930_mixer(amd7930_t *amd)
913 {
914         snd_card_t *card;
915         int idx, err;
916
917         snd_assert(amd != NULL && amd->card != NULL, return -EINVAL);
918
919         card = amd->card;
920         strcpy(card->mixername, card->shortname);
921
922         for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
923                 if ((err = snd_ctl_add(card,
924                                        snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
925                         return err;
926         }
927
928         return 0;
929 }
930
931 static int snd_amd7930_free(amd7930_t *amd)
932 {
933         amd7930_idle(amd);
934
935         if (amd->irq)
936                 free_irq(amd->irq, amd);
937
938         if (amd->regs)
939                 sbus_iounmap(amd->regs, amd->regs_size);
940
941         kfree(amd);
942
943         return 0;
944 }
945
946 static int snd_amd7930_dev_free(snd_device_t *device)
947 {
948         amd7930_t *amd = device->device_data;
949
950         return snd_amd7930_free(amd);
951 }
952
953 static snd_device_ops_t snd_amd7930_dev_ops = {
954         .dev_free       =       snd_amd7930_dev_free,
955 };
956
957 static int __init snd_amd7930_create(snd_card_t *card,
958                                      struct sbus_dev *sdev,
959                                      struct resource *rp,
960                                      unsigned int reg_size,
961                                      struct linux_prom_irqs *irq_prop,
962                                      int dev,
963                                      amd7930_t **ramd)
964 {
965         unsigned long flags;
966         amd7930_t *amd;
967         int err;
968
969         *ramd = NULL;
970         amd = kcalloc(1, sizeof(*amd), GFP_KERNEL);
971         if (amd == NULL)
972                 return -ENOMEM;
973
974         spin_lock_init(&amd->lock);
975         amd->card = card;
976         amd->sdev = sdev;
977         amd->regs_size = reg_size;
978
979         amd->regs = sbus_ioremap(rp, 0, amd->regs_size, "amd7930");
980         if (!amd->regs) {
981                 snd_printk("amd7930-%d: Unable to map chip registers.\n", dev);
982                 return -EIO;
983         }
984
985         amd7930_idle(amd);
986
987         if (request_irq(irq_prop->pri, snd_amd7930_interrupt,
988                         SA_INTERRUPT | SA_SHIRQ, "amd7930", amd)) {
989                 snd_printk("amd7930-%d: Unable to grab IRQ %s\n",
990                            dev,
991                            __irq_itoa(irq_prop->pri));
992                 snd_amd7930_free(amd);
993                 return -EBUSY;
994         }
995         amd->irq = irq_prop->pri;
996
997         amd7930_enable_ints(amd);
998
999         spin_lock_irqsave(&amd->lock, flags);
1000
1001         amd->rgain = 128;
1002         amd->pgain = 200;
1003         amd->mgain = 0;
1004
1005         memset(&amd->map, 0, sizeof(amd->map));
1006         amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
1007                          AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
1008         amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
1009
1010         __amd7930_update_map(amd);
1011
1012         /* Always MUX audio (Ba) to channel Bb. */
1013         sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
1014         sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
1015                     amd->regs + AMD7930_DR);
1016
1017         spin_unlock_irqrestore(&amd->lock, flags);
1018
1019         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1020                                   amd, &snd_amd7930_dev_ops)) < 0) {
1021                 snd_amd7930_free(amd);
1022                 return err;
1023         }
1024
1025         *ramd = amd;
1026         return 0;
1027 }
1028
1029 static int __init amd7930_attach(int prom_node, struct sbus_dev *sdev)
1030 {
1031         static int dev;
1032         struct linux_prom_registers reg_prop;
1033         struct linux_prom_irqs irq_prop;
1034         struct resource res, *rp;
1035         snd_card_t *card;
1036         amd7930_t *amd;
1037         int err;
1038
1039         if (dev >= SNDRV_CARDS)
1040                 return -ENODEV;
1041         if (!enable[dev]) {
1042                 dev++;
1043                 return -ENOENT;
1044         }
1045
1046         err = prom_getproperty(prom_node, "intr",
1047                                (char *) &irq_prop, sizeof(irq_prop));
1048         if (err < 0) {
1049                 snd_printk("amd7930-%d: Firmware node lacks IRQ property.\n", dev);
1050                 return -ENODEV;
1051         }
1052
1053         err = prom_getproperty(prom_node, "reg",
1054                                (char *) &reg_prop, sizeof(reg_prop));
1055         if (err < 0) {
1056                 snd_printk("amd7930-%d: Firmware node lacks register property.\n", dev);
1057                 return -ENODEV;
1058         }
1059
1060         if (sdev) {
1061                 rp = &sdev->resource[0];
1062         } else {
1063                 rp = &res;
1064                 rp->start = reg_prop.phys_addr;
1065                 rp->end = rp->start + reg_prop.reg_size - 1;
1066                 rp->flags = IORESOURCE_IO | (reg_prop.which_io & 0xff);
1067         }
1068
1069         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1070         if (card == NULL)
1071                 return -ENOMEM;
1072
1073         strcpy(card->driver, "AMD7930");
1074         strcpy(card->shortname, "Sun AMD7930");
1075         sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s",
1076                 card->shortname,
1077                 rp->flags & 0xffL,
1078                 rp->start,
1079                 __irq_itoa(irq_prop.pri));
1080
1081         if ((err = snd_amd7930_create(card, sdev, rp, reg_prop.reg_size,
1082                                           &irq_prop, dev, &amd)) < 0)
1083                 goto out_err;
1084
1085         if ((err = snd_amd7930_pcm(amd)) < 0)
1086                 goto out_err;
1087
1088         if ((err = snd_amd7930_mixer(amd)) < 0)
1089                 goto out_err;
1090
1091         if ((err = snd_card_set_generic_dev(card)) < 0)
1092                 goto out_err;
1093
1094         if ((err = snd_card_register(card)) < 0)
1095                 goto out_err;
1096
1097         amd->next = amd7930_list;
1098         amd7930_list = amd;
1099
1100         dev++;
1101         return 0;
1102
1103 out_err:
1104         snd_card_free(card);
1105         return err;
1106 }
1107
1108 static int __init amd7930_init(void)
1109 {
1110         struct sbus_bus *sbus;
1111         struct sbus_dev *sdev;
1112         int node, found;
1113
1114         found = 0;
1115
1116         /* Try to find the sun4c "audio" node first. */
1117         node = prom_getchild(prom_root_node);
1118         node = prom_searchsiblings(node, "audio");
1119         if (node && amd7930_attach(node, NULL) == 0)
1120                 found++;
1121
1122         /* Probe each SBUS for amd7930 chips. */
1123         for_all_sbusdev(sdev, sbus) {
1124                 if (!strcmp(sdev->prom_name, "audio")) {
1125                         if (amd7930_attach(sdev->prom_node, sdev) == 0)
1126                                 found++;
1127                 }
1128         }
1129
1130         return (found > 0) ? 0 : -EIO;
1131 }
1132
1133 static void __exit amd7930_exit(void)
1134 {
1135         amd7930_t *p = amd7930_list;
1136
1137         while (p != NULL) {
1138                 amd7930_t *next = p->next;
1139
1140                 snd_card_free(p->card);
1141
1142                 p = next;
1143         }
1144
1145         amd7930_list = NULL;
1146 }
1147
1148 module_init(amd7930_init);
1149 module_exit(amd7930_exit);