[ALSA] Remove sound/driver.h
[linux-2.6.git] / sound / sparc / amd7930.c
1 /*
2  * Driver for AMD7930 sound chips found on Sparcs.
3  * Copyright (C) 2002 David S. Miller <davem@redhat.com>
4  *
5  * Based entirely upon drivers/sbus/audio/amd7930.c which is:
6  * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
7  *
8  * --- Notes from Thomas's original driver ---
9  * This is the lowlevel driver for the AMD7930 audio chip found on all
10  * sun4c machines and some sun4m machines.
11  *
12  * The amd7930 is actually an ISDN chip which has a very simple
13  * integrated audio encoder/decoder. When Sun decided on what chip to
14  * use for audio, they had the brilliant idea of using the amd7930 and
15  * only connecting the audio encoder/decoder pins.
16  *
17  * Thanks to the AMD engineer who was able to get us the AMD79C30
18  * databook which has all the programming information and gain tables.
19  *
20  * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
21  * SparcStation 1+.  The chip provides microphone and speaker interfaces
22  * which provide mono-channel audio at 8K samples per second via either
23  * 8-bit A-law or 8-bit mu-law encoding.  Also, the chip features an
24  * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
25  * which performs basic D channel LAPD processing and provides raw
26  * B channel data.  The digital audio channel, the two ISDN B channels,
27  * and two 64 Kbps channels to the microprocessor are all interconnected
28  * via a multiplexer.
29  * --- End of notes from Thoamas's original driver ---
30  */
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/slab.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/moduleparam.h>
38
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/info.h>
42 #include <sound/control.h>
43 #include <sound/initval.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47 #include <asm/sbus.h>
48 #include <asm/prom.h>
49
50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
51 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
52 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
53
54 module_param_array(index, int, NULL, 0444);
55 MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
56 module_param_array(id, charp, NULL, 0444);
57 MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
58 module_param_array(enable, bool, NULL, 0444);
59 MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
60 MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
61 MODULE_DESCRIPTION("Sun AMD7930");
62 MODULE_LICENSE("GPL");
63 MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
64
65 /* Device register layout.  */
66
67 /* Register interface presented to the CPU by the amd7930. */
68 #define AMD7930_CR      0x00UL          /* Command Register (W) */
69 #define AMD7930_IR      AMD7930_CR      /* Interrupt Register (R) */
70 #define AMD7930_DR      0x01UL          /* Data Register (R/W) */
71 #define AMD7930_DSR1    0x02UL          /* D-channel Status Register 1 (R) */
72 #define AMD7930_DER     0x03UL          /* D-channel Error Register (R) */
73 #define AMD7930_DCTB    0x04UL          /* D-channel Transmit Buffer (W) */
74 #define AMD7930_DCRB    AMD7930_DCTB    /* D-channel Receive Buffer (R) */
75 #define AMD7930_BBTB    0x05UL          /* Bb-channel Transmit Buffer (W) */
76 #define AMD7930_BBRB    AMD7930_BBTB    /* Bb-channel Receive Buffer (R) */
77 #define AMD7930_BCTB    0x06UL          /* Bc-channel Transmit Buffer (W) */
78 #define AMD7930_BCRB    AMD7930_BCTB    /* Bc-channel Receive Buffer (R) */
79 #define AMD7930_DSR2    0x07UL          /* D-channel Status Register 2 (R) */
80
81 /* Indirect registers in the Main Audio Processor. */
82 struct amd7930_map {
83         __u16   x[8];
84         __u16   r[8];
85         __u16   gx;
86         __u16   gr;
87         __u16   ger;
88         __u16   stgr;
89         __u16   ftgr;
90         __u16   atgr;
91         __u8    mmr1;
92         __u8    mmr2;
93 };
94
95 /* After an amd7930 interrupt, reading the Interrupt Register (ir)
96  * clears the interrupt and returns a bitmask indicating which
97  * interrupt source(s) require service.
98  */
99
100 #define AMR_IR_DTTHRSH                  0x01 /* D-channel xmit threshold */
101 #define AMR_IR_DRTHRSH                  0x02 /* D-channel recv threshold */
102 #define AMR_IR_DSRI                     0x04 /* D-channel packet status */
103 #define AMR_IR_DERI                     0x08 /* D-channel error */
104 #define AMR_IR_BBUF                     0x10 /* B-channel data xfer */
105 #define AMR_IR_LSRI                     0x20 /* LIU status */
106 #define AMR_IR_DSR2I                    0x40 /* D-channel buffer status */
107 #define AMR_IR_MLTFRMI                  0x80 /* multiframe or PP */
108
109 /* The amd7930 has "indirect registers" which are accessed by writing
110  * the register number into the Command Register and then reading or
111  * writing values from the Data Register as appropriate. We define the
112  * AMR_* macros to be the indirect register numbers and AM_* macros to
113  * be bits in whatever register is referred to.
114  */
115
116 /* Initialization */
117 #define AMR_INIT                        0x21
118 #define         AM_INIT_ACTIVE                  0x01
119 #define         AM_INIT_DATAONLY                0x02
120 #define         AM_INIT_POWERDOWN               0x03
121 #define         AM_INIT_DISABLE_INTS            0x04
122 #define AMR_INIT2                       0x20
123 #define         AM_INIT2_ENABLE_POWERDOWN       0x20
124 #define         AM_INIT2_ENABLE_MULTIFRAME      0x10
125
126 /* Line Interface Unit */
127 #define AMR_LIU_LSR                     0xA1
128 #define         AM_LIU_LSR_STATE                0x07
129 #define         AM_LIU_LSR_F3                   0x08
130 #define         AM_LIU_LSR_F7                   0x10
131 #define         AM_LIU_LSR_F8                   0x20
132 #define         AM_LIU_LSR_HSW                  0x40
133 #define         AM_LIU_LSR_HSW_CHG              0x80
134 #define AMR_LIU_LPR                     0xA2
135 #define AMR_LIU_LMR1                    0xA3
136 #define         AM_LIU_LMR1_B1_ENABL            0x01
137 #define         AM_LIU_LMR1_B2_ENABL            0x02
138 #define         AM_LIU_LMR1_F_DISABL            0x04
139 #define         AM_LIU_LMR1_FA_DISABL           0x08
140 #define         AM_LIU_LMR1_REQ_ACTIV           0x10
141 #define         AM_LIU_LMR1_F8_F3               0x20
142 #define         AM_LIU_LMR1_LIU_ENABL           0x40
143 #define AMR_LIU_LMR2                    0xA4
144 #define         AM_LIU_LMR2_DECHO               0x01
145 #define         AM_LIU_LMR2_DLOOP               0x02
146 #define         AM_LIU_LMR2_DBACKOFF            0x04
147 #define         AM_LIU_LMR2_EN_F3_INT           0x08
148 #define         AM_LIU_LMR2_EN_F8_INT           0x10
149 #define         AM_LIU_LMR2_EN_HSW_INT          0x20
150 #define         AM_LIU_LMR2_EN_F7_INT           0x40
151 #define AMR_LIU_2_4                     0xA5
152 #define AMR_LIU_MF                      0xA6
153 #define AMR_LIU_MFSB                    0xA7
154 #define AMR_LIU_MFQB                    0xA8
155
156 /* Multiplexor */
157 #define AMR_MUX_MCR1                    0x41
158 #define AMR_MUX_MCR2                    0x42
159 #define AMR_MUX_MCR3                    0x43
160 #define         AM_MUX_CHANNEL_B1               0x01
161 #define         AM_MUX_CHANNEL_B2               0x02
162 #define         AM_MUX_CHANNEL_Ba               0x03
163 #define         AM_MUX_CHANNEL_Bb               0x04
164 #define         AM_MUX_CHANNEL_Bc               0x05
165 #define         AM_MUX_CHANNEL_Bd               0x06
166 #define         AM_MUX_CHANNEL_Be               0x07
167 #define         AM_MUX_CHANNEL_Bf               0x08
168 #define AMR_MUX_MCR4                    0x44
169 #define         AM_MUX_MCR4_ENABLE_INTS         0x08
170 #define         AM_MUX_MCR4_REVERSE_Bb          0x10
171 #define         AM_MUX_MCR4_REVERSE_Bc          0x20
172 #define AMR_MUX_1_4                     0x45
173
174 /* Main Audio Processor */
175 #define AMR_MAP_X                       0x61
176 #define AMR_MAP_R                       0x62
177 #define AMR_MAP_GX                      0x63
178 #define AMR_MAP_GR                      0x64
179 #define AMR_MAP_GER                     0x65
180 #define AMR_MAP_STGR                    0x66
181 #define AMR_MAP_FTGR_1_2                0x67
182 #define AMR_MAP_ATGR_1_2                0x68
183 #define AMR_MAP_MMR1                    0x69
184 #define         AM_MAP_MMR1_ALAW                0x01
185 #define         AM_MAP_MMR1_GX                  0x02
186 #define         AM_MAP_MMR1_GR                  0x04
187 #define         AM_MAP_MMR1_GER                 0x08
188 #define         AM_MAP_MMR1_X                   0x10
189 #define         AM_MAP_MMR1_R                   0x20
190 #define         AM_MAP_MMR1_STG                 0x40
191 #define         AM_MAP_MMR1_LOOPBACK            0x80
192 #define AMR_MAP_MMR2                    0x6A
193 #define         AM_MAP_MMR2_AINB                0x01
194 #define         AM_MAP_MMR2_LS                  0x02
195 #define         AM_MAP_MMR2_ENABLE_DTMF         0x04
196 #define         AM_MAP_MMR2_ENABLE_TONEGEN      0x08
197 #define         AM_MAP_MMR2_ENABLE_TONERING     0x10
198 #define         AM_MAP_MMR2_DISABLE_HIGHPASS    0x20
199 #define         AM_MAP_MMR2_DISABLE_AUTOZERO    0x40
200 #define AMR_MAP_1_10                    0x6B
201 #define AMR_MAP_MMR3                    0x6C
202 #define AMR_MAP_STRA                    0x6D
203 #define AMR_MAP_STRF                    0x6E
204 #define AMR_MAP_PEAKX                   0x70
205 #define AMR_MAP_PEAKR                   0x71
206 #define AMR_MAP_15_16                   0x72
207
208 /* Data Link Controller */
209 #define AMR_DLC_FRAR_1_2_3              0x81
210 #define AMR_DLC_SRAR_1_2_3              0x82
211 #define AMR_DLC_TAR                     0x83
212 #define AMR_DLC_DRLR                    0x84
213 #define AMR_DLC_DTCR                    0x85
214 #define AMR_DLC_DMR1                    0x86
215 #define         AMR_DLC_DMR1_DTTHRSH_INT        0x01
216 #define         AMR_DLC_DMR1_DRTHRSH_INT        0x02
217 #define         AMR_DLC_DMR1_TAR_ENABL          0x04
218 #define         AMR_DLC_DMR1_EORP_INT           0x08
219 #define         AMR_DLC_DMR1_EN_ADDR1           0x10
220 #define         AMR_DLC_DMR1_EN_ADDR2           0x20
221 #define         AMR_DLC_DMR1_EN_ADDR3           0x40
222 #define         AMR_DLC_DMR1_EN_ADDR4           0x80
223 #define         AMR_DLC_DMR1_EN_ADDRS           0xf0
224 #define AMR_DLC_DMR2                    0x87
225 #define         AMR_DLC_DMR2_RABRT_INT          0x01
226 #define         AMR_DLC_DMR2_RESID_INT          0x02
227 #define         AMR_DLC_DMR2_COLL_INT           0x04
228 #define         AMR_DLC_DMR2_FCS_INT            0x08
229 #define         AMR_DLC_DMR2_OVFL_INT           0x10
230 #define         AMR_DLC_DMR2_UNFL_INT           0x20
231 #define         AMR_DLC_DMR2_OVRN_INT           0x40
232 #define         AMR_DLC_DMR2_UNRN_INT           0x80
233 #define AMR_DLC_1_7                     0x88
234 #define AMR_DLC_DRCR                    0x89
235 #define AMR_DLC_RNGR1                   0x8A
236 #define AMR_DLC_RNGR2                   0x8B
237 #define AMR_DLC_FRAR4                   0x8C
238 #define AMR_DLC_SRAR4                   0x8D
239 #define AMR_DLC_DMR3                    0x8E
240 #define         AMR_DLC_DMR3_VA_INT             0x01
241 #define         AMR_DLC_DMR3_EOTP_INT           0x02
242 #define         AMR_DLC_DMR3_LBRP_INT           0x04
243 #define         AMR_DLC_DMR3_RBA_INT            0x08
244 #define         AMR_DLC_DMR3_LBT_INT            0x10
245 #define         AMR_DLC_DMR3_TBE_INT            0x20
246 #define         AMR_DLC_DMR3_RPLOST_INT         0x40
247 #define         AMR_DLC_DMR3_KEEP_FCS           0x80
248 #define AMR_DLC_DMR4                    0x8F
249 #define         AMR_DLC_DMR4_RCV_1              0x00
250 #define         AMR_DLC_DMR4_RCV_2              0x01
251 #define         AMR_DLC_DMR4_RCV_4              0x02
252 #define         AMR_DLC_DMR4_RCV_8              0x03
253 #define         AMR_DLC_DMR4_RCV_16             0x01
254 #define         AMR_DLC_DMR4_RCV_24             0x02
255 #define         AMR_DLC_DMR4_RCV_30             0x03
256 #define         AMR_DLC_DMR4_XMT_1              0x00
257 #define         AMR_DLC_DMR4_XMT_2              0x04
258 #define         AMR_DLC_DMR4_XMT_4              0x08
259 #define         AMR_DLC_DMR4_XMT_8              0x0c
260 #define         AMR_DLC_DMR4_XMT_10             0x08
261 #define         AMR_DLC_DMR4_XMT_14             0x0c
262 #define         AMR_DLC_DMR4_IDLE_MARK          0x00
263 #define         AMR_DLC_DMR4_IDLE_FLAG          0x10
264 #define         AMR_DLC_DMR4_ADDR_BOTH          0x00
265 #define         AMR_DLC_DMR4_ADDR_1ST           0x20
266 #define         AMR_DLC_DMR4_ADDR_2ND           0xa0
267 #define         AMR_DLC_DMR4_CR_ENABLE          0x40
268 #define AMR_DLC_12_15                   0x90
269 #define AMR_DLC_ASR                     0x91
270 #define AMR_DLC_EFCR                    0x92
271 #define         AMR_DLC_EFCR_EXTEND_FIFO        0x01
272 #define         AMR_DLC_EFCR_SEC_PKT_INT        0x02
273
274 #define AMR_DSR1_VADDR                  0x01
275 #define AMR_DSR1_EORP                   0x02
276 #define AMR_DSR1_PKT_IP                 0x04
277 #define AMR_DSR1_DECHO_ON               0x08
278 #define AMR_DSR1_DLOOP_ON               0x10
279 #define AMR_DSR1_DBACK_OFF              0x20
280 #define AMR_DSR1_EOTP                   0x40
281 #define AMR_DSR1_CXMT_ABRT              0x80
282
283 #define AMR_DSR2_LBRP                   0x01
284 #define AMR_DSR2_RBA                    0x02
285 #define AMR_DSR2_RPLOST                 0x04
286 #define AMR_DSR2_LAST_BYTE              0x08
287 #define AMR_DSR2_TBE                    0x10
288 #define AMR_DSR2_MARK_IDLE              0x20
289 #define AMR_DSR2_FLAG_IDLE              0x40
290 #define AMR_DSR2_SECOND_PKT             0x80
291
292 #define AMR_DER_RABRT                   0x01
293 #define AMR_DER_RFRAME                  0x02
294 #define AMR_DER_COLLISION               0x04
295 #define AMR_DER_FCS                     0x08
296 #define AMR_DER_OVFL                    0x10
297 #define AMR_DER_UNFL                    0x20
298 #define AMR_DER_OVRN                    0x40
299 #define AMR_DER_UNRN                    0x80
300
301 /* Peripheral Port */
302 #define AMR_PP_PPCR1                    0xC0
303 #define AMR_PP_PPSR                     0xC1
304 #define AMR_PP_PPIER                    0xC2
305 #define AMR_PP_MTDR                     0xC3
306 #define AMR_PP_MRDR                     0xC3
307 #define AMR_PP_CITDR0                   0xC4
308 #define AMR_PP_CIRDR0                   0xC4
309 #define AMR_PP_CITDR1                   0xC5
310 #define AMR_PP_CIRDR1                   0xC5
311 #define AMR_PP_PPCR2                    0xC8
312 #define AMR_PP_PPCR3                    0xC9
313
314 struct snd_amd7930 {
315         spinlock_t              lock;
316         void __iomem            *regs;
317         u32                     flags;
318 #define AMD7930_FLAG_PLAYBACK   0x00000001
319 #define AMD7930_FLAG_CAPTURE    0x00000002
320
321         struct amd7930_map      map;
322
323         struct snd_card         *card;
324         struct snd_pcm          *pcm;
325         struct snd_pcm_substream        *playback_substream;
326         struct snd_pcm_substream        *capture_substream;
327
328         /* Playback/Capture buffer state. */
329         unsigned char           *p_orig, *p_cur;
330         int                     p_left;
331         unsigned char           *c_orig, *c_cur;
332         int                     c_left;
333
334         int                     rgain;
335         int                     pgain;
336         int                     mgain;
337
338         unsigned int            irq;
339         unsigned int            regs_size;
340         struct snd_amd7930      *next;
341 };
342
343 static struct snd_amd7930 *amd7930_list;
344
345 /* Idle the AMD7930 chip.  The amd->lock is not held.  */
346 static __inline__ void amd7930_idle(struct snd_amd7930 *amd)
347 {
348         unsigned long flags;
349
350         spin_lock_irqsave(&amd->lock, flags);
351         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
352         sbus_writeb(0, amd->regs + AMD7930_DR);
353         spin_unlock_irqrestore(&amd->lock, flags);
354 }
355
356 /* Enable chip interrupts.  The amd->lock is not held.  */
357 static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd)
358 {
359         unsigned long flags;
360
361         spin_lock_irqsave(&amd->lock, flags);
362         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
363         sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
364         spin_unlock_irqrestore(&amd->lock, flags);
365 }
366
367 /* Disable chip interrupts.  The amd->lock is not held.  */
368 static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd)
369 {
370         unsigned long flags;
371
372         spin_lock_irqsave(&amd->lock, flags);
373         sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
374         sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
375         spin_unlock_irqrestore(&amd->lock, flags);
376 }
377
378 /* Commit amd7930_map settings to the hardware.
379  * The amd->lock is held and local interrupts are disabled.
380  */
381 static void __amd7930_write_map(struct snd_amd7930 *amd)
382 {
383         struct amd7930_map *map = &amd->map;
384
385         sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
386         sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
387         sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
388
389         sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
390         sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
391         sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
392
393         sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
394         sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
395         sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
396
397         sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
398         sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
399         sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
400
401         sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
402         sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
403
404         sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
405         sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
406 }
407
408 /* gx, gr & stg gains.  this table must contain 256 elements with
409  * the 0th being "infinity" (the magic value 9008).  The remaining
410  * elements match sun's gain curve (but with higher resolution):
411  * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
412  */
413 static __const__ __u16 gx_coeff[256] = {
414         0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
415         0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
416         0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
417         0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
418         0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
419         0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
420         0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
421         0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
422         0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
423         0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
424         0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
425         0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
426         0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
427         0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
428         0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
429         0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
430         0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
431         0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
432         0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
433         0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
434         0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
435         0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
436         0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
437         0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
438         0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
439         0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
440         0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
441         0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
442         0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
443         0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
444         0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
445         0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
446 };
447
448 static __const__ __u16 ger_coeff[] = {
449         0x431f, /* 5. dB */
450         0x331f, /* 5.5 dB */
451         0x40dd, /* 6. dB */
452         0x11dd, /* 6.5 dB */
453         0x440f, /* 7. dB */
454         0x411f, /* 7.5 dB */
455         0x311f, /* 8. dB */
456         0x5520, /* 8.5 dB */
457         0x10dd, /* 9. dB */
458         0x4211, /* 9.5 dB */
459         0x410f, /* 10. dB */
460         0x111f, /* 10.5 dB */
461         0x600b, /* 11. dB */
462         0x00dd, /* 11.5 dB */
463         0x4210, /* 12. dB */
464         0x110f, /* 13. dB */
465         0x7200, /* 14. dB */
466         0x2110, /* 15. dB */
467         0x2200, /* 15.9 dB */
468         0x000b, /* 16.9 dB */
469         0x000f  /* 18. dB */
470 };
471
472 /* Update amd7930_map settings and program them into the hardware.
473  * The amd->lock is held and local interrupts are disabled.
474  */
475 static void __amd7930_update_map(struct snd_amd7930 *amd)
476 {
477         struct amd7930_map *map = &amd->map;
478         int level;
479
480         map->gx = gx_coeff[amd->rgain];
481         map->stgr = gx_coeff[amd->mgain];
482         level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
483         if (level >= 256) {
484                 map->ger = ger_coeff[level - 256];
485                 map->gr = gx_coeff[255];
486         } else {
487                 map->ger = ger_coeff[0];
488                 map->gr = gx_coeff[level];
489         }
490         __amd7930_write_map(amd);
491 }
492
493 static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id)
494 {
495         struct snd_amd7930 *amd = dev_id;
496         unsigned int elapsed;
497         u8 ir;
498
499         spin_lock(&amd->lock);
500
501         elapsed = 0;
502
503         ir = sbus_readb(amd->regs + AMD7930_IR);
504         if (ir & AMR_IR_BBUF) {
505                 u8 byte;
506
507                 if (amd->flags & AMD7930_FLAG_PLAYBACK) {
508                         if (amd->p_left > 0) {
509                                 byte = *(amd->p_cur++);
510                                 amd->p_left--;
511                                 sbus_writeb(byte, amd->regs + AMD7930_BBTB);
512                                 if (amd->p_left == 0)
513                                         elapsed |= AMD7930_FLAG_PLAYBACK;
514                         } else
515                                 sbus_writeb(0, amd->regs + AMD7930_BBTB);
516                 } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
517                         byte = sbus_readb(amd->regs + AMD7930_BBRB);
518                         if (amd->c_left > 0) {
519                                 *(amd->c_cur++) = byte;
520                                 amd->c_left--;
521                                 if (amd->c_left == 0)
522                                         elapsed |= AMD7930_FLAG_CAPTURE;
523                         }
524                 }
525         }
526         spin_unlock(&amd->lock);
527
528         if (elapsed & AMD7930_FLAG_PLAYBACK)
529                 snd_pcm_period_elapsed(amd->playback_substream);
530         else
531                 snd_pcm_period_elapsed(amd->capture_substream);
532
533         return IRQ_HANDLED;
534 }
535
536 static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd)
537 {
538         unsigned long flags;
539         int result = 0;
540
541         spin_lock_irqsave(&amd->lock, flags);
542         if (cmd == SNDRV_PCM_TRIGGER_START) {
543                 if (!(amd->flags & flag)) {
544                         amd->flags |= flag;
545
546                         /* Enable B channel interrupts.  */
547                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
548                         sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
549                 }
550         } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
551                 if (amd->flags & flag) {
552                         amd->flags &= ~flag;
553
554                         /* Disable B channel interrupts.  */
555                         sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
556                         sbus_writeb(0, amd->regs + AMD7930_DR);
557                 }
558         } else {
559                 result = -EINVAL;
560         }
561         spin_unlock_irqrestore(&amd->lock, flags);
562
563         return result;
564 }
565
566 static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream,
567                                         int cmd)
568 {
569         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
570         return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
571 }
572
573 static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream,
574                                        int cmd)
575 {
576         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
577         return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
578 }
579
580 static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream)
581 {
582         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
583         struct snd_pcm_runtime *runtime = substream->runtime;
584         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
585         unsigned long flags;
586         u8 new_mmr1;
587
588         spin_lock_irqsave(&amd->lock, flags);
589
590         amd->flags |= AMD7930_FLAG_PLAYBACK;
591
592         /* Setup the pseudo-dma transfer pointers.  */
593         amd->p_orig = amd->p_cur = runtime->dma_area;
594         amd->p_left = size;
595
596         /* Put the chip into the correct encoding format.  */
597         new_mmr1 = amd->map.mmr1;
598         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
599                 new_mmr1 |= AM_MAP_MMR1_ALAW;
600         else
601                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
602         if (new_mmr1 != amd->map.mmr1) {
603                 amd->map.mmr1 = new_mmr1;
604                 __amd7930_update_map(amd);
605         }
606
607         spin_unlock_irqrestore(&amd->lock, flags);
608
609         return 0;
610 }
611
612 static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream)
613 {
614         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
615         struct snd_pcm_runtime *runtime = substream->runtime;
616         unsigned int size = snd_pcm_lib_buffer_bytes(substream);
617         unsigned long flags;
618         u8 new_mmr1;
619
620         spin_lock_irqsave(&amd->lock, flags);
621
622         amd->flags |= AMD7930_FLAG_CAPTURE;
623
624         /* Setup the pseudo-dma transfer pointers.  */
625         amd->c_orig = amd->c_cur = runtime->dma_area;
626         amd->c_left = size;
627
628         /* Put the chip into the correct encoding format.  */
629         new_mmr1 = amd->map.mmr1;
630         if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
631                 new_mmr1 |= AM_MAP_MMR1_ALAW;
632         else
633                 new_mmr1 &= ~AM_MAP_MMR1_ALAW;
634         if (new_mmr1 != amd->map.mmr1) {
635                 amd->map.mmr1 = new_mmr1;
636                 __amd7930_update_map(amd);
637         }
638
639         spin_unlock_irqrestore(&amd->lock, flags);
640
641         return 0;
642 }
643
644 static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream)
645 {
646         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
647         size_t ptr;
648
649         if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
650                 return 0;
651         ptr = amd->p_cur - amd->p_orig;
652         return bytes_to_frames(substream->runtime, ptr);
653 }
654
655 static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream)
656 {
657         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
658         size_t ptr;
659
660         if (!(amd->flags & AMD7930_FLAG_CAPTURE))
661                 return 0;
662
663         ptr = amd->c_cur - amd->c_orig;
664         return bytes_to_frames(substream->runtime, ptr);
665 }
666
667 /* Playback and capture have identical properties.  */
668 static struct snd_pcm_hardware snd_amd7930_pcm_hw =
669 {
670         .info                   = (SNDRV_PCM_INFO_MMAP |
671                                    SNDRV_PCM_INFO_MMAP_VALID |
672                                    SNDRV_PCM_INFO_INTERLEAVED |
673                                    SNDRV_PCM_INFO_BLOCK_TRANSFER |
674                                    SNDRV_PCM_INFO_HALF_DUPLEX),
675         .formats                = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
676         .rates                  = SNDRV_PCM_RATE_8000,
677         .rate_min               = 8000,
678         .rate_max               = 8000,
679         .channels_min           = 1,
680         .channels_max           = 1,
681         .buffer_bytes_max       = (64*1024),
682         .period_bytes_min       = 1,
683         .period_bytes_max       = (64*1024),
684         .periods_min            = 1,
685         .periods_max            = 1024,
686 };
687
688 static int snd_amd7930_playback_open(struct snd_pcm_substream *substream)
689 {
690         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
691         struct snd_pcm_runtime *runtime = substream->runtime;
692
693         amd->playback_substream = substream;
694         runtime->hw = snd_amd7930_pcm_hw;
695         return 0;
696 }
697
698 static int snd_amd7930_capture_open(struct snd_pcm_substream *substream)
699 {
700         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
701         struct snd_pcm_runtime *runtime = substream->runtime;
702
703         amd->capture_substream = substream;
704         runtime->hw = snd_amd7930_pcm_hw;
705         return 0;
706 }
707
708 static int snd_amd7930_playback_close(struct snd_pcm_substream *substream)
709 {
710         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
711
712         amd->playback_substream = NULL;
713         return 0;
714 }
715
716 static int snd_amd7930_capture_close(struct snd_pcm_substream *substream)
717 {
718         struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
719
720         amd->capture_substream = NULL;
721         return 0;
722 }
723
724 static int snd_amd7930_hw_params(struct snd_pcm_substream *substream,
725                                     struct snd_pcm_hw_params *hw_params)
726 {
727         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
728 }
729
730 static int snd_amd7930_hw_free(struct snd_pcm_substream *substream)
731 {
732         return snd_pcm_lib_free_pages(substream);
733 }
734
735 static struct snd_pcm_ops snd_amd7930_playback_ops = {
736         .open           =       snd_amd7930_playback_open,
737         .close          =       snd_amd7930_playback_close,
738         .ioctl          =       snd_pcm_lib_ioctl,
739         .hw_params      =       snd_amd7930_hw_params,
740         .hw_free        =       snd_amd7930_hw_free,
741         .prepare        =       snd_amd7930_playback_prepare,
742         .trigger        =       snd_amd7930_playback_trigger,
743         .pointer        =       snd_amd7930_playback_pointer,
744 };
745
746 static struct snd_pcm_ops snd_amd7930_capture_ops = {
747         .open           =       snd_amd7930_capture_open,
748         .close          =       snd_amd7930_capture_close,
749         .ioctl          =       snd_pcm_lib_ioctl,
750         .hw_params      =       snd_amd7930_hw_params,
751         .hw_free        =       snd_amd7930_hw_free,
752         .prepare        =       snd_amd7930_capture_prepare,
753         .trigger        =       snd_amd7930_capture_trigger,
754         .pointer        =       snd_amd7930_capture_pointer,
755 };
756
757 static int __devinit snd_amd7930_pcm(struct snd_amd7930 *amd)
758 {
759         struct snd_pcm *pcm;
760         int err;
761
762         if ((err = snd_pcm_new(amd->card,
763                                /* ID */             "sun_amd7930",
764                                /* device */         0,
765                                /* playback count */ 1,
766                                /* capture count */  1, &pcm)) < 0)
767                 return err;
768         snd_assert(pcm != NULL, return -EINVAL);
769
770         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
771         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
772
773         pcm->private_data = amd;
774         pcm->info_flags = 0;
775         strcpy(pcm->name, amd->card->shortname);
776         amd->pcm = pcm;
777
778         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
779                                               snd_dma_continuous_data(GFP_KERNEL),
780                                               64*1024, 64*1024);
781
782         return 0;
783 }
784
785 #define VOLUME_MONITOR  0
786 #define VOLUME_CAPTURE  1
787 #define VOLUME_PLAYBACK 2
788
789 static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo)
790 {
791         int type = kctl->private_value;
792
793         snd_assert(type == VOLUME_MONITOR ||
794                    type == VOLUME_CAPTURE ||
795                    type == VOLUME_PLAYBACK, return -EINVAL);
796         (void) type;
797
798         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
799         uinfo->count = 1;
800         uinfo->value.integer.min = 0;
801         uinfo->value.integer.max = 255;
802
803         return 0;
804 }
805
806 static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
807 {
808         struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
809         int type = kctl->private_value;
810         int *swval;
811
812         snd_assert(type == VOLUME_MONITOR ||
813                    type == VOLUME_CAPTURE ||
814                    type == VOLUME_PLAYBACK, return -EINVAL);
815
816         switch (type) {
817         case VOLUME_MONITOR:
818                 swval = &amd->mgain;
819                 break;
820         case VOLUME_CAPTURE:
821                 swval = &amd->rgain;
822                 break;
823         case VOLUME_PLAYBACK:
824         default:
825                 swval = &amd->pgain;
826                 break;
827         };
828
829         ucontrol->value.integer.value[0] = *swval;
830
831         return 0;
832 }
833
834 static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
835 {
836         struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
837         unsigned long flags;
838         int type = kctl->private_value;
839         int *swval, change;
840
841         snd_assert(type == VOLUME_MONITOR ||
842                    type == VOLUME_CAPTURE ||
843                    type == VOLUME_PLAYBACK, return -EINVAL);
844
845         switch (type) {
846         case VOLUME_MONITOR:
847                 swval = &amd->mgain;
848                 break;
849         case VOLUME_CAPTURE:
850                 swval = &amd->rgain;
851                 break;
852         case VOLUME_PLAYBACK:
853         default:
854                 swval = &amd->pgain;
855                 break;
856         };
857
858         spin_lock_irqsave(&amd->lock, flags);
859
860         if (*swval != ucontrol->value.integer.value[0]) {
861                 *swval = ucontrol->value.integer.value[0] & 0xff;
862                 __amd7930_update_map(amd);
863                 change = 1;
864         } else
865                 change = 0;
866
867         spin_unlock_irqrestore(&amd->lock, flags);
868
869         return change;
870 }
871
872 static struct snd_kcontrol_new amd7930_controls[] __devinitdata = {
873         {
874                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
875                 .name           =       "Monitor Volume",
876                 .index          =       0,
877                 .info           =       snd_amd7930_info_volume,
878                 .get            =       snd_amd7930_get_volume,
879                 .put            =       snd_amd7930_put_volume,
880                 .private_value  =       VOLUME_MONITOR,
881         },
882         {
883                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
884                 .name           =       "Capture Volume",
885                 .index          =       0,
886                 .info           =       snd_amd7930_info_volume,
887                 .get            =       snd_amd7930_get_volume,
888                 .put            =       snd_amd7930_put_volume,
889                 .private_value  =       VOLUME_CAPTURE,
890         },
891         {
892                 .iface          =       SNDRV_CTL_ELEM_IFACE_MIXER,
893                 .name           =       "Playback Volume",
894                 .index          =       0,
895                 .info           =       snd_amd7930_info_volume,
896                 .get            =       snd_amd7930_get_volume,
897                 .put            =       snd_amd7930_put_volume,
898                 .private_value  =       VOLUME_PLAYBACK,
899         },
900 };
901
902 static int __devinit snd_amd7930_mixer(struct snd_amd7930 *amd)
903 {
904         struct snd_card *card;
905         int idx, err;
906
907         snd_assert(amd != NULL && amd->card != NULL, return -EINVAL);
908
909         card = amd->card;
910         strcpy(card->mixername, card->shortname);
911
912         for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
913                 if ((err = snd_ctl_add(card,
914                                        snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
915                         return err;
916         }
917
918         return 0;
919 }
920
921 static int snd_amd7930_free(struct snd_amd7930 *amd)
922 {
923         amd7930_idle(amd);
924
925         if (amd->irq)
926                 free_irq(amd->irq, amd);
927
928         if (amd->regs)
929                 sbus_iounmap(amd->regs, amd->regs_size);
930
931         kfree(amd);
932
933         return 0;
934 }
935
936 static int snd_amd7930_dev_free(struct snd_device *device)
937 {
938         struct snd_amd7930 *amd = device->device_data;
939
940         return snd_amd7930_free(amd);
941 }
942
943 static struct snd_device_ops snd_amd7930_dev_ops = {
944         .dev_free       =       snd_amd7930_dev_free,
945 };
946
947 static int __devinit snd_amd7930_create(struct snd_card *card,
948                                         struct resource *rp,
949                                         unsigned int reg_size,
950                                         int irq, int dev,
951                                         struct snd_amd7930 **ramd)
952 {
953         unsigned long flags;
954         struct snd_amd7930 *amd;
955         int err;
956
957         *ramd = NULL;
958         amd = kzalloc(sizeof(*amd), GFP_KERNEL);
959         if (amd == NULL)
960                 return -ENOMEM;
961
962         spin_lock_init(&amd->lock);
963         amd->card = card;
964         amd->regs_size = reg_size;
965
966         amd->regs = sbus_ioremap(rp, 0, amd->regs_size, "amd7930");
967         if (!amd->regs) {
968                 snd_printk("amd7930-%d: Unable to map chip registers.\n", dev);
969                 return -EIO;
970         }
971
972         amd7930_idle(amd);
973
974         if (request_irq(irq, snd_amd7930_interrupt,
975                         IRQF_DISABLED | IRQF_SHARED, "amd7930", amd)) {
976                 snd_printk("amd7930-%d: Unable to grab IRQ %d\n",
977                            dev, irq);
978                 snd_amd7930_free(amd);
979                 return -EBUSY;
980         }
981         amd->irq = irq;
982
983         amd7930_enable_ints(amd);
984
985         spin_lock_irqsave(&amd->lock, flags);
986
987         amd->rgain = 128;
988         amd->pgain = 200;
989         amd->mgain = 0;
990
991         memset(&amd->map, 0, sizeof(amd->map));
992         amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
993                          AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
994         amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
995
996         __amd7930_update_map(amd);
997
998         /* Always MUX audio (Ba) to channel Bb. */
999         sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
1000         sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
1001                     amd->regs + AMD7930_DR);
1002
1003         spin_unlock_irqrestore(&amd->lock, flags);
1004
1005         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
1006                                   amd, &snd_amd7930_dev_ops)) < 0) {
1007                 snd_amd7930_free(amd);
1008                 return err;
1009         }
1010
1011         *ramd = amd;
1012         return 0;
1013 }
1014
1015 static int __devinit amd7930_attach_common(struct resource *rp, int irq)
1016 {
1017         static int dev_num;
1018         struct snd_card *card;
1019         struct snd_amd7930 *amd;
1020         int err;
1021
1022         if (dev_num >= SNDRV_CARDS)
1023                 return -ENODEV;
1024         if (!enable[dev_num]) {
1025                 dev_num++;
1026                 return -ENOENT;
1027         }
1028
1029         card = snd_card_new(index[dev_num], id[dev_num], THIS_MODULE, 0);
1030         if (card == NULL)
1031                 return -ENOMEM;
1032
1033         strcpy(card->driver, "AMD7930");
1034         strcpy(card->shortname, "Sun AMD7930");
1035         sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d",
1036                 card->shortname,
1037                 rp->flags & 0xffL,
1038                 (unsigned long long)rp->start,
1039                 irq);
1040
1041         if ((err = snd_amd7930_create(card, rp,
1042                                       (rp->end - rp->start) + 1,
1043                                       irq, dev_num, &amd)) < 0)
1044                 goto out_err;
1045
1046         if ((err = snd_amd7930_pcm(amd)) < 0)
1047                 goto out_err;
1048
1049         if ((err = snd_amd7930_mixer(amd)) < 0)
1050                 goto out_err;
1051
1052         if ((err = snd_card_register(card)) < 0)
1053                 goto out_err;
1054
1055         amd->next = amd7930_list;
1056         amd7930_list = amd;
1057
1058         dev_num++;
1059
1060         return 0;
1061
1062 out_err:
1063         snd_card_free(card);
1064         return err;
1065 }
1066
1067 static int __devinit amd7930_obio_attach(struct device_node *dp)
1068 {
1069         const struct linux_prom_registers *regs;
1070         const struct linux_prom_irqs *irqp;
1071         struct resource res, *rp;
1072         int len;
1073
1074         irqp = of_get_property(dp, "intr", &len);
1075         if (!irqp) {
1076                 snd_printk("%s: Firmware node lacks IRQ property.\n",
1077                            dp->full_name);
1078                 return -ENODEV;
1079         }
1080
1081         regs = of_get_property(dp, "reg", &len);
1082         if (!regs) {
1083                 snd_printk("%s: Firmware node lacks register property.\n",
1084                            dp->full_name);
1085                 return -ENODEV;
1086         }
1087
1088         rp = &res;
1089         rp->start = regs->phys_addr;
1090         rp->end = rp->start + regs->reg_size - 1;
1091         rp->flags = IORESOURCE_IO | (regs->which_io & 0xff);
1092
1093         return amd7930_attach_common(rp, irqp->pri);
1094 }
1095
1096 static int __devinit amd7930_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1097 {
1098         struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1099
1100         return amd7930_attach_common(&sdev->resource[0], sdev->irqs[0]);
1101 }
1102
1103 static struct of_device_id amd7930_match[] = {
1104         {
1105                 .name = "audio",
1106         },
1107         {},
1108 };
1109
1110 static struct of_platform_driver amd7930_sbus_driver = {
1111         .name           = "audio",
1112         .match_table    = amd7930_match,
1113         .probe          = amd7930_sbus_probe,
1114 };
1115
1116 static int __init amd7930_init(void)
1117 {
1118         struct device_node *dp;
1119
1120         /* Try to find the sun4c "audio" node first. */
1121         dp = of_find_node_by_path("/");
1122         dp = dp->child;
1123         while (dp) {
1124                 if (!strcmp(dp->name, "audio"))
1125                         amd7930_obio_attach(dp);
1126
1127                 dp = dp->sibling;
1128         }
1129
1130         /* Probe each SBUS for amd7930 chips. */
1131         return of_register_driver(&amd7930_sbus_driver, &sbus_bus_type);
1132 }
1133
1134 static void __exit amd7930_exit(void)
1135 {
1136         struct snd_amd7930 *p = amd7930_list;
1137
1138         while (p != NULL) {
1139                 struct snd_amd7930 *next = p->next;
1140
1141                 snd_card_free(p->card);
1142
1143                 p = next;
1144         }
1145
1146         amd7930_list = NULL;
1147
1148         of_unregister_driver(&amd7930_sbus_driver);
1149 }
1150
1151 module_init(amd7930_init);
1152 module_exit(amd7930_exit);