soc: codecs: rt5639: Implement i2c shutdown
[linux-2.6.git] / sound / soc / tegra / tegra_asoc_utils.c
1 /*
2  * tegra_asoc_utils.c - Harmony machine ASoC driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (c) 2010-12, NVIDIA CORPORATION. All rights reserved.
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21
22 #include <linux/clk.h>
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27
28 #include <mach/clk.h>
29
30 #include <sound/soc.h>
31
32 #include "tegra_pcm.h"
33 #include "tegra_asoc_utils.h"
34
35 int g_is_call_mode;
36
37 #ifdef CONFIG_SWITCH
38 static bool is_switch_registered;
39 struct switch_dev *psdev;
40 /* These values are copied from WiredAccessoryObserver */
41 enum headset_state {
42         BIT_NO_HEADSET = 0,
43         BIT_HEADSET = (1 << 0),
44         BIT_HEADSET_NO_MIC = (1 << 1),
45 };
46 #endif
47
48 bool tegra_is_voice_call_active(void)
49 {
50         if (g_is_call_mode)
51                 return true;
52         else
53                 return false;
54 }
55 EXPORT_SYMBOL_GPL(tegra_is_voice_call_active);
56
57 static int tegra_get_avp_device(struct snd_kcontrol *kcontrol,
58                                 struct snd_ctl_elem_value *ucontrol)
59 {
60         struct  tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
61
62         ucontrol->value.integer.value[0] = data->avp_device_id;
63         return 0;
64 }
65
66 static int tegra_set_avp_device(struct snd_kcontrol *kcontrol,
67                                 struct snd_ctl_elem_value *ucontrol)
68 {
69         struct  tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
70         struct snd_soc_card *card = data->card;
71         struct snd_soc_pcm_runtime *rtd;
72         struct snd_pcm_substream *substream;
73         struct tegra_runtime_data *prtd;
74         int id, old_id = data->avp_device_id;
75
76         id = ucontrol->value.integer.value[0];
77         if ((id >= card->num_rtd) || (id < 0))
78                 id = -1;
79
80         if (old_id >= 0) {
81                 rtd = &card->rtd[old_id];
82                 substream =
83                         rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
84                 if (substream && substream->runtime) {
85                         prtd = substream->runtime->private_data;
86                         if (!prtd)
87                                 return -EINVAL;
88                         if (prtd->running)
89                                 return -EBUSY;
90                         prtd->disable_intr = false;
91                 }
92         }
93
94         if (id >= 0) {
95                 rtd = &card->rtd[id];
96                 substream =
97                         rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
98                 if (substream && substream->runtime) {
99                         prtd = substream->runtime->private_data;
100                         if (!prtd)
101                                 return -EINVAL;
102                         if (prtd->running)
103                                 return -EBUSY;
104                         prtd->disable_intr = true;
105                         if (data->avp_dma_addr || prtd->avp_dma_addr)
106                                 prtd->avp_dma_addr = data->avp_dma_addr;
107                 }
108         }
109         data->avp_device_id = id;
110         return 1;
111 }
112
113 static int tegra_get_dma_ch_id(struct snd_kcontrol *kcontrol,
114                                struct snd_ctl_elem_value *ucontrol)
115 {
116         struct  tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
117         struct snd_soc_card *card = data->card;
118         struct snd_soc_pcm_runtime *rtd;
119         struct snd_pcm_substream *substream;
120         struct tegra_runtime_data *prtd;
121
122         ucontrol->value.integer.value[0] = -1;
123         if (data->avp_device_id < 0)
124                 return 0;
125
126         rtd = &card->rtd[data->avp_device_id];
127         substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
128         if (!substream || !substream->runtime)
129                 return 0;
130
131         prtd = substream->runtime->private_data;
132         if (!prtd || !prtd->dma_chan)
133                 return 0;
134
135         ucontrol->value.integer.value[0] =
136                 tegra_dma_get_channel_id(prtd->dma_chan);
137         return 0;
138 }
139
140 static int tegra_set_dma_addr(struct snd_kcontrol *kcontrol,
141                               struct snd_ctl_elem_value *ucontrol)
142 {
143         struct tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
144         struct snd_soc_card *card = data->card;
145         struct snd_soc_pcm_runtime *rtd;
146         struct snd_pcm_substream *substream;
147         struct tegra_runtime_data *prtd;
148
149         if (data->avp_device_id < 0)
150                 return 0;
151
152         data->avp_dma_addr = ucontrol->value.integer.value[0];
153
154         rtd = &card->rtd[data->avp_device_id];
155         substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
156         if (!substream || !substream->runtime)
157                 return 0;
158
159         prtd = substream->runtime->private_data;
160         if (!prtd)
161                 return 0;
162
163         prtd->avp_dma_addr = data->avp_dma_addr;
164         return 1;
165 }
166
167 static int tegra_get_dma_addr(struct snd_kcontrol *kcontrol,
168                               struct snd_ctl_elem_value *ucontrol)
169 {
170         struct  tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
171         struct snd_soc_card *card = data->card;
172         struct snd_soc_pcm_runtime *rtd;
173         struct snd_pcm_substream *substream;
174         struct tegra_runtime_data *prtd;
175
176         ucontrol->value.integer.value[0] = 0;
177         if (data->avp_device_id < 0)
178                 return 0;
179
180         rtd = &card->rtd[data->avp_device_id];
181         substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
182         if (!substream || !substream->runtime)
183                 return 0;
184
185         prtd = substream->runtime->private_data;
186         if (!prtd || !prtd->dma_chan)
187                 return 0;
188
189         ucontrol->value.integer.value[0] = prtd->avp_dma_addr ?
190                                            prtd->avp_dma_addr :
191                                            substream->runtime->dma_addr;
192
193         return 0;
194 }
195
196 struct snd_kcontrol_new tegra_avp_controls[] = {
197         SOC_SINGLE_EXT("AVP alsa device select", 0, 0, TEGRA_ALSA_MAX_DEVICES, \
198                         0, tegra_get_avp_device, tegra_set_avp_device),
199         SOC_SINGLE_EXT("AVP DMA channel id", 0, 0, TEGRA_DMA_MAX_CHANNELS, \
200                         0, tegra_get_dma_ch_id, NULL),
201         SOC_SINGLE_EXT("AVP DMA address", 0, 0, 0xFFFFFFFF, \
202                         0, tegra_get_dma_addr, tegra_set_dma_addr),
203 };
204
205 static int tegra_set_headset_plug_state(struct snd_kcontrol *kcontrol,
206                               struct snd_ctl_elem_value *ucontrol)
207 {
208         struct tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
209         int switch_state;
210
211         data->headset_plug_state = ucontrol->value.integer.value[0];
212         switch_state = data->headset_plug_state == 1 ? BIT_HEADSET
213                 : BIT_NO_HEADSET;
214         if (psdev)
215                 switch_set_state(psdev, switch_state);
216
217         return 1;
218 }
219
220 static int tegra_get_headset_plug_state(struct snd_kcontrol *kcontrol,
221                               struct snd_ctl_elem_value *ucontrol)
222 {
223         struct  tegra_asoc_utils_data *data = snd_kcontrol_chip(kcontrol);
224
225         ucontrol->value.integer.value[0] = data->headset_plug_state;
226
227         return 0;
228 }
229
230 struct snd_kcontrol_new tegra_switch_controls =
231         SOC_SINGLE_EXT("Headset Plug State", 0, 0, 1, \
232         0, tegra_get_headset_plug_state, tegra_set_headset_plug_state);
233
234
235 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
236                               int mclk)
237 {
238         int new_baseclock;
239         bool clk_change;
240         int err;
241         bool reenable_clock;
242
243         switch (srate) {
244         case 11025:
245         case 22050:
246         case 44100:
247         case 88200:
248 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
249                 new_baseclock = 56448000;
250 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
251                 new_baseclock = 564480000;
252 #else
253                 new_baseclock = 282240000;
254 #endif
255                 break;
256         case 8000:
257         case 16000:
258         case 32000:
259         case 48000:
260         case 64000:
261         case 96000:
262 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
263                 new_baseclock = 73728000;
264 #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
265                 new_baseclock = 552960000;
266 #else
267                 new_baseclock = 368640000;
268 #endif
269                 break;
270         default:
271                 return -EINVAL;
272         }
273
274         clk_change = ((new_baseclock != data->set_baseclock) ||
275                         (mclk != data->set_mclk));
276         if (!clk_change)
277                 return 0;
278
279         /* Don't change rate if already one dai-link is using it */
280         if (data->lock_count)
281                 return -EINVAL;
282
283         data->set_baseclock = 0;
284         data->set_mclk = 0;
285
286         reenable_clock = false;
287         if(tegra_is_clk_enabled(data->clk_pll_a)) {
288                 clk_disable(data->clk_pll_a);
289                 reenable_clock = true;
290         }
291         err = clk_set_rate(data->clk_pll_a, new_baseclock);
292         if (err) {
293                 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
294                 return err;
295         }
296         if(reenable_clock)
297                 clk_enable(data->clk_pll_a);
298
299         reenable_clock = false;
300         if(tegra_is_clk_enabled(data->clk_pll_a_out0)) {
301                 clk_disable(data->clk_pll_a_out0);
302                 reenable_clock = true;
303         }
304         err = clk_set_rate(data->clk_pll_a_out0, mclk);
305         if (err) {
306                 dev_err(data->dev, "Can't set clk_pll_a_out0 rate: %d\n", err);
307                 return err;
308         }
309         if(reenable_clock)
310                 clk_enable(data->clk_pll_a_out0);
311
312
313         data->set_baseclock = new_baseclock;
314         data->set_mclk = mclk;
315
316         return 0;
317 }
318 EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
319
320 void tegra_asoc_utils_lock_clk_rate(struct tegra_asoc_utils_data *data,
321                                     int lock)
322 {
323         if (lock)
324                 data->lock_count++;
325         else if (data->lock_count)
326                 data->lock_count--;
327 }
328 EXPORT_SYMBOL_GPL(tegra_asoc_utils_lock_clk_rate);
329
330 int tegra_asoc_utils_clk_enable(struct tegra_asoc_utils_data *data)
331 {
332         int err;
333
334         err = clk_enable(data->clk_cdev1);
335         if (err) {
336                 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
337                 return err;
338         }
339
340         return 0;
341 }
342 EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_enable);
343
344 int tegra_asoc_utils_clk_disable(struct tegra_asoc_utils_data *data)
345 {
346         clk_disable(data->clk_cdev1);
347         return 0;
348 }
349 EXPORT_SYMBOL_GPL(tegra_asoc_utils_clk_disable);
350
351 int tegra_asoc_utils_register_ctls(struct tegra_asoc_utils_data *data)
352 {
353         int i;
354         int ret = 0;
355
356         /* Add AVP related alsa controls */
357         data->avp_device_id = -1;
358         for (i = 0; i < ARRAY_SIZE(tegra_avp_controls); i++) {
359                 ret = snd_ctl_add(data->card->snd_card,
360                                 snd_ctl_new1(&tegra_avp_controls[i], data));
361                 if (ret < 0) {
362                         dev_err(data->dev, "Can't add avp alsa controls");
363                         return ret;
364                 }
365         }
366
367         ret = snd_ctl_add(data->card->snd_card,
368                         snd_ctl_new1(&tegra_switch_controls, data));
369         if (ret < 0) {
370                 dev_err(data->dev, "Can't add switch alsa control");
371                 return ret;
372         }
373
374         return ret;
375 }
376 EXPORT_SYMBOL_GPL(tegra_asoc_utils_register_ctls);
377
378 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
379                           struct device *dev, struct snd_soc_card *card)
380 {
381         int ret;
382
383         data->dev = dev;
384         data->card = card;
385
386         data->clk_pll_p_out1 = clk_get_sys(NULL, "pll_p_out1");
387         if (IS_ERR(data->clk_pll_p_out1)) {
388                 dev_err(data->dev, "Can't retrieve clk pll_p_out1\n");
389                 ret = PTR_ERR(data->clk_pll_p_out1);
390                 goto err;
391         }
392
393         data->clk_pll_a = clk_get_sys(NULL, "pll_a");
394         if (IS_ERR(data->clk_pll_a)) {
395                 dev_err(data->dev, "Can't retrieve clk pll_a\n");
396                 ret = PTR_ERR(data->clk_pll_a);
397                 goto err_put_pll_p_out1;
398         }
399
400         data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
401         if (IS_ERR(data->clk_pll_a_out0)) {
402                 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
403                 ret = PTR_ERR(data->clk_pll_a_out0);
404                 goto err_put_pll_a;
405         }
406
407         data->clk_m = clk_get_sys(NULL, "clk_m");
408         if (IS_ERR(data->clk_m)) {
409                 dev_err(data->dev, "Can't retrieve clk clk_m\n");
410                 ret = PTR_ERR(data->clk_m);
411                 goto err;
412         }
413
414 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
415         data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
416 #else
417         data->clk_cdev1 = clk_get_sys("extern1", NULL);
418 #endif
419         if (IS_ERR(data->clk_cdev1)) {
420                 dev_err(data->dev, "Can't retrieve clk cdev1\n");
421                 ret = PTR_ERR(data->clk_cdev1);
422                 goto err_put_pll_a_out0;
423         }
424
425 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
426         data->clk_out1 = ERR_PTR(-ENOENT);
427 #else
428         data->clk_out1 = clk_get_sys("clk_out_1", "extern1");
429         if (IS_ERR(data->clk_out1)) {
430                 dev_err(data->dev, "Can't retrieve clk out1\n");
431                 ret = PTR_ERR(data->clk_out1);
432                 goto err_put_cdev1;
433         }
434 #endif
435
436         ret = clk_enable(data->clk_cdev1);
437         if (ret) {
438                 dev_err(data->dev, "Can't enable clk cdev1/extern1");
439                 goto err_put_out1;
440         }
441
442         if (!IS_ERR(data->clk_out1)) {
443                 ret = clk_enable(data->clk_out1);
444                 if (ret) {
445                         dev_err(data->dev, "Can't enable clk out1");
446                         goto err_put_out1;
447                 }
448         }
449
450         ret = tegra_asoc_utils_set_rate(data, 48000, 256 * 48000);
451         if (ret)
452                 goto err_put_out1;
453
454         return 0;
455
456 err_put_out1:
457         if (!IS_ERR(data->clk_out1))
458                 clk_put(data->clk_out1);
459 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
460 err_put_cdev1:
461 #endif
462         clk_put(data->clk_cdev1);
463 err_put_pll_a_out0:
464         clk_put(data->clk_pll_a_out0);
465 err_put_pll_a:
466         clk_put(data->clk_pll_a);
467 err_put_pll_p_out1:
468         clk_put(data->clk_pll_p_out1);
469 err:
470         return ret;
471 }
472 EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
473
474 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
475 int tegra_asoc_utils_set_parent (struct tegra_asoc_utils_data *data,
476                                 int is_i2s_master)
477 {
478         int ret = -ENODEV;
479
480         if (is_i2s_master) {
481                 ret = clk_set_parent(data->clk_cdev1, data->clk_pll_a_out0);
482                 if (ret) {
483                         dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
484                         return ret;
485                 }
486         } else {
487                 if(clk_get_rate(data->clk_m) == 26000000)
488                         clk_set_rate(data->clk_cdev1, 13000000);
489
490                 ret = clk_set_parent(data->clk_cdev1, data->clk_m);
491                 if (ret) {
492                         dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
493                         return ret;
494                 }
495         }
496
497         return 0;
498 }
499 EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_parent);
500 #endif
501
502 void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
503 {
504         if (!IS_ERR(data->clk_out1))
505                 clk_put(data->clk_out1);
506
507         clk_put(data->clk_cdev1);
508         /* Just to make sure that clk_cdev1 should turn off in case if it is
509          * switched on by some codec whose hw switch is not registered.*/
510         if (tegra_is_clk_enabled(data->clk_cdev1))
511                 clk_disable(data->clk_cdev1);
512
513         if (!IS_ERR(data->clk_pll_a_out0))
514                 clk_put(data->clk_pll_a_out0);
515
516         if (!IS_ERR(data->clk_pll_a))
517                 clk_put(data->clk_pll_a);
518
519         if (!IS_ERR(data->clk_pll_p_out1))
520                 clk_put(data->clk_pll_p_out1);
521 }
522 EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
523
524 #ifdef CONFIG_SWITCH
525 int tegra_asoc_switch_register(struct switch_dev *sdev)
526 {
527         int ret;
528
529         if (is_switch_registered)
530                 return -EBUSY;
531
532         ret = switch_dev_register(sdev);
533
534         if (ret >= 0) {
535                 psdev = sdev;
536                 is_switch_registered = true;
537         }
538
539         return ret;
540 }
541 EXPORT_SYMBOL_GPL(tegra_asoc_switch_register);
542
543 void tegra_asoc_switch_unregister(struct switch_dev *sdev)
544 {
545         if (!is_switch_registered)
546                 return;
547
548         switch_dev_unregister(sdev);
549         is_switch_registered = false;
550         psdev = NULL;
551 }
552 EXPORT_SYMBOL_GPL(tegra_asoc_switch_unregister);
553 #endif
554
555
556 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
557 MODULE_DESCRIPTION("Tegra ASoC utility code");
558 MODULE_LICENSE("GPL");