Merge commit 'main-jb-2012.08.03-B4' into t114-0806
[linux-2.6.git] / sound / soc / tegra / tegra30_i2s.c
1 /*
2  * tegra30_i2s.c - Tegra 30 I2S driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (c) 2010-2011, NVIDIA Corporation.
6  *
7  * Based on code copyright/by:
8  *
9  * Copyright (c) 2009-2010, NVIDIA Corporation.
10  * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
11  * Scott Peterson <speterson@nvidia.com>
12  *
13  * Copyright (C) 2010 Google, Inc.
14  * Iliyan Malchev <malchev@google.com>
15  *
16  * This program is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License
18  * version 2 as published by the Free Software Foundation.
19  *
20  * This program is distributed in the hope that it will be useful, but
21  * WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
23  * General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
28  * 02110-1301 USA
29  *
30  */
31
32 #include <linux/clk.h>
33 #include <linux/module.h>
34 #include <linux/debugfs.h>
35 #include <linux/device.h>
36 #include <linux/platform_device.h>
37 #include <linux/seq_file.h>
38 #include <linux/slab.h>
39 #include <linux/io.h>
40 #include <linux/delay.h>
41 #include <mach/iomap.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46
47 #include "tegra30_ahub.h"
48 #include "tegra30_dam.h"
49 #include "tegra30_i2s.h"
50
51 #define DRV_NAME "tegra30-i2s"
52
53 static struct tegra30_i2s  i2scont[TEGRA30_NR_I2S_IFC];
54
55 static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
56 {
57 #ifdef CONFIG_PM
58         i2s->reg_cache[reg >> 2] = val;
59 #endif
60         __raw_writel(val, i2s->regs + reg);
61 }
62
63 static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
64 {
65         return __raw_readl(i2s->regs + reg);
66 }
67
68 static void tegra30_i2s_enable_clocks(struct tegra30_i2s *i2s)
69 {
70         tegra30_ahub_enable_clocks();
71         clk_enable(i2s->clk_i2s);
72 }
73
74 static void tegra30_i2s_disable_clocks(struct tegra30_i2s *i2s)
75 {
76         clk_disable(i2s->clk_i2s);
77         tegra30_ahub_disable_clocks();
78 }
79
80 #ifdef CONFIG_DEBUG_FS
81 static int tegra30_i2s_show(struct seq_file *s, void *unused)
82 {
83 #define REG(r) { r, #r }
84         static const struct {
85                 int offset;
86                 const char *name;
87         } regs[] = {
88                 REG(TEGRA30_I2S_CTRL),
89                 REG(TEGRA30_I2S_TIMING),
90                 REG(TEGRA30_I2S_OFFSET),
91                 REG(TEGRA30_I2S_CH_CTRL),
92                 REG(TEGRA30_I2S_SLOT_CTRL),
93                 REG(TEGRA30_I2S_CIF_TX_CTRL),
94                 REG(TEGRA30_I2S_CIF_RX_CTRL),
95                 REG(TEGRA30_I2S_FLOWCTL),
96                 REG(TEGRA30_I2S_TX_STEP),
97                 REG(TEGRA30_I2S_FLOW_STATUS),
98                 REG(TEGRA30_I2S_FLOW_TOTAL),
99                 REG(TEGRA30_I2S_FLOW_OVER),
100                 REG(TEGRA30_I2S_FLOW_UNDER),
101                 REG(TEGRA30_I2S_LCOEF_1_4_0),
102                 REG(TEGRA30_I2S_LCOEF_1_4_1),
103                 REG(TEGRA30_I2S_LCOEF_1_4_2),
104                 REG(TEGRA30_I2S_LCOEF_1_4_3),
105                 REG(TEGRA30_I2S_LCOEF_1_4_4),
106                 REG(TEGRA30_I2S_LCOEF_1_4_5),
107                 REG(TEGRA30_I2S_LCOEF_2_4_0),
108                 REG(TEGRA30_I2S_LCOEF_2_4_1),
109                 REG(TEGRA30_I2S_LCOEF_2_4_2),
110         };
111 #undef REG
112
113         struct tegra30_i2s *i2s = s->private;
114         int i;
115
116         tegra30_i2s_enable_clocks(i2s);
117
118         for (i = 0; i < ARRAY_SIZE(regs); i++) {
119                 u32 val = tegra30_i2s_read(i2s, regs[i].offset);
120                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
121         }
122
123         tegra30_i2s_disable_clocks(i2s);
124
125         return 0;
126 }
127
128 static int tegra30_i2s_debug_open(struct inode *inode, struct file *file)
129 {
130         return single_open(file, tegra30_i2s_show, inode->i_private);
131 }
132
133 static const struct file_operations tegra30_i2s_debug_fops = {
134         .open    = tegra30_i2s_debug_open,
135         .read    = seq_read,
136         .llseek  = seq_lseek,
137         .release = single_release,
138 };
139
140 static void tegra30_i2s_debug_add(struct tegra30_i2s *i2s)
141 {
142         char name[] = DRV_NAME ".0";
143
144         snprintf(name, sizeof(name), DRV_NAME);
145         i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
146                                                 i2s, &tegra30_i2s_debug_fops);
147 }
148
149 static void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
150 {
151         if (i2s->debug)
152                 debugfs_remove(i2s->debug);
153 }
154 #else
155 static inline void tegra30_i2s_debug_add(struct tegra30_i2s *i2s)
156 {
157 }
158
159 static inline void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
160 {
161 }
162 #endif
163
164 int tegra30_i2s_startup(struct snd_pcm_substream *substream,
165                         struct snd_soc_dai *dai)
166 {
167         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
168         int ret;
169
170         tegra30_i2s_enable_clocks(i2s);
171
172         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
173                 /* increment the playback ref count */
174                 i2s->playback_ref_count++;
175
176                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->txcif,
177                                         &i2s->playback_dma_data.addr,
178                                         &i2s->playback_dma_data.req_sel);
179                 i2s->playback_dma_data.wrap = 4;
180                 i2s->playback_dma_data.width = 32;
181
182                 if (!i2s->is_dam_used)
183                         tegra30_ahub_set_rx_cif_source(
184                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
185                                 i2s->txcif);
186         } else {
187                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->rxcif,
188                                         &i2s->capture_dma_data.addr,
189                                         &i2s->capture_dma_data.req_sel);
190                 i2s->capture_dma_data.wrap = 4;
191                 i2s->capture_dma_data.width = 32;
192                 tegra30_ahub_set_rx_cif_source(i2s->rxcif,
193                                         TEGRA30_AHUB_TXCIF_I2S0_TX0 + i2s->id);
194         }
195
196         tegra30_i2s_disable_clocks(i2s);
197
198         return ret;
199 }
200
201 void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
202                         struct snd_soc_dai *dai)
203 {
204         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
205
206         tegra30_i2s_enable_clocks(i2s);
207
208         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
209                 if (i2s->playback_ref_count == 1)
210                         tegra30_ahub_unset_rx_cif_source(
211                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id);
212
213                 /* free the apbif dma channel*/
214                 tegra30_ahub_free_tx_fifo(i2s->txcif);
215
216                 /* decrement the playback ref count */
217                 i2s->playback_ref_count--;
218         } else {
219                 tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
220                 tegra30_ahub_free_rx_fifo(i2s->rxcif);
221         }
222
223         tegra30_i2s_disable_clocks(i2s);
224 }
225
226 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
227                                 unsigned int fmt)
228 {
229         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
230
231         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
232         case SND_SOC_DAIFMT_NB_NF:
233                 break;
234         default:
235                 return -EINVAL;
236         }
237
238         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
239         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
240         case SND_SOC_DAIFMT_CBS_CFS:
241                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
242                 break;
243         case SND_SOC_DAIFMT_CBM_CFM:
244                 break;
245         default:
246                 return -EINVAL;
247         }
248
249         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
250                                 TEGRA30_I2S_CTRL_LRCK_MASK);
251         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
252         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
253         case SND_SOC_DAIFMT_DSP_A:
254                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
255                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
256                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
257                 break;
258         case SND_SOC_DAIFMT_DSP_B:
259                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
260                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
261                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
262                 break;
263         case SND_SOC_DAIFMT_I2S:
264                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
265                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
266                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
267                 break;
268         case SND_SOC_DAIFMT_RIGHT_J:
269                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
270                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
271                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
272                 break;
273         case SND_SOC_DAIFMT_LEFT_J:
274                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
275                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
276                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
277                 break;
278         default:
279                 return -EINVAL;
280         }
281
282         return 0;
283 }
284
285 static void tegra30_i2s_set_channel_bit_count(struct tegra30_i2s *i2s,
286                                 int i2sclock, int srate)
287 {
288         int sym_bitclk, bitcnt;
289         u32 val;
290
291         bitcnt = (i2sclock / (2 * srate)) - 1;
292         sym_bitclk = !(i2sclock % (2 * srate));
293
294         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
295
296         if (!sym_bitclk)
297                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
298
299         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
300 }
301
302 static void tegra30_i2s_set_data_offset(struct tegra30_i2s *i2s)
303 {
304         u32 val;
305         int rx_data_offset = i2s->dsp_config.rx_data_offset;
306         int tx_data_offset = i2s->dsp_config.tx_data_offset;
307
308         val = (rx_data_offset <<
309                                 TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
310                         (tx_data_offset <<
311                                 TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
312
313         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
314 }
315
316 static void tegra30_i2s_set_slot_control(struct tegra30_i2s *i2s, int stream)
317 {
318         u32 val;
319         int tx_mask = i2s->dsp_config.tx_mask;
320         int rx_mask = i2s->dsp_config.rx_mask;
321
322         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
323         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
324                 val &= ~TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
325                 val |= (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
326         } else {
327                 val &= ~TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
328                 val |= (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
329         }
330
331         val &= ~TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK;
332         val |= (i2s->dsp_config.num_slots - 1)
333                         << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT;
334
335         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
336 }
337
338 static int tegra30_i2s_tdm_setup_clocks(struct device *dev,
339                                 struct tegra30_i2s *i2s, int *i2sclock)
340 {
341         int ret;
342
343         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
344
345                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
346                 if (ret) {
347                         dev_err(dev, "Can't set parent of I2S clock\n");
348                         return ret;
349                 }
350
351                 ret = clk_set_rate(i2s->clk_i2s, *i2sclock);
352                 if (ret) {
353                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
354                         return ret;
355                 }
356         } else {
357
358                 ret = clk_set_rate(i2s->clk_i2s_sync, *i2sclock);
359                 if (ret) {
360                         dev_err(dev, "Can't set I2S sync clock rate\n");
361                         return ret;
362                 }
363
364                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
365                                                 i2s->clk_i2s_sync);
366                 if (ret) {
367                         dev_err(dev, "Can't set parent of audio2x clock\n");
368                         return ret;
369                 }
370
371                 ret = clk_set_rate(i2s->clk_audio_2x, *i2sclock);
372                 if (ret) {
373                         dev_err(dev, "Can't set audio2x clock rate\n");
374                         return ret;
375                 }
376
377                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
378                 if (ret) {
379                         dev_err(dev, "Can't set parent of i2s clock\n");
380                         return ret;
381                 }
382         }
383         return ret;
384 }
385
386
387 static int tegra30_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
388                                 struct snd_pcm_hw_params *params,
389                                 struct snd_soc_dai *dai)
390 {
391         struct device *dev = substream->pcm->card->dev;
392         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
393         u32 val;
394         int i2s_client_ch, i2s_audio_ch;
395         int i2s_audio_bits = 0, i2s_client_bits = 0;
396         int i2sclock, srate;
397         int ret;
398
399         srate = params_rate(params);
400
401         i2sclock = srate *
402                                 i2s->dsp_config.num_slots *
403                                 i2s->dsp_config.slot_width;
404
405         ret = tegra30_i2s_tdm_setup_clocks(dev, i2s, &i2sclock);
406         if (ret)
407                 return -EINVAL;
408
409         /* Run ahub clock greater than i2sclock */
410         tegra30_ahub_clock_set_rate(i2sclock*2);
411
412         tegra30_i2s_enable_clocks(i2s);
413
414         tegra30_i2s_set_channel_bit_count(i2s, i2sclock*2, srate);
415
416         i2s_client_ch = i2s->dsp_config.num_slots;
417         i2s_audio_ch = i2s->dsp_config.num_slots;
418
419         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
420         switch (i2s->dsp_config.slot_width) {
421         case 16:
422                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_16;
423                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_16;
424                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
425                 break;
426         case 32:
427                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_32;
428                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_32;
429                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_32;
430                 break;
431         default:
432                 dev_err(dev, "unknown slot_width %d\n",
433                                 i2s->dsp_config.slot_width);
434                 return -EINVAL;
435         }
436
437         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
438                         ((i2s_audio_ch - 1) <<
439                          TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
440                         ((i2s_client_ch - 1) <<
441                          TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
442                         (i2s_audio_bits <<
443                          TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
444                         (i2s_client_bits <<
445                          TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT);
446
447         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
448                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
449                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
450
451                 tegra30_ahub_set_tx_cif_channels(i2s->txcif,
452                                                 i2s_audio_ch,
453                                                 i2s_client_ch);
454                 tegra30_ahub_set_tx_cif_bits(i2s->txcif,
455                                                 i2s_audio_bits,
456                                                 i2s_client_bits);
457                 tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif, 0);
458
459         } else {
460                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
461                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
462
463                 tegra30_ahub_set_rx_cif_channels(i2s->rxcif,
464                                                 i2s_audio_ch,
465                                                 i2s_client_ch);
466                 tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
467                                                 i2s_audio_bits,
468                                                 i2s_client_bits);
469                 tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif, 0);
470         }
471
472         tegra30_i2s_set_slot_control(i2s, substream->stream);
473
474         tegra30_i2s_set_data_offset(i2s);
475
476         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK;
477         i2s->reg_ch_ctrl |= (i2s->dsp_config.slot_width - 1) <<
478                         TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT;
479         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
480
481         tegra30_i2s_disable_clocks(i2s);
482
483         return 0;
484 }
485
486 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
487                                 struct snd_pcm_hw_params *params,
488                                 struct snd_soc_dai *dai)
489 {
490         struct device *dev = substream->pcm->card->dev;
491         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
492         u32 val;
493         int ret, sample_size, srate, i2sclock, bitcnt, sym_bitclk;
494         int i2s_client_ch;
495
496         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
497         switch (params_format(params)) {
498         case SNDRV_PCM_FORMAT_S16_LE:
499                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
500                 sample_size = 16;
501                 break;
502         default:
503                 return -EINVAL;
504         }
505
506         /* TDM mode */
507         if ((i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) &&
508                 (i2s->dsp_config.slot_width > 2))
509                 return tegra30_i2s_tdm_hw_params(substream, params, dai);
510
511         srate = params_rate(params);
512
513         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
514                 i2sclock = srate * params_channels(params) * sample_size;
515
516                 /* Additional "* 4" is needed for FSYNC mode */
517                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
518                         i2sclock *= 4;
519
520 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
521                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
522                         i2sclock = 13000000;
523                         __raw_writel(((0x3 << 30) | (0x1 << 28) | 0x0),
524                                 IO_ADDRESS(TEGRA_CLK_RESET_BASE)+0x1d8);
525                 } else {
526                         i2sclock = 13000000/2;
527                         __raw_writel(((0x3 << 30) | (0x1 << 28) | 0x1),
528                                 IO_ADDRESS(TEGRA_CLK_RESET_BASE)+0x1d8);
529                 }
530 #else
531                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
532                 if (ret) {
533                         dev_err(dev, "Can't set parent of I2S clock\n");
534                         return ret;
535                 }
536
537                 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
538                 if (ret) {
539                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
540                         return ret;
541                 }
542 #endif
543                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) {
544                         bitcnt = (i2sclock / srate) - 1;
545                         sym_bitclk = !(i2sclock % srate);
546                 } else {
547                         bitcnt = (i2sclock / (2 * srate)) - 1;
548                         sym_bitclk = !(i2sclock % (2 * srate));
549                 }
550                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
551
552                 if (!sym_bitclk)
553                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
554
555                 tegra30_i2s_enable_clocks(i2s);
556
557                 tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
558         } else {
559                 i2sclock = srate * params_channels(params) * sample_size;
560
561                 /* Additional "* 2" is needed for FSYNC mode */
562                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
563                         i2sclock *= 2;
564
565                 ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock);
566                 if (ret) {
567                         dev_err(dev, "Can't set I2S sync clock rate\n");
568                         return ret;
569                 }
570
571                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
572                                                 i2s->clk_i2s_sync);
573                 if (ret) {
574                         dev_err(dev, "Can't set parent of audio2x clock\n");
575                         return ret;
576                 }
577
578                 ret = clk_set_rate(i2s->clk_audio_2x, i2sclock);
579                 if (ret) {
580                         dev_err(dev, "Can't set I2S sync clock rate\n");
581                         return ret;
582                 }
583
584                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
585                 if (ret) {
586                         dev_err(dev, "Can't set parent of audio2x clock\n");
587                         return ret;
588                 }
589
590                 tegra30_i2s_enable_clocks(i2s);
591         }
592
593         i2s_client_ch = (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) ?
594                         params_channels(params) : 2;
595
596         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
597               ((params_channels(params) - 1) <<
598                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
599               ((i2s_client_ch - 1) <<
600                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
601               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
602               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
603
604         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
605                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
606                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
607
608                 tegra30_ahub_set_tx_cif_channels(i2s->txcif,
609                                                  params_channels(params),
610                                                  params_channels(params));
611         } else {
612                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
613                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
614
615                 tegra30_ahub_set_rx_cif_channels(i2s->rxcif,
616                                                  params_channels(params),
617                                                  params_channels(params));
618         }
619
620         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
621               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
622         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
623
624         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
625
626         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
627         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
628                 val &= ~TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
629                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
630         } else {
631                 val &= ~TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
632                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
633         }
634         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
635
636         tegra30_i2s_disable_clocks(i2s);
637
638         return 0;
639 }
640
641 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
642 {
643         tegra30_ahub_enable_tx_fifo(i2s->txcif);
644         /* if this is the only user of i2s tx then enable it*/
645         if (i2s->playback_ref_count == 1) {
646                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
647                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
648         }
649 }
650
651 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
652 {
653         int dcnt = 10;
654         /* if this is the only user of i2s tx then disable it*/
655         tegra30_ahub_disable_tx_fifo(i2s->txcif);
656         if (i2s->playback_ref_count == 1) {
657                 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
658                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
659         }
660         while (tegra30_ahub_tx_fifo_is_enabled(i2s->id) && dcnt--)
661                 udelay(100);
662 }
663
664 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
665 {
666         tegra30_ahub_enable_rx_fifo(i2s->rxcif);
667         if (!i2s->is_call_mode_rec) {
668                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
669                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
670         }
671 }
672
673 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
674 {
675         int dcnt = 10;
676         tegra30_ahub_disable_rx_fifo(i2s->rxcif);
677         if (!i2s->is_call_mode_rec) {
678                 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
679                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
680         }
681         while (tegra30_ahub_rx_fifo_is_enabled(i2s->id) && dcnt--)
682                 udelay(100);
683 }
684
685 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
686                                 struct snd_soc_dai *dai)
687 {
688         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
689
690         switch (cmd) {
691         case SNDRV_PCM_TRIGGER_START:
692         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
693         case SNDRV_PCM_TRIGGER_RESUME:
694                 tegra30_i2s_enable_clocks(i2s);
695                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
696                         tegra30_i2s_start_playback(i2s);
697                 else
698                         tegra30_i2s_start_capture(i2s);
699                 break;
700         case SNDRV_PCM_TRIGGER_STOP:
701         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
702         case SNDRV_PCM_TRIGGER_SUSPEND:
703                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
704                         tegra30_i2s_stop_playback(i2s);
705                 else
706                         tegra30_i2s_stop_capture(i2s);
707                 tegra30_i2s_disable_clocks(i2s);
708                 break;
709         default:
710                 return -EINVAL;
711         }
712
713         return 0;
714 }
715
716 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
717 {
718         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
719 #ifdef CONFIG_PM
720         int i;
721 #endif
722
723         dai->capture_dma_data = &i2s->capture_dma_data;
724         dai->playback_dma_data = &i2s->playback_dma_data;
725
726 #ifdef CONFIG_PM
727         tegra30_i2s_enable_clocks(i2s);
728
729         /*cache the POR values of i2s regs*/
730         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
731                 i2s->reg_cache[i] = tegra30_i2s_read(i2s, i<<2);
732
733         tegra30_i2s_disable_clocks(i2s);
734 #endif
735
736         /* Default values for DSP mode */
737         i2s->dsp_config.num_slots = 1;
738         i2s->dsp_config.slot_width = 2;
739         i2s->dsp_config.tx_mask = 1;
740         i2s->dsp_config.rx_mask = 1;
741         i2s->dsp_config.rx_data_offset = 1;
742         i2s->dsp_config.tx_data_offset = 1;
743
744
745         return 0;
746 }
747
748 int tegra30_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
749                                                         unsigned int tx_mask,
750                                                         unsigned int rx_mask,
751                                                         int slots,
752                                                         int slot_width)
753 {
754         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
755
756         i2s->dsp_config.num_slots = slots;
757         i2s->dsp_config.slot_width = slot_width;
758         i2s->dsp_config.tx_mask = tx_mask;
759         i2s->dsp_config.rx_mask = rx_mask;
760         i2s->dsp_config.rx_data_offset = 0;
761         i2s->dsp_config.tx_data_offset = 0;
762
763         return 0;
764 }
765
766 #ifdef CONFIG_PM
767 int tegra30_i2s_resume(struct snd_soc_dai *cpu_dai)
768 {
769         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
770         int i, ret = 0;
771
772         tegra30_i2s_enable_clocks(i2s);
773
774         /*restore the i2s regs*/
775         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
776                 tegra30_i2s_write(i2s, i<<2, i2s->reg_cache[i]);
777
778         tegra30_ahub_apbif_resume();
779
780         tegra30_i2s_disable_clocks(i2s);
781
782         if (i2s->dam_ch_refcount)
783                 ret = tegra30_dam_resume(i2s->dam_ifc);
784
785         return ret;
786 }
787 #else
788 #define tegra30_i2s_resume NULL
789 #endif
790
791 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
792         .startup        = tegra30_i2s_startup,
793         .shutdown       = tegra30_i2s_shutdown,
794         .set_fmt        = tegra30_i2s_set_fmt,
795         .hw_params      = tegra30_i2s_hw_params,
796         .trigger        = tegra30_i2s_trigger,
797         .set_tdm_slot = tegra30_i2s_set_tdm_slot,
798 };
799
800 #define TEGRA30_I2S_DAI(id) \
801         { \
802                 .name = DRV_NAME "." #id, \
803                 .probe = tegra30_i2s_probe, \
804                 .resume = tegra30_i2s_resume, \
805                 .playback = { \
806                         .channels_min = 1, \
807                         .channels_max = 16, \
808                         .rates = SNDRV_PCM_RATE_8000_96000, \
809                         .formats = SNDRV_PCM_FMTBIT_S16_LE, \
810                 }, \
811                 .capture = { \
812                         .channels_min = 1, \
813                         .channels_max = 16, \
814                         .rates = SNDRV_PCM_RATE_8000_96000, \
815                         .formats = SNDRV_PCM_FMTBIT_S16_LE, \
816                 }, \
817                 .ops = &tegra30_i2s_dai_ops, \
818                 .symmetric_rates = 1, \
819         }
820
821 struct snd_soc_dai_driver tegra30_i2s_dai[] = {
822         TEGRA30_I2S_DAI(0),
823         TEGRA30_I2S_DAI(1),
824         TEGRA30_I2S_DAI(2),
825         TEGRA30_I2S_DAI(3),
826         TEGRA30_I2S_DAI(4),
827 };
828
829 static int configure_baseband_i2s(struct tegra30_i2s  *i2s, int is_i2smaster,
830                 int is_formatdsp, int channels, int rate, int bitsize)
831 {
832         u32 val;
833         int i2sclock, bitcnt, ret;
834
835         i2sclock = rate * channels * bitsize * 2;
836
837         /* additional 8 for baseband */
838         if (is_formatdsp)
839                 i2sclock *= 8;
840
841         if (is_i2smaster) {
842                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
843                 if (ret) {
844                         pr_err("Can't set parent of I2S clock\n");
845                         return ret;
846                 }
847
848                 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
849                 if (ret) {
850                         pr_err("Can't set I2S clock rate: %d\n", ret);
851                         return ret;
852                 }
853         } else {
854                 ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock);
855                 if (ret) {
856                         pr_err("Can't set I2S sync clock rate\n");
857                         return ret;
858                 }
859
860                 ret = clk_set_rate(i2s->clk_audio_2x, i2sclock);
861                 if (ret) {
862                         pr_err("Can't set I2S sync clock rate\n");
863                         return ret;
864                 }
865
866                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
867                 if (ret) {
868                         pr_err("Can't set parent of audio2x clock\n");
869                         return ret;
870                 }
871         }
872
873         tegra30_i2s_enable_clocks(i2s);
874
875         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
876                                         TEGRA30_I2S_CTRL_LRCK_MASK |
877                                         TEGRA30_I2S_CTRL_MASTER_ENABLE);
878         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
879
880         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
881
882         if (is_i2smaster)
883                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
884
885         if (is_formatdsp) {
886                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
887                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
888                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
889         } else {
890                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
891                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
892                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
893         }
894
895         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
896
897         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
898         val &= ~(TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK |
899                 TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK);
900         val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT |
901                 1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
902         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
903
904         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
905               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
906         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
907
908         if (is_formatdsp) {
909                 bitcnt = (i2sclock/rate) - 1;
910                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
911                 if (i2sclock % (rate))
912                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
913         } else {
914                 bitcnt = (i2sclock/(2*rate)) - 1;
915                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
916                 if (i2sclock % (2*rate))
917                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
918         }
919
920         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
921
922         /* configure the i2s cif*/
923         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
924               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
925               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
926               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
927               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
928         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
929         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
930
931         val &= ~TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK;
932         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
933         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
934
935         return 0;
936 }
937
938 static int configure_dam(struct tegra30_i2s  *i2s, int out_channel,
939                 int out_rate, int out_bitsize, int in_channels,
940                 int in_rate, int in_bitsize)
941 {
942
943         if (!i2s->dam_ch_refcount)
944                 i2s->dam_ifc = tegra30_dam_allocate_controller();
945
946         tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
947         i2s->dam_ch_refcount++;
948         tegra30_dam_enable_clock(i2s->dam_ifc);
949         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHOUT, out_rate);
950         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
951                                 in_rate);
952         tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
953         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
954                         in_channels, in_bitsize, 1, 16);
955         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
956                         out_channel, out_bitsize, out_channel, out_bitsize);
957
958         return 0;
959 }
960
961
962 int tegra30_make_voice_call_connections(struct codec_config *codec_info,
963                                 struct codec_config *bb_info)
964 {
965         struct tegra30_i2s  *codec_i2s;
966         struct tegra30_i2s  *bb_i2s;
967
968         codec_i2s = &i2scont[codec_info->i2s_id];
969         bb_i2s = &i2scont[bb_info->i2s_id];
970
971         /* increment the codec i2s playback ref count */
972         codec_i2s->playback_ref_count++;
973         bb_i2s->playback_ref_count++;
974
975         /*Configure codec i2s*/
976         configure_baseband_i2s(codec_i2s, codec_info->is_i2smaster,
977                 codec_info->is_format_dsp, codec_info->channels,
978                 codec_info->rate, codec_info->bitsize);
979
980         /*Configure bb i2s*/
981         configure_baseband_i2s(bb_i2s, bb_info->is_i2smaster,
982                 bb_info->is_format_dsp, bb_info->channels,
983                 bb_info->rate, bb_info->bitsize);
984
985         /*configure codec dam*/
986         configure_dam(codec_i2s, codec_info->channels,
987                 codec_info->rate, codec_info->bitsize, bb_info->channels,
988                 bb_info->rate, bb_info->bitsize);
989
990         /*configure bb dam*/
991         configure_dam(bb_i2s, bb_info->channels,
992                 bb_info->rate, bb_info->bitsize, codec_info->channels,
993                 codec_info->rate, codec_info->bitsize);
994
995         /*make ahub connections*/
996
997         /* if this is the only user of i2s tx then make ahub i2s rx connection*/
998         if (codec_i2s->playback_ref_count == 1) {
999                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1000                                 codec_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
1001                                 codec_i2s->dam_ifc);
1002         }
1003
1004         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1005                         bb_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
1006                         bb_i2s->dam_ifc);
1007         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1008                 (codec_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1009                 bb_info->i2s_id);
1010         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1011                 (bb_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1012                 codec_info->i2s_id);
1013
1014         /*enable dam and i2s*/
1015         tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1016                 TEGRA30_DAM_CHIN0_SRC);
1017         tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1018                 TEGRA30_DAM_CHIN0_SRC);
1019
1020         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1021         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1022         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1023                 codec_i2s->reg_ctrl);
1024         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1025         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1026         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1027                 bb_i2s->reg_ctrl);
1028
1029         return 0;
1030 }
1031
1032 int tegra30_break_voice_call_connections(struct codec_config *codec_info,
1033                                 struct codec_config *bb_info)
1034 {
1035         struct tegra30_i2s  *codec_i2s;
1036         struct tegra30_i2s  *bb_i2s;
1037         int dcnt = 10;
1038
1039         codec_i2s = &i2scont[codec_info->i2s_id];
1040         bb_i2s = &i2scont[bb_info->i2s_id];
1041
1042         /*Disable Codec I2S RX (TX to ahub)*/
1043         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1044         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1045
1046         while (tegra30_ahub_rx_fifo_is_enabled(codec_i2s->id) && dcnt--)
1047                 udelay(100);
1048
1049         dcnt = 10;
1050
1051         /*Disable baseband DAM*/
1052         tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_DISABLE,
1053                         TEGRA30_DAM_CHIN0_SRC);
1054         tegra30_dam_free_channel(bb_i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
1055         bb_i2s->dam_ch_refcount--;
1056         if (!bb_i2s->dam_ch_refcount)
1057                 tegra30_dam_free_controller(bb_i2s->dam_ifc);
1058
1059         /*Disable baseband I2S TX (RX from ahub)*/
1060         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1061         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1062
1063         while (tegra30_ahub_tx_fifo_is_enabled(bb_i2s->id) && dcnt--)
1064                 udelay(100);
1065
1066         dcnt = 10;
1067
1068         /*Disable baseband I2S RX (TX to ahub)*/
1069         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1070         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1071
1072         while (tegra30_ahub_rx_fifo_is_enabled(bb_i2s->id) && dcnt--)
1073                 udelay(100);
1074
1075         dcnt = 10;
1076
1077         /*Disable Codec DAM*/
1078         tegra30_dam_enable(codec_i2s->dam_ifc,
1079                 TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
1080         tegra30_dam_free_channel(codec_i2s->dam_ifc,
1081                 TEGRA30_DAM_CHIN0_SRC);
1082         codec_i2s->dam_ch_refcount--;
1083         if (!codec_i2s->dam_ch_refcount)
1084                 tegra30_dam_free_controller(codec_i2s->dam_ifc);
1085
1086         /*Disable Codec I2S TX (RX from ahub)*/
1087         if (codec_i2s->playback_ref_count == 1)
1088                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1089
1090         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1091
1092         while (tegra30_ahub_tx_fifo_is_enabled(codec_i2s->id) && dcnt--)
1093                 udelay(100);
1094
1095         dcnt = 10;
1096
1097         /* Disconnect the ahub connections */
1098         /* If this is the only user of i2s tx then break ahub
1099         i2s rx connection */
1100         if (codec_i2s->playback_ref_count == 1)
1101                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
1102                         + codec_info->i2s_id);
1103
1104         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
1105                                 + bb_info->i2s_id);
1106         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1107                                 + (codec_i2s->dam_ifc*2));
1108         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1109                                 + (bb_i2s->dam_ifc*2));
1110
1111         /* Decrement the codec and bb i2s playback ref count */
1112         codec_i2s->playback_ref_count--;
1113         bb_i2s->playback_ref_count--;
1114
1115         /* Disable the clocks */
1116         tegra30_i2s_disable_clocks(codec_i2s);
1117         tegra30_i2s_disable_clocks(bb_i2s);
1118         tegra30_dam_disable_clock(codec_i2s->dam_ifc);
1119         tegra30_dam_disable_clock(bb_i2s->dam_ifc);
1120
1121         return 0;
1122 }
1123
1124 static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
1125 {
1126         struct tegra30_i2s *i2s;
1127         struct resource *mem, *memregion;
1128         int ret;
1129
1130         if ((pdev->id < 0) ||
1131                 (pdev->id >= ARRAY_SIZE(tegra30_i2s_dai))) {
1132                 dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
1133                 return -EINVAL;
1134         }
1135
1136         i2s = &i2scont[pdev->id];
1137         dev_set_drvdata(&pdev->dev, i2s);
1138         i2s->id = pdev->id;
1139
1140         i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
1141         if (IS_ERR(i2s->clk_i2s)) {
1142                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
1143                 ret = PTR_ERR(i2s->clk_i2s);
1144                 goto exit;
1145         }
1146         i2s->clk_i2s_sync = clk_get(&pdev->dev, "ext_audio_sync");
1147         if (IS_ERR(i2s->clk_i2s_sync)) {
1148                 dev_err(&pdev->dev, "Can't retrieve i2s_sync clock\n");
1149                 ret = PTR_ERR(i2s->clk_i2s_sync);
1150                 goto err_i2s_clk_put;
1151         }
1152
1153         i2s->clk_audio_2x = clk_get(&pdev->dev, "audio_sync_2x");
1154         if (IS_ERR(i2s->clk_audio_2x)) {
1155                 dev_err(&pdev->dev, "Can't retrieve audio 2x clock\n");
1156                 ret = PTR_ERR(i2s->clk_audio_2x);
1157                 goto err_i2s_sync_clk_put;
1158         }
1159
1160         i2s->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
1161         if (IS_ERR(i2s->clk_pll_a_out0)) {
1162                 dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
1163                 ret = PTR_ERR(i2s->clk_pll_a_out0);
1164                 goto err_audio_2x_clk_put;
1165         }
1166
1167         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1168         if (!mem) {
1169                 dev_err(&pdev->dev, "No memory resource\n");
1170                 ret = -ENODEV;
1171                 goto err_pll_a_out0_clk_put;
1172         }
1173
1174         memregion = request_mem_region(mem->start, resource_size(mem),
1175                                         DRV_NAME);
1176         if (!memregion) {
1177                 dev_err(&pdev->dev, "Memory region already claimed\n");
1178                 ret = -EBUSY;
1179                 goto err_pll_a_out0_clk_put;
1180         }
1181
1182         i2s->regs = ioremap(mem->start, resource_size(mem));
1183         if (!i2s->regs) {
1184                 dev_err(&pdev->dev, "ioremap failed\n");
1185                 ret = -ENOMEM;
1186                 goto err_release;
1187         }
1188
1189         ret = snd_soc_register_dai(&pdev->dev, &tegra30_i2s_dai[pdev->id]);
1190         if (ret) {
1191                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
1192                 ret = -ENOMEM;
1193                 goto err_unmap;
1194         }
1195
1196         tegra30_i2s_debug_add(i2s);
1197
1198         return 0;
1199
1200 err_unmap:
1201         iounmap(i2s->regs);
1202 err_release:
1203         release_mem_region(mem->start, resource_size(mem));
1204 err_pll_a_out0_clk_put:
1205         clk_put(i2s->clk_pll_a_out0);
1206 err_audio_2x_clk_put:
1207         clk_put(i2s->clk_audio_2x);
1208 err_i2s_sync_clk_put:
1209         clk_put(i2s->clk_i2s_sync);
1210 err_i2s_clk_put:
1211         clk_put(i2s->clk_i2s);
1212 exit:
1213         return ret;
1214 }
1215
1216 static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
1217 {
1218         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
1219         struct resource *res;
1220
1221         snd_soc_unregister_dai(&pdev->dev);
1222
1223         tegra30_i2s_debug_remove(i2s);
1224
1225         iounmap(i2s->regs);
1226
1227         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1228         release_mem_region(res->start, resource_size(res));
1229
1230         clk_put(i2s->clk_pll_a_out0);
1231         clk_put(i2s->clk_audio_2x);
1232         clk_put(i2s->clk_i2s_sync);
1233         clk_put(i2s->clk_i2s);
1234
1235         kfree(i2s);
1236
1237         return 0;
1238 }
1239
1240 static struct platform_driver tegra30_i2s_driver = {
1241         .driver = {
1242                 .name = DRV_NAME,
1243                 .owner = THIS_MODULE,
1244         },
1245         .probe = tegra30_i2s_platform_probe,
1246         .remove = __devexit_p(tegra30_i2s_platform_remove),
1247 };
1248
1249 static int __init snd_tegra30_i2s_init(void)
1250 {
1251         return platform_driver_register(&tegra30_i2s_driver);
1252 }
1253 module_init(snd_tegra30_i2s_init);
1254
1255 static void __exit snd_tegra30_i2s_exit(void)
1256 {
1257         platform_driver_unregister(&tegra30_i2s_driver);
1258 }
1259 module_exit(snd_tegra30_i2s_exit);
1260
1261 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
1262 MODULE_DESCRIPTION("Tegra 30 I2S ASoC driver");
1263 MODULE_LICENSE("GPL");
1264 MODULE_ALIAS("platform:" DRV_NAME);