soc: codecs: rt5639: Implement i2c shutdown
[linux-2.6.git] / sound / soc / tegra / tegra30_i2s.c
1 /*
2  * tegra30_i2s.c - Tegra 30 I2S driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (c) 2010-2011, NVIDIA Corporation.
6  *
7  * Based on code copyright/by:
8  *
9  * Copyright (c) 2009-2013, NVIDIA Corporation.
10  * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
11  * Scott Peterson <speterson@nvidia.com>
12  *
13  * Copyright (C) 2010 Google, Inc.
14  * Iliyan Malchev <malchev@google.com>
15  *
16  * This program is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License
18  * version 2 as published by the Free Software Foundation.
19  *
20  * This program is distributed in the hope that it will be useful, but
21  * WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
23  * General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
28  * 02110-1301 USA
29  *
30  */
31
32 #include <linux/clk.h>
33 #include <linux/module.h>
34 #include <linux/debugfs.h>
35 #include <linux/device.h>
36 #include <linux/platform_device.h>
37 #include <linux/seq_file.h>
38 #include <linux/slab.h>
39 #include <linux/io.h>
40 #include <linux/delay.h>
41 #include <mach/iomap.h>
42 #include <mach/tegra_asoc_pdata.h>
43 #include <sound/core.h>
44 #include <sound/pcm.h>
45 #include <sound/pcm_params.h>
46 #include <sound/soc.h>
47
48 #include "tegra30_ahub.h"
49 #include "tegra30_dam.h"
50 #include "tegra30_i2s.h"
51
52 #define DRV_NAME "tegra30-i2s"
53
54 static struct tegra30_i2s  i2scont[TEGRA30_NR_I2S_IFC];
55
56 static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
57 {
58 #ifdef CONFIG_PM
59         i2s->reg_cache[reg >> 2] = val;
60 #endif
61         __raw_writel(val, i2s->regs + reg);
62 }
63
64 static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
65 {
66         return __raw_readl(i2s->regs + reg);
67 }
68
69 static void tegra30_i2s_enable_clocks(struct tegra30_i2s *i2s)
70 {
71         tegra30_ahub_enable_clocks();
72         clk_enable(i2s->clk_i2s);
73 }
74
75 static void tegra30_i2s_disable_clocks(struct tegra30_i2s *i2s)
76 {
77         clk_disable(i2s->clk_i2s);
78         tegra30_ahub_disable_clocks();
79 }
80
81 #ifdef CONFIG_DEBUG_FS
82 static int tegra30_i2s_show(struct seq_file *s, void *unused)
83 {
84 #define REG(r) { r, #r }
85         static const struct {
86                 int offset;
87                 const char *name;
88         } regs[] = {
89                 REG(TEGRA30_I2S_CTRL),
90                 REG(TEGRA30_I2S_TIMING),
91                 REG(TEGRA30_I2S_OFFSET),
92                 REG(TEGRA30_I2S_CH_CTRL),
93                 REG(TEGRA30_I2S_SLOT_CTRL),
94                 REG(TEGRA30_I2S_CIF_TX_CTRL),
95                 REG(TEGRA30_I2S_CIF_RX_CTRL),
96                 REG(TEGRA30_I2S_FLOWCTL),
97                 REG(TEGRA30_I2S_TX_STEP),
98                 REG(TEGRA30_I2S_FLOW_STATUS),
99                 REG(TEGRA30_I2S_FLOW_TOTAL),
100                 REG(TEGRA30_I2S_FLOW_OVER),
101                 REG(TEGRA30_I2S_FLOW_UNDER),
102                 REG(TEGRA30_I2S_LCOEF_1_4_0),
103                 REG(TEGRA30_I2S_LCOEF_1_4_1),
104                 REG(TEGRA30_I2S_LCOEF_1_4_2),
105                 REG(TEGRA30_I2S_LCOEF_1_4_3),
106                 REG(TEGRA30_I2S_LCOEF_1_4_4),
107                 REG(TEGRA30_I2S_LCOEF_1_4_5),
108                 REG(TEGRA30_I2S_LCOEF_2_4_0),
109                 REG(TEGRA30_I2S_LCOEF_2_4_1),
110                 REG(TEGRA30_I2S_LCOEF_2_4_2),
111 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
112                 REG(TEGRA30_I2S_SLOT_CTRL2),
113 #endif
114         };
115 #undef REG
116
117         struct tegra30_i2s *i2s = s->private;
118         int i;
119
120         tegra30_i2s_enable_clocks(i2s);
121
122         for (i = 0; i < ARRAY_SIZE(regs); i++) {
123                 u32 val = tegra30_i2s_read(i2s, regs[i].offset);
124                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
125         }
126
127         tegra30_i2s_disable_clocks(i2s);
128
129         return 0;
130 }
131
132 static int tegra30_i2s_debug_open(struct inode *inode, struct file *file)
133 {
134         return single_open(file, tegra30_i2s_show, inode->i_private);
135 }
136
137 static const struct file_operations tegra30_i2s_debug_fops = {
138         .open    = tegra30_i2s_debug_open,
139         .read    = seq_read,
140         .llseek  = seq_lseek,
141         .release = single_release,
142 };
143
144 static void tegra30_i2s_debug_add(struct tegra30_i2s *i2s, int id)
145 {
146         char name[] = DRV_NAME ".0";
147
148         snprintf(name, sizeof(name), DRV_NAME".%1d", id);
149         i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
150                                                 i2s, &tegra30_i2s_debug_fops);
151 }
152
153 static void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
154 {
155         if (i2s->debug)
156                 debugfs_remove(i2s->debug);
157 }
158 #else
159 static inline void tegra30_i2s_debug_add(struct tegra30_i2s *i2s, int id)
160 {
161 }
162
163 static inline void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
164 {
165 }
166 #endif
167
168 int tegra30_i2s_startup(struct snd_pcm_substream *substream,
169                         struct snd_soc_dai *dai)
170 {
171         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
172         int ret;
173
174         tegra30_i2s_enable_clocks(i2s);
175
176         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
177                 /* increment the playback ref count */
178                 i2s->playback_ref_count++;
179
180                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->txcif,
181                                         &i2s->playback_dma_data.addr,
182                                         &i2s->playback_dma_data.req_sel);
183                 i2s->playback_dma_data.wrap = 4;
184                 i2s->playback_dma_data.width = 32;
185
186                 if (!i2s->is_dam_used)
187                         tegra30_ahub_set_rx_cif_source(
188                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
189                                 i2s->txcif);
190         } else {
191                 i2s->capture_ref_count++;
192                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->rxcif,
193                                         &i2s->capture_dma_data.addr,
194                                         &i2s->capture_dma_data.req_sel);
195                 i2s->capture_dma_data.wrap = 4;
196                 i2s->capture_dma_data.width = 32;
197                 tegra30_ahub_set_rx_cif_source(i2s->rxcif,
198                                         TEGRA30_AHUB_TXCIF_I2S0_TX0 + i2s->id);
199         }
200
201         tegra30_i2s_disable_clocks(i2s);
202
203         return ret;
204 }
205
206 void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
207                         struct snd_soc_dai *dai)
208 {
209         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
210
211         tegra30_i2s_enable_clocks(i2s);
212
213         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
214                 if (i2s->playback_ref_count == 1)
215                         tegra30_ahub_unset_rx_cif_source(
216                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id);
217
218                 /* free the apbif dma channel*/
219                 tegra30_ahub_free_tx_fifo(i2s->txcif);
220
221                 /* decrement the playback ref count */
222                 i2s->playback_ref_count--;
223         } else {
224                 if (i2s->capture_ref_count == 1)
225                         tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
226                 tegra30_ahub_free_rx_fifo(i2s->rxcif);
227                 i2s->capture_ref_count--;
228         }
229
230         tegra30_i2s_disable_clocks(i2s);
231 }
232
233 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
234                                 unsigned int fmt)
235 {
236         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
237
238         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
239         case SND_SOC_DAIFMT_NB_NF:
240                 break;
241         default:
242                 return -EINVAL;
243         }
244
245         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
246         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
247         case SND_SOC_DAIFMT_CBS_CFS:
248                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
249                 break;
250         case SND_SOC_DAIFMT_CBM_CFM:
251                 break;
252         default:
253                 return -EINVAL;
254         }
255
256         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
257                                 TEGRA30_I2S_CTRL_LRCK_MASK);
258         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
259         i2s->daifmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
260         switch (i2s->daifmt) {
261         case SND_SOC_DAIFMT_DSP_A:
262                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
263                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
264                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
265                 break;
266         case SND_SOC_DAIFMT_DSP_B:
267                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
268                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
269                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
270                 break;
271         case SND_SOC_DAIFMT_I2S:
272                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
273                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
274                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
275                 break;
276         case SND_SOC_DAIFMT_RIGHT_J:
277                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
278                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
279                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
280                 break;
281         case SND_SOC_DAIFMT_LEFT_J:
282                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
283                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
284                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
285                 break;
286         default:
287                 return -EINVAL;
288         }
289         return 0;
290 }
291
292 static void tegra30_i2s_set_channel_bit_count(struct tegra30_i2s *i2s,
293                                 int i2sclock, int srate)
294 {
295         int sym_bitclk, bitcnt;
296         u32 val;
297
298         bitcnt = (i2sclock / (2 * srate)) - 1;
299         sym_bitclk = !(i2sclock % (2 * srate));
300
301         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
302
303         if (!sym_bitclk)
304                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
305
306         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
307 }
308
309 static void tegra30_i2s_set_data_offset(struct tegra30_i2s *i2s)
310 {
311         u32 val;
312         int rx_data_offset = i2s->dsp_config.rx_data_offset;
313         int tx_data_offset = i2s->dsp_config.tx_data_offset;
314
315         val = (rx_data_offset <<
316                                 TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
317                         (tx_data_offset <<
318                                 TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
319
320         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
321 }
322
323 static void tegra30_i2s_set_slot_control(struct tegra30_i2s *i2s, int stream)
324 {
325         u32 val;
326         int tx_mask = i2s->dsp_config.tx_mask;
327         int rx_mask = i2s->dsp_config.rx_mask;
328
329         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
330         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
331                 val &= ~TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
332                 val |= (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
333         } else {
334                 val &= ~TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
335                 val |= (rx_mask << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
336         }
337
338         val &= ~TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK;
339         val |= (i2s->dsp_config.num_slots - 1)
340                         << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT;
341
342         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
343 }
344
345 static int tegra30_i2s_tdm_setup_clocks(struct device *dev,
346                                 struct tegra30_i2s *i2s, int *i2sclock)
347 {
348         int ret;
349
350         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
351
352                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
353                 if (ret) {
354                         dev_err(dev, "Can't set parent of I2S clock\n");
355                         return ret;
356                 }
357
358                 ret = clk_set_rate(i2s->clk_i2s, *i2sclock);
359                 if (ret) {
360                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
361                         return ret;
362                 }
363         } else {
364
365                 ret = clk_set_rate(i2s->clk_i2s_sync, *i2sclock);
366                 if (ret) {
367                         dev_err(dev, "Can't set I2S sync clock rate\n");
368                         return ret;
369                 }
370
371                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
372                                                 i2s->clk_i2s_sync);
373                 if (ret) {
374                         dev_err(dev, "Can't set parent of audio2x clock\n");
375                         return ret;
376                 }
377
378                 ret = clk_set_rate(i2s->clk_audio_2x, *i2sclock);
379                 if (ret) {
380                         dev_err(dev, "Can't set audio2x clock rate\n");
381                         return ret;
382                 }
383
384                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
385                 if (ret) {
386                         dev_err(dev, "Can't set parent of i2s clock\n");
387                         return ret;
388                 }
389         }
390         return ret;
391 }
392
393
394 static int tegra30_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
395                                 struct snd_pcm_hw_params *params,
396                                 struct snd_soc_dai *dai)
397 {
398         struct device *dev = substream->pcm->card->dev;
399         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
400         u32 val;
401         int i2s_client_ch, i2s_audio_ch;
402         int i2s_audio_bits = 0, i2s_client_bits = 0;
403         int i2sclock, srate;
404         int ret;
405
406         srate = params_rate(params);
407
408         i2sclock = srate *
409                                 i2s->dsp_config.num_slots *
410                                 i2s->dsp_config.slot_width;
411
412         ret = tegra30_i2s_tdm_setup_clocks(dev, i2s, &i2sclock);
413         if (ret)
414                 return -EINVAL;
415
416         /* Run ahub clock greater than i2sclock */
417         tegra30_ahub_clock_set_rate(i2sclock*2);
418
419         tegra30_i2s_enable_clocks(i2s);
420
421         tegra30_i2s_set_channel_bit_count(i2s, i2sclock*2, srate);
422
423         i2s_client_ch = i2s->dsp_config.num_slots;
424         i2s_audio_ch = i2s->dsp_config.num_slots;
425
426         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
427         switch (i2s->dsp_config.slot_width) {
428         case 16:
429                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_16;
430                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_16;
431                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
432                 break;
433         case 32:
434                 i2s_audio_bits = TEGRA30_AUDIOCIF_BITS_32;
435                 i2s_client_bits = TEGRA30_AUDIOCIF_BITS_32;
436                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_32;
437                 break;
438         default:
439                 dev_err(dev, "unknown slot_width %d\n",
440                                 i2s->dsp_config.slot_width);
441                 return -EINVAL;
442         }
443
444         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
445                         ((i2s_audio_ch - 1) <<
446                          TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
447                         ((i2s_client_ch - 1) <<
448                          TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
449                         (i2s_audio_bits <<
450                          TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
451                         (i2s_client_bits <<
452                          TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT);
453
454         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
455                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
456                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
457
458                 tegra30_ahub_set_tx_cif_channels(i2s->txcif,
459                                                 i2s_audio_ch,
460                                                 i2s_client_ch);
461                 tegra30_ahub_set_tx_cif_bits(i2s->txcif,
462                                                 i2s_audio_bits,
463                                                 i2s_client_bits);
464                 tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif, 0);
465
466         } else {
467                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
468                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
469
470                 tegra30_ahub_set_rx_cif_channels(i2s->rxcif,
471                                                 i2s_audio_ch,
472                                                 i2s_client_ch);
473                 tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
474                                                 i2s_audio_bits,
475                                                 i2s_client_bits);
476                 tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif, 0);
477         }
478
479         tegra30_i2s_set_slot_control(i2s, substream->stream);
480
481         tegra30_i2s_set_data_offset(i2s);
482
483         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK;
484         i2s->reg_ch_ctrl |= (i2s->dsp_config.slot_width - 1) <<
485                         TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT;
486         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
487
488         tegra30_i2s_disable_clocks(i2s);
489
490         return 0;
491 }
492
493 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
494                                 struct snd_pcm_hw_params *params,
495                                 struct snd_soc_dai *dai)
496 {
497         struct device *dev = substream->pcm->card->dev;
498         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
499         u32 val, i;
500         int ret, sample_size, srate, i2sclock, bitcnt, sym_bitclk;
501         int i2s_client_ch;
502
503         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
504         switch (params_format(params)) {
505         case SNDRV_PCM_FORMAT_S8:
506                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_8;
507                 sample_size = 8;
508                 break;
509         case SNDRV_PCM_FORMAT_S16_LE:
510                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
511                 sample_size = 16;
512                 break;
513         case SNDRV_PCM_FORMAT_S24_LE:
514                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_24;
515                 sample_size = 24;
516                 break;
517         case SNDRV_PCM_FORMAT_S32_LE:
518                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_32;
519                 sample_size = 32;
520                 break;
521         default:
522                 return -EINVAL;
523         }
524
525         bitcnt = sample_size;
526         i = 0;
527
528         /* TDM mode */
529         if ((i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) &&
530                 (i2s->dsp_config.slot_width > 2))
531                 return tegra30_i2s_tdm_hw_params(substream, params, dai);
532
533         srate = params_rate(params);
534
535         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_MASTER_ENABLE) {
536                 i2sclock = srate * params_channels(params) * sample_size;
537
538                 /* Additional "* 4" is needed for FSYNC mode */
539                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
540                         i2sclock *= 4;
541
542 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
543                 /* If the I2S is used for voice also, it is not
544                 *  necessary to set its clock if it had been set
545                 *  like during voice call.*/
546                 if (!(i2s->playback_ref_count - 1) ||
547                         !(i2s->capture_ref_count - 1)) {
548                         ret = clk_set_parent(i2s->clk_i2s,
549                                 i2s->clk_pll_a_out0);
550                         if (ret) {
551                                 dev_err(dev,
552                                 "Can't set parent of I2S clock\n");
553                                 return ret;
554                         }
555
556                         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
557                         if (ret) {
558                                 dev_err(dev,
559                                 "Can't set I2S clock rate: %d\n", ret);
560                                 return ret;
561                         }
562                 }
563 #else
564                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_pll_a_out0);
565                 if (ret) {
566                         dev_err(dev, "Can't set parent of I2S clock\n");
567                         return ret;
568                 }
569
570                 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
571                 if (ret) {
572                         dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
573                         return ret;
574                 }
575 #endif
576
577                 tegra30_i2s_enable_clocks(i2s);
578
579                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) {
580                         bitcnt = (i2sclock / srate) - 1;
581                         sym_bitclk = !(i2sclock % srate);
582 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
583                         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL2);
584
585                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
586                                 val &=
587                                   ~TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_MASK;
588                                 val |= ((1 << params_channels(params)) - 1) <<
589                                   TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT;
590                         } else {
591                                 val &=
592                                   ~TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_MASK;
593                                 val |= ((1 << params_channels(params)) - 1) <<
594                                   TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT;
595                         }
596                         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL2, val);
597 #endif
598                 } else {
599                         bitcnt = (i2sclock / (2 * srate)) - 1;
600                         sym_bitclk = !(i2sclock % (2 * srate));
601                 }
602                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
603
604                 if (!sym_bitclk)
605                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
606
607                 tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
608         } else {
609                 i2sclock = srate * params_channels(params) * sample_size;
610
611                 /* Additional "* 2" is needed for FSYNC mode */
612                 if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
613                         i2sclock *= 2;
614
615                 ret = clk_set_rate(i2s->clk_i2s_sync, i2sclock);
616                 if (ret) {
617                         dev_err(dev, "Can't set I2S sync clock rate\n");
618                         return ret;
619                 }
620
621                 ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x),
622                                                 i2s->clk_i2s_sync);
623                 if (ret) {
624                         dev_err(dev, "Can't set parent of audio2x clock\n");
625                         return ret;
626                 }
627
628                 ret = clk_set_rate(i2s->clk_audio_2x, i2sclock);
629                 if (ret) {
630                         dev_err(dev, "Can't set I2S sync clock rate\n");
631                         return ret;
632                 }
633
634                 ret = clk_set_parent(i2s->clk_i2s, i2s->clk_audio_2x);
635                 if (ret) {
636                         dev_err(dev, "Can't set parent of audio2x clock\n");
637                         return ret;
638                 }
639
640                 tegra30_i2s_enable_clocks(i2s);
641         }
642
643         i2s_client_ch = (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) ?
644                         params_channels(params) : 2;
645
646         switch (sample_size) {
647         case 8:
648                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
649               ((params_channels(params) - 1) <<
650                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
651               ((i2s_client_ch - 1) <<
652                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
653               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 |
654               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8;
655                 break;
656
657         case 16:
658                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
659               ((params_channels(params) - 1) <<
660                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
661               ((i2s_client_ch - 1) <<
662                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
663               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
664               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
665                 break;
666
667         case 24:
668                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
669               ((params_channels(params) - 1) <<
670                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
671               ((i2s_client_ch - 1) <<
672                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
673               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 |
674               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24;
675                 break;
676
677         case 32:
678                 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
679               ((params_channels(params) - 1) <<
680                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
681               ((i2s_client_ch - 1) <<
682                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
683               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 |
684               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32;
685                 break;
686
687         default:
688                 pr_err("Error in sample size\n");
689                 val = 0;
690                 break;
691         }
692
693         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
694                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
695                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
696
697                 tegra30_ahub_set_tx_cif_channels(i2s->txcif,
698                                                  params_channels(params),
699                                                  params_channels(params));
700
701                 switch (sample_size) {
702                 case 8:
703                         tegra30_ahub_set_tx_cif_bits(i2s->txcif,
704                           TEGRA30_AUDIOCIF_BITS_8, TEGRA30_AUDIOCIF_BITS_8);
705                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif,
706                           TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4);
707                         break;
708
709                 case 16:
710                         tegra30_ahub_set_tx_cif_bits(i2s->txcif,
711                           TEGRA30_AUDIOCIF_BITS_16, TEGRA30_AUDIOCIF_BITS_16);
712                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif,
713                           TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16);
714                         break;
715
716                 case 24:
717                         tegra30_ahub_set_tx_cif_bits(i2s->txcif,
718                           TEGRA30_AUDIOCIF_BITS_24, TEGRA30_AUDIOCIF_BITS_24);
719                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif, 0);
720                         break;
721
722                 case 32:
723                         tegra30_ahub_set_tx_cif_bits(i2s->txcif,
724                           TEGRA30_AUDIOCIF_BITS_32, TEGRA30_AUDIOCIF_BITS_32);
725                         tegra30_ahub_set_tx_fifo_pack_mode(i2s->txcif, 0);
726                         break;
727
728                 default:
729                         pr_err("Error in sample_size\n");
730                         break;
731                 }
732         } else {
733                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
734                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
735
736                 tegra30_ahub_set_rx_cif_channels(i2s->rxcif,
737                                                  params_channels(params),
738                                                  params_channels(params));
739
740                 switch (sample_size) {
741                 case 8:
742                         tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
743                           TEGRA30_AUDIOCIF_BITS_8, TEGRA30_AUDIOCIF_BITS_8);
744                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif,
745                           TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4);
746                         break;
747
748                 case 16:
749                         tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
750                           TEGRA30_AUDIOCIF_BITS_16, TEGRA30_AUDIOCIF_BITS_16);
751                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif,
752                           TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16);
753                         break;
754
755                 case 24:
756                         tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
757                           TEGRA30_AUDIOCIF_BITS_24, TEGRA30_AUDIOCIF_BITS_24);
758                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif, 0);
759                         break;
760
761                 case 32:
762                         tegra30_ahub_set_rx_cif_bits(i2s->rxcif,
763                           TEGRA30_AUDIOCIF_BITS_32, TEGRA30_AUDIOCIF_BITS_32);
764                         tegra30_ahub_set_rx_fifo_pack_mode(i2s->rxcif, 0);
765                         break;
766
767                 default:
768                         pr_err("Error in sample_size\n");
769                         break;
770                 }
771         }
772         switch (i2s->daifmt) {
773         case SND_SOC_DAIFMT_RIGHT_J:
774                 val = 0;
775                 if ((bitcnt - sample_size) > 0)
776                         val = bitcnt - sample_size;
777                 break;
778         case SND_SOC_DAIFMT_DSP_B:
779         case SND_SOC_DAIFMT_LEFT_J:
780                 val = 0;
781                 break;
782         case SND_SOC_DAIFMT_I2S:
783         case SND_SOC_DAIFMT_DSP_A: /* fall through */
784                 val = 1;
785                 break;
786         default:
787                 return -EINVAL;
788         }
789         val = (val << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
790                   (val << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
791         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
792
793         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
794
795 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
796         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
797         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
798                 val &= ~TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
799                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
800         } else {
801                 val &= ~TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
802                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
803         }
804 #else
805         val = 0;
806         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
807                 val = params_channels(params) - 1;
808 #endif
809
810         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
811
812         tegra30_i2s_disable_clocks(i2s);
813         return 0;
814 }
815
816 static int tegra30_i2s_soft_reset(struct tegra30_i2s *i2s)
817 {
818         int dcnt = 10;
819
820         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_SOFT_RESET;
821         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
822
823         while ((tegra30_i2s_read(i2s, TEGRA30_I2S_CTRL) &
824                        TEGRA30_I2S_CTRL_SOFT_RESET) && dcnt--)
825                 udelay(100);
826
827         /* Restore reg_ctrl to ensure if a concurrent playback/capture
828            session was active it continues after SOFT_RESET */
829         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
830         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
831
832         return (dcnt < 0) ? -ETIMEDOUT : 0;
833 }
834
835 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
836 {
837         tegra30_ahub_enable_tx_fifo(i2s->txcif);
838         /* if this is the only user of i2s tx then enable it*/
839         if (i2s->playback_ref_count == 1) {
840                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
841                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
842         }
843 }
844
845 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
846 {
847         int dcnt = 10;
848         /* if this is the only user of i2s tx then disable it*/
849         tegra30_ahub_disable_tx_fifo(i2s->txcif);
850         if (i2s->playback_ref_count == 1) {
851                 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
852                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
853                 while (tegra30_ahub_tx_fifo_is_enabled(i2s->id) && dcnt--)
854                         udelay(100);
855
856                 dcnt = 10;
857                 while (!tegra30_ahub_tx_fifo_is_empty(i2s->id) && dcnt--)
858                         udelay(100);
859
860                 /* In case I2S FIFO does not get empty do a soft reset of the
861                    I2S channel to prevent channel reversal in next session */
862                 if (dcnt < 0) {
863                         tegra30_i2s_soft_reset(i2s);
864
865                         dcnt = 10;
866                         while (!tegra30_ahub_tx_fifo_is_empty(i2s->id) &&
867                                dcnt--)
868                                 udelay(100);
869                 }
870         }
871 }
872
873 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
874 {
875         tegra30_ahub_enable_rx_fifo(i2s->rxcif);
876         if (!i2s->is_call_mode_rec && (i2s->capture_ref_count == 1)) {
877                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
878                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
879         }
880 }
881
882 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
883 {
884         int dcnt = 10;
885         if (!i2s->is_call_mode_rec && (i2s->capture_ref_count == 1)) {
886                 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
887                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
888                 while (tegra30_ahub_rx_fifo_is_enabled(i2s->id) && dcnt--)
889                         udelay(100);
890
891                 dcnt = 10;
892                 while (!tegra30_ahub_rx_fifo_is_empty(i2s->id) && dcnt--)
893                         udelay(100);
894
895                 /* In case I2S FIFO does not get empty do a soft reset of
896                    the I2S channel to prevent channel reversal in next capture
897                    session */
898                 if (dcnt < 0) {
899                         tegra30_i2s_soft_reset(i2s);
900
901                         dcnt = 10;
902                         while (!tegra30_ahub_rx_fifo_is_empty(i2s->id) &&
903                                dcnt--)
904                                 udelay(100);
905                 }
906                 tegra30_ahub_disable_rx_fifo(i2s->rxcif);
907         }
908 }
909
910 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
911                                 struct snd_soc_dai *dai)
912 {
913         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
914
915         switch (cmd) {
916         case SNDRV_PCM_TRIGGER_START:
917         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
918         case SNDRV_PCM_TRIGGER_RESUME:
919                 tegra30_i2s_enable_clocks(i2s);
920                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
921                         tegra30_i2s_start_playback(i2s);
922                 else
923                         tegra30_i2s_start_capture(i2s);
924                 break;
925         case SNDRV_PCM_TRIGGER_STOP:
926         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
927         case SNDRV_PCM_TRIGGER_SUSPEND:
928                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
929                         tegra30_i2s_stop_playback(i2s);
930                 else
931                         tegra30_i2s_stop_capture(i2s);
932                 tegra30_i2s_disable_clocks(i2s);
933                 break;
934         default:
935                 return -EINVAL;
936         }
937
938         return 0;
939 }
940
941 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
942 {
943         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
944 #ifdef CONFIG_PM
945         int i;
946 #endif
947
948         dai->capture_dma_data = &i2s->capture_dma_data;
949         dai->playback_dma_data = &i2s->playback_dma_data;
950
951 #ifdef CONFIG_PM
952         tegra30_i2s_enable_clocks(i2s);
953
954         /*cache the POR values of i2s regs*/
955         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
956                 i2s->reg_cache[i] = tegra30_i2s_read(i2s, i<<2);
957
958         tegra30_i2s_disable_clocks(i2s);
959 #endif
960
961         /* Default values for DSP mode */
962         i2s->dsp_config.num_slots = 1;
963         i2s->dsp_config.slot_width = 2;
964         i2s->dsp_config.tx_mask = 1;
965         i2s->dsp_config.rx_mask = 1;
966         i2s->dsp_config.rx_data_offset = 1;
967         i2s->dsp_config.tx_data_offset = 1;
968
969
970         return 0;
971 }
972
973 int tegra30_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,
974                                                         unsigned int tx_mask,
975                                                         unsigned int rx_mask,
976                                                         int slots,
977                                                         int slot_width)
978 {
979         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
980
981         i2s->dsp_config.num_slots = slots;
982         i2s->dsp_config.slot_width = slot_width;
983         i2s->dsp_config.tx_mask = tx_mask;
984         i2s->dsp_config.rx_mask = rx_mask;
985         i2s->dsp_config.rx_data_offset = 0;
986         i2s->dsp_config.tx_data_offset = 0;
987
988         return 0;
989 }
990
991 #ifdef CONFIG_PM
992 int tegra30_i2s_resume(struct snd_soc_dai *cpu_dai)
993 {
994         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
995         int i, ret = 0;
996
997         tegra30_i2s_enable_clocks(i2s);
998
999         /*restore the i2s regs*/
1000         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
1001                 tegra30_i2s_write(i2s, i<<2, i2s->reg_cache[i]);
1002
1003         tegra30_ahub_apbif_resume();
1004
1005         tegra30_i2s_disable_clocks(i2s);
1006
1007         if (i2s->dam_ch_refcount > 1)
1008                 ret = tegra30_dam_resume(i2s->dam_ifc);
1009
1010         return ret;
1011 }
1012 #else
1013 #define tegra30_i2s_resume NULL
1014 #endif
1015
1016 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
1017         .startup        = tegra30_i2s_startup,
1018         .shutdown       = tegra30_i2s_shutdown,
1019         .set_fmt        = tegra30_i2s_set_fmt,
1020         .hw_params      = tegra30_i2s_hw_params,
1021         .trigger        = tegra30_i2s_trigger,
1022         .set_tdm_slot = tegra30_i2s_set_tdm_slot,
1023 };
1024
1025 #define TEGRA30_I2S_DAI(id) \
1026         { \
1027                 .name = DRV_NAME "." #id, \
1028                 .probe = tegra30_i2s_probe, \
1029                 .resume = tegra30_i2s_resume, \
1030                 .playback = { \
1031                         .channels_min = 1, \
1032                         .channels_max = 16, \
1033                         .rates = SNDRV_PCM_RATE_8000_96000, \
1034                         .formats = SNDRV_PCM_FMTBIT_S8 | \
1035                                    SNDRV_PCM_FMTBIT_S16_LE | \
1036                                    SNDRV_PCM_FMTBIT_S24_LE | \
1037                                    SNDRV_PCM_FMTBIT_S32_LE, \
1038                 }, \
1039                 .capture = { \
1040                         .channels_min = 1, \
1041                         .channels_max = 16, \
1042                         .rates = SNDRV_PCM_RATE_8000_96000, \
1043                         .formats = SNDRV_PCM_FMTBIT_S8 | \
1044                                    SNDRV_PCM_FMTBIT_S16_LE | \
1045                                    SNDRV_PCM_FMTBIT_S24_LE | \
1046                                    SNDRV_PCM_FMTBIT_S32_LE, \
1047                 }, \
1048                 .ops = &tegra30_i2s_dai_ops, \
1049                 .symmetric_rates = 1, \
1050         }
1051
1052 struct snd_soc_dai_driver tegra30_i2s_dai[] = {
1053         TEGRA30_I2S_DAI(0),
1054         TEGRA30_I2S_DAI(1),
1055         TEGRA30_I2S_DAI(2),
1056         TEGRA30_I2S_DAI(3),
1057         TEGRA30_I2S_DAI(4),
1058 };
1059
1060 static int configure_voice_call_clocks(struct codec_config *codec_info,
1061         int codec_i2sclock, struct codec_config *bb_info, int bb_i2sclock)
1062 {
1063         struct tegra30_i2s  *codec_i2s;
1064         struct tegra30_i2s  *bb_i2s;
1065         int ret;
1066
1067         codec_i2s = &i2scont[codec_info->i2s_id];
1068         bb_i2s = &i2scont[bb_info->i2s_id];
1069
1070         if (bb_info->is_i2smaster && codec_info->is_i2smaster) {
1071                 /* set modem clock */
1072                 ret = clk_set_parent(bb_i2s->clk_i2s, bb_i2s->clk_pll_a_out0);
1073                 if (ret) {
1074                         pr_err("Can't set parent of I2S clock\n");
1075                         return ret;
1076                 }
1077
1078                 ret = clk_set_rate(bb_i2s->clk_i2s, bb_i2sclock);
1079                 if (ret) {
1080                         pr_err("Can't set I2S clock rate: %d\n", ret);
1081                         return ret;
1082                 }
1083                 /* set codec clock */
1084                 ret = clk_set_parent(codec_i2s->clk_i2s,
1085                         codec_i2s->clk_pll_a_out0);
1086                 if (ret) {
1087                         pr_err("Can't set parent of I2S clock\n");
1088                         return ret;
1089                 }
1090
1091                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1092                 if (ret) {
1093                         pr_err("Can't set I2S clock rate: %d\n", ret);
1094                         return ret;
1095                 }
1096
1097         } else if (!bb_info->is_i2smaster && codec_info->is_i2smaster) {
1098
1099                 /* set modem clock */
1100                 ret = clk_set_rate(bb_i2s->clk_i2s_sync, bb_i2sclock);
1101                 if (ret) {
1102                         pr_err("Can't set I2S sync clock rate\n");
1103                         return ret;
1104                 }
1105
1106                 ret = clk_set_parent(clk_get_parent(bb_i2s->clk_audio_2x),
1107                                                 bb_i2s->clk_i2s_sync);
1108                 if (ret) {
1109                         pr_err("Can't set parent of audiox clock\n");
1110                         return ret;
1111                 }
1112
1113                 ret = clk_set_rate(bb_i2s->clk_audio_2x, bb_i2sclock);
1114                 if (ret) {
1115                         pr_err("Can't set audio2x clock rate\n");
1116                         return ret;
1117                 }
1118
1119                 ret = clk_set_parent(bb_i2s->clk_i2s, bb_i2s->clk_audio_2x);
1120                 if (ret) {
1121                         pr_err("Can't set parent of clk_i2s clock\n");
1122                         return ret;
1123                 }
1124
1125                 /* Modify or ensure the frequency division*/
1126                 ret = clk_set_rate(bb_i2s->clk_i2s, bb_i2sclock);
1127                 if (ret) {
1128                         pr_err("Can't set I2S clock rate: %d\n", ret);
1129                         return ret;
1130                 }
1131
1132 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1133                 /* set codec clock */
1134                 /* use modem clock to drive codec
1135                 * to avoid sound to being discontinuous */
1136                 ret = clk_set_parent(clk_get_parent(codec_i2s->clk_audio_2x),
1137                                                 bb_i2s->clk_i2s_sync);
1138                 if (ret) {
1139                         pr_err("Can't set parent of audiox clock\n");
1140                         return ret;
1141                 }
1142
1143                 ret = clk_set_rate(codec_i2s->clk_audio_2x, bb_i2sclock);
1144                 if (ret) {
1145                         pr_err("Can't set audio2x clock rate\n");
1146                         return ret;
1147                 }
1148
1149                 ret = clk_set_parent(codec_i2s->clk_i2s,
1150                         codec_i2s->clk_audio_2x);
1151                 if (ret) {
1152                         pr_err("Can't set parent of clk_i2s clock\n");
1153                         return ret;
1154                 }
1155
1156                 /* Modify or ensure the frequency division*/
1157                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1158                 if (ret) {
1159                         pr_err("Can't set I2S clock rate: %d\n", ret);
1160                         return ret;
1161                 }
1162 #else
1163                 /* set codec clock */
1164                 ret = clk_set_parent(codec_i2s->clk_i2s,
1165                         codec_i2s->clk_pll_a_out0);
1166                 if (ret) {
1167                         pr_err("Can't set parent of I2S clock\n");
1168                         return ret;
1169                 }
1170
1171                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1172                 if (ret) {
1173                         pr_err("Can't set I2S clock rate: %d\n", ret);
1174                         return ret;
1175                 }
1176 #endif
1177
1178         } else if (bb_info->is_i2smaster && !codec_info->is_i2smaster) {
1179                 /* Just because by now there is no use case about using Codec's
1180                  * Clock for Modem when Code is Master and Modem is slave,
1181                  * I do not add modification about it.
1182                  * If necessarily, it can be added.*/
1183                 /* set modem clock */
1184                 ret = clk_set_parent(bb_i2s->clk_i2s, bb_i2s->clk_pll_a_out0);
1185                 if (ret) {
1186                         pr_err("Can't set parent of I2S clock\n");
1187                         return ret;
1188                 }
1189
1190                 ret = clk_set_rate(bb_i2s->clk_i2s, bb_i2sclock);
1191                 if (ret) {
1192                         pr_err("Can't set I2S clock rate: %d\n", ret);
1193                         return ret;
1194                 }
1195
1196                 /* set codec clock */
1197                 ret = clk_set_rate(codec_i2s->clk_i2s_sync, codec_i2sclock);
1198                 if (ret) {
1199                         pr_err("Can't set I2S sync clock rate\n");
1200                         return ret;
1201                 }
1202
1203                 ret = clk_set_parent(clk_get_parent(codec_i2s->clk_audio_2x),
1204                                                 codec_i2s->clk_i2s_sync);
1205                 if (ret) {
1206                         pr_err("Can't set parent of audiox clock\n");
1207                         return ret;
1208                 }
1209
1210                 ret = clk_set_rate(codec_i2s->clk_audio_2x, codec_i2sclock);
1211                 if (ret) {
1212                         pr_err("Can't set audio2x clock rate\n");
1213                         return ret;
1214                 }
1215
1216                 ret = clk_set_parent(codec_i2s->clk_i2s,
1217                         codec_i2s->clk_audio_2x);
1218                 if (ret) {
1219                         pr_err("Can't set parent of clk_i2s clock\n");
1220                         return ret;
1221                 }
1222
1223                 /* Modify or ensure the frequency division*/
1224                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1225                 if (ret) {
1226                         pr_err("Can't set I2S clock rate: %d\n", ret);
1227                         return ret;
1228                 }
1229
1230         } else if (!bb_info->is_i2smaster && !codec_info->is_i2smaster) {
1231                 /* set modem clock */
1232                 ret = clk_set_rate(bb_i2s->clk_i2s_sync, bb_i2sclock);
1233                 if (ret) {
1234                         pr_err("Can't set I2S sync clock rate\n");
1235                         return ret;
1236                 }
1237
1238                 ret = clk_set_parent(clk_get_parent(bb_i2s->clk_audio_2x),
1239                                                 bb_i2s->clk_i2s_sync);
1240                 if (ret) {
1241                         pr_err("Can't set parent of audiox clock\n");
1242                         return ret;
1243                 }
1244
1245                 ret = clk_set_rate(bb_i2s->clk_audio_2x, bb_i2sclock);
1246                 if (ret) {
1247                         pr_err("Can't set audio2x clock rate\n");
1248                         return ret;
1249                 }
1250
1251                 ret = clk_set_parent(bb_i2s->clk_i2s, bb_i2s->clk_audio_2x);
1252                 if (ret) {
1253                         pr_err("Can't set parent of clk_i2s clock\n");
1254                         return ret;
1255                 }
1256
1257                 /* Modify or ensure the frequency division*/
1258                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1259                 if (ret) {
1260                         pr_err("Can't set I2S clock rate: %d\n", ret);
1261                         return ret;
1262                 }
1263
1264                 /* set codec clock */
1265                 ret = clk_set_rate(codec_i2s->clk_i2s_sync, codec_i2sclock);
1266                 if (ret) {
1267                         pr_err("Can't set I2S sync clock rate\n");
1268                         return ret;
1269                 }
1270
1271                 ret = clk_set_parent(clk_get_parent(codec_i2s->clk_audio_2x),
1272                                                 codec_i2s->clk_i2s_sync);
1273                 if (ret) {
1274                         pr_err("Can't set parent of audiox clock\n");
1275                         return ret;
1276                 }
1277
1278                 ret = clk_set_rate(codec_i2s->clk_audio_2x, codec_i2sclock);
1279                 if (ret) {
1280                         pr_err("Can't set audio2x clock rate\n");
1281                         return ret;
1282                 }
1283
1284                 ret = clk_set_parent(codec_i2s->clk_i2s,
1285                         codec_i2s->clk_audio_2x);
1286                 if (ret) {
1287                         pr_err("Can't set parent of clk_i2s clock\n");
1288                         return ret;
1289                 }
1290
1291                 /* Modify or ensure the frequency division*/
1292                 ret = clk_set_rate(codec_i2s->clk_i2s, codec_i2sclock);
1293                 if (ret) {
1294                         pr_err("Can't set I2S clock rate: %d\n", ret);
1295                         return ret;
1296                 }
1297
1298         }
1299         return 0;
1300 }
1301
1302 static int configure_baseband_i2s(struct tegra30_i2s *i2s,
1303         struct codec_config *i2s_info,
1304         int i2sclock, int is_formatdsp)
1305 {
1306         u32 val;
1307         int bitcnt;
1308 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1309         u32  i;
1310 #endif
1311
1312         tegra30_i2s_enable_clocks(i2s);
1313
1314         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
1315                                         TEGRA30_I2S_CTRL_LRCK_MASK |
1316                                         TEGRA30_I2S_CTRL_MASTER_ENABLE);
1317         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
1318
1319         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
1320
1321         if (i2s_info->is_i2smaster)
1322                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
1323
1324         if (i2s_info->i2s_mode == TEGRA_DAIFMT_DSP_A) {
1325                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
1326                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
1327                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
1328         } else if (i2s_info->i2s_mode == TEGRA_DAIFMT_DSP_B) {
1329                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
1330                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
1331                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
1332         } else {
1333                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
1334                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
1335                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
1336         }
1337
1338         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
1339
1340 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1341         val = 0;
1342         for (i = 0; i < i2s_info->channels; i++)
1343                 val |= (1 << i);
1344
1345         val |= val <<
1346           TEGRA30_I2S_SLOT_CTRL2_TX_SLOT_ENABLES_SHIFT;
1347         val |= val <<
1348           TEGRA30_I2S_SLOT_CTRL2_RX_SLOT_ENABLES_SHIFT;
1349         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL2, val);
1350
1351         val = 0;
1352         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
1353                 val = i2s_info->channels - 1;
1354
1355         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
1356 #else
1357         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
1358         val &= ~(TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK |
1359                 TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK);
1360         val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT |
1361                 1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
1362         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
1363 #endif
1364
1365         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
1366               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
1367         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
1368
1369         if (is_formatdsp) {
1370                 bitcnt = (i2sclock/i2s_info->rate) - 1;
1371                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
1372                 if (i2sclock % (i2s_info->rate))
1373                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
1374         } else {
1375                 bitcnt = (i2sclock/(2*i2s_info->rate)) - 1;
1376                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
1377                 if (i2sclock % (2*i2s_info->rate))
1378                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
1379         }
1380
1381         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
1382
1383         /* configure the i2s cif*/
1384         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
1385                 ((i2s_info->channels - 1) <<
1386                 TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
1387                 ((i2s_info->channels - 1) <<
1388                 TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
1389               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
1390               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
1391         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
1392         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1393
1394         val &= ~TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK;
1395         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
1396         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
1397
1398         return 0;
1399 }
1400
1401 static int configure_dam(struct tegra30_i2s  *i2s, int out_channel,
1402                 int out_rate, int out_bitsize, int in_channels,
1403                 int in_rate, int in_bitsize)
1404 {
1405
1406         if (!i2s->dam_ch_refcount)
1407                 i2s->dam_ifc = tegra30_dam_allocate_controller();
1408
1409         if (i2s->dam_ifc < 0) {
1410                 pr_err("Error : Failed to allocate DAM controller\n");
1411                 return -ENOENT;
1412         }
1413         tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
1414         i2s->dam_ch_refcount++;
1415         tegra30_dam_enable_clock(i2s->dam_ifc);
1416         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHOUT, out_rate);
1417         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1418                                 in_rate);
1419         tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
1420 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1421         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1422                         in_channels, in_bitsize, 1, 32);
1423         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
1424                         out_channel, out_bitsize, out_channel, 32);
1425 #else
1426         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
1427                         in_channels, in_bitsize, 1, 16);
1428         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
1429                         out_channel, out_bitsize, out_channel, out_bitsize);
1430 #endif
1431
1432 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1433         if (in_rate != out_rate) {
1434                 tegra30_dam_write_coeff_ram(i2s->dam_ifc, in_rate, out_rate);
1435                 tegra30_dam_set_farrow_param(i2s->dam_ifc, in_rate, out_rate);
1436                 tegra30_dam_set_biquad_fixed_coef(i2s->dam_ifc);
1437                 tegra30_dam_enable_coeff_ram(i2s->dam_ifc);
1438                 tegra30_dam_set_filter_stages(i2s->dam_ifc, in_rate, out_rate);
1439         } else {
1440                 tegra30_dam_enable_stereo_mixing(i2s->dam_ifc);
1441         }
1442 #endif
1443
1444         return 0;
1445 }
1446
1447
1448 int tegra30_make_bt_voice_call_connections(struct codec_config *codec_info,
1449                                 struct codec_config *bb_info,
1450                                 int uses_voice_codec)
1451 {
1452         struct tegra30_i2s  *codec_i2s;
1453         struct tegra30_i2s  *bb_i2s;
1454         int reg, ret;
1455 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1456         int val;
1457 #endif
1458         int bb_i2sclock, bb_is_formatdsp, codec_i2sclock, codec_is_formatdsp;
1459
1460         codec_i2s = &i2scont[codec_info->i2s_id];
1461         bb_i2s = &i2scont[bb_info->i2s_id];
1462
1463         /* increment the codec i2s playback ref count */
1464         codec_i2s->playback_ref_count++;
1465         bb_i2s->playback_ref_count++;
1466         codec_i2s->capture_ref_count++;
1467         bb_i2s->capture_ref_count++;
1468
1469         /* Make sure i2s is disabled during the configiration */
1470         /* Soft reset to make sure DL and UL be not lost*/
1471         tegra30_i2s_enable_clocks(codec_i2s);
1472         reg = codec_i2s->reg_ctrl;
1473         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1474         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1475         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1476         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1477                 reg | TEGRA30_I2S_CTRL_SOFT_RESET);
1478         tegra30_i2s_disable_clocks(codec_i2s);
1479
1480         tegra30_i2s_enable_clocks(bb_i2s);
1481         reg = bb_i2s->reg_ctrl;
1482         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1483         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1484         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1485         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1486                 reg | TEGRA30_I2S_CTRL_SOFT_RESET);
1487         tegra30_i2s_disable_clocks(bb_i2s);
1488
1489         msleep(20);
1490
1491         /* get bitclock of modem */
1492         codec_is_formatdsp = (codec_info->i2s_mode == TEGRA_DAIFMT_DSP_A) ||
1493                         (codec_info->i2s_mode == TEGRA_DAIFMT_DSP_B);
1494
1495         if (codec_info->bit_clk) {
1496                 codec_i2sclock = codec_info->bit_clk;
1497         } else {
1498                 codec_i2sclock = codec_info->rate * codec_info->channels *
1499                         codec_info->bitsize * 2;
1500                 /* additional 8 for baseband */
1501                 if (codec_is_formatdsp)
1502                         codec_i2sclock *= 8;
1503         }
1504
1505         /* get bitclock of codec */
1506         bb_is_formatdsp = (bb_info->i2s_mode == TEGRA_DAIFMT_DSP_A) ||
1507                         (bb_info->i2s_mode == TEGRA_DAIFMT_DSP_B);
1508
1509         if (bb_info->bit_clk) {
1510                 bb_i2sclock = bb_info->bit_clk;
1511         } else {
1512                 bb_i2sclock = bb_info->rate * bb_info->channels *
1513                         bb_info->bitsize * 2;
1514                 /* additional 8 for baseband */
1515                 if (bb_is_formatdsp)
1516                         bb_i2sclock *= 8;
1517         }
1518         /* If we have two modems and one is master device and the other
1519         * is slave.Audio will be inaduible with the slave modem after
1520         * using the master modem*/
1521         configure_voice_call_clocks(codec_info, codec_i2sclock,
1522                 bb_info, bb_i2sclock);
1523
1524         /* Configure codec i2s */
1525         configure_baseband_i2s(codec_i2s, codec_info,
1526                 codec_i2sclock, codec_is_formatdsp);
1527
1528         /* Configure bb i2s */
1529         configure_baseband_i2s(bb_i2s, bb_info,
1530                 bb_i2sclock, bb_is_formatdsp);
1531
1532         if (uses_voice_codec) {
1533                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1534                         codec_info->i2s_id);
1535                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1536                         bb_info->i2s_id);
1537
1538                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1539                             bb_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1540                             codec_info->i2s_id);
1541                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1542                             codec_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1543                             bb_info->i2s_id);
1544         } else {
1545
1546                 /*configure codec dam*/
1547                 ret = configure_dam(codec_i2s,
1548                                     codec_info->channels,
1549                                     codec_info->rate,
1550                                     codec_info->bitsize,
1551                                     bb_info->channels,
1552                                     bb_info->rate,
1553                                     bb_info->bitsize);
1554                 if (ret != 0) {
1555                         pr_err("Error: Failed configure_dam\n");
1556                         return ret;
1557                 }
1558
1559                 /*configure bb dam*/
1560                 ret = configure_dam(bb_i2s,
1561                                     bb_info->channels,
1562                                     bb_info->rate,
1563                                     bb_info->bitsize,
1564                                     codec_info->channels,
1565                                     codec_info->rate,
1566                                     codec_info->bitsize);
1567                 if (ret != 0) {
1568                         pr_err("Error: Failed configure_dam\n");
1569                         return ret;
1570                 }
1571
1572                 /*make ahub connections*/
1573
1574                 /*if this is the only user of i2s tx, make i2s rx connection*/
1575                 if (codec_i2s->playback_ref_count == 1) {
1576                         tegra30_ahub_set_rx_cif_source(
1577                           TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id,
1578                           TEGRA30_AHUB_TXCIF_DAM0_TX0 + codec_i2s->dam_ifc);
1579                 }
1580
1581                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1582                                 bb_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
1583                                 bb_i2s->dam_ifc);
1584                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1585                         (codec_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1586                         bb_info->i2s_id);
1587                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
1588                         (bb_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1589                         codec_info->i2s_id);
1590
1591                 /*enable dam and i2s*/
1592                 tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1593                         TEGRA30_DAM_CHIN0_SRC);
1594                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1595                         TEGRA30_DAM_CHIN0_SRC);
1596         }
1597 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1598         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_FLOWCTL, 0);
1599         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_FLOWCTL, 0);
1600         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_TX_STEP, 0);
1601         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_TX_STEP, 0);
1602         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1603         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1604
1605         if (!bb_info->is_i2smaster && codec_info->is_i2smaster) {
1606                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_FLOWCTL,
1607                         TEGRA30_I2S_FLOWCTL_FILTER_QUAD |
1608                         4 << TEGRA30_I2S_FLOWCTL_START_SHIFT |
1609                         4 << TEGRA30_I2S_FLOWCTL_HIGH_SHIFT |
1610                         4 << TEGRA30_I2S_FLOWCTL_LOW_SHIFT);
1611                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_FLOWCTL,
1612                         TEGRA30_I2S_FLOWCTL_FILTER_QUAD |
1613                         4 << TEGRA30_I2S_FLOWCTL_START_SHIFT |
1614                         4 << TEGRA30_I2S_FLOWCTL_HIGH_SHIFT |
1615                         4 << TEGRA30_I2S_FLOWCTL_LOW_SHIFT);
1616                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_TX_STEP, 4);
1617                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_TX_STEP, 4);
1618                 codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1619                 bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1620
1621                 val = tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CIF_RX_CTRL);
1622                 val &= ~(0xf << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1623                 val |= (4 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1624                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1625                 val = tegra30_i2s_read(bb_i2s, TEGRA30_I2S_CIF_RX_CTRL);
1626                 val &= ~(0xf << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1627                 val |= (4 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1628                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1629         }
1630 #endif
1631
1632         msleep(20);
1633
1634         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1635         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1636         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1637                 codec_i2s->reg_ctrl);
1638
1639         msleep(20);
1640
1641         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1642         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1643         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1644                 bb_i2s->reg_ctrl);
1645
1646         return 0;
1647 }
1648
1649 int tegra30_break_bt_voice_call_connections(struct codec_config *codec_info,
1650                                 struct codec_config *bb_info,
1651                                 int uses_voice_codec)
1652 {
1653         struct tegra30_i2s  *codec_i2s;
1654         struct tegra30_i2s  *bb_i2s;
1655         int dcnt = 10;
1656
1657         codec_i2s = &i2scont[codec_info->i2s_id];
1658         bb_i2s = &i2scont[bb_info->i2s_id];
1659
1660         /*Disable Codec I2S RX (TX to ahub)*/
1661         if (codec_i2s->capture_ref_count == 1)
1662                 codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1663
1664         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1665
1666         while (!tegra30_ahub_rx_fifo_is_empty(codec_i2s->id) && dcnt--)
1667                 udelay(100);
1668
1669         dcnt = 10;
1670
1671         /*Disable baseband I2S TX (RX from ahub)*/
1672         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1673         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1674
1675         while (!tegra30_ahub_tx_fifo_is_empty(bb_i2s->id) && dcnt--)
1676                 udelay(100);
1677
1678         dcnt = 10;
1679
1680         /*Disable baseband I2S RX (TX to ahub)*/
1681         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1682         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
1683
1684         while (!tegra30_ahub_rx_fifo_is_empty(bb_i2s->id) && dcnt--)
1685                 udelay(100);
1686
1687         dcnt = 10;
1688
1689         /*Disable Codec I2S TX (RX from ahub)*/
1690         if (codec_i2s->playback_ref_count == 1)
1691                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1692
1693         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1694
1695         while (!tegra30_ahub_tx_fifo_is_empty(codec_i2s->id) && dcnt--)
1696                 udelay(100);
1697
1698         dcnt = 10;
1699
1700         if (uses_voice_codec) {
1701                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1702                             bb_info->i2s_id);
1703                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1704                             codec_info->i2s_id);
1705         } else {
1706
1707                 /*Disable baseband DAM*/
1708                 tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_DISABLE,
1709                                 TEGRA30_DAM_CHIN0_SRC);
1710                 tegra30_dam_free_channel(bb_i2s->dam_ifc,
1711                                 TEGRA30_DAM_CHIN0_SRC);
1712                 bb_i2s->dam_ch_refcount--;
1713                 if (!bb_i2s->dam_ch_refcount)
1714                         tegra30_dam_free_controller(bb_i2s->dam_ifc);
1715
1716                 /*Disable Codec DAM*/
1717                 tegra30_dam_enable(codec_i2s->dam_ifc,
1718                         TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
1719                 tegra30_dam_free_channel(codec_i2s->dam_ifc,
1720                         TEGRA30_DAM_CHIN0_SRC);
1721                 codec_i2s->dam_ch_refcount--;
1722                 if (!codec_i2s->dam_ch_refcount)
1723                         tegra30_dam_free_controller(codec_i2s->dam_ifc);
1724
1725                 /* Disconnect the ahub connections */
1726                 /* If this is the only user of i2s tx then break ahub
1727                 i2s rx connection */
1728                 if (codec_i2s->playback_ref_count == 1)
1729                         tegra30_ahub_unset_rx_cif_source(
1730                            TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id);
1731
1732                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
1733                                         + bb_info->i2s_id);
1734                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1735                                         + (codec_i2s->dam_ifc*2));
1736                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
1737                                         + (bb_i2s->dam_ifc*2));
1738
1739                 tegra30_dam_disable_clock(codec_i2s->dam_ifc);
1740                 tegra30_dam_disable_clock(bb_i2s->dam_ifc);
1741         }
1742
1743         /* Decrement the codec and bb i2s playback ref count */
1744         codec_i2s->playback_ref_count--;
1745         bb_i2s->playback_ref_count--;
1746         codec_i2s->capture_ref_count--;
1747         bb_i2s->capture_ref_count--;
1748
1749         /* Soft reset */
1750         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1751                 codec_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
1752         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1753                 bb_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
1754
1755         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1756         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1757         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
1758         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
1759
1760         while ((tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CTRL) &
1761                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
1762                 udelay(100);
1763         dcnt = 10;
1764         while ((tegra30_i2s_read(bb_i2s, TEGRA30_I2S_CTRL) &
1765                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
1766                 udelay(100);
1767
1768         /* Disable the clocks */
1769         tegra30_i2s_disable_clocks(codec_i2s);
1770         tegra30_i2s_disable_clocks(bb_i2s);
1771
1772         return 0;
1773 }
1774
1775 int tegra30_make_voice_call_connections(struct codec_config *codec_info,
1776                                 struct codec_config *bb_info,
1777                                 int uses_voice_codec)
1778 {
1779         struct tegra30_i2s  *codec_i2s;
1780         struct tegra30_i2s  *bb_i2s;
1781         int reg, ret;
1782 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1783         int val;
1784 #endif
1785         int bb_i2sclock, bb_is_formatdsp, codec_i2sclock, codec_is_formatdsp;
1786
1787         codec_i2s = &i2scont[codec_info->i2s_id];
1788         bb_i2s = &i2scont[bb_info->i2s_id];
1789
1790         /* increment the codec i2s playback ref count */
1791         codec_i2s->playback_ref_count++;
1792         bb_i2s->playback_ref_count++;
1793         codec_i2s->capture_ref_count++;
1794         bb_i2s->capture_ref_count++;
1795
1796         /* Make sure i2s is disabled during the configiration */
1797         /* Soft reset to make sure DL and UL be not lost*/
1798         tegra30_i2s_enable_clocks(codec_i2s);
1799         reg = codec_i2s->reg_ctrl;
1800         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1801         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1802         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1803         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1804                 reg | TEGRA30_I2S_CTRL_SOFT_RESET);
1805         tegra30_i2s_disable_clocks(codec_i2s);
1806
1807         tegra30_i2s_enable_clocks(bb_i2s);
1808         reg = bb_i2s->reg_ctrl;
1809         reg &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1810         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
1811         reg &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1812         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1813                 reg | TEGRA30_I2S_CTRL_SOFT_RESET);
1814         tegra30_i2s_disable_clocks(bb_i2s);
1815
1816         msleep(20);
1817
1818         /* get bitclock of modem */
1819         codec_is_formatdsp = (codec_info->i2s_mode == TEGRA_DAIFMT_DSP_A) ||
1820                         (codec_info->i2s_mode == TEGRA_DAIFMT_DSP_B);
1821
1822         if (codec_info->bit_clk) {
1823                 codec_i2sclock = codec_info->bit_clk;
1824         } else {
1825                 codec_i2sclock = codec_info->rate * codec_info->channels *
1826                         codec_info->bitsize * 2;
1827                 /* additional 8 for baseband */
1828                 if (codec_is_formatdsp)
1829                         codec_i2sclock *= 8;
1830         }
1831
1832         /* get bitclock of codec */
1833         bb_is_formatdsp = (bb_info->i2s_mode == TEGRA_DAIFMT_DSP_A) ||
1834                         (bb_info->i2s_mode == TEGRA_DAIFMT_DSP_B);
1835
1836         if (bb_info->bit_clk) {
1837                 bb_i2sclock = bb_info->bit_clk;
1838         } else {
1839                 bb_i2sclock = bb_info->rate * bb_info->channels *
1840                         bb_info->bitsize * 2;
1841                 /* additional 8 for baseband */
1842                 if (bb_is_formatdsp)
1843                         bb_i2sclock *= 8;
1844         }
1845         /* If we have two modems and one is master device and the other
1846         * is slave.Audio will be inaduible with the slave modem after
1847         * using the master modem*/
1848         configure_voice_call_clocks(codec_info, codec_i2sclock,
1849                 bb_info, bb_i2sclock);
1850
1851         /* Configure codec i2s */
1852         configure_baseband_i2s(codec_i2s, codec_info,
1853                 codec_i2sclock, codec_is_formatdsp);
1854
1855         /* Configure bb i2s */
1856         configure_baseband_i2s(bb_i2s, bb_info,
1857                 bb_i2sclock, bb_is_formatdsp);
1858
1859         if (uses_voice_codec) {
1860                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1861                         codec_info->i2s_id);
1862                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0 +
1863                         bb_info->i2s_id);
1864
1865                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1866                             bb_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1867                             codec_info->i2s_id);
1868                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
1869                             codec_info->i2s_id, TEGRA30_AHUB_TXCIF_I2S0_TX0 +
1870                             bb_info->i2s_id);
1871         } else {
1872
1873                 /*configure codec dam*/
1874                 ret = configure_dam(codec_i2s,
1875                                     codec_info->channels,
1876                                     codec_info->rate,
1877                                     codec_info->bitsize,
1878                                     bb_info->channels,
1879                                     48000,
1880                                     bb_info->bitsize);
1881                 if (ret != 0) {
1882                         pr_err("Error: Failed configure_dam\n");
1883                         return ret;
1884                 }
1885
1886                 ret = tegra30_dam_allocate_channel(codec_i2s->dam_ifc,
1887                                                 TEGRA30_DAM_CHIN1);
1888                 if (ret)
1889                         pr_info("%s:Failed to allocate dam\n", __func__);
1890
1891                 tegra30_dam_set_gain(codec_i2s->dam_ifc,
1892                                 TEGRA30_DAM_CHIN1, 0x1000);
1893                 tegra30_dam_set_acif(codec_i2s->dam_ifc, TEGRA30_DAM_CHIN1, 1,
1894                                 bb_info->bitsize, 1, 32);
1895                 tegra30_dam_set_acif(codec_i2s->dam_ifc, TEGRA30_DAM_CHOUT,
1896                                 2, codec_info->bitsize, 1, 32);
1897                 tegra30_dam_ch0_set_datasync(codec_i2s->dam_ifc, 2);
1898                 tegra30_dam_ch1_set_datasync(codec_i2s->dam_ifc, 0);
1899
1900                 /* do routing in ahub */
1901                 tegra30_ahub_set_rx_cif_source(
1902                         TEGRA30_AHUB_RXCIF_DAM0_RX1 + (codec_i2s->dam_ifc*2),
1903                         TEGRA30_AHUB_RXCIF_I2S0_RX0 + bb_info->i2s_id);
1904
1905                 tegra30_ahub_set_rx_cif_source(
1906                         TEGRA30_AHUB_RXCIF_DAM0_RX0 + (codec_i2s->dam_ifc*2),
1907                         codec_i2s->txcif);
1908
1909                 tegra30_ahub_set_rx_cif_source(
1910                         TEGRA30_AHUB_RXCIF_I2S0_RX0 + codec_info->i2s_id,
1911                         TEGRA30_AHUB_TXCIF_DAM0_TX0 + codec_i2s->dam_ifc);
1912
1913                 tegra30_ahub_set_rx_cif_source(
1914                         TEGRA30_AHUB_RXCIF_I2S0_RX0 + bb_info->i2s_id,
1915                         TEGRA30_AHUB_TXCIF_I2S0_TX0 + codec_info->i2s_id);
1916
1917                 /* enable the dam*/
1918                 tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1919                         TEGRA30_DAM_CHIN0_SRC);
1920
1921                 tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
1922                                 TEGRA30_DAM_CHIN1);
1923
1924         }
1925 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
1926         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_FLOWCTL, 0);
1927         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_FLOWCTL, 0);
1928         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_TX_STEP, 0);
1929         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_TX_STEP, 0);
1930         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1931         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1932
1933         if (!bb_info->is_i2smaster && codec_info->is_i2smaster) {
1934                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_FLOWCTL,
1935                         TEGRA30_I2S_FLOWCTL_FILTER_QUAD |
1936                         4 << TEGRA30_I2S_FLOWCTL_START_SHIFT |
1937                         4 << TEGRA30_I2S_FLOWCTL_HIGH_SHIFT |
1938                         4 << TEGRA30_I2S_FLOWCTL_LOW_SHIFT);
1939                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_FLOWCTL,
1940                         TEGRA30_I2S_FLOWCTL_FILTER_QUAD |
1941                         4 << TEGRA30_I2S_FLOWCTL_START_SHIFT |
1942                         4 << TEGRA30_I2S_FLOWCTL_HIGH_SHIFT |
1943                         4 << TEGRA30_I2S_FLOWCTL_LOW_SHIFT);
1944                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_TX_STEP, 4);
1945                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_TX_STEP, 4);
1946                 codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1947                 bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
1948
1949                 val = tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CIF_RX_CTRL);
1950                 val &= ~(0xf << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1951                 val |= (4 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1952                 tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1953                 val = tegra30_i2s_read(bb_i2s, TEGRA30_I2S_CIF_RX_CTRL);
1954                 val &= ~(0xf << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1955                 val |= (4 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT);
1956                 tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
1957         }
1958 #endif
1959
1960         msleep(20);
1961
1962         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1963         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1964         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
1965                 codec_i2s->reg_ctrl);
1966
1967         msleep(20);
1968
1969         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
1970         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
1971         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
1972                 bb_i2s->reg_ctrl);
1973
1974         return 0;
1975 }
1976
1977 int tegra30_break_voice_call_connections(struct codec_config *codec_info,
1978                                 struct codec_config *bb_info,
1979                                 int uses_voice_codec)
1980 {
1981         struct tegra30_i2s  *codec_i2s;
1982         struct tegra30_i2s  *bb_i2s;
1983         int dcnt = 10;
1984
1985         codec_i2s = &i2scont[codec_info->i2s_id];
1986         bb_i2s = &i2scont[bb_info->i2s_id];
1987
1988         /*Disable Codec I2S RX (TX to ahub)*/
1989         if (codec_i2s->capture_ref_count == 1)
1990                 codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
1991
1992         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
1993
1994         while (!tegra30_ahub_rx_fifo_is_empty(codec_i2s->id) && dcnt--)
1995                 udelay(100);
1996
1997         dcnt = 10;
1998
1999         /*Disable baseband I2S TX (RX from ahub)*/
2000         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
2001         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
2002
2003         while (!tegra30_ahub_tx_fifo_is_empty(bb_i2s->id) && dcnt--)
2004                 udelay(100);
2005
2006         dcnt = 10;
2007
2008         /*Disable baseband I2S RX (TX to ahub)*/
2009         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
2010         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
2011
2012         while (!tegra30_ahub_rx_fifo_is_empty(bb_i2s->id) && dcnt--)
2013                 udelay(100);
2014
2015         dcnt = 10;
2016
2017         /*Disable Codec I2S TX (RX from ahub)*/
2018         if (codec_i2s->playback_ref_count == 1)
2019                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
2020
2021         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
2022
2023         while (!tegra30_ahub_tx_fifo_is_empty(codec_i2s->id) && dcnt--)
2024                 udelay(100);
2025
2026         dcnt = 10;
2027
2028         if (uses_voice_codec) {
2029                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
2030                             bb_info->i2s_id);
2031                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
2032                             codec_info->i2s_id);
2033         } else {
2034
2035                 /* Disable DAM in DL path */
2036                 tegra30_dam_enable(codec_i2s->dam_ifc,
2037                         TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
2038                 tegra30_dam_free_channel(codec_i2s->dam_ifc,
2039                         TEGRA30_DAM_CHIN0_SRC);
2040
2041                 tegra30_dam_enable(codec_i2s->dam_ifc,
2042                         TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN1);
2043                 tegra30_dam_free_channel(codec_i2s->dam_ifc,
2044                         TEGRA30_DAM_CHIN1);
2045
2046                 codec_i2s->dam_ch_refcount--;
2047                 if (!codec_i2s->dam_ch_refcount)
2048                         tegra30_dam_free_controller(codec_i2s->dam_ifc);
2049
2050                 /* Disconnect the ahub connections */
2051                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
2052                                 bb_info->i2s_id);
2053
2054                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 +
2055                                 (codec_i2s->dam_ifc*2));
2056
2057                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
2058                         (codec_i2s->dam_ifc*2));
2059
2060                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
2061                                 codec_info->i2s_id);
2062
2063                 tegra30_dam_ch0_set_datasync(codec_i2s->dam_ifc, 0);
2064                 tegra30_dam_ch1_set_datasync(codec_i2s->dam_ifc, 0);
2065
2066                 tegra30_dam_disable_clock(codec_i2s->dam_ifc);
2067         }
2068
2069         /* Decrement the codec and bb i2s playback ref count */
2070         codec_i2s->playback_ref_count--;
2071         bb_i2s->playback_ref_count--;
2072         codec_i2s->capture_ref_count--;
2073         bb_i2s->capture_ref_count--;
2074
2075         /* Soft reset */
2076         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
2077                 codec_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
2078         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
2079                 bb_i2s->reg_ctrl | TEGRA30_I2S_CTRL_SOFT_RESET);
2080
2081         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
2082         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_TX_FLOWCTL_EN;
2083         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
2084         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_SOFT_RESET;
2085
2086         while ((tegra30_i2s_read(codec_i2s, TEGRA30_I2S_CTRL) &
2087                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
2088                 udelay(100);
2089         dcnt = 10;
2090         while ((tegra30_i2s_read(bb_i2s, TEGRA30_I2S_CTRL) &
2091                         TEGRA30_I2S_CTRL_SOFT_RESET)  && dcnt--)
2092                 udelay(100);
2093
2094         /* Disable the clocks */
2095         tegra30_i2s_disable_clocks(codec_i2s);
2096         tegra30_i2s_disable_clocks(bb_i2s);
2097
2098         return 0;
2099 }
2100
2101 static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
2102 {
2103         struct tegra30_i2s *i2s;
2104         struct resource *mem, *memregion;
2105         int ret;
2106
2107         if ((pdev->id < 0) ||
2108                 (pdev->id >= ARRAY_SIZE(tegra30_i2s_dai))) {
2109                 dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
2110                 return -EINVAL;
2111         }
2112
2113         i2s = &i2scont[pdev->id];
2114         dev_set_drvdata(&pdev->dev, i2s);
2115         i2s->id = pdev->id;
2116         switch (i2s->id) {
2117         case 0:
2118                 i2s->dam_ifc = 1;
2119                 break;
2120         case 1:
2121                 i2s->dam_ifc = 0;
2122                 break;
2123         case 2:
2124                 break;
2125         case 3:
2126                 i2s->dam_ifc = 2;
2127                 break;
2128         default:
2129                 break;
2130         }
2131         i2s->dam_ch_refcount++;
2132
2133         i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
2134         if (IS_ERR(i2s->clk_i2s)) {
2135                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
2136                 ret = PTR_ERR(i2s->clk_i2s);
2137                 goto exit;
2138         }
2139         i2s->clk_i2s_sync = clk_get(&pdev->dev, "ext_audio_sync");
2140         if (IS_ERR(i2s->clk_i2s_sync)) {
2141                 dev_err(&pdev->dev, "Can't retrieve i2s_sync clock\n");
2142                 ret = PTR_ERR(i2s->clk_i2s_sync);
2143                 goto err_i2s_clk_put;
2144         }
2145
2146         i2s->clk_audio_2x = clk_get(&pdev->dev, "audio_sync_2x");
2147         if (IS_ERR(i2s->clk_audio_2x)) {
2148                 dev_err(&pdev->dev, "Can't retrieve audio 2x clock\n");
2149                 ret = PTR_ERR(i2s->clk_audio_2x);
2150                 goto err_i2s_sync_clk_put;
2151         }
2152
2153         i2s->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
2154         if (IS_ERR(i2s->clk_pll_a_out0)) {
2155                 dev_err(&pdev->dev, "Can't retrieve pll_a_out0 clock\n");
2156                 ret = PTR_ERR(i2s->clk_pll_a_out0);
2157                 goto err_audio_2x_clk_put;
2158         }
2159
2160         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2161         if (!mem) {
2162                 dev_err(&pdev->dev, "No memory resource\n");
2163                 ret = -ENODEV;
2164                 goto err_pll_a_out0_clk_put;
2165         }
2166
2167         memregion = request_mem_region(mem->start, resource_size(mem),
2168                                         DRV_NAME);
2169         if (!memregion) {
2170                 dev_err(&pdev->dev, "Memory region already claimed\n");
2171                 ret = -EBUSY;
2172                 goto err_pll_a_out0_clk_put;
2173         }
2174
2175         i2s->regs = ioremap(mem->start, resource_size(mem));
2176         if (!i2s->regs) {
2177                 dev_err(&pdev->dev, "ioremap failed\n");
2178                 ret = -ENOMEM;
2179                 goto err_release;
2180         }
2181
2182         ret = snd_soc_register_dai(&pdev->dev, &tegra30_i2s_dai[pdev->id]);
2183         if (ret) {
2184                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
2185                 ret = -ENOMEM;
2186                 goto err_unmap;
2187         }
2188
2189         tegra30_i2s_debug_add(i2s, pdev->id);
2190
2191         return 0;
2192
2193 err_unmap:
2194         iounmap(i2s->regs);
2195 err_release:
2196         release_mem_region(mem->start, resource_size(mem));
2197 err_pll_a_out0_clk_put:
2198         clk_put(i2s->clk_pll_a_out0);
2199 err_audio_2x_clk_put:
2200         clk_put(i2s->clk_audio_2x);
2201 err_i2s_sync_clk_put:
2202         clk_put(i2s->clk_i2s_sync);
2203 err_i2s_clk_put:
2204         clk_put(i2s->clk_i2s);
2205 exit:
2206         return ret;
2207 }
2208
2209 static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
2210 {
2211         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
2212         struct resource *res;
2213
2214         snd_soc_unregister_dai(&pdev->dev);
2215
2216         tegra30_i2s_debug_remove(i2s);
2217
2218         iounmap(i2s->regs);
2219
2220         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2221         release_mem_region(res->start, resource_size(res));
2222
2223         clk_put(i2s->clk_pll_a_out0);
2224         clk_put(i2s->clk_audio_2x);
2225         clk_put(i2s->clk_i2s_sync);
2226         clk_put(i2s->clk_i2s);
2227
2228         kfree(i2s);
2229
2230         return 0;
2231 }
2232
2233 static struct platform_driver tegra30_i2s_driver = {
2234         .driver = {
2235                 .name = DRV_NAME,
2236                 .owner = THIS_MODULE,
2237         },
2238         .probe = tegra30_i2s_platform_probe,
2239         .remove = __devexit_p(tegra30_i2s_platform_remove),
2240 };
2241
2242 static int __init snd_tegra30_i2s_init(void)
2243 {
2244         return platform_driver_register(&tegra30_i2s_driver);
2245 }
2246 module_init(snd_tegra30_i2s_init);
2247
2248 static void __exit snd_tegra30_i2s_exit(void)
2249 {
2250         platform_driver_unregister(&tegra30_i2s_driver);
2251 }
2252 module_exit(snd_tegra30_i2s_exit);
2253
2254 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2255 MODULE_DESCRIPTION("Tegra 30 I2S ASoC driver");
2256 MODULE_LICENSE("GPL");
2257 MODULE_ALIAS("platform:" DRV_NAME);