a789dbba3c4896b4d616f9a3e3f1ea10a674084f
[linux-2.6.git] / sound / soc / tegra / tegra30_i2s.c
1 /*
2  * tegra30_i2s.c - Tegra 30 I2S driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (c) 2010-2011, NVIDIA Corporation.
6  *
7  * Based on code copyright/by:
8  *
9  * Copyright (c) 2009-2010, NVIDIA Corporation.
10  * Scott Peterson <speterson@nvidia.com>
11  *
12  * Copyright (C) 2010 Google, Inc.
13  * Iliyan Malchev <malchev@google.com>
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License
17  * version 2 as published by the Free Software Foundation.
18  *
19  * This program is distributed in the hope that it will be useful, but
20  * WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
22  * General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27  * 02110-1301 USA
28  *
29  */
30
31 #include <linux/clk.h>
32 #include <linux/module.h>
33 #include <linux/debugfs.h>
34 #include <linux/device.h>
35 #include <linux/platform_device.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/io.h>
39 #include <mach/iomap.h>
40 #include <sound/core.h>
41 #include <sound/pcm.h>
42 #include <sound/pcm_params.h>
43 #include <sound/soc.h>
44
45 #include "tegra30_ahub.h"
46 #include "tegra30_dam.h"
47 #include "tegra30_i2s.h"
48
49 #define DRV_NAME "tegra30-i2s"
50
51 static struct tegra30_i2s  i2scont[TEGRA30_NR_I2S_IFC];
52
53 static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
54 {
55 #ifdef CONFIG_PM
56         i2s->reg_cache[reg >> 2] = val;
57 #endif
58         __raw_writel(val, i2s->regs + reg);
59 }
60
61 static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
62 {
63         return __raw_readl(i2s->regs + reg);
64 }
65
66 static void tegra30_i2s_enable_clocks(struct tegra30_i2s *i2s)
67 {
68         tegra30_ahub_enable_clocks();
69         clk_enable(i2s->clk_i2s);
70 }
71
72 static void tegra30_i2s_disable_clocks(struct tegra30_i2s *i2s)
73 {
74         clk_disable(i2s->clk_i2s);
75         tegra30_ahub_disable_clocks();
76 }
77
78 #ifdef CONFIG_DEBUG_FS
79 static int tegra30_i2s_show(struct seq_file *s, void *unused)
80 {
81 #define REG(r) { r, #r }
82         static const struct {
83                 int offset;
84                 const char *name;
85         } regs[] = {
86                 REG(TEGRA30_I2S_CTRL),
87                 REG(TEGRA30_I2S_TIMING),
88                 REG(TEGRA30_I2S_OFFSET),
89                 REG(TEGRA30_I2S_CH_CTRL),
90                 REG(TEGRA30_I2S_SLOT_CTRL),
91                 REG(TEGRA30_I2S_CIF_TX_CTRL),
92                 REG(TEGRA30_I2S_CIF_RX_CTRL),
93                 REG(TEGRA30_I2S_FLOWCTL),
94                 REG(TEGRA30_I2S_TX_STEP),
95                 REG(TEGRA30_I2S_FLOW_STATUS),
96                 REG(TEGRA30_I2S_FLOW_TOTAL),
97                 REG(TEGRA30_I2S_FLOW_OVER),
98                 REG(TEGRA30_I2S_FLOW_UNDER),
99                 REG(TEGRA30_I2S_LCOEF_1_4_0),
100                 REG(TEGRA30_I2S_LCOEF_1_4_1),
101                 REG(TEGRA30_I2S_LCOEF_1_4_2),
102                 REG(TEGRA30_I2S_LCOEF_1_4_3),
103                 REG(TEGRA30_I2S_LCOEF_1_4_4),
104                 REG(TEGRA30_I2S_LCOEF_1_4_5),
105                 REG(TEGRA30_I2S_LCOEF_2_4_0),
106                 REG(TEGRA30_I2S_LCOEF_2_4_1),
107                 REG(TEGRA30_I2S_LCOEF_2_4_2),
108         };
109 #undef REG
110
111         struct tegra30_i2s *i2s = s->private;
112         int i;
113
114         tegra30_i2s_enable_clocks(i2s);
115
116         for (i = 0; i < ARRAY_SIZE(regs); i++) {
117                 u32 val = tegra30_i2s_read(i2s, regs[i].offset);
118                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
119         }
120
121         tegra30_i2s_disable_clocks(i2s);
122
123         return 0;
124 }
125
126 static int tegra30_i2s_debug_open(struct inode *inode, struct file *file)
127 {
128         return single_open(file, tegra30_i2s_show, inode->i_private);
129 }
130
131 static const struct file_operations tegra30_i2s_debug_fops = {
132         .open    = tegra30_i2s_debug_open,
133         .read    = seq_read,
134         .llseek  = seq_lseek,
135         .release = single_release,
136 };
137
138 static void tegra30_i2s_debug_add(struct tegra30_i2s *i2s, int id)
139 {
140         char name[] = DRV_NAME ".0";
141
142         snprintf(name, sizeof(name), DRV_NAME".%1d", id);
143         i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
144                                                 i2s, &tegra30_i2s_debug_fops);
145 }
146
147 static void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
148 {
149         if (i2s->debug)
150                 debugfs_remove(i2s->debug);
151 }
152 #else
153 static inline void tegra30_i2s_debug_add(struct tegra30_i2s *i2s, int id)
154 {
155 }
156
157 static inline void tegra30_i2s_debug_remove(struct tegra30_i2s *i2s)
158 {
159 }
160 #endif
161
162 int tegra30_i2s_startup(struct snd_pcm_substream *substream,
163                         struct snd_soc_dai *dai)
164 {
165         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
166         int ret;
167
168         tegra30_i2s_enable_clocks(i2s);
169
170         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
171                 /* increment the playback ref count */
172                 i2s->playback_ref_count++;
173
174                 ret = tegra30_ahub_allocate_tx_fifo(&i2s->txcif,
175                                         &i2s->playback_dma_data.addr,
176                                         &i2s->playback_dma_data.req_sel);
177                 i2s->playback_dma_data.wrap = 4;
178                 i2s->playback_dma_data.width = 32;
179
180                 if (!i2s->is_dam_used)
181                         tegra30_ahub_set_rx_cif_source(
182                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id,
183                                 i2s->txcif);
184         } else {
185                 ret = tegra30_ahub_allocate_rx_fifo(&i2s->rxcif,
186                                         &i2s->capture_dma_data.addr,
187                                         &i2s->capture_dma_data.req_sel);
188                 i2s->capture_dma_data.wrap = 4;
189                 i2s->capture_dma_data.width = 32;
190                 tegra30_ahub_set_rx_cif_source(i2s->rxcif,
191                                         TEGRA30_AHUB_TXCIF_I2S0_TX0 + i2s->id);
192         }
193
194         tegra30_i2s_disable_clocks(i2s);
195
196         return ret;
197 }
198
199 void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
200                         struct snd_soc_dai *dai)
201 {
202         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
203
204         tegra30_i2s_enable_clocks(i2s);
205
206         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
207                 if (i2s->playback_ref_count == 1)
208                         tegra30_ahub_unset_rx_cif_source(
209                                 TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id);
210
211                 /* free the apbif dma channel*/
212                 tegra30_ahub_free_tx_fifo(i2s->txcif);
213
214                 /* decrement the playback ref count */
215                 i2s->playback_ref_count--;
216         } else {
217                 tegra30_ahub_unset_rx_cif_source(i2s->rxcif);
218                 tegra30_ahub_free_rx_fifo(i2s->rxcif);
219         }
220
221         tegra30_i2s_disable_clocks(i2s);
222 }
223
224 static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
225                                 unsigned int fmt)
226 {
227         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
228
229         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
230         case SND_SOC_DAIFMT_NB_NF:
231                 break;
232         default:
233                 return -EINVAL;
234         }
235
236         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
237         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
238         case SND_SOC_DAIFMT_CBS_CFS:
239                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
240                 break;
241         case SND_SOC_DAIFMT_CBM_CFM:
242                 break;
243         default:
244                 return -EINVAL;
245         }
246
247         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
248                                 TEGRA30_I2S_CTRL_LRCK_MASK);
249         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
250         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
251         case SND_SOC_DAIFMT_DSP_A:
252                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
253                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
254                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
255                 break;
256         case SND_SOC_DAIFMT_DSP_B:
257                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
258                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
259                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
260                 break;
261         case SND_SOC_DAIFMT_I2S:
262                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
263                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
264                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
265                 break;
266         case SND_SOC_DAIFMT_RIGHT_J:
267                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
268                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
269                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
270                 break;
271         case SND_SOC_DAIFMT_LEFT_J:
272                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
273                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
274                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
275                 break;
276         default:
277                 return -EINVAL;
278         }
279
280         return 0;
281 }
282
283 static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
284                                 struct snd_pcm_hw_params *params,
285                                 struct snd_soc_dai *dai)
286 {
287         struct device *dev = substream->pcm->card->dev;
288         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
289         u32 val;
290         int ret, sample_size, srate, i2sclock, bitcnt, sym_bitclk;
291         int i2s_client_ch;
292
293         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
294         switch (params_format(params)) {
295         case SNDRV_PCM_FORMAT_S16_LE:
296                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
297                 sample_size = 16;
298                 break;
299         default:
300                 return -EINVAL;
301         }
302
303         srate = params_rate(params);
304
305         /* Final "* 2" required by Tegra hardware */
306         i2sclock = srate * params_channels(params) * sample_size * 2;
307
308         /* Additional "* 2" is needed for FSYNC mode */
309         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC)
310                 i2sclock *= 2;
311
312         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
313         if (ret) {
314                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
315                 return ret;
316         }
317
318         if (i2s->reg_ctrl & TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC) {
319                 bitcnt = (i2sclock / srate) - 1;
320                 sym_bitclk = !(i2sclock % srate);
321                 i2s_client_ch = params_channels(params);
322         } else {
323                 bitcnt = (i2sclock / (2 * srate)) - 1;
324                 sym_bitclk = !(i2sclock % (2 * srate));
325                 i2s_client_ch = 2;
326         }
327
328         tegra30_i2s_enable_clocks(i2s);
329
330         val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
331
332         if (!sym_bitclk)
333                 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
334
335         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
336
337         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
338               ((params_channels(params) - 1) <<
339                         TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
340               ((i2s_client_ch - 1) <<
341                         TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
342               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
343               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
344
345         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
346                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
347                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
348
349                 tegra30_ahub_set_tx_cif_channels(i2s->txcif,
350                                                  params_channels(params),
351                                                  params_channels(params));
352         } else {
353                 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
354                 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
355
356                 tegra30_ahub_set_rx_cif_channels(i2s->rxcif,
357                                                  params_channels(params),
358                                                  params_channels(params));
359         }
360
361         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
362               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
363         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
364
365         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
366
367         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
368         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
369                 val &= ~TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK;
370                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT);
371         } else {
372                 val &= ~TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK;
373                 val |= (1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
374         }
375         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
376
377         tegra30_i2s_disable_clocks(i2s);
378
379         return 0;
380 }
381
382 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
383 {
384         tegra30_ahub_enable_tx_fifo(i2s->txcif);
385         /* if this is the only user of i2s tx then enable it*/
386         if (i2s->playback_ref_count == 1) {
387                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
388                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
389         }
390 }
391
392 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
393 {
394         tegra30_ahub_disable_tx_fifo(i2s->txcif);
395         /* if this is the only user of i2s tx then disable it*/
396         if (i2s->playback_ref_count == 1) {
397                 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
398                 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
399         }
400 }
401
402 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
403 {
404         tegra30_ahub_enable_rx_fifo(i2s->rxcif);
405         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
406         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
407 }
408
409 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
410 {
411         tegra30_ahub_disable_rx_fifo(i2s->rxcif);
412         i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
413         tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
414 }
415
416 static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
417                                 struct snd_soc_dai *dai)
418 {
419         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
420
421         switch (cmd) {
422         case SNDRV_PCM_TRIGGER_START:
423         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
424         case SNDRV_PCM_TRIGGER_RESUME:
425                 tegra30_i2s_enable_clocks(i2s);
426                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
427                         tegra30_i2s_start_playback(i2s);
428                 else
429                         tegra30_i2s_start_capture(i2s);
430                 break;
431         case SNDRV_PCM_TRIGGER_STOP:
432         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
433         case SNDRV_PCM_TRIGGER_SUSPEND:
434                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
435                         tegra30_i2s_stop_playback(i2s);
436                 else
437                         tegra30_i2s_stop_capture(i2s);
438                 tegra30_i2s_disable_clocks(i2s);
439                 break;
440         default:
441                 return -EINVAL;
442         }
443
444         return 0;
445 }
446
447 static int tegra30_i2s_probe(struct snd_soc_dai *dai)
448 {
449         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
450         int i;
451
452         dai->capture_dma_data = &i2s->capture_dma_data;
453         dai->playback_dma_data = &i2s->playback_dma_data;
454
455         tegra30_i2s_enable_clocks(i2s);
456
457         /*cache the POR values of i2s regs*/
458         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
459                 i2s->reg_cache[i] = tegra30_i2s_read(i2s, i<<2);
460
461         tegra30_i2s_disable_clocks(i2s);
462
463         return 0;
464 }
465
466 #ifdef CONFIG_PM
467 int tegra30_i2s_resume(struct snd_soc_dai *cpu_dai)
468 {
469         struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
470         int i, ret = 0;
471
472         tegra30_i2s_enable_clocks(i2s);
473
474         /*restore the i2s regs*/
475         for (i = 0; i < ((TEGRA30_I2S_CIF_TX_CTRL>>2) + 1); i++)
476                 tegra30_i2s_write(i2s, i<<2, i2s->reg_cache[i]);
477
478         tegra30_ahub_apbif_resume();
479
480         tegra30_i2s_disable_clocks(i2s);
481
482         if (i2s->dam_ch_refcount)
483                 ret = tegra30_dam_resume(i2s->dam_ifc);
484
485         return ret;
486 }
487 #else
488 #define tegra30_i2s_resume NULL
489 #endif
490
491 static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
492         .startup        = tegra30_i2s_startup,
493         .shutdown       = tegra30_i2s_shutdown,
494         .set_fmt        = tegra30_i2s_set_fmt,
495         .hw_params      = tegra30_i2s_hw_params,
496         .trigger        = tegra30_i2s_trigger,
497 };
498
499 #define TEGRA30_I2S_DAI(id) \
500         { \
501                 .name = DRV_NAME "." #id, \
502                 .probe = tegra30_i2s_probe, \
503                 .resume = tegra30_i2s_resume, \
504                 .playback = { \
505                         .channels_min = 1, \
506                         .channels_max = 2, \
507                         .rates = SNDRV_PCM_RATE_8000_96000, \
508                         .formats = SNDRV_PCM_FMTBIT_S16_LE, \
509                 }, \
510                 .capture = { \
511                         .channels_min = 1, \
512                         .channels_max = 2, \
513                         .rates = SNDRV_PCM_RATE_8000_96000, \
514                         .formats = SNDRV_PCM_FMTBIT_S16_LE, \
515                 }, \
516                 .ops = &tegra30_i2s_dai_ops, \
517                 .symmetric_rates = 1, \
518         }
519
520 struct snd_soc_dai_driver tegra30_i2s_dai[] = {
521         TEGRA30_I2S_DAI(0),
522         TEGRA30_I2S_DAI(1),
523         TEGRA30_I2S_DAI(2),
524         TEGRA30_I2S_DAI(3),
525         TEGRA30_I2S_DAI(4),
526 };
527
528 static int configure_baseband_i2s(struct tegra30_i2s  *i2s, int is_i2smaster,
529                 int is_formatdsp, int channels, int rate, int bitsize)
530 {
531         u32 val;
532         int i2sclock, bitcnt;
533
534         i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
535                                         TEGRA30_I2S_CTRL_LRCK_MASK |
536                                         TEGRA30_I2S_CTRL_MASTER_ENABLE);
537         i2s->reg_ch_ctrl &= ~TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
538
539         i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
540
541         if (is_i2smaster)
542                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
543
544         if (is_formatdsp) {
545                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
546                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
547                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
548         } else {
549                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
550                 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
551                 i2s->reg_ch_ctrl |= TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE;
552         }
553
554         tegra30_i2s_write(i2s, TEGRA30_I2S_CH_CTRL, i2s->reg_ch_ctrl);
555
556         val = tegra30_i2s_read(i2s, TEGRA30_I2S_SLOT_CTRL);
557         val &= ~(TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK |
558                 TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK);
559         val |= (1 << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT |
560                 1 << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT);
561         tegra30_i2s_write(i2s, TEGRA30_I2S_SLOT_CTRL, val);
562
563         val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
564               (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
565         tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
566
567         i2sclock = rate * channels * bitsize * 2;
568
569         /* additional 8 for baseband */
570         if (is_formatdsp)
571                 i2sclock *= 8;
572
573         clk_set_rate(i2s->clk_i2s, i2sclock);
574
575         if (is_formatdsp) {
576                 bitcnt = (i2sclock/rate) - 1;
577                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
578                 if (i2sclock % (rate))
579                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
580         } else {
581                 bitcnt = (i2sclock/(2*rate)) - 1;
582                 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
583                 if (i2sclock % (2*rate))
584                         val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
585         }
586
587         tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
588
589         /* configure the i2s cif*/
590         val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
591               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
592               ((channels - 1) << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
593               TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
594               TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
595         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
596         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
597
598         val &= ~TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK;
599         val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
600         tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
601
602         return 0;
603 }
604
605 static int configure_dam(struct tegra30_i2s  *i2s, int out_channel,
606                 int out_rate, int out_bitsize, int in_channels,
607                 int in_rate, int in_bitsize)
608 {
609
610         if (!i2s->dam_ch_refcount)
611                 i2s->dam_ifc = tegra30_dam_allocate_controller();
612
613         tegra30_dam_allocate_channel(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
614         i2s->dam_ch_refcount++;
615         tegra30_dam_enable_clock(i2s->dam_ifc);
616         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHOUT, out_rate);
617         tegra30_dam_set_samplerate(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
618                                 in_rate);
619         tegra30_dam_set_gain(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC, 0x1000);
620         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC,
621                         in_channels, in_bitsize, 1, 16);
622         tegra30_dam_set_acif(i2s->dam_ifc, TEGRA30_DAM_CHOUT,
623                         out_channel, out_bitsize, out_channel, out_bitsize);
624
625         return 0;
626 }
627
628
629 int tegra30_make_voice_call_connections(struct codec_config *codec_info,
630                                 struct codec_config *bb_info)
631 {
632         struct tegra30_i2s  *codec_i2s;
633         struct tegra30_i2s  *bb_i2s;
634
635         codec_i2s = &i2scont[codec_info->i2s_id];
636         bb_i2s = &i2scont[bb_info->i2s_id];
637         tegra30_i2s_enable_clocks(codec_i2s);
638         tegra30_i2s_enable_clocks(bb_i2s);
639
640         /* increment the codec i2s playback ref count */
641         codec_i2s->playback_ref_count++;
642         bb_i2s->playback_ref_count++;
643
644         /*Configure codec i2s*/
645         configure_baseband_i2s(codec_i2s, codec_info->is_i2smaster,
646                 codec_info->is_format_dsp, codec_info->channels,
647                 codec_info->rate, codec_info->bitsize);
648
649         /*Configure bb i2s*/
650         configure_baseband_i2s(bb_i2s, bb_info->is_i2smaster,
651                 bb_info->is_format_dsp, bb_info->channels,
652                 bb_info->rate, bb_info->bitsize);
653
654         /*configure codec dam*/
655         configure_dam(codec_i2s, codec_info->channels,
656                 codec_info->rate, codec_info->bitsize, bb_info->channels,
657                 bb_info->rate, bb_info->bitsize);
658
659         /*configure bb dam*/
660         configure_dam(bb_i2s, bb_info->channels,
661                 bb_info->rate, bb_info->bitsize, codec_info->channels,
662                 codec_info->rate, codec_info->bitsize);
663
664         /*make ahub connections*/
665
666         /* if this is the only user of i2s tx then make ahub i2s rx connection*/
667         if (codec_i2s->playback_ref_count == 1) {
668                 tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
669                                 codec_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
670                                 codec_i2s->dam_ifc);
671         }
672
673         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0 +
674                         bb_info->i2s_id, TEGRA30_AHUB_TXCIF_DAM0_TX0 +
675                         bb_i2s->dam_ifc);
676         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
677                 (codec_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
678                 bb_info->i2s_id);
679         tegra30_ahub_set_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 +
680                 (bb_i2s->dam_ifc*2), TEGRA30_AHUB_TXCIF_I2S0_TX0 +
681                 codec_info->i2s_id);
682
683         /*enable dam and i2s*/
684         tegra30_dam_enable(codec_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
685                 TEGRA30_DAM_CHIN0_SRC);
686         tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_ENABLE,
687                 TEGRA30_DAM_CHIN0_SRC);
688
689         /* if this is the only user of i2s tx then enable it*/
690         if (codec_i2s->playback_ref_count == 1)
691                 codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
692
693         codec_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
694         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL,
695                 codec_i2s->reg_ctrl);
696         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
697         bb_i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
698         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL,
699                 bb_i2s->reg_ctrl);
700
701         return 0;
702 }
703
704 int tegra30_break_voice_call_connections(struct codec_config *codec_info,
705                                 struct codec_config *bb_info)
706 {
707         struct tegra30_i2s  *codec_i2s;
708         struct tegra30_i2s  *bb_i2s;
709
710         codec_i2s = &i2scont[codec_info->i2s_id];
711         bb_i2s = &i2scont[bb_info->i2s_id];
712
713         /* disconnect the ahub connections */
714
715         /* if this is the only user of i2s tx then break ahub
716         i2s rx connection */
717         if (codec_i2s->playback_ref_count == 1)
718                 tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
719                         + codec_info->i2s_id);
720
721         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_I2S0_RX0
722                                 + bb_info->i2s_id);
723         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
724                                 + (codec_i2s->dam_ifc*2));
725         tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0
726                                 + (bb_i2s->dam_ifc*2));
727
728         /* disable the i2s */
729
730         /* if this is the only user of i2s tx then disable it*/
731         if (codec_i2s->playback_ref_count == 1)
732                         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
733
734         codec_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
735         tegra30_i2s_write(codec_i2s, TEGRA30_I2S_CTRL, codec_i2s->reg_ctrl);
736         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
737         bb_i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
738         tegra30_i2s_write(bb_i2s, TEGRA30_I2S_CTRL, bb_i2s->reg_ctrl);
739         tegra30_i2s_disable_clocks(codec_i2s);
740         tegra30_i2s_disable_clocks(bb_i2s);
741
742         /* decrement the codec i2s playback ref count */
743         codec_i2s->playback_ref_count--;
744         bb_i2s->playback_ref_count--;
745
746         /* disable the codec dam */
747         tegra30_dam_enable(codec_i2s->dam_ifc,
748                 TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC);
749         tegra30_dam_disable_clock(codec_i2s->dam_ifc);
750         tegra30_dam_free_channel(codec_i2s->dam_ifc,
751                 TEGRA30_DAM_CHIN0_SRC);
752         codec_i2s->dam_ch_refcount--;
753         if (!codec_i2s->dam_ch_refcount)
754                 tegra30_dam_free_controller(codec_i2s->dam_ifc);
755
756         /* disable the bb dam */
757         tegra30_dam_enable(bb_i2s->dam_ifc, TEGRA30_DAM_DISABLE,
758                         TEGRA30_DAM_CHIN0_SRC);
759         tegra30_dam_disable_clock(bb_i2s->dam_ifc);
760         tegra30_dam_free_channel(bb_i2s->dam_ifc, TEGRA30_DAM_CHIN0_SRC);
761         bb_i2s->dam_ch_refcount--;
762         if (!bb_i2s->dam_ch_refcount)
763                 tegra30_dam_free_controller(bb_i2s->dam_ifc);
764
765         return 0;
766 }
767
768 static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
769 {
770         struct tegra30_i2s *i2s;
771         struct resource *mem, *memregion;
772         int ret;
773
774         if ((pdev->id < 0) ||
775                 (pdev->id >= ARRAY_SIZE(tegra30_i2s_dai))) {
776                 dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
777                 return -EINVAL;
778         }
779
780         i2s = &i2scont[pdev->id];
781         dev_set_drvdata(&pdev->dev, i2s);
782         i2s->id = pdev->id;
783
784         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
785         if (IS_ERR(i2s->clk_i2s)) {
786                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
787                 ret = PTR_ERR(i2s->clk_i2s);
788                 goto err_free;
789         }
790
791         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
792         if (!mem) {
793                 dev_err(&pdev->dev, "No memory resource\n");
794                 ret = -ENODEV;
795                 goto err_clk_put;
796         }
797
798         memregion = request_mem_region(mem->start, resource_size(mem),
799                                         DRV_NAME);
800         if (!memregion) {
801                 dev_err(&pdev->dev, "Memory region already claimed\n");
802                 ret = -EBUSY;
803                 goto err_clk_put;
804         }
805
806         i2s->regs = ioremap(mem->start, resource_size(mem));
807         if (!i2s->regs) {
808                 dev_err(&pdev->dev, "ioremap failed\n");
809                 ret = -ENOMEM;
810                 goto err_release;
811         }
812
813         ret = snd_soc_register_dai(&pdev->dev, &tegra30_i2s_dai[pdev->id]);
814         if (ret) {
815                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
816                 ret = -ENOMEM;
817                 goto err_unmap;
818         }
819
820         tegra30_i2s_debug_add(i2s, pdev->id);
821
822         return 0;
823
824 err_unmap:
825         iounmap(i2s->regs);
826 err_release:
827         release_mem_region(mem->start, resource_size(mem));
828 err_clk_put:
829         clk_put(i2s->clk_i2s);
830 err_free:
831         kfree(i2s);
832 exit:
833         return ret;
834 }
835
836 static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
837 {
838         struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
839         struct resource *res;
840
841         snd_soc_unregister_dai(&pdev->dev);
842
843         tegra30_i2s_debug_remove(i2s);
844
845         iounmap(i2s->regs);
846
847         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848         release_mem_region(res->start, resource_size(res));
849
850         clk_put(i2s->clk_i2s);
851
852         kfree(i2s);
853
854         return 0;
855 }
856
857 static struct platform_driver tegra30_i2s_driver = {
858         .driver = {
859                 .name = DRV_NAME,
860                 .owner = THIS_MODULE,
861         },
862         .probe = tegra30_i2s_platform_probe,
863         .remove = __devexit_p(tegra30_i2s_platform_remove),
864 };
865
866 static int __init snd_tegra30_i2s_init(void)
867 {
868         return platform_driver_register(&tegra30_i2s_driver);
869 }
870 module_init(snd_tegra30_i2s_init);
871
872 static void __exit snd_tegra30_i2s_exit(void)
873 {
874         platform_driver_unregister(&tegra30_i2s_driver);
875 }
876 module_exit(snd_tegra30_i2s_exit);
877
878 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
879 MODULE_DESCRIPTION("Tegra 30 I2S ASoC driver");
880 MODULE_LICENSE("GPL");
881 MODULE_ALIAS("platform:" DRV_NAME);