asoc: tegra: Add PCM driver for TDM mode
[linux-2.6.git] / sound / soc / tegra / tegra30_dam.h
1 /*
2  * tegra30_dam.h - Tegra 30 DAM driver.
3  *
4  * Author: Nikesh Oswal <noswal@nvidia.com>
5  * Copyright (C) 2011 - NVIDIA, Inc.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19  * 02110-1301 USA
20  *
21  */
22
23 #ifndef __TEGRA30_DAM_H
24 #define __TEGRA30_DAM_H
25
26 /* Register offsets from TEGRA30_DAM*_BASE */
27 #define TEGRA30_DAM_CTRL                                0
28 #define TEGRA30_DAM_CLIP                                4
29 #define TEGRA30_DAM_CLIP_THRESHOLD                      8
30 #define TEGRA30_DAM_AUDIOCIF_OUT_CTRL                   0x0C
31 #define TEGRA30_DAM_CH0_CTRL                            0x10
32 #define TEGRA30_DAM_CH0_CONV                            0x14
33 #define TEGRA30_DAM_AUDIOCIF_CH0_CTRL                   0x1C
34 #define TEGRA30_DAM_CH1_CTRL                            0x20
35 #define TEGRA30_DAM_CH1_CONV                            0x24
36 #define TEGRA30_DAM_AUDIOCIF_CH1_CTRL                   0x2C
37 #define TEGRA30_DAM_CTRL_REGINDEX                       (TEGRA30_DAM_AUDIOCIF_CH1_CTRL >> 2)
38 #define TEGRA30_DAM_CTRL_RSVD_6                         6
39 #define TEGRA30_DAM_CTRL_RSVD_10                        10
40
41 #define TEGRA30_NR_DAM_IFC                              3
42
43 #define TEGRA30_DAM_NUM_INPUT_CHANNELS                  2
44
45 /* Fields in TEGRA30_DAM_CTRL */
46 #define TEGRA30_DAM_CTRL_SOFT_RESET_ENABLE              (1 << 31)
47 #define TEGRA30_DAM_CTRL_FSOUT_SHIFT                    4
48 #define TEGRA30_DAM_CTRL_FSOUT_MASK                     (0xf << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
49 #define TEGRA30_DAM_FS_8KHZ                             0
50 #define TEGRA30_DAM_FS_16KHZ                            1
51 #define TEGRA30_DAM_FS_44KHZ                            2
52 #define TEGRA30_DAM_FS_48KHZ                            3
53 #define TEGRA30_DAM_CTRL_FSOUT_FS8                      (TEGRA30_DAM_FS_8KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
54 #define TEGRA30_DAM_CTRL_FSOUT_FS16                     (TEGRA30_DAM_FS_16KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
55 #define TEGRA30_DAM_CTRL_FSOUT_FS44                     (TEGRA30_DAM_FS_44KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
56 #define TEGRA30_DAM_CTRL_FSOUT_FS48                     (TEGRA30_DAM_FS_48KHZ << TEGRA30_DAM_CTRL_FSOUT_SHIFT)
57 #define TEGRA30_DAM_CTRL_CG_EN                          (1 << 1)
58 #define TEGRA30_DAM_CTRL_DAM_EN                         (1 << 0)
59
60
61 /* Fields in TEGRA30_DAM_CLIP */
62 #define TEGRA30_DAM_CLIP_COUNTER_ENABLE                 (1 << 31)
63 #define TEGRA30_DAM_CLIP_COUNT_MASK                     0x7fffffff
64
65
66 /* Fields in TEGRA30_DAM_CH0_CTRL */
67 #define TEGRA30_STEP_RESET                              1
68 #define TEGRA30_DAM_DATA_SYNC                           1
69 #define TEGRA30_DAM_DATA_SYNC_SHIFT                     4
70 #define TEGRA30_DAM_CH0_CTRL_FSIN_SHIFT                 8
71 #define TEGRA30_DAM_CH0_CTRL_STEP_SHIFT                 16
72 #define TEGRA30_DAM_CH0_CTRL_STEP_MASK                  (0xffff << 16)
73 #define TEGRA30_DAM_CH0_CTRL_STEP_RESET                 (TEGRA30_STEP_RESET << 16)
74 #define TEGRA30_DAM_CH0_CTRL_FSIN_MASK                  (0xf << 8)
75 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS8                   (TEGRA30_DAM_FS_8KHZ << 8)
76 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS16                  (TEGRA30_DAM_FS_16KHZ << 8)
77 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS44                  (TEGRA30_DAM_FS_44KHZ << 8)
78 #define TEGRA30_DAM_CH0_CTRL_FSIN_FS48                  (TEGRA30_DAM_FS_48KHZ << 8)
79 #define TEGRA30_DAM_CH0_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
80 #define TEGRA30_DAM_CH0_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
81 #define TEGRA30_DAM_CH0_CTRL_EN                         (1 << 0)
82
83
84 /* Fields in TEGRA30_DAM_CH0_CONV */
85 #define TEGRA30_DAM_GAIN                                1
86 #define TEGRA30_DAM_GAIN_SHIFT                          0
87 #define TEGRA30_DAM_CH0_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
88
89 /* Fields in TEGRA30_DAM_CH1_CTRL */
90 #define TEGRA30_DAM_CH1_CTRL_DATA_SYNC_MASK             (0xf << TEGRA30_DAM_DATA_SYNC_SHIFT)
91 #define TEGRA30_DAM_CH1_CTRL_DATA_SYNC                  (TEGRA30_DAM_DATA_SYNC << TEGRA30_DAM_DATA_SYNC_SHIFT)
92 #define TEGRA30_DAM_CH1_CTRL_EN                         (1 << 0)
93
94 /* Fields in TEGRA30_DAM_CH1_CONV */
95 #define TEGRA30_DAM_CH1_CONV_GAIN                       (TEGRA30_DAM_GAIN << TEGRA30_DAM_GAIN_SHIFT)
96
97 #define TEGRA30_AUDIO_CHANNELS_SHIFT                    24
98 #define TEGRA30_AUDIO_CHANNELS_MASK                     (7 << TEGRA30_AUDIO_CHANNELS_SHIFT)
99 #define TEGRA30_CLIENT_CHANNELS_SHIFT                   16
100 #define TEGRA30_CLIENT_CHANNELS_MASK                    (7 << TEGRA30_CLIENT_CHANNELS_SHIFT)
101 #define TEGRA30_AUDIO_BITS_SHIFT                        12
102 #define TEGRA30_AUDIO_BITS_MASK                         (7 << TEGRA30_AUDIO_BITS_SHIFT)
103 #define TEGRA30_CLIENT_BITS_SHIFT                       8
104 #define TEGRA30_CLIENT_BITS_MASK                        (7 << TEGRA30_CLIENT_BITS_SHIFT)
105 #define TEGRA30_CIF_DIRECTION_TX                        (0 << 2)
106 #define TEGRA30_CIF_DIRECTION_RX                        (1 << 2)
107 #define TEGRA30_CIF_BIT24                               5
108 #define TEGRA30_CIF_BIT16                               3
109 #define TEGRA30_CIF_CH1                                 0
110 #define TEGRA30_CIF_MONOCONV_COPY                       (1<<0)
111 #define TEGRA30_CIF_STEREOCONV_CH0                      (0<<4)
112
113 /*
114 * Audio Samplerates
115 */
116 #define TEGRA30_AUDIO_SAMPLERATE_8000                   8000
117 #define TEGRA30_AUDIO_SAMPLERATE_16000                  16000
118 #define TEGRA30_AUDIO_SAMPLERATE_44100                  44100
119 #define TEGRA30_AUDIO_SAMPLERATE_48000                  48000
120
121 #define TEGRA30_DAM_CHIN0_SRC                           0
122 #define TEGRA30_DAM_CHIN1                               1
123 #define TEGRA30_DAM_CHOUT                               2
124 #define TEGRA30_DAM_ENABLE                              1
125 #define TEGRA30_DAM_DISABLE                             0
126
127 struct tegra30_dam_context {
128         int                     outsamplerate;
129         bool                    ch_alloc[TEGRA30_DAM_NUM_INPUT_CHANNELS];
130         int                     ch_enable_refcnt[TEGRA30_DAM_NUM_INPUT_CHANNELS];
131         int                     ch_insamplerate[TEGRA30_DAM_NUM_INPUT_CHANNELS];
132 #ifdef CONFIG_PM
133         int                     reg_cache[TEGRA30_DAM_CTRL_REGINDEX + 1];
134 #endif
135         struct clk              *dam_clk;
136         bool                    in_use;
137         void __iomem            *damregs;
138         struct dentry           *debug;
139 };
140
141 struct tegra30_dam_src_step_table {
142         int insample;
143         int outsample;
144         int stepreset;
145 };
146
147 #ifdef CONFIG_PM
148 int tegra30_dam_resume(int ifc);
149 #endif
150 void tegra30_dam_disable_clock(int ifc);
151 int tegra30_dam_enable_clock(int ifc);
152 int tegra30_dam_allocate_controller(void);
153 int tegra30_dam_allocate_channel(int ifc, int chid);
154 int tegra30_dam_free_channel(int ifc, int chid);
155 int tegra30_dam_free_controller(int ifc);
156 void tegra30_dam_set_samplerate(int ifc, int chtype, int samplerate);
157 int tegra30_dam_set_gain(int ifc, int chtype, int gain);
158 int tegra30_dam_set_acif(int ifc, int chtype, unsigned int audio_channels,
159         unsigned int audio_bits, unsigned int client_channels,
160         unsigned int client_bits);
161 void tegra30_dam_enable(int ifc, int on, int chtype);
162
163 #endif