soc: codecs: rt5639: Implement i2c shutdown
[linux-2.6.git] / sound / soc / tegra / tegra30_ahub.h
1 /*
2  * tegra30_ahub.h - Definitions for Tegra 30 AHUB driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (C) 2011 - NVIDIA, Inc.
6  * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #ifndef __TEGRA30_AHUB_H__
25 #define __TEGRA30_AHUB_H__
26
27 /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
28
29 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT      28
30 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US    0xf
31 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK       (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
32
33 /* Channel count minus 1 */
34 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT      24
35 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US    7
36 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK       (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
37
38 /* Channel count minus 1 */
39 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT     16
40 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US   7
41 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK      (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
42
43 #define TEGRA30_AUDIOCIF_BITS_4                         0
44 #define TEGRA30_AUDIOCIF_BITS_8                         1
45 #define TEGRA30_AUDIOCIF_BITS_12                        2
46 #define TEGRA30_AUDIOCIF_BITS_16                        3
47 #define TEGRA30_AUDIOCIF_BITS_20                        4
48 #define TEGRA30_AUDIOCIF_BITS_24                        5
49 #define TEGRA30_AUDIOCIF_BITS_28                        6
50 #define TEGRA30_AUDIOCIF_BITS_32                        7
51
52 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT          12
53 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK           (7                        << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
54 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4              (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
55 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8              (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
56 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12             (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
57 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16             (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
58 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20             (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
59 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24             (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
60 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28             (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
61 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32             (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
62
63 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT         8
64 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK          (7                        << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
65 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4             (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
66 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8             (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
67 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12            (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
68 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16            (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
69 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20            (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
70 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24            (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
71 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28            (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
72 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32            (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
73
74 #define TEGRA30_AUDIOCIF_EXPAND_ZERO                    0
75 #define TEGRA30_AUDIOCIF_EXPAND_ONE                     1
76 #define TEGRA30_AUDIOCIF_EXPAND_LFSR                    2
77
78 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT              6
79 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK               (3                            << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
80 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO               (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
81 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE                (TEGRA30_AUDIOCIF_EXPAND_ONE  << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
82 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR               (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
83
84 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0                0
85 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1                1
86 #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG                2
87
88 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT         4
89 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK          (3                                << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
90 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0           (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
91 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1           (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
92 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG           (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
93
94 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE                 3
95
96 #define TEGRA30_AUDIOCIF_DIRECTION_TX                   0
97 #define TEGRA30_AUDIOCIF_DIRECTION_RX                   1
98
99 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT           2
100 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK            (1                             << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
101 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX              (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
102 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX              (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
103
104 #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND                 0
105 #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP                  1
106
107 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT            1
108 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK             (1                               << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
109 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND            (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
110 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP             (TEGRA30_AUDIOCIF_TRUNCATE_CHOP  << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
111
112 #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO                 0
113 #define TEGRA30_AUDIOCIF_MONO_CONV_COPY                 1
114
115 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT           0
116 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK            (1                               << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
117 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO            (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
118 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY            (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
119
120 /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */
121
122 /* TEGRA30_AHUB_CHANNEL_CTRL */
123
124 #define TEGRA30_AHUB_CHANNEL_CTRL                       0x0
125 #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE                0x20
126 #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT                 4
127 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN                 (1 << 31)
128 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN                 (1 << 30)
129 #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK              (1 << 29)
130
131 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT    16
132 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US  0xff
133 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT)
134
135 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT    8
136 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US  0xff
137 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT)
138
139 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN            (1 << 6)
140
141 #define TEGRA30_PACK_8_4                                2
142 #define TEGRA30_PACK_16                                 3
143
144 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT         4
145 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US       3
146 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
147 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
148 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
149
150 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN            (1 << 2)
151
152 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT         0
153 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US       3
154 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
155 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
156 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
157
158 /* TEGRA30_AHUB_CHANNEL_CLEAR */
159
160 #define TEGRA30_AHUB_CHANNEL_CLEAR                      0x4
161 #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE               0x20
162 #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT                4
163 #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET        (1 << 31)
164 #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET        (1 << 30)
165
166 /* TEGRA30_AHUB_CHANNEL_STATUS */
167
168 #define TEGRA30_AHUB_CHANNEL_STATUS                     0x8
169 #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE              0x20
170 #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT               4
171 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT       24
172 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US     0xff
173 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT)
174 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT       16
175 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US     0xff
176 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT)
177 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG             (1 << 1)
178 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG             (1 << 0)
179
180 /* TEGRA30_AHUB_CHANNEL_TXFIFO */
181
182 #define TEGRA30_AHUB_CHANNEL_TXFIFO                     0xc
183 #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE              0x20
184 #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT               4
185
186 /* TEGRA30_AHUB_CHANNEL_RXFIFO */
187
188 #define TEGRA30_AHUB_CHANNEL_RXFIFO                     0x10
189 #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE              0x20
190 #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT               4
191
192 /* TEGRA30_AHUB_CIF_TX_CTRL */
193
194 #define TEGRA30_AHUB_CIF_TX_CTRL                        0x14
195 #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE                 0x20
196 #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT                  4
197 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
198
199 /* TEGRA30_AHUB_CIF_RX_CTRL */
200
201 #define TEGRA30_AHUB_CIF_RX_CTRL                        0x18
202 #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE                 0x20
203 #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT                  4
204 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
205
206 /* TEGRA30_AHUB_CONFIG_LINK_CTRL */
207
208 #define TEGRA30_AHUB_CONFIG_LINK_CTRL                                   0x80
209 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT        28
210 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US      0xf
211 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK         (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT)
212 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT                 16
213 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US               0xfff
214 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK                  (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT)
215 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT                    5
216 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US                  0xfff
217 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK                     (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT)
218 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN                             (1 << 2)
219 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR                (1 << 1)
220 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET                        (1 << 0)
221
222 /* TEGRA30_AHUB_MISC_CTRL */
223
224 #define TEGRA30_AHUB_MISC_CTRL                          0x84
225 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE             (1 << 31)
226 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN              (1 << 9)
227 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT      0
228 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK       (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT)
229
230 /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */
231
232 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS                         0x88
233 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL    (1 << 31)
234 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL    (1 << 30)
235 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL    (1 << 29)
236 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL    (1 << 28)
237 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL    (1 << 27)
238 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL    (1 << 26)
239 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL    (1 << 25)
240 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL    (1 << 24)
241 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY   (1 << 23)
242 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY   (1 << 22)
243 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY   (1 << 21)
244 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY   (1 << 20)
245 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY   (1 << 19)
246 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY   (1 << 18)
247 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY   (1 << 17)
248 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY   (1 << 16)
249 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL    (1 << 15)
250 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL    (1 << 14)
251 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL    (1 << 13)
252 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL    (1 << 12)
253 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL    (1 << 11)
254 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL    (1 << 10)
255 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL    (1 << 9)
256 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL    (1 << 8)
257 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY   (1 << 7)
258 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY   (1 << 6)
259 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY   (1 << 5)
260 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY   (1 << 4)
261 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY   (1 << 3)
262 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY   (1 << 2)
263 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY   (1 << 1)
264 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY   (1 << 0)
265
266 /* TEGRA30_AHUB_I2S_LIVE_STATUS */
267
268 #define TEGRA30_AHUB_I2S_LIVE_STATUS                            0x8c
269 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL          (1 << 29)
270 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL          (1 << 28)
271 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL          (1 << 27)
272 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL          (1 << 26)
273 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL          (1 << 25)
274 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL          (1 << 24)
275 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL          (1 << 23)
276 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL          (1 << 22)
277 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL          (1 << 21)
278 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL          (1 << 20)
279 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED       (1 << 19)
280 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED       (1 << 18)
281 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED       (1 << 17)
282 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED       (1 << 16)
283 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED       (1 << 15)
284 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED       (1 << 14)
285 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED       (1 << 13)
286 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED       (1 << 12)
287 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED       (1 << 11)
288 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED       (1 << 10)
289 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY         (1 << 9)
290 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY         (1 << 8)
291 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY         (1 << 7)
292 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY         (1 << 6)
293 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY         (1 << 5)
294 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY         (1 << 4)
295 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY         (1 << 3)
296 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY         (1 << 2)
297 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY         (1 << 1)
298 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY         (1 << 0)
299
300 /* TEGRA30_AHUB_DAM0_LIVE_STATUS */
301
302 #define TEGRA30_AHUB_DAM_LIVE_STATUS                            0x90
303 #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE                     0x8
304 #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT                      3
305 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED                 (1 << 26)
306 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED                (1 << 25)
307 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED                (1 << 24)
308 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL                (1 << 15)
309 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL               (1 << 9)
310 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL               (1 << 8)
311 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY               (1 << 7)
312 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY              (1 << 1)
313 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY              (1 << 0)
314
315 /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */
316
317 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS                          0xa8
318 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED          (1 << 11)
319 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED          (1 << 10)
320 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED          (1 << 9)
321 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED          (1 << 8)
322 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL         (1 << 7)
323 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL         (1 << 6)
324 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL         (1 << 5)
325 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL         (1 << 4)
326 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY        (1 << 3)
327 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY        (1 << 2)
328 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY        (1 << 1)
329 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY        (1 << 0)
330
331 /* TEGRA30_AHUB_I2S_INT_MASK */
332
333 #define TEGRA30_AHUB_I2S_INT_MASK                               0xb0
334
335 /* TEGRA30_AHUB_DAM_INT_MASK */
336
337 #define TEGRA30_AHUB_DAM_INT_MASK                               0xb4
338
339 /* TEGRA30_AHUB_SPDIF_INT_MASK */
340
341 #define TEGRA30_AHUB_SPDIF_INT_MASK                             0xbc
342
343 /* TEGRA30_AHUB_APBIF_INT_MASK */
344
345 #define TEGRA30_AHUB_APBIF_INT_MASK                             0xc0
346
347 /* TEGRA30_AHUB_I2S_INT_STATUS */
348
349 #define TEGRA30_AHUB_I2S_INT_STATUS                             0xc8
350
351 /* TEGRA30_AHUB_DAM_INT_STATUS */
352
353 #define TEGRA30_AHUB_DAM_INT_STATUS                             0xcc
354
355 /* TEGRA30_AHUB_SPDIF_INT_STATUS */
356
357 #define TEGRA30_AHUB_SPDIF_INT_STATUS                           0xd4
358
359 /* TEGRA30_AHUB_APBIF_INT_STATUS */
360
361 #define TEGRA30_AHUB_APBIF_INT_STATUS                           0xd8
362
363 /* TEGRA30_AHUB_I2S_INT_SOURCE */
364
365 #define TEGRA30_AHUB_I2S_INT_SOURCE                             0xe0
366
367 /* TEGRA30_AHUB_DAM_INT_SOURCE */
368
369 #define TEGRA30_AHUB_DAM_INT_SOURCE                             0xe4
370
371 /* TEGRA30_AHUB_SPDIF_INT_SOURCE */
372
373 #define TEGRA30_AHUB_SPDIF_INT_SOURCE                           0xec
374
375 /* TEGRA30_AHUB_APBIF_INT_SOURCE */
376
377 #define TEGRA30_AHUB_APBIF_INT_SOURCE                           0xf0
378
379 /* TEGRA30_AHUB_I2S_INT_SET */
380
381 #define TEGRA30_AHUB_I2S_INT_SET                                0xf8
382
383 /* TEGRA30_AHUB_DAM_INT_SET */
384
385 #define TEGRA30_AHUB_DAM_INT_SET                                0xfc
386
387 /* TEGRA30_AHUB_SPDIF_INT_SET */
388
389 #define TEGRA30_AHUB_SPDIF_INT_SET                              0x100
390
391 /* TEGRA30_AHUB_APBIF_INT_SET */
392
393 #define TEGRA30_AHUB_APBIF_INT_SET                              0x104
394
395 /* Registers within TEGRA30_AHUB_BASE */
396
397 #define TEGRA30_AHUB_AUDIO_RX                                   0x0
398 #define TEGRA30_AHUB_AUDIO_RX_STRIDE                            0x4
399 #define TEGRA30_AHUB_AUDIO_RX_COUNT                             17
400 /* This register repeats once for each entry in enum tegra30_ahub_rxcif */
401 /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */
402
403 /* apbif register count */
404 #define TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL               ((TEGRA30_AHUB_CIF_RX_CTRL>>2) + 1)
405 #define TEGRA30_APBIF_CACHE_REG_COUNT                           ((TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1) * TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
406
407 /* cache index to be skipped */
408 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD                      TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL
409 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD_STRIDE               (TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1)
410
411 /*
412  * Terminology:
413  * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
414  *       I2S controllers, SPDIF controllers, and DAMs.
415  * XBAR: The core cross-bar component of the AHUB.
416  * CIF:  Client Interface; the HW module connecting an audio device to the
417  *       XBAR.
418  * DAM:  Digital Audio Mixer: A HW module that mixes multiple audio streams,
419  *       possibly including sample-rate conversion.
420  *
421  * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
422  * transmitted by a particular TX CIF.
423  *
424  * This driver is currently very simplistic; many HW features are not
425  * exposed; DAMs are not supported, only 16-bit stereo audio is supported,
426  * etc.
427  */
428
429 enum tegra30_ahub_txcif {
430         TEGRA30_AHUB_TXCIF_APBIF_TX0,
431         TEGRA30_AHUB_TXCIF_APBIF_TX1,
432         TEGRA30_AHUB_TXCIF_APBIF_TX2,
433         TEGRA30_AHUB_TXCIF_APBIF_TX3,
434         TEGRA30_AHUB_TXCIF_I2S0_TX0,
435         TEGRA30_AHUB_TXCIF_I2S1_TX0,
436         TEGRA30_AHUB_TXCIF_I2S2_TX0,
437         TEGRA30_AHUB_TXCIF_I2S3_TX0,
438         TEGRA30_AHUB_TXCIF_I2S4_TX0,
439         TEGRA30_AHUB_TXCIF_DAM0_TX0,
440         TEGRA30_AHUB_TXCIF_DAM1_TX0,
441         TEGRA30_AHUB_TXCIF_DAM2_TX0,
442         TEGRA30_AHUB_TXCIF_SPDIF_TX0,
443         TEGRA30_AHUB_TXCIF_SPDIF_TX1,
444 };
445
446 enum tegra30_ahub_rxcif {
447         TEGRA30_AHUB_RXCIF_APBIF_RX0,
448         TEGRA30_AHUB_RXCIF_APBIF_RX1,
449         TEGRA30_AHUB_RXCIF_APBIF_RX2,
450         TEGRA30_AHUB_RXCIF_APBIF_RX3,
451         TEGRA30_AHUB_RXCIF_I2S0_RX0,
452         TEGRA30_AHUB_RXCIF_I2S1_RX0,
453         TEGRA30_AHUB_RXCIF_I2S2_RX0,
454         TEGRA30_AHUB_RXCIF_I2S3_RX0,
455         TEGRA30_AHUB_RXCIF_I2S4_RX0,
456         TEGRA30_AHUB_RXCIF_DAM0_RX0,
457         TEGRA30_AHUB_RXCIF_DAM0_RX1,
458         TEGRA30_AHUB_RXCIF_DAM1_RX0,
459         TEGRA30_AHUB_RXCIF_DAM1_RX1,
460         TEGRA30_AHUB_RXCIF_DAM2_RX0,
461         TEGRA30_AHUB_RXCIF_DAM2_RX1,
462         TEGRA30_AHUB_RXCIF_SPDIF_RX0,
463         TEGRA30_AHUB_RXCIF_SPDIF_RX1,
464 };
465
466 extern void tegra30_ahub_enable_clocks(void);
467 extern void tegra30_ahub_disable_clocks(void);
468 extern void tegra30_ahub_clock_set_rate(int rate);
469
470 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
471                                          unsigned long *fiforeg,
472                                          unsigned long *reqsel);
473 extern int tegra30_ahub_set_rx_cif_channels(enum tegra30_ahub_rxcif rxcif,
474                                             unsigned int audio_ch,
475                                             unsigned int client_ch);
476 extern int tegra30_ahub_set_rx_cif_bits(enum tegra30_ahub_rxcif rxcif,
477                                             unsigned int audio_bits,
478                                             unsigned int client_bits);
479 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
480 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
481 extern int tegra30_ahub_set_rx_fifo_pack_mode(enum tegra30_ahub_rxcif rxcif,
482                                                 unsigned int pack_mode);
483 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
484
485 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
486                                          unsigned long *fiforeg,
487                                          unsigned long *reqsel);
488 extern int tegra30_ahub_set_tx_cif_channels(enum tegra30_ahub_txcif txcif,
489                                             unsigned int audio_ch,
490                                             unsigned int client_ch);
491 extern int tegra30_ahub_set_tx_cif_bits(enum tegra30_ahub_txcif txcif,
492                                             unsigned int audio_bits,
493                                             unsigned int client_bits);
494 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
495 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
496 extern int tegra30_ahub_set_tx_fifo_pack_mode(enum tegra30_ahub_txcif txcif,
497                                                 unsigned int pack_mode);
498 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
499
500 extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
501                                           enum tegra30_ahub_txcif txcif);
502 extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);
503
504 extern int tegra30_ahub_rx_fifo_is_enabled(int i2s_id);
505 extern int tegra30_ahub_tx_fifo_is_enabled(int i2s_id);
506 extern int tegra30_ahub_rx_fifo_is_empty(int i2s_id);
507 extern int tegra30_ahub_tx_fifo_is_empty(int i2s_id);
508 extern int tegra30_ahub_dam_ch0_is_enabled(int dam_id);
509 extern int tegra30_ahub_dam_ch1_is_enabled(int dam_id);
510 extern int tegra30_ahub_dam_tx_is_enabled(int dam_id);
511 extern int tegra30_ahub_dam_ch0_is_empty(int dam_id);
512 extern int tegra30_ahub_dam_ch1_is_empty(int dam_id);
513 extern int tegra30_ahub_dam_tx_is_empty(int dam_id);
514
515
516 #ifdef CONFIG_PM
517 extern int tegra30_ahub_apbif_resume(void);
518 #endif
519
520 struct tegra30_ahub {
521         struct device *dev;
522         struct clk *clk_d_audio;
523         struct clk *clk_apbif;
524         resource_size_t apbif_addr;
525         void __iomem *apbif_regs;
526         void __iomem *audio_regs;
527         DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
528         DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
529         struct dentry *debug;
530 #ifdef CONFIG_PM
531         u32 ahub_reg_cache[TEGRA30_AHUB_AUDIO_RX_COUNT];
532         u32 apbif_reg_cache[TEGRA30_APBIF_CACHE_REG_COUNT];
533 #endif
534 };
535
536 #endif