ASoC: Tegra: Fix compiler warnings
[linux-2.6.git] / sound / soc / tegra / tegra30_ahub.h
1 /*
2  * tegra30_ahub.h - Definitions for Tegra 30 AHUB driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (C) 2011 - NVIDIA, Inc.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19  * 02110-1301 USA
20  *
21  */
22
23 #ifndef __TEGRA30_AHUB_H__
24 #define __TEGRA30_AHUB_H__
25
26 /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */
27
28 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT      28
29 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US    0xf
30 #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK       (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT)
31
32 /* Channel count minus 1 */
33 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT      24
34 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US    7
35 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK       (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT)
36
37 /* Channel count minus 1 */
38 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT     16
39 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US   7
40 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK      (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT)
41
42 #define TEGRA30_AUDIOCIF_BITS_4                         0
43 #define TEGRA30_AUDIOCIF_BITS_8                         1
44 #define TEGRA30_AUDIOCIF_BITS_12                        2
45 #define TEGRA30_AUDIOCIF_BITS_16                        3
46 #define TEGRA30_AUDIOCIF_BITS_20                        4
47 #define TEGRA30_AUDIOCIF_BITS_24                        5
48 #define TEGRA30_AUDIOCIF_BITS_28                        6
49 #define TEGRA30_AUDIOCIF_BITS_32                        7
50
51 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT          12
52 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK           (7                        << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
53 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4              (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
54 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8              (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
55 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12             (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
56 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16             (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
57 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20             (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
58 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24             (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
59 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28             (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
60 #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32             (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT)
61
62 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT         8
63 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK          (7                        << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
64 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4             (TEGRA30_AUDIOCIF_BITS_4  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
65 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8             (TEGRA30_AUDIOCIF_BITS_8  << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
66 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12            (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
67 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16            (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
68 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20            (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
69 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24            (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
70 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28            (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
71 #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32            (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT)
72
73 #define TEGRA30_AUDIOCIF_EXPAND_ZERO                    0
74 #define TEGRA30_AUDIOCIF_EXPAND_ONE                     1
75 #define TEGRA30_AUDIOCIF_EXPAND_LFSR                    2
76
77 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT              6
78 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK               (3                            << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
79 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO               (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
80 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE                (TEGRA30_AUDIOCIF_EXPAND_ONE  << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
81 #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR               (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT)
82
83 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0                0
84 #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1                1
85 #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG                2
86
87 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT         4
88 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK          (3                                << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
89 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0           (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
90 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1           (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
91 #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG           (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT)
92
93 #define TEGRA30_AUDIOCIF_CTRL_REPLICATE                 3
94
95 #define TEGRA30_AUDIOCIF_DIRECTION_TX                   0
96 #define TEGRA30_AUDIOCIF_DIRECTION_RX                   1
97
98 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT           2
99 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK            (1                             << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
100 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX              (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
101 #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX              (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT)
102
103 #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND                 0
104 #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP                  1
105
106 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT            1
107 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK             (1                               << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
108 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND            (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
109 #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP             (TEGRA30_AUDIOCIF_TRUNCATE_CHOP  << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT)
110
111 #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO                 0
112 #define TEGRA30_AUDIOCIF_MONO_CONV_COPY                 1
113
114 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT           0
115 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK            (1                               << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
116 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO            (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
117 #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY            (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT)
118
119 /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */
120
121 /* TEGRA30_AHUB_CHANNEL_CTRL */
122
123 #define TEGRA30_AHUB_CHANNEL_CTRL                       0x0
124 #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE                0x20
125 #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT                 4
126 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN                 (1 << 31)
127 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN                 (1 << 30)
128 #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK              (1 << 29)
129
130 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT    16
131 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US  0xff
132 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT)
133
134 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT    8
135 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US  0xff
136 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK     (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT)
137
138 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN            (1 << 6)
139
140 #define TEGRA30_PACK_8_4                                2
141 #define TEGRA30_PACK_16                                 3
142
143 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT         4
144 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US       3
145 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
146 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
147 #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT)
148
149 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN            (1 << 2)
150
151 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT         0
152 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US       3
153 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK          (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
154 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4           (TEGRA30_PACK_8_4                          << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
155 #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16            (TEGRA30_PACK_16                           << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT)
156
157 /* TEGRA30_AHUB_CHANNEL_CLEAR */
158
159 #define TEGRA30_AHUB_CHANNEL_CLEAR                      0x4
160 #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE               0x20
161 #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT                4
162 #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET        (1 << 31)
163 #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET        (1 << 30)
164
165 /* TEGRA30_AHUB_CHANNEL_STATUS */
166
167 #define TEGRA30_AHUB_CHANNEL_STATUS                     0x8
168 #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE              0x20
169 #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT               4
170 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT       24
171 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US     0xff
172 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT)
173 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT       16
174 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US     0xff
175 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK        (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT)
176 #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG             (1 << 1)
177 #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG             (1 << 0)
178
179 /* TEGRA30_AHUB_CHANNEL_TXFIFO */
180
181 #define TEGRA30_AHUB_CHANNEL_TXFIFO                     0xc
182 #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE              0x20
183 #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT               4
184
185 /* TEGRA30_AHUB_CHANNEL_RXFIFO */
186
187 #define TEGRA30_AHUB_CHANNEL_RXFIFO                     0x10
188 #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE              0x20
189 #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT               4
190
191 /* TEGRA30_AHUB_CIF_TX_CTRL */
192
193 #define TEGRA30_AHUB_CIF_TX_CTRL                        0x14
194 #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE                 0x20
195 #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT                  4
196 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
197
198 /* TEGRA30_AHUB_CIF_RX_CTRL */
199
200 #define TEGRA30_AHUB_CIF_RX_CTRL                        0x18
201 #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE                 0x20
202 #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT                  4
203 /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */
204
205 /* TEGRA30_AHUB_CONFIG_LINK_CTRL */
206
207 #define TEGRA30_AHUB_CONFIG_LINK_CTRL                                   0x80
208 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT        28
209 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US      0xf
210 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK         (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT)
211 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT                 16
212 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US               0xfff
213 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK                  (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT)
214 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT                    5
215 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US                  0xfff
216 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK                     (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT)
217 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN                             (1 << 2)
218 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR                (1 << 1)
219 #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET                        (1 << 0)
220
221 /* TEGRA30_AHUB_MISC_CTRL */
222
223 #define TEGRA30_AHUB_MISC_CTRL                          0x84
224 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE             (1 << 31)
225 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN              (1 << 9)
226 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT      0
227 #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK       (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT)
228
229 /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */
230
231 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS                         0x88
232 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL    (1 << 31)
233 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL    (1 << 30)
234 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL    (1 << 29)
235 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL    (1 << 28)
236 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL    (1 << 27)
237 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL    (1 << 26)
238 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL    (1 << 25)
239 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL    (1 << 24)
240 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY   (1 << 23)
241 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY   (1 << 22)
242 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY   (1 << 21)
243 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY   (1 << 20)
244 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY   (1 << 19)
245 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY   (1 << 18)
246 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY   (1 << 17)
247 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY   (1 << 16)
248 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL    (1 << 15)
249 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL    (1 << 14)
250 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL    (1 << 13)
251 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL    (1 << 12)
252 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL    (1 << 11)
253 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL    (1 << 10)
254 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL    (1 << 9)
255 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL    (1 << 8)
256 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY   (1 << 7)
257 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY   (1 << 6)
258 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY   (1 << 5)
259 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY   (1 << 4)
260 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY   (1 << 3)
261 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY   (1 << 2)
262 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY   (1 << 1)
263 #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY   (1 << 0)
264
265 /* TEGRA30_AHUB_I2S_LIVE_STATUS */
266
267 #define TEGRA30_AHUB_I2S_LIVE_STATUS                            0x8c
268 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL          (1 << 29)
269 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL          (1 << 28)
270 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL          (1 << 27)
271 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL          (1 << 26)
272 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL          (1 << 25)
273 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL          (1 << 24)
274 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL          (1 << 23)
275 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL          (1 << 22)
276 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL          (1 << 21)
277 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL          (1 << 20)
278 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED       (1 << 19)
279 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED       (1 << 18)
280 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED       (1 << 17)
281 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED       (1 << 16)
282 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED       (1 << 15)
283 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED       (1 << 14)
284 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED       (1 << 13)
285 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED       (1 << 12)
286 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED       (1 << 11)
287 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED       (1 << 10)
288 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY         (1 << 9)
289 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY         (1 << 8)
290 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY         (1 << 7)
291 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY         (1 << 6)
292 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY         (1 << 5)
293 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY         (1 << 4)
294 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY         (1 << 3)
295 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY         (1 << 2)
296 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY         (1 << 1)
297 #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY         (1 << 0)
298
299 /* TEGRA30_AHUB_DAM0_LIVE_STATUS */
300
301 #define TEGRA30_AHUB_DAM_LIVE_STATUS                            0x90
302 #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE                     0x8
303 #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT                      3
304 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED                 (1 << 26)
305 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED                (1 << 25)
306 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED                (1 << 24)
307 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL                (1 << 15)
308 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL               (1 << 9)
309 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL               (1 << 8)
310 #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY               (1 << 7)
311 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY              (1 << 1)
312 #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY              (1 << 0)
313
314 /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */
315
316 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS                          0xa8
317 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED          (1 << 11)
318 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED          (1 << 10)
319 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED          (1 << 9)
320 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED          (1 << 8)
321 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL         (1 << 7)
322 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL         (1 << 6)
323 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL         (1 << 5)
324 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL         (1 << 4)
325 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY        (1 << 3)
326 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY        (1 << 2)
327 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY        (1 << 1)
328 #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY        (1 << 0)
329
330 /* TEGRA30_AHUB_I2S_INT_MASK */
331
332 #define TEGRA30_AHUB_I2S_INT_MASK                               0xb0
333
334 /* TEGRA30_AHUB_DAM_INT_MASK */
335
336 #define TEGRA30_AHUB_DAM_INT_MASK                               0xb4
337
338 /* TEGRA30_AHUB_SPDIF_INT_MASK */
339
340 #define TEGRA30_AHUB_SPDIF_INT_MASK                             0xbc
341
342 /* TEGRA30_AHUB_APBIF_INT_MASK */
343
344 #define TEGRA30_AHUB_APBIF_INT_MASK                             0xc0
345
346 /* TEGRA30_AHUB_I2S_INT_STATUS */
347
348 #define TEGRA30_AHUB_I2S_INT_STATUS                             0xc8
349
350 /* TEGRA30_AHUB_DAM_INT_STATUS */
351
352 #define TEGRA30_AHUB_DAM_INT_STATUS                             0xcc
353
354 /* TEGRA30_AHUB_SPDIF_INT_STATUS */
355
356 #define TEGRA30_AHUB_SPDIF_INT_STATUS                           0xd4
357
358 /* TEGRA30_AHUB_APBIF_INT_STATUS */
359
360 #define TEGRA30_AHUB_APBIF_INT_STATUS                           0xd8
361
362 /* TEGRA30_AHUB_I2S_INT_SOURCE */
363
364 #define TEGRA30_AHUB_I2S_INT_SOURCE                             0xe0
365
366 /* TEGRA30_AHUB_DAM_INT_SOURCE */
367
368 #define TEGRA30_AHUB_DAM_INT_SOURCE                             0xe4
369
370 /* TEGRA30_AHUB_SPDIF_INT_SOURCE */
371
372 #define TEGRA30_AHUB_SPDIF_INT_SOURCE                           0xec
373
374 /* TEGRA30_AHUB_APBIF_INT_SOURCE */
375
376 #define TEGRA30_AHUB_APBIF_INT_SOURCE                           0xf0
377
378 /* TEGRA30_AHUB_I2S_INT_SET */
379
380 #define TEGRA30_AHUB_I2S_INT_SET                                0xf8
381
382 /* TEGRA30_AHUB_DAM_INT_SET */
383
384 #define TEGRA30_AHUB_DAM_INT_SET                                0xfc
385
386 /* TEGRA30_AHUB_SPDIF_INT_SET */
387
388 #define TEGRA30_AHUB_SPDIF_INT_SET                              0x100
389
390 /* TEGRA30_AHUB_APBIF_INT_SET */
391
392 #define TEGRA30_AHUB_APBIF_INT_SET                              0x104
393
394 /* Registers within TEGRA30_AHUB_BASE */
395
396 #define TEGRA30_AHUB_AUDIO_RX                                   0x0
397 #define TEGRA30_AHUB_AUDIO_RX_STRIDE                            0x4
398 #define TEGRA30_AHUB_AUDIO_RX_COUNT                             17
399 /* This register repeats once for each entry in enum tegra30_ahub_rxcif */
400 /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */
401
402 /* apbif register count */
403 #define TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL               ((TEGRA30_AHUB_CIF_RX_CTRL>>2) + 1)
404 #define TEGRA30_APBIF_CACHE_REG_COUNT                           ((TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1) * TEGRA30_AHUB_CHANNEL_CTRL_COUNT)
405
406 /* cache index to be skipped */
407 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD                      TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL
408 #define TEGRA30_APBIF_CACHE_REG_INDEX_RSVD_STRIDE               (TEGRA30_APBIF_CACHE_REG_COUNT_PER_CHANNEL + 1)
409
410 /*
411  * Terminology:
412  * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs,
413  *       I2S controllers, SPDIF controllers, and DAMs.
414  * XBAR: The core cross-bar component of the AHUB.
415  * CIF:  Client Interface; the HW module connecting an audio device to the
416  *       XBAR.
417  * DAM:  Digital Audio Mixer: A HW module that mixes multiple audio streams,
418  *       possibly including sample-rate conversion.
419  *
420  * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
421  * transmitted by a particular TX CIF.
422  *
423  * This driver is currently very simplistic; many HW features are not
424  * exposed; DAMs are not supported, only 16-bit stereo audio is supported,
425  * etc.
426  */
427
428 enum tegra30_ahub_txcif {
429         TEGRA30_AHUB_TXCIF_APBIF_TX0,
430         TEGRA30_AHUB_TXCIF_APBIF_TX1,
431         TEGRA30_AHUB_TXCIF_APBIF_TX2,
432         TEGRA30_AHUB_TXCIF_APBIF_TX3,
433         TEGRA30_AHUB_TXCIF_I2S0_TX0,
434         TEGRA30_AHUB_TXCIF_I2S1_TX0,
435         TEGRA30_AHUB_TXCIF_I2S2_TX0,
436         TEGRA30_AHUB_TXCIF_I2S3_TX0,
437         TEGRA30_AHUB_TXCIF_I2S4_TX0,
438         TEGRA30_AHUB_TXCIF_DAM0_TX0,
439         TEGRA30_AHUB_TXCIF_DAM1_TX0,
440         TEGRA30_AHUB_TXCIF_DAM2_TX0,
441         TEGRA30_AHUB_TXCIF_SPDIF_TX0,
442         TEGRA30_AHUB_TXCIF_SPDIF_TX1,
443 };
444
445 enum tegra30_ahub_rxcif {
446         TEGRA30_AHUB_RXCIF_APBIF_RX0,
447         TEGRA30_AHUB_RXCIF_APBIF_RX1,
448         TEGRA30_AHUB_RXcIF_APBIF_RX2,
449         TEGRA30_AHUB_RXCIF_APBIF_RX3,
450         TEGRA30_AHUB_RXCIF_I2S0_RX0,
451         TEGRA30_AHUB_RXCIF_I2S1_RX0,
452         TEGRA30_AHUB_RXCIF_I2S2_RX0,
453         TEGRA30_AHUB_RXCIF_I2S3_RX0,
454         TEGRA30_AHUB_RXCIF_I2S4_RX0,
455         TEGRA30_AHUB_RXCIF_DAM0_RX0,
456         TEGRA30_AHUB_RXCIF_DAM0_RX1,
457         TEGRA30_AHUB_RXCIF_DAM1_RX0,
458         TEGRA30_AHUB_RXCIF_DAM2_RX1,
459         TEGRA30_AHUB_RXCIF_DAM3_RX0,
460         TEGRA30_AHUB_RXCIF_DAM3_RX1,
461         TEGRA30_AHUB_RXCIF_SPDIF_RX0,
462         TEGRA30_AHUB_RXCIF_SPDIF_RX1,
463 };
464
465 extern void tegra30_ahub_enable_clocks(void);
466 extern void tegra30_ahub_disable_clocks(void);
467
468 extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
469                                          unsigned long *fiforeg,
470                                          unsigned long *reqsel);
471 extern int tegra30_ahub_set_rx_cif_channels(enum tegra30_ahub_rxcif rxcif,
472                                             unsigned int audio_ch,
473                                             unsigned int client_ch);
474 extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
475 extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
476 extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
477
478 extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
479                                          unsigned long *fiforeg,
480                                          unsigned long *reqsel);
481 extern int tegra30_ahub_set_tx_cif_channels(enum tegra30_ahub_txcif txcif,
482                                             unsigned int audio_ch,
483                                             unsigned int client_ch);
484 extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
485 extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
486 extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
487
488 extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
489                                           enum tegra30_ahub_txcif txcif);
490 extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif);
491
492 #ifdef CONFIG_PM
493 extern int tegra30_ahub_apbif_resume(void);
494 #endif
495
496 struct tegra30_ahub {
497         struct device *dev;
498         struct clk *clk_d_audio;
499         struct clk *clk_apbif;
500         resource_size_t apbif_addr;
501         void __iomem *apbif_regs;
502         void __iomem *audio_regs;
503         DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
504         DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT);
505         struct dentry *debug;
506 #ifdef CONFIG_PM
507         u32 ahub_reg_cache[TEGRA30_AHUB_AUDIO_RX_COUNT];
508         u32 apbif_reg_cache[TEGRA30_APBIF_CACHE_REG_COUNT];
509 #endif
510 };
511
512 #endif