soc: codecs: rt5639: Implement i2c shutdown
[linux-2.6.git] / sound / soc / tegra / tegra20_i2s.c
1 /*
2  * tegra20_i2s.c - Tegra20 I2S driver
3  *
4  * Author: Stephen Warren <swarren@nvidia.com>
5  * Copyright (C) 2010 - NVIDIA, Inc.
6  *
7  * Based on code copyright/by:
8  *
9  * Copyright (c) 2009-2010, NVIDIA Corporation.
10  * Scott Peterson <speterson@nvidia.com>
11  *
12  * Copyright (C) 2010 Google, Inc.
13  * Iliyan Malchev <malchev@google.com>
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License
17  * version 2 as published by the Free Software Foundation.
18  *
19  * This program is distributed in the hope that it will be useful, but
20  * WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
22  * General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, write to the Free Software
26  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
27  * 02110-1301 USA
28  *
29  */
30 #include <asm/mach-types.h>
31 #include <linux/clk.h>
32 #include <linux/module.h>
33 #include <linux/debugfs.h>
34 #include <linux/device.h>
35 #include <linux/platform_device.h>
36 #include <linux/seq_file.h>
37 #include <linux/slab.h>
38 #include <linux/io.h>
39 #include <linux/of.h>
40 #include <mach/iomap.h>
41 #include <sound/core.h>
42 #include <sound/pcm.h>
43 #include <sound/pcm_params.h>
44 #include <sound/soc.h>
45
46 #include "tegra20_i2s.h"
47 #include "tegra20_das.h"
48
49 #define DRV_NAME "tegra20-i2s"
50
51 static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
52 {
53 #ifdef CONFIG_PM
54         i2s->reg_cache[reg >> 2] = val;
55 #endif
56         __raw_writel(val, i2s->regs + reg);
57 }
58
59 static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
60 {
61         return __raw_readl(i2s->regs + reg);
62 }
63
64 #ifdef CONFIG_DEBUG_FS
65 static int tegra20_i2s_show(struct seq_file *s, void *unused)
66 {
67 #define REG(r) { r, #r }
68         static const struct {
69                 int offset;
70                 const char *name;
71         } regs[] = {
72                 REG(TEGRA20_I2S_CTRL),
73                 REG(TEGRA20_I2S_STATUS),
74                 REG(TEGRA20_I2S_TIMING),
75                 REG(TEGRA20_I2S_FIFO_SCR),
76                 REG(TEGRA20_I2S_PCM_CTRL),
77                 REG(TEGRA20_I2S_NW_CTRL),
78                 REG(TEGRA20_I2S_TDM_CTRL),
79                 REG(TEGRA20_I2S_TDM_TX_RX_CTRL),
80         };
81 #undef REG
82
83         struct tegra20_i2s *i2s = s->private;
84         int i;
85
86         clk_enable(i2s->clk_i2s);
87
88         for (i = 0; i < ARRAY_SIZE(regs); i++) {
89                 u32 val = tegra20_i2s_read(i2s, regs[i].offset);
90                 seq_printf(s, "%s = %08x\n", regs[i].name, val);
91         }
92
93         clk_disable(i2s->clk_i2s);
94
95         return 0;
96 }
97
98 static int tegra20_i2s_debug_open(struct inode *inode, struct file *file)
99 {
100         return single_open(file, tegra20_i2s_show, inode->i_private);
101 }
102
103 static const struct file_operations tegra20_i2s_debug_fops = {
104         .open    = tegra20_i2s_debug_open,
105         .read    = seq_read,
106         .llseek  = seq_lseek,
107         .release = single_release,
108 };
109
110 static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s)
111 {
112         i2s->debug = debugfs_create_file(i2s->dai.name, S_IRUGO,
113                                          snd_soc_debugfs_root, i2s,
114                                          &tegra20_i2s_debug_fops);
115 }
116
117 static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
118 {
119         if (i2s->debug)
120                 debugfs_remove(i2s->debug);
121 }
122 #else
123 static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
124 {
125 }
126
127 static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
128 {
129 }
130 #endif
131
132 static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
133                                 unsigned int fmt)
134 {
135         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
136
137         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
138         case SND_SOC_DAIFMT_NB_NF:
139                 break;
140         default:
141                 return -EINVAL;
142         }
143
144         i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
145         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
146         case SND_SOC_DAIFMT_CBS_CFS:
147                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
148                 break;
149         case SND_SOC_DAIFMT_CBM_CFM:
150                 break;
151         default:
152                 return -EINVAL;
153         }
154
155         i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
156                                 TEGRA20_I2S_CTRL_LRCK_MASK);
157         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
158         case SND_SOC_DAIFMT_DSP_A:
159                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
160                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
161                 break;
162         case SND_SOC_DAIFMT_DSP_B:
163                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
164                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
165                 break;
166         case SND_SOC_DAIFMT_I2S:
167                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
168                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
169                 break;
170         case SND_SOC_DAIFMT_RIGHT_J:
171                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
172                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
173                 break;
174         case SND_SOC_DAIFMT_LEFT_J:
175                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
176                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
177                 break;
178         default:
179                 return -EINVAL;
180         }
181
182         return 0;
183 }
184
185 static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
186                                 struct snd_pcm_hw_params *params,
187                                 struct snd_soc_dai *dai)
188 {
189         struct device *dev = substream->pcm->card->dev;
190         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
191         u32 reg;
192         int ret, sample_size, srate, i2sclock, bitcnt, i2sclk_div;
193         u32 bit_format = i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_MASK;
194
195         if ((bit_format == TEGRA20_I2S_CTRL_BIT_FORMAT_I2S) &&
196             (params_channels(params) != 2)) {
197                 dev_err(dev, "Only Stereo is supported in I2s mode\n");
198                 return -EINVAL;
199         }
200
201         i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
202         switch (params_format(params)) {
203         case SNDRV_PCM_FORMAT_S16_LE:
204                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
205                 sample_size = 16;
206                 break;
207         case SNDRV_PCM_FORMAT_S24_LE:
208                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
209                 sample_size = 24;
210                 break;
211         case SNDRV_PCM_FORMAT_S32_LE:
212                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
213                 sample_size = 32;
214                 break;
215         default:
216                 return -EINVAL;
217         }
218
219         srate = params_rate(params);
220
221         /* Final "* 2" required by Tegra hardware */
222         i2sclock = srate * params_channels(params) * sample_size * 2;
223
224         /* Additional "* 2" is needed for DSP mode */
225         if (i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_DSP && !machine_is_whistler())
226                 i2sclock *= 2;
227
228         ret = clk_set_rate(i2s->clk_i2s, i2sclock);
229         if (ret) {
230                 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
231                 return ret;
232         }
233
234         if (i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_DSP)
235                 i2sclk_div = srate;
236         else
237                 i2sclk_div = params_channels(params) * srate;
238
239         bitcnt = (i2sclock / i2sclk_div) - 1;
240
241         if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
242                 return -EINVAL;
243         reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
244
245         if (i2sclock % i2sclk_div)
246                 reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
247
248         clk_enable(i2s->clk_i2s);
249
250         tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
251
252         if (sample_size * params_channels(params) >= 32)
253                 tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
254                         TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
255                         TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
256         else
257                 tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
258                         TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS |
259                         TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS);
260
261         i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
262         reg = tegra20_i2s_read(i2s, TEGRA20_I2S_PCM_CTRL);
263         if (i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_DSP) {
264                 if (sample_size == 16)
265                         i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB;
266                 else if (sample_size == 24)
267                         i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB;
268                 else
269                         i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO_FORMAT_32;
270
271                 i2s->capture_dma_data.width = sample_size;
272                 i2s->playback_dma_data.width = sample_size;
273
274                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
275                         reg |= TEGRA20_I2S_PCM_CTRL_TRM_MODE_EN;
276                 else
277                         reg |= TEGRA20_I2S_PCM_CTRL_RCV_MODE_EN;
278         } else {
279                 i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
280                 i2s->capture_dma_data.width = 32;
281                 i2s->playback_dma_data.width = 32;
282                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
283                         reg &= ~TEGRA20_I2S_PCM_CTRL_TRM_MODE_EN;
284                 else
285                         reg &= ~TEGRA20_I2S_PCM_CTRL_RCV_MODE_EN;
286         }
287         tegra20_i2s_write(i2s, TEGRA20_I2S_PCM_CTRL, reg);
288
289         clk_disable(i2s->clk_i2s);
290
291         return 0;
292 }
293
294 static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
295 {
296         i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
297         tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
298 }
299
300 static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
301 {
302         i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
303         tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
304 }
305
306 static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
307 {
308         i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
309         tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
310 }
311
312 static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
313 {
314         i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
315         tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
316 }
317
318 static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
319                                 struct snd_soc_dai *dai)
320 {
321         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
322
323         switch (cmd) {
324         case SNDRV_PCM_TRIGGER_START:
325         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
326         case SNDRV_PCM_TRIGGER_RESUME:
327                 clk_enable(i2s->clk_i2s);
328                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
329                         tegra20_i2s_start_playback(i2s);
330                 else
331                         tegra20_i2s_start_capture(i2s);
332                 break;
333         case SNDRV_PCM_TRIGGER_STOP:
334         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
335         case SNDRV_PCM_TRIGGER_SUSPEND:
336                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
337                         tegra20_i2s_stop_playback(i2s);
338                 else
339                         tegra20_i2s_stop_capture(i2s);
340                 clk_disable(i2s->clk_i2s);
341                 break;
342         default:
343                 return -EINVAL;
344         }
345
346         return 0;
347 }
348
349 static int tegra20_i2s_probe(struct snd_soc_dai *dai)
350 {
351         struct tegra20_i2s * i2s = snd_soc_dai_get_drvdata(dai);
352 #ifdef CONFIG_PM
353         int i;
354 #endif
355
356         dai->capture_dma_data = &i2s->capture_dma_data;
357         dai->playback_dma_data = &i2s->playback_dma_data;
358
359 #ifdef CONFIG_PM
360         /* populate the i2s reg cache with POR values*/
361         clk_enable(i2s->clk_i2s);
362
363         for (i = 0; i < ((TEGRA20_I2S_TDM_TX_RX_CTRL >> 2) + 1); i++) {
364                 if ((i == TEGRA20_I2S_CACHE_RSVD_6) ||
365                         (i == TEGRA20_I2S_CACHE_RSVD_7))
366                         continue;
367
368                 i2s->reg_cache[i] = tegra20_i2s_read(i2s, i << 2);
369         }
370
371         clk_disable(i2s->clk_i2s);
372 #endif
373
374         return 0;
375 }
376
377 #ifdef CONFIG_PM
378 int tegra20_i2s_resume(struct snd_soc_dai *cpu_dai)
379 {
380         struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai);
381         int i;
382
383         clk_enable(i2s->clk_i2s);
384
385         /*restore the i2s regs*/
386         for (i = 0; i < ((TEGRA20_I2S_TDM_TX_RX_CTRL >> 2) + 1); i++) {
387                 if ((i == TEGRA20_I2S_CACHE_RSVD_6) ||
388                         (i == TEGRA20_I2S_CACHE_RSVD_7))
389                         continue;
390
391                 tegra20_i2s_write(i2s, i << 2, i2s->reg_cache[i]);
392         }
393
394         /*restore the das regs*/
395         tegra20_das_resume();
396
397         clk_disable(i2s->clk_i2s);
398
399         return 0;
400 }
401 #else
402 #define tegra20_i2s_resume NULL
403 #endif
404
405 static const struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
406         .set_fmt        = tegra20_i2s_set_fmt,
407         .hw_params      = tegra20_i2s_hw_params,
408         .trigger        = tegra20_i2s_trigger,
409 };
410
411 static const struct snd_soc_dai_driver tegra20_i2s_dai_template = {
412         .probe = tegra20_i2s_probe,
413         .resume = tegra20_i2s_resume,
414         .playback = {
415                 .channels_min = 1,
416                 .channels_max = 2,
417                 .rates = SNDRV_PCM_RATE_8000_96000,
418                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
419         },
420         .capture = {
421                 .channels_min = 1,
422                 .channels_max = 2,
423                 .rates = SNDRV_PCM_RATE_8000_96000,
424                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
425         },
426         .ops = &tegra20_i2s_dai_ops,
427         .symmetric_rates = 1,
428 };
429
430 static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
431 {
432         struct tegra20_i2s * i2s;
433         struct resource *mem, *memregion, *dmareq;
434         u32 of_dma[2];
435         u32 dma_ch;
436         int ret;
437
438         i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_i2s), GFP_KERNEL);
439         if (!i2s) {
440                 dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
441                 ret = -ENOMEM;
442                 goto err;
443         }
444         dev_set_drvdata(&pdev->dev, i2s);
445
446         i2s->dai = tegra20_i2s_dai_template;
447         i2s->dai.name = dev_name(&pdev->dev);
448
449         i2s->clk_i2s = clk_get(&pdev->dev, NULL);
450         if (IS_ERR(i2s->clk_i2s)) {
451                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
452                 ret = PTR_ERR(i2s->clk_i2s);
453                 goto err;
454         }
455
456         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457         if (!mem) {
458                 dev_err(&pdev->dev, "No memory resource\n");
459                 ret = -ENODEV;
460                 goto err_clk_put;
461         }
462
463         dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
464         if (!dmareq) {
465                 if (of_property_read_u32_array(pdev->dev.of_node,
466                                         "nvidia,dma-request-selector",
467                                         of_dma, 2) < 0) {
468                         dev_err(&pdev->dev, "No DMA resource\n");
469                         ret = -ENODEV;
470                         goto err_clk_put;
471                 }
472                 dma_ch = of_dma[1];
473         } else {
474                 dma_ch = dmareq->start;
475         }
476
477         memregion = devm_request_mem_region(&pdev->dev, mem->start,
478                                             resource_size(mem), DRV_NAME);
479         if (!memregion) {
480                 dev_err(&pdev->dev, "Memory region already claimed\n");
481                 ret = -EBUSY;
482                 goto err_clk_put;
483         }
484
485         i2s->regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
486         if (!i2s->regs) {
487                 dev_err(&pdev->dev, "ioremap failed\n");
488                 ret = -ENOMEM;
489                 goto err_clk_put;
490         }
491
492         i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
493         i2s->capture_dma_data.wrap = 4;
494         i2s->capture_dma_data.width = 32;
495         i2s->capture_dma_data.req_sel = dma_ch;
496
497         i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
498         i2s->playback_dma_data.wrap = 4;
499         i2s->playback_dma_data.width = 32;
500         i2s->playback_dma_data.req_sel = dma_ch;
501
502         ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
503         if (ret) {
504                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
505                 ret = -ENOMEM;
506                 goto err_clk_put;
507         }
508
509         tegra20_i2s_debug_add(i2s);
510
511         return 0;
512
513 err_clk_put:
514         clk_put(i2s->clk_i2s);
515 err:
516         return ret;
517 }
518
519 static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
520 {
521         struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
522
523         snd_soc_unregister_dai(&pdev->dev);
524
525         tegra20_i2s_debug_remove(i2s);
526
527         clk_put(i2s->clk_i2s);
528
529         return 0;
530 }
531
532 static const struct of_device_id tegra20_i2s_of_match[] __devinitconst = {
533         { .compatible = "nvidia,tegra20-i2s", },
534         {},
535 };
536
537 static struct platform_driver tegra20_i2s_driver = {
538         .driver = {
539                 .name = DRV_NAME,
540                 .owner = THIS_MODULE,
541                 .of_match_table = tegra20_i2s_of_match,
542         },
543         .probe = tegra20_i2s_platform_probe,
544         .remove = __devexit_p(tegra20_i2s_platform_remove),
545 };
546 module_platform_driver(tegra20_i2s_driver);
547
548 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
549 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
550 MODULE_LICENSE("GPL");
551 MODULE_ALIAS("platform:" DRV_NAME);
552 MODULE_DEVICE_TABLE(of, tegra20_i2s_of_match);