ALSA: ASoC: Blackfin: update SPORT0 port selector (v2)
[linux-2.6.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32
33 #include <mach/control.h>
34 #include <mach/dma.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
37 #include "omap-pcm.h"
38
39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_44100 | \
40                                  SNDRV_PCM_RATE_48000 | \
41                                  SNDRV_PCM_RATE_KNOT)
42
43 struct omap_mcbsp_data {
44         unsigned int                    bus_id;
45         struct omap_mcbsp_reg_cfg       regs;
46         unsigned int                    fmt;
47         /*
48          * Flags indicating is the bus already activated and configured by
49          * another substream
50          */
51         int                             active;
52         int                             configured;
53 };
54
55 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
56
57 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
58
59 /*
60  * Stream DMA parameters. DMA request line and port address are set runtime
61  * since they are different between OMAP1 and later OMAPs
62  */
63 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
64
65 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
66 static const int omap1_dma_reqs[][2] = {
67         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
68         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
69         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
70 };
71 static const unsigned long omap1_mcbsp_port[][2] = {
72         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
73           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
74         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
75           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
76         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
77           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
78 };
79 #else
80 static const int omap1_dma_reqs[][2] = {};
81 static const unsigned long omap1_mcbsp_port[][2] = {};
82 #endif
83
84 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
85 static const int omap24xx_dma_reqs[][2] = {
86         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
87         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
88 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
89         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
90         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
91         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
92 #endif
93 };
94 #else
95 static const int omap24xx_dma_reqs[][2] = {};
96 #endif
97
98 #if defined(CONFIG_ARCH_OMAP2420)
99 static const unsigned long omap2420_mcbsp_port[][2] = {
100         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
101           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
102         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
103           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
104 };
105 #else
106 static const unsigned long omap2420_mcbsp_port[][2] = {};
107 #endif
108
109 #if defined(CONFIG_ARCH_OMAP2430)
110 static const unsigned long omap2430_mcbsp_port[][2] = {
111         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
112           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
113         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
114           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
115         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
116           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
117         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
118           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
119         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
120           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
121 };
122 #else
123 static const unsigned long omap2430_mcbsp_port[][2] = {};
124 #endif
125
126 #if defined(CONFIG_ARCH_OMAP34XX)
127 static const unsigned long omap34xx_mcbsp_port[][2] = {
128         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
129           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
130         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
131           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
132         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
133           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
134         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
135           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
136         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
137           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
138 };
139 #else
140 static const unsigned long omap34xx_mcbsp_port[][2] = {};
141 #endif
142
143 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
144 {
145         struct snd_soc_pcm_runtime *rtd = substream->private_data;
146         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
147         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
148         int err = 0;
149
150         if (!cpu_dai->active)
151                 err = omap_mcbsp_request(mcbsp_data->bus_id);
152
153         return err;
154 }
155
156 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
157 {
158         struct snd_soc_pcm_runtime *rtd = substream->private_data;
159         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
160         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
161
162         if (!cpu_dai->active) {
163                 omap_mcbsp_free(mcbsp_data->bus_id);
164                 mcbsp_data->configured = 0;
165         }
166 }
167
168 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
169 {
170         struct snd_soc_pcm_runtime *rtd = substream->private_data;
171         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
172         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
173         int err = 0;
174
175         switch (cmd) {
176         case SNDRV_PCM_TRIGGER_START:
177         case SNDRV_PCM_TRIGGER_RESUME:
178         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
179                 if (!mcbsp_data->active++)
180                         omap_mcbsp_start(mcbsp_data->bus_id);
181                 break;
182
183         case SNDRV_PCM_TRIGGER_STOP:
184         case SNDRV_PCM_TRIGGER_SUSPEND:
185         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
186                 if (!--mcbsp_data->active)
187                         omap_mcbsp_stop(mcbsp_data->bus_id);
188                 break;
189         default:
190                 err = -EINVAL;
191         }
192
193         return err;
194 }
195
196 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
197                                     struct snd_pcm_hw_params *params)
198 {
199         struct snd_soc_pcm_runtime *rtd = substream->private_data;
200         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
201         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
202         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
203         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
204         int wlen;
205         unsigned long port;
206
207         if (cpu_class_is_omap1()) {
208                 dma = omap1_dma_reqs[bus_id][substream->stream];
209                 port = omap1_mcbsp_port[bus_id][substream->stream];
210         } else if (cpu_is_omap2420()) {
211                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
212                 port = omap2420_mcbsp_port[bus_id][substream->stream];
213         } else if (cpu_is_omap2430()) {
214                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
215                 port = omap2430_mcbsp_port[bus_id][substream->stream];
216         } else if (cpu_is_omap343x()) {
217                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
218                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
219         } else {
220                 return -ENODEV;
221         }
222         omap_mcbsp_dai_dma_params[id][substream->stream].name =
223                 substream->stream ? "Audio Capture" : "Audio Playback";
224         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
225         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
226         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
227
228         if (mcbsp_data->configured) {
229                 /* McBSP already configured by another stream */
230                 return 0;
231         }
232
233         switch (params_channels(params)) {
234         case 2:
235                 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
236                 regs->rcr2      |= RFRLEN2(1 - 1) | RPHASE;
237                 regs->rcr1      |= RFRLEN1(1 - 1);
238                 regs->xcr2      |= XFRLEN2(1 - 1) | XPHASE;
239                 regs->xcr1      |= XFRLEN1(1 - 1);
240                 break;
241         default:
242                 /* Unsupported number of channels */
243                 return -EINVAL;
244         }
245
246         switch (params_format(params)) {
247         case SNDRV_PCM_FORMAT_S16_LE:
248                 /* Set word lengths */
249                 wlen = 16;
250                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
251                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
252                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
253                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
254                 break;
255         default:
256                 /* Unsupported PCM format */
257                 return -EINVAL;
258         }
259
260         /* Set FS period and length in terms of bit clock periods */
261         switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
262         case SND_SOC_DAIFMT_I2S:
263                 regs->srgr2     |= FPER(wlen * 2 - 1);
264                 regs->srgr1     |= FWID(wlen - 1);
265                 break;
266         case SND_SOC_DAIFMT_DSP_A:
267                 regs->srgr2     |= FPER(wlen * 2 - 1);
268                 regs->srgr1     |= FWID(wlen * 2 - 2);
269                 break;
270         }
271
272         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
273         mcbsp_data->configured = 1;
274
275         return 0;
276 }
277
278 /*
279  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
280  * cache is initialized here
281  */
282 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
283                                       unsigned int fmt)
284 {
285         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
286         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
287
288         if (mcbsp_data->configured)
289                 return 0;
290
291         mcbsp_data->fmt = fmt;
292         memset(regs, 0, sizeof(*regs));
293         /* Generic McBSP register settings */
294         regs->spcr2     |= XINTM(3) | FREE;
295         regs->spcr1     |= RINTM(3);
296         regs->rcr2      |= RFIG;
297         regs->xcr2      |= XFIG;
298
299         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
300         case SND_SOC_DAIFMT_I2S:
301                 /* 1-bit data delay */
302                 regs->rcr2      |= RDATDLY(1);
303                 regs->xcr2      |= XDATDLY(1);
304                 break;
305         case SND_SOC_DAIFMT_DSP_A:
306                 /* 0-bit data delay */
307                 regs->rcr2      |= RDATDLY(0);
308                 regs->xcr2      |= XDATDLY(0);
309                 break;
310         default:
311                 /* Unsupported data format */
312                 return -EINVAL;
313         }
314
315         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
316         case SND_SOC_DAIFMT_CBS_CFS:
317                 /* McBSP master. Set FS and bit clocks as outputs */
318                 regs->pcr0      |= FSXM | FSRM |
319                                    CLKXM | CLKRM;
320                 /* Sample rate generator drives the FS */
321                 regs->srgr2     |= FSGM;
322                 break;
323         case SND_SOC_DAIFMT_CBM_CFM:
324                 /* McBSP slave */
325                 break;
326         default:
327                 /* Unsupported master/slave configuration */
328                 return -EINVAL;
329         }
330
331         /* Set bit clock (CLKX/CLKR) and FS polarities */
332         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
333         case SND_SOC_DAIFMT_NB_NF:
334                 /*
335                  * Normal BCLK + FS.
336                  * FS active low. TX data driven on falling edge of bit clock
337                  * and RX data sampled on rising edge of bit clock.
338                  */
339                 regs->pcr0      |= FSXP | FSRP |
340                                    CLKXP | CLKRP;
341                 break;
342         case SND_SOC_DAIFMT_NB_IF:
343                 regs->pcr0      |= CLKXP | CLKRP;
344                 break;
345         case SND_SOC_DAIFMT_IB_NF:
346                 regs->pcr0      |= FSXP | FSRP;
347                 break;
348         case SND_SOC_DAIFMT_IB_IF:
349                 break;
350         default:
351                 return -EINVAL;
352         }
353
354         return 0;
355 }
356
357 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
358                                      int div_id, int div)
359 {
360         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
361         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
362
363         if (div_id != OMAP_MCBSP_CLKGDV)
364                 return -ENODEV;
365
366         regs->srgr1     |= CLKGDV(div - 1);
367
368         return 0;
369 }
370
371 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
372                                        int clk_id)
373 {
374         int sel_bit;
375         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
376
377         if (cpu_class_is_omap1()) {
378                 /* OMAP1's can use only external source clock */
379                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
380                         return -EINVAL;
381                 else
382                         return 0;
383         }
384
385         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
386                 return -EINVAL;
387
388         if (cpu_is_omap343x())
389                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
390
391         switch (mcbsp_data->bus_id) {
392         case 0:
393                 reg = OMAP2_CONTROL_DEVCONF0;
394                 sel_bit = 2;
395                 break;
396         case 1:
397                 reg = OMAP2_CONTROL_DEVCONF0;
398                 sel_bit = 6;
399                 break;
400         case 2:
401                 reg = reg_devconf1;
402                 sel_bit = 0;
403                 break;
404         case 3:
405                 reg = reg_devconf1;
406                 sel_bit = 2;
407                 break;
408         case 4:
409                 reg = reg_devconf1;
410                 sel_bit = 4;
411                 break;
412         default:
413                 return -EINVAL;
414         }
415
416         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
417                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
418         else
419                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
420
421         return 0;
422 }
423
424 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
425                                          int clk_id, unsigned int freq,
426                                          int dir)
427 {
428         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
429         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
430         int err = 0;
431
432         switch (clk_id) {
433         case OMAP_MCBSP_SYSCLK_CLK:
434                 regs->srgr2     |= CLKSM;
435                 break;
436         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
437         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
438                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
439                 break;
440
441         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
442                 regs->srgr2     |= CLKSM;
443         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
444                 regs->pcr0      |= SCLKME;
445                 break;
446         default:
447                 err = -ENODEV;
448         }
449
450         return err;
451 }
452
453 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
454 {                                                               \
455         .name = "omap-mcbsp-dai-(link_id)",                     \
456         .id = (link_id),                                        \
457         .type = SND_SOC_DAI_I2S,                                \
458         .playback = {                                           \
459                 .channels_min = 2,                              \
460                 .channels_max = 2,                              \
461                 .rates = OMAP_MCBSP_RATES,                      \
462                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
463         },                                                      \
464         .capture = {                                            \
465                 .channels_min = 2,                              \
466                 .channels_max = 2,                              \
467                 .rates = OMAP_MCBSP_RATES,                      \
468                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
469         },                                                      \
470         .ops = {                                                \
471                 .startup = omap_mcbsp_dai_startup,              \
472                 .shutdown = omap_mcbsp_dai_shutdown,            \
473                 .trigger = omap_mcbsp_dai_trigger,              \
474                 .hw_params = omap_mcbsp_dai_hw_params,          \
475         },                                                      \
476         .dai_ops = {                                            \
477                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,          \
478                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,        \
479                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,    \
480         },                                                      \
481         .private_data = &mcbsp_data[(link_id)].bus_id,          \
482 }
483
484 struct snd_soc_dai omap_mcbsp_dai[] = {
485         OMAP_MCBSP_DAI_BUILDER(0),
486         OMAP_MCBSP_DAI_BUILDER(1),
487 #if NUM_LINKS >= 3
488         OMAP_MCBSP_DAI_BUILDER(2),
489 #endif
490 #if NUM_LINKS == 5
491         OMAP_MCBSP_DAI_BUILDER(3),
492         OMAP_MCBSP_DAI_BUILDER(4),
493 #endif
494 };
495
496 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
497
498 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
499 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
500 MODULE_LICENSE("GPL");