Merge tag 'sound-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[linux-2.6.git] / sound / soc / codecs / wm8994.c
1 /*
2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
3  *
4  * Copyright 2009 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM1811_JACKDET_MODE_NONE  0x0000
42 #define WM1811_JACKDET_MODE_JACK  0x0100
43 #define WM1811_JACKDET_MODE_MIC   0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
45
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ  3
48
49 static int wm8994_drc_base[] = {
50         WM8994_AIF1_DRC1_1,
51         WM8994_AIF1_DRC2_1,
52         WM8994_AIF2_DRC_1,
53 };
54
55 static int wm8994_retune_mobile_base[] = {
56         WM8994_AIF1_DAC1_EQ_GAINS_1,
57         WM8994_AIF1_DAC2_EQ_GAINS_1,
58         WM8994_AIF2_EQ_GAINS_1,
59 };
60
61 static void wm8958_default_micdet(u16 status, void *data);
62
63 static const struct wm8958_micd_rate micdet_rates[] = {
64         { 32768,       true,  1, 4 },
65         { 32768,       false, 1, 1 },
66         { 44100 * 256, true,  7, 10 },
67         { 44100 * 256, false, 7, 10 },
68 };
69
70 static const struct wm8958_micd_rate jackdet_rates[] = {
71         { 32768,       true,  0, 1 },
72         { 32768,       false, 0, 1 },
73         { 44100 * 256, true,  7, 10 },
74         { 44100 * 256, false, 7, 10 },
75 };
76
77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78 {
79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80         int best, i, sysclk, val;
81         bool idle;
82         const struct wm8958_micd_rate *rates;
83         int num_rates;
84
85         if (wm8994->jack_cb != wm8958_default_micdet)
86                 return;
87
88         idle = !wm8994->jack_mic;
89
90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91         if (sysclk & WM8994_SYSCLK_SRC)
92                 sysclk = wm8994->aifclk[1];
93         else
94                 sysclk = wm8994->aifclk[0];
95
96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
97                 rates = wm8994->pdata->micd_rates;
98                 num_rates = wm8994->pdata->num_micd_rates;
99         } else if (wm8994->jackdet) {
100                 rates = jackdet_rates;
101                 num_rates = ARRAY_SIZE(jackdet_rates);
102         } else {
103                 rates = micdet_rates;
104                 num_rates = ARRAY_SIZE(micdet_rates);
105         }
106
107         best = 0;
108         for (i = 0; i < num_rates; i++) {
109                 if (rates[i].idle != idle)
110                         continue;
111                 if (abs(rates[i].sysclk - sysclk) <
112                     abs(rates[best].sysclk - sysclk))
113                         best = i;
114                 else if (rates[best].idle != idle)
115                         best = i;
116         }
117
118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120
121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122                             WM8958_MICD_BIAS_STARTTIME_MASK |
123                             WM8958_MICD_RATE_MASK, val);
124 }
125
126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127 {
128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
129         int rate;
130         int reg1 = 0;
131         int offset;
132
133         if (aif)
134                 offset = 4;
135         else
136                 offset = 0;
137
138         switch (wm8994->sysclk[aif]) {
139         case WM8994_SYSCLK_MCLK1:
140                 rate = wm8994->mclk[0];
141                 break;
142
143         case WM8994_SYSCLK_MCLK2:
144                 reg1 |= 0x8;
145                 rate = wm8994->mclk[1];
146                 break;
147
148         case WM8994_SYSCLK_FLL1:
149                 reg1 |= 0x10;
150                 rate = wm8994->fll[0].out;
151                 break;
152
153         case WM8994_SYSCLK_FLL2:
154                 reg1 |= 0x18;
155                 rate = wm8994->fll[1].out;
156                 break;
157
158         default:
159                 return -EINVAL;
160         }
161
162         if (rate >= 13500000) {
163                 rate /= 2;
164                 reg1 |= WM8994_AIF1CLK_DIV;
165
166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167                         aif + 1, rate);
168         }
169
170         wm8994->aifclk[aif] = rate;
171
172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174                             reg1);
175
176         return 0;
177 }
178
179 static int configure_clock(struct snd_soc_codec *codec)
180 {
181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
182         int change, new;
183
184         /* Bring up the AIF clocks first */
185         configure_aif_clock(codec, 0);
186         configure_aif_clock(codec, 1);
187
188         /* Then switch CLK_SYS over to the higher of them; a change
189          * can only happen as a result of a clocking change which can
190          * only be made outside of DAPM so we can safely redo the
191          * clocking.
192          */
193
194         /* If they're equal it doesn't matter which is used */
195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196                 wm8958_micd_set_rate(codec);
197                 return 0;
198         }
199
200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
201                 new = WM8994_SYSCLK_SRC;
202         else
203                 new = 0;
204
205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206                                      WM8994_SYSCLK_SRC, new);
207         if (change)
208                 snd_soc_dapm_sync(&codec->dapm);
209
210         wm8958_micd_set_rate(codec);
211
212         return 0;
213 }
214
215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
216                          struct snd_soc_dapm_widget *sink)
217 {
218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219         const char *clk;
220
221         /* Check what we're currently using for CLK_SYS */
222         if (reg & WM8994_SYSCLK_SRC)
223                 clk = "AIF2CLK";
224         else
225                 clk = "AIF1CLK";
226
227         return strcmp(source->name, clk) == 0;
228 }
229
230 static const char *sidetone_hpf_text[] = {
231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232 };
233
234 static const struct soc_enum sidetone_hpf =
235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
237 static const char *adc_hpf_text[] = {
238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
239 };
240
241 static const struct soc_enum aif1adc1_hpf =
242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244 static const struct soc_enum aif1adc2_hpf =
245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247 static const struct soc_enum aif2adc_hpf =
248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
257
258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261         .put = wm8994_put_drc_sw, \
262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265                              struct snd_ctl_elem_value *ucontrol)
266 {
267         struct soc_mixer_control *mc =
268                 (struct soc_mixer_control *)kcontrol->private_value;
269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270         int mask, ret;
271
272         /* Can't enable both ADC and DAC paths simultaneously */
273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
276         else
277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279         ret = snd_soc_read(codec, mc->reg);
280         if (ret < 0)
281                 return ret;
282         if (ret & mask)
283                 return -EINVAL;
284
285         return snd_soc_put_volsw(kcontrol, ucontrol);
286 }
287
288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289 {
290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
291         struct wm8994_pdata *pdata = wm8994->pdata;
292         int base = wm8994_drc_base[drc];
293         int cfg = wm8994->drc_cfg[drc];
294         int save, i;
295
296         /* Save any enables; the configuration should clear them. */
297         save = snd_soc_read(codec, base);
298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299                 WM8994_AIF1ADC1R_DRC_ENA;
300
301         for (i = 0; i < WM8994_DRC_REGS; i++)
302                 snd_soc_update_bits(codec, base + i, 0xffff,
303                                     pdata->drc_cfgs[cfg].regs[i]);
304
305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306                              WM8994_AIF1ADC1L_DRC_ENA |
307                              WM8994_AIF1ADC1R_DRC_ENA, save);
308 }
309
310 /* Icky as hell but saves code duplication */
311 static int wm8994_get_drc(const char *name)
312 {
313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
314                 return 0;
315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
316                 return 1;
317         if (strcmp(name, "AIF2DRC Mode") == 0)
318                 return 2;
319         return -EINVAL;
320 }
321
322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323                                struct snd_ctl_elem_value *ucontrol)
324 {
325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
327         struct wm8994_pdata *pdata = wm8994->pdata;
328         int drc = wm8994_get_drc(kcontrol->id.name);
329         int value = ucontrol->value.integer.value[0];
330
331         if (drc < 0)
332                 return drc;
333
334         if (value >= pdata->num_drc_cfgs)
335                 return -EINVAL;
336
337         wm8994->drc_cfg[drc] = value;
338
339         wm8994_set_drc(codec, drc);
340
341         return 0;
342 }
343
344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345                                struct snd_ctl_elem_value *ucontrol)
346 {
347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
349         int drc = wm8994_get_drc(kcontrol->id.name);
350
351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353         return 0;
354 }
355
356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357 {
358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
359         struct wm8994_pdata *pdata = wm8994->pdata;
360         int base = wm8994_retune_mobile_base[block];
361         int iface, best, best_val, save, i, cfg;
362
363         if (!pdata || !wm8994->num_retune_mobile_texts)
364                 return;
365
366         switch (block) {
367         case 0:
368         case 1:
369                 iface = 0;
370                 break;
371         case 2:
372                 iface = 1;
373                 break;
374         default:
375                 return;
376         }
377
378         /* Find the version of the currently selected configuration
379          * with the nearest sample rate. */
380         cfg = wm8994->retune_mobile_cfg[block];
381         best = 0;
382         best_val = INT_MAX;
383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
386                     abs(pdata->retune_mobile_cfgs[i].rate
387                         - wm8994->dac_rates[iface]) < best_val) {
388                         best = i;
389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
390                                        - wm8994->dac_rates[iface]);
391                 }
392         }
393
394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395                 block,
396                 pdata->retune_mobile_cfgs[best].name,
397                 pdata->retune_mobile_cfgs[best].rate,
398                 wm8994->dac_rates[iface]);
399
400         /* The EQ will be disabled while reconfiguring it, remember the
401          * current configuration. 
402          */
403         save = snd_soc_read(codec, base);
404         save &= WM8994_AIF1DAC1_EQ_ENA;
405
406         for (i = 0; i < WM8994_EQ_REGS; i++)
407                 snd_soc_update_bits(codec, base + i, 0xffff,
408                                 pdata->retune_mobile_cfgs[best].regs[i]);
409
410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411 }
412
413 /* Icky as hell but saves code duplication */
414 static int wm8994_get_retune_mobile_block(const char *name)
415 {
416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417                 return 0;
418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419                 return 1;
420         if (strcmp(name, "AIF2 EQ Mode") == 0)
421                 return 2;
422         return -EINVAL;
423 }
424
425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426                                          struct snd_ctl_elem_value *ucontrol)
427 {
428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430         struct wm8994_pdata *pdata = wm8994->pdata;
431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432         int value = ucontrol->value.integer.value[0];
433
434         if (block < 0)
435                 return block;
436
437         if (value >= pdata->num_retune_mobile_cfgs)
438                 return -EINVAL;
439
440         wm8994->retune_mobile_cfg[block] = value;
441
442         wm8994_set_retune_mobile(codec, block);
443
444         return 0;
445 }
446
447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448                                          struct snd_ctl_elem_value *ucontrol)
449 {
450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456         return 0;
457 }
458
459 static const char *aif_chan_src_text[] = {
460         "Left", "Right"
461 };
462
463 static const struct soc_enum aif1adcl_src =
464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466 static const struct soc_enum aif1adcr_src =
467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469 static const struct soc_enum aif2adcl_src =
470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472 static const struct soc_enum aif2adcr_src =
473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
475 static const struct soc_enum aif1dacl_src =
476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
477
478 static const struct soc_enum aif1dacr_src =
479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
480
481 static const struct soc_enum aif2dacl_src =
482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
483
484 static const struct soc_enum aif2dacr_src =
485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
486
487 static const char *osr_text[] = {
488         "Low Power", "High Performance",
489 };
490
491 static const struct soc_enum dac_osr =
492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494 static const struct soc_enum adc_osr =
495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
500                  1, 119, 0, digital_tlv),
501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
503                  1, 119, 0, digital_tlv),
504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
506                  1, 119, 0, digital_tlv),
507
508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
512
513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
517
518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545                5, 12, 0, st_tlv),
546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547                0, 12, 0, st_tlv),
548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549                5, 12, 0, st_tlv),
550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551                0, 12, 0, st_tlv),
552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
564 SOC_ENUM("ADC OSR", adc_osr),
565 SOC_ENUM("DAC OSR", dac_osr),
566
567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578                6, 1, 1, wm_hubs_spkmix_tlv),
579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580                2, 1, 1, wm_hubs_spkmix_tlv),
581
582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583                6, 1, 1, wm_hubs_spkmix_tlv),
584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585                2, 1, 1, wm_hubs_spkmix_tlv),
586
587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588                10, 15, 0, wm8994_3d_tlv),
589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
590            8, 1, 0),
591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592                10, 15, 0, wm8994_3d_tlv),
593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594            8, 1, 0),
595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
596                10, 15, 0, wm8994_3d_tlv),
597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
598            8, 1, 0),
599 };
600
601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603                eq_tlv),
604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605                eq_tlv),
606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607                eq_tlv),
608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609                eq_tlv),
610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611                eq_tlv),
612
613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614                eq_tlv),
615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616                eq_tlv),
617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618                eq_tlv),
619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620                eq_tlv),
621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622                eq_tlv),
623
624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625                eq_tlv),
626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627                eq_tlv),
628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629                eq_tlv),
630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631                eq_tlv),
632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633                eq_tlv),
634 };
635
636 static const char *wm8958_ng_text[] = {
637         "30ms", "125ms", "250ms", "500ms",
638 };
639
640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648 static const struct soc_enum wm8958_aif2dac_ng_hold =
649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
654
655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660                7, 1, ng_tlv),
661
662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667                7, 1, ng_tlv),
668
669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674                7, 1, ng_tlv),
675 };
676
677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679                mixin_boost_tlv),
680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681                mixin_boost_tlv),
682 };
683
684 /* We run all mode setting through a function to enforce audio mode */
685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686 {
687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689         if (!wm8994->jackdet || !wm8994->jack_cb)
690                 return;
691
692         if (wm8994->active_refcount)
693                 mode = WM1811_JACKDET_MODE_AUDIO;
694
695         if (mode == wm8994->jackdet_mode)
696                 return;
697
698         wm8994->jackdet_mode = mode;
699
700         /* Always use audio mode to detect while the system is active */
701         if (mode != WM1811_JACKDET_MODE_NONE)
702                 mode = WM1811_JACKDET_MODE_AUDIO;
703
704         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
705                             WM1811_JACKDET_MODE_MASK, mode);
706 }
707
708 static void active_reference(struct snd_soc_codec *codec)
709 {
710         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
711
712         mutex_lock(&wm8994->accdet_lock);
713
714         wm8994->active_refcount++;
715
716         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
717                 wm8994->active_refcount);
718
719         /* If we're using jack detection go into audio mode */
720         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
721
722         mutex_unlock(&wm8994->accdet_lock);
723 }
724
725 static void active_dereference(struct snd_soc_codec *codec)
726 {
727         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
728         u16 mode;
729
730         mutex_lock(&wm8994->accdet_lock);
731
732         wm8994->active_refcount--;
733
734         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
735                 wm8994->active_refcount);
736
737         if (wm8994->active_refcount == 0) {
738                 /* Go into appropriate detection only mode */
739                 if (wm8994->jack_mic || wm8994->mic_detecting)
740                         mode = WM1811_JACKDET_MODE_MIC;
741                 else
742                         mode = WM1811_JACKDET_MODE_JACK;
743
744                 wm1811_jackdet_set_mode(codec, mode);
745         }
746
747         mutex_unlock(&wm8994->accdet_lock);
748 }
749
750 static int clk_sys_event(struct snd_soc_dapm_widget *w,
751                          struct snd_kcontrol *kcontrol, int event)
752 {
753         struct snd_soc_codec *codec = w->codec;
754
755         switch (event) {
756         case SND_SOC_DAPM_PRE_PMU:
757                 return configure_clock(codec);
758
759         case SND_SOC_DAPM_POST_PMD:
760                 configure_clock(codec);
761                 break;
762         }
763
764         return 0;
765 }
766
767 static void vmid_reference(struct snd_soc_codec *codec)
768 {
769         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
770
771         pm_runtime_get_sync(codec->dev);
772
773         wm8994->vmid_refcount++;
774
775         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
776                 wm8994->vmid_refcount);
777
778         if (wm8994->vmid_refcount == 1) {
779                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
780                                     WM8994_LINEOUT1_DISCH |
781                                     WM8994_LINEOUT2_DISCH, 0);
782
783                 wm_hubs_vmid_ena(codec);
784
785                 switch (wm8994->vmid_mode) {
786                 default:
787                         WARN_ON(0 == "Invalid VMID mode");
788                 case WM8994_VMID_NORMAL:
789                         /* Startup bias, VMID ramp & buffer */
790                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
791                                             WM8994_BIAS_SRC |
792                                             WM8994_VMID_DISCH |
793                                             WM8994_STARTUP_BIAS_ENA |
794                                             WM8994_VMID_BUF_ENA |
795                                             WM8994_VMID_RAMP_MASK,
796                                             WM8994_BIAS_SRC |
797                                             WM8994_STARTUP_BIAS_ENA |
798                                             WM8994_VMID_BUF_ENA |
799                                             (0x3 << WM8994_VMID_RAMP_SHIFT));
800
801                         /* Main bias enable, VMID=2x40k */
802                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803                                             WM8994_BIAS_ENA |
804                                             WM8994_VMID_SEL_MASK,
805                                             WM8994_BIAS_ENA | 0x2);
806
807                         msleep(50);
808
809                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810                                             WM8994_VMID_RAMP_MASK |
811                                             WM8994_BIAS_SRC,
812                                             0);
813                         break;
814
815                 case WM8994_VMID_FORCE:
816                         /* Startup bias, slow VMID ramp & buffer */
817                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
818                                             WM8994_BIAS_SRC |
819                                             WM8994_VMID_DISCH |
820                                             WM8994_STARTUP_BIAS_ENA |
821                                             WM8994_VMID_BUF_ENA |
822                                             WM8994_VMID_RAMP_MASK,
823                                             WM8994_BIAS_SRC |
824                                             WM8994_STARTUP_BIAS_ENA |
825                                             WM8994_VMID_BUF_ENA |
826                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
827
828                         /* Main bias enable, VMID=2x40k */
829                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
830                                             WM8994_BIAS_ENA |
831                                             WM8994_VMID_SEL_MASK,
832                                             WM8994_BIAS_ENA | 0x2);
833
834                         msleep(400);
835
836                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
837                                             WM8994_VMID_RAMP_MASK |
838                                             WM8994_BIAS_SRC,
839                                             0);
840                         break;
841                 }
842         }
843 }
844
845 static void vmid_dereference(struct snd_soc_codec *codec)
846 {
847         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
848
849         wm8994->vmid_refcount--;
850
851         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
852                 wm8994->vmid_refcount);
853
854         if (wm8994->vmid_refcount == 0) {
855                 if (wm8994->hubs.lineout1_se)
856                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
857                                             WM8994_LINEOUT1N_ENA |
858                                             WM8994_LINEOUT1P_ENA,
859                                             WM8994_LINEOUT1N_ENA |
860                                             WM8994_LINEOUT1P_ENA);
861
862                 if (wm8994->hubs.lineout2_se)
863                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
864                                             WM8994_LINEOUT2N_ENA |
865                                             WM8994_LINEOUT2P_ENA,
866                                             WM8994_LINEOUT2N_ENA |
867                                             WM8994_LINEOUT2P_ENA);
868
869                 /* Start discharging VMID */
870                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
871                                     WM8994_BIAS_SRC |
872                                     WM8994_VMID_DISCH,
873                                     WM8994_BIAS_SRC |
874                                     WM8994_VMID_DISCH);
875
876                 switch (wm8994->vmid_mode) {
877                 case WM8994_VMID_FORCE:
878                         msleep(350);
879                         break;
880                 default:
881                         break;
882                 }
883
884                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
885                                     WM8994_VROI, WM8994_VROI);
886
887                 /* Active discharge */
888                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
889                                     WM8994_LINEOUT1_DISCH |
890                                     WM8994_LINEOUT2_DISCH,
891                                     WM8994_LINEOUT1_DISCH |
892                                     WM8994_LINEOUT2_DISCH);
893
894                 msleep(150);
895
896                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
897                                     WM8994_LINEOUT1N_ENA |
898                                     WM8994_LINEOUT1P_ENA |
899                                     WM8994_LINEOUT2N_ENA |
900                                     WM8994_LINEOUT2P_ENA, 0);
901
902                 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
903                                     WM8994_VROI, 0);
904
905                 /* Switch off startup biases */
906                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907                                     WM8994_BIAS_SRC |
908                                     WM8994_STARTUP_BIAS_ENA |
909                                     WM8994_VMID_BUF_ENA |
910                                     WM8994_VMID_RAMP_MASK, 0);
911
912                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
913                                     WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
914
915                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
916                                     WM8994_VMID_RAMP_MASK, 0);
917         }
918
919         pm_runtime_put(codec->dev);
920 }
921
922 static int vmid_event(struct snd_soc_dapm_widget *w,
923                       struct snd_kcontrol *kcontrol, int event)
924 {
925         struct snd_soc_codec *codec = w->codec;
926
927         switch (event) {
928         case SND_SOC_DAPM_PRE_PMU:
929                 vmid_reference(codec);
930                 break;
931
932         case SND_SOC_DAPM_POST_PMD:
933                 vmid_dereference(codec);
934                 break;
935         }
936
937         return 0;
938 }
939
940 static void wm8994_update_class_w(struct snd_soc_codec *codec)
941 {
942         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
943         int enable = 1;
944         int source = 0;  /* GCC flow analysis can't track enable */
945         int reg, reg_r;
946
947         /* Only support direct DAC->headphone paths */
948         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
949         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
950                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
951                 enable = 0;
952         }
953
954         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
955         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
956                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
957                 enable = 0;
958         }
959
960         /* We also need the same setting for L/R and only one path */
961         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
962         switch (reg) {
963         case WM8994_AIF2DACL_TO_DAC1L:
964                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
965                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
966                 break;
967         case WM8994_AIF1DAC2L_TO_DAC1L:
968                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
969                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
970                 break;
971         case WM8994_AIF1DAC1L_TO_DAC1L:
972                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
973                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
974                 break;
975         default:
976                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
977                 enable = 0;
978                 break;
979         }
980
981         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
982         if (reg_r != reg) {
983                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
984                 enable = 0;
985         }
986
987         if (enable) {
988                 dev_dbg(codec->dev, "Class W enabled\n");
989                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
990                                     WM8994_CP_DYN_PWR |
991                                     WM8994_CP_DYN_SRC_SEL_MASK,
992                                     source | WM8994_CP_DYN_PWR);
993                 wm8994->hubs.class_w = true;
994                 
995         } else {
996                 dev_dbg(codec->dev, "Class W disabled\n");
997                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
998                                     WM8994_CP_DYN_PWR, 0);
999                 wm8994->hubs.class_w = false;
1000         }
1001 }
1002
1003 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1004                           struct snd_kcontrol *kcontrol, int event)
1005 {
1006         struct snd_soc_codec *codec = w->codec;
1007         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1008
1009         switch (event) {
1010         case SND_SOC_DAPM_PRE_PMU:
1011                 if (wm8994->aif1clk_enable) {
1012                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1013                                             WM8994_AIF1CLK_ENA_MASK,
1014                                             WM8994_AIF1CLK_ENA);
1015                         wm8994->aif1clk_enable = 0;
1016                 }
1017                 if (wm8994->aif2clk_enable) {
1018                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1019                                             WM8994_AIF2CLK_ENA_MASK,
1020                                             WM8994_AIF2CLK_ENA);
1021                         wm8994->aif2clk_enable = 0;
1022                 }
1023                 break;
1024         }
1025
1026         /* We may also have postponed startup of DSP, handle that. */
1027         wm8958_aif_ev(w, kcontrol, event);
1028
1029         return 0;
1030 }
1031
1032 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033                            struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038         switch (event) {
1039         case SND_SOC_DAPM_POST_PMD:
1040                 if (wm8994->aif1clk_disable) {
1041                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042                                             WM8994_AIF1CLK_ENA_MASK, 0);
1043                         wm8994->aif1clk_disable = 0;
1044                 }
1045                 if (wm8994->aif2clk_disable) {
1046                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047                                             WM8994_AIF2CLK_ENA_MASK, 0);
1048                         wm8994->aif2clk_disable = 0;
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057                       struct snd_kcontrol *kcontrol, int event)
1058 {
1059         struct snd_soc_codec *codec = w->codec;
1060         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062         switch (event) {
1063         case SND_SOC_DAPM_PRE_PMU:
1064                 wm8994->aif1clk_enable = 1;
1065                 break;
1066         case SND_SOC_DAPM_POST_PMD:
1067                 wm8994->aif1clk_disable = 1;
1068                 break;
1069         }
1070
1071         return 0;
1072 }
1073
1074 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1075                       struct snd_kcontrol *kcontrol, int event)
1076 {
1077         struct snd_soc_codec *codec = w->codec;
1078         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1079
1080         switch (event) {
1081         case SND_SOC_DAPM_PRE_PMU:
1082                 wm8994->aif2clk_enable = 1;
1083                 break;
1084         case SND_SOC_DAPM_POST_PMD:
1085                 wm8994->aif2clk_disable = 1;
1086                 break;
1087         }
1088
1089         return 0;
1090 }
1091
1092 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1093                       struct snd_kcontrol *kcontrol, int event)
1094 {
1095         late_enable_ev(w, kcontrol, event);
1096         return 0;
1097 }
1098
1099 static int micbias_ev(struct snd_soc_dapm_widget *w,
1100                       struct snd_kcontrol *kcontrol, int event)
1101 {
1102         late_enable_ev(w, kcontrol, event);
1103         return 0;
1104 }
1105
1106 static int dac_ev(struct snd_soc_dapm_widget *w,
1107                   struct snd_kcontrol *kcontrol, int event)
1108 {
1109         struct snd_soc_codec *codec = w->codec;
1110         unsigned int mask = 1 << w->shift;
1111
1112         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1113                             mask, mask);
1114         return 0;
1115 }
1116
1117 static const char *hp_mux_text[] = {
1118         "Mixer",
1119         "DAC",
1120 };
1121
1122 #define WM8994_HP_ENUM(xname, xenum) \
1123 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1124         .info = snd_soc_info_enum_double, \
1125         .get = snd_soc_dapm_get_enum_double, \
1126         .put = wm8994_put_hp_enum, \
1127         .private_value = (unsigned long)&xenum }
1128
1129 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1130                               struct snd_ctl_elem_value *ucontrol)
1131 {
1132         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1133         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1134         struct snd_soc_codec *codec = w->codec;
1135         int ret;
1136
1137         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1138
1139         wm8994_update_class_w(codec);
1140
1141         return ret;
1142 }
1143
1144 static const struct soc_enum hpl_enum =
1145         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1146
1147 static const struct snd_kcontrol_new hpl_mux =
1148         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1149
1150 static const struct soc_enum hpr_enum =
1151         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1152
1153 static const struct snd_kcontrol_new hpr_mux =
1154         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1155
1156 static const char *adc_mux_text[] = {
1157         "ADC",
1158         "DMIC",
1159 };
1160
1161 static const struct soc_enum adc_enum =
1162         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1163
1164 static const struct snd_kcontrol_new adcl_mux =
1165         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1166
1167 static const struct snd_kcontrol_new adcr_mux =
1168         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1169
1170 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1171 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1172 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1173 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1174 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1175 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1176 };
1177
1178 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1179 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1180 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1181 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1182 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1183 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1184 };
1185
1186 /* Debugging; dump chip status after DAPM transitions */
1187 static int post_ev(struct snd_soc_dapm_widget *w,
1188             struct snd_kcontrol *kcontrol, int event)
1189 {
1190         struct snd_soc_codec *codec = w->codec;
1191         dev_dbg(codec->dev, "SRC status: %x\n",
1192                 snd_soc_read(codec,
1193                              WM8994_RATE_STATUS));
1194         return 0;
1195 }
1196
1197 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1198 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1199                 1, 1, 0),
1200 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1201                 0, 1, 0),
1202 };
1203
1204 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1205 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1206                 1, 1, 0),
1207 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1208                 0, 1, 0),
1209 };
1210
1211 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1212 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1213                 1, 1, 0),
1214 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1215                 0, 1, 0),
1216 };
1217
1218 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1219 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1220                 1, 1, 0),
1221 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1222                 0, 1, 0),
1223 };
1224
1225 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1226 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1227                 5, 1, 0),
1228 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1229                 4, 1, 0),
1230 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1231                 2, 1, 0),
1232 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1233                 1, 1, 0),
1234 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1235                 0, 1, 0),
1236 };
1237
1238 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1239 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1240                 5, 1, 0),
1241 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1242                 4, 1, 0),
1243 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1244                 2, 1, 0),
1245 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1246                 1, 1, 0),
1247 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1248                 0, 1, 0),
1249 };
1250
1251 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1252 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1253         .info = snd_soc_info_volsw, \
1254         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1255         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1256
1257 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1258                               struct snd_ctl_elem_value *ucontrol)
1259 {
1260         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1261         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1262         struct snd_soc_codec *codec = w->codec;
1263         int ret;
1264
1265         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1266
1267         wm8994_update_class_w(codec);
1268
1269         return ret;
1270 }
1271
1272 static const struct snd_kcontrol_new dac1l_mix[] = {
1273 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1274                       5, 1, 0),
1275 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1276                       4, 1, 0),
1277 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1278                       2, 1, 0),
1279 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1280                       1, 1, 0),
1281 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1282                       0, 1, 0),
1283 };
1284
1285 static const struct snd_kcontrol_new dac1r_mix[] = {
1286 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1287                       5, 1, 0),
1288 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1289                       4, 1, 0),
1290 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1291                       2, 1, 0),
1292 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1293                       1, 1, 0),
1294 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1295                       0, 1, 0),
1296 };
1297
1298 static const char *sidetone_text[] = {
1299         "ADC/DMIC1", "DMIC2",
1300 };
1301
1302 static const struct soc_enum sidetone1_enum =
1303         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1304
1305 static const struct snd_kcontrol_new sidetone1_mux =
1306         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1307
1308 static const struct soc_enum sidetone2_enum =
1309         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1310
1311 static const struct snd_kcontrol_new sidetone2_mux =
1312         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1313
1314 static const char *aif1dac_text[] = {
1315         "AIF1DACDAT", "AIF3DACDAT",
1316 };
1317
1318 static const struct soc_enum aif1dac_enum =
1319         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1320
1321 static const struct snd_kcontrol_new aif1dac_mux =
1322         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1323
1324 static const char *aif2dac_text[] = {
1325         "AIF2DACDAT", "AIF3DACDAT",
1326 };
1327
1328 static const struct soc_enum aif2dac_enum =
1329         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1330
1331 static const struct snd_kcontrol_new aif2dac_mux =
1332         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1333
1334 static const char *aif2adc_text[] = {
1335         "AIF2ADCDAT", "AIF3DACDAT",
1336 };
1337
1338 static const struct soc_enum aif2adc_enum =
1339         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1340
1341 static const struct snd_kcontrol_new aif2adc_mux =
1342         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1343
1344 static const char *aif3adc_text[] = {
1345         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1346 };
1347
1348 static const struct soc_enum wm8994_aif3adc_enum =
1349         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1350
1351 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1352         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1353
1354 static const struct soc_enum wm8958_aif3adc_enum =
1355         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1356
1357 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1358         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1359
1360 static const char *mono_pcm_out_text[] = {
1361         "None", "AIF2ADCL", "AIF2ADCR", 
1362 };
1363
1364 static const struct soc_enum mono_pcm_out_enum =
1365         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1366
1367 static const struct snd_kcontrol_new mono_pcm_out_mux =
1368         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1369
1370 static const char *aif2dac_src_text[] = {
1371         "AIF2", "AIF3",
1372 };
1373
1374 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1375 static const struct soc_enum aif2dacl_src_enum =
1376         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1377
1378 static const struct snd_kcontrol_new aif2dacl_src_mux =
1379         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1380
1381 static const struct soc_enum aif2dacr_src_enum =
1382         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1383
1384 static const struct snd_kcontrol_new aif2dacr_src_mux =
1385         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1386
1387 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1388 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1389         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1390 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1391         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1392
1393 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1394         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1395 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1396         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1397 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1398         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1399 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1400         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1401 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1402         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1403
1404 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1405                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1406                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1407 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1408                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1409                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1410 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1411                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1412 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1413                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1414
1415 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1416 };
1417
1418 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1419 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1420 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1421 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1422 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1423                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1424 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1425                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1426 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1427 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1428 };
1429
1430 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1431 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1432         dac_ev, SND_SOC_DAPM_PRE_PMU),
1433 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1434         dac_ev, SND_SOC_DAPM_PRE_PMU),
1435 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1436         dac_ev, SND_SOC_DAPM_PRE_PMU),
1437 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1438         dac_ev, SND_SOC_DAPM_PRE_PMU),
1439 };
1440
1441 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1442 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1443 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1444 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1445 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1446 };
1447
1448 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1449 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1450                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1451 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1452                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1453 };
1454
1455 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1456 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1457 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1458 };
1459
1460 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1461 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1462 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1463 SND_SOC_DAPM_INPUT("Clock"),
1464
1465 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1466                       SND_SOC_DAPM_PRE_PMU),
1467 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1468                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1469
1470 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1471                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472
1473 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1474 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1475 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1476
1477 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1478                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1479 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1480                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1481 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1482                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1483                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1484 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1485                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1486                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1487
1488 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1489                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1490 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1491                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1492 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1493                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1494                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1495 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1496                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1497                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1498
1499 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1500                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1501 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1502                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1503
1504 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1505                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1506 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1507                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1508
1509 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1510                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1511 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1512                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1513
1514 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1515 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1516
1517 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1518                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1519 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1520                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1521
1522 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1523                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1524 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1525                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1526 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1527                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1528                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1529 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1530                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1531                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1532
1533 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1534 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1535 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1536 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1537
1538 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1539 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1540 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1541
1542 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1543 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1544
1545 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1546
1547 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1548 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1549 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1550 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1551
1552 /* Power is done with the muxes since the ADC power also controls the
1553  * downsampling chain, the chip will automatically manage the analogue
1554  * specific portions.
1555  */
1556 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1557 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1558
1559 SND_SOC_DAPM_POST("Debug log", post_ev),
1560 };
1561
1562 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1563 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1564 };
1565
1566 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1567 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1568 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1569 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1570 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1571 };
1572
1573 static const struct snd_soc_dapm_route intercon[] = {
1574         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1575         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1576
1577         { "DSP1CLK", NULL, "CLK_SYS" },
1578         { "DSP2CLK", NULL, "CLK_SYS" },
1579         { "DSPINTCLK", NULL, "CLK_SYS" },
1580
1581         { "AIF1ADC1L", NULL, "AIF1CLK" },
1582         { "AIF1ADC1L", NULL, "DSP1CLK" },
1583         { "AIF1ADC1R", NULL, "AIF1CLK" },
1584         { "AIF1ADC1R", NULL, "DSP1CLK" },
1585         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1586
1587         { "AIF1DAC1L", NULL, "AIF1CLK" },
1588         { "AIF1DAC1L", NULL, "DSP1CLK" },
1589         { "AIF1DAC1R", NULL, "AIF1CLK" },
1590         { "AIF1DAC1R", NULL, "DSP1CLK" },
1591         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1592
1593         { "AIF1ADC2L", NULL, "AIF1CLK" },
1594         { "AIF1ADC2L", NULL, "DSP1CLK" },
1595         { "AIF1ADC2R", NULL, "AIF1CLK" },
1596         { "AIF1ADC2R", NULL, "DSP1CLK" },
1597         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1598
1599         { "AIF1DAC2L", NULL, "AIF1CLK" },
1600         { "AIF1DAC2L", NULL, "DSP1CLK" },
1601         { "AIF1DAC2R", NULL, "AIF1CLK" },
1602         { "AIF1DAC2R", NULL, "DSP1CLK" },
1603         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1604
1605         { "AIF2ADCL", NULL, "AIF2CLK" },
1606         { "AIF2ADCL", NULL, "DSP2CLK" },
1607         { "AIF2ADCR", NULL, "AIF2CLK" },
1608         { "AIF2ADCR", NULL, "DSP2CLK" },
1609         { "AIF2ADCR", NULL, "DSPINTCLK" },
1610
1611         { "AIF2DACL", NULL, "AIF2CLK" },
1612         { "AIF2DACL", NULL, "DSP2CLK" },
1613         { "AIF2DACR", NULL, "AIF2CLK" },
1614         { "AIF2DACR", NULL, "DSP2CLK" },
1615         { "AIF2DACR", NULL, "DSPINTCLK" },
1616
1617         { "DMIC1L", NULL, "DMIC1DAT" },
1618         { "DMIC1L", NULL, "CLK_SYS" },
1619         { "DMIC1R", NULL, "DMIC1DAT" },
1620         { "DMIC1R", NULL, "CLK_SYS" },
1621         { "DMIC2L", NULL, "DMIC2DAT" },
1622         { "DMIC2L", NULL, "CLK_SYS" },
1623         { "DMIC2R", NULL, "DMIC2DAT" },
1624         { "DMIC2R", NULL, "CLK_SYS" },
1625
1626         { "ADCL", NULL, "AIF1CLK" },
1627         { "ADCL", NULL, "DSP1CLK" },
1628         { "ADCL", NULL, "DSPINTCLK" },
1629
1630         { "ADCR", NULL, "AIF1CLK" },
1631         { "ADCR", NULL, "DSP1CLK" },
1632         { "ADCR", NULL, "DSPINTCLK" },
1633
1634         { "ADCL Mux", "ADC", "ADCL" },
1635         { "ADCL Mux", "DMIC", "DMIC1L" },
1636         { "ADCR Mux", "ADC", "ADCR" },
1637         { "ADCR Mux", "DMIC", "DMIC1R" },
1638
1639         { "DAC1L", NULL, "AIF1CLK" },
1640         { "DAC1L", NULL, "DSP1CLK" },
1641         { "DAC1L", NULL, "DSPINTCLK" },
1642
1643         { "DAC1R", NULL, "AIF1CLK" },
1644         { "DAC1R", NULL, "DSP1CLK" },
1645         { "DAC1R", NULL, "DSPINTCLK" },
1646
1647         { "DAC2L", NULL, "AIF2CLK" },
1648         { "DAC2L", NULL, "DSP2CLK" },
1649         { "DAC2L", NULL, "DSPINTCLK" },
1650
1651         { "DAC2R", NULL, "AIF2DACR" },
1652         { "DAC2R", NULL, "AIF2CLK" },
1653         { "DAC2R", NULL, "DSP2CLK" },
1654         { "DAC2R", NULL, "DSPINTCLK" },
1655
1656         { "TOCLK", NULL, "CLK_SYS" },
1657
1658         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1659         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1660         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1661
1662         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1663         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1664         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1665
1666         /* AIF1 outputs */
1667         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1668         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1669         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1670
1671         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1672         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1673         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1674
1675         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1676         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1677         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1678
1679         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1680         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1681         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1682
1683         /* Pin level routing for AIF3 */
1684         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1685         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1686         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1687         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1688
1689         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1690         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1691         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1692         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1693         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1694         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1695         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1696
1697         /* DAC1 inputs */
1698         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1699         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1700         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1701         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1702         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1703
1704         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1705         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1706         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1707         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1708         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1709
1710         /* DAC2/AIF2 outputs  */
1711         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1712         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1713         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1714         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1715         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1716         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1717
1718         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1719         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1720         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1721         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1722         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1723         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1724
1725         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1726         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1727         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1728         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1729
1730         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1731
1732         /* AIF3 output */
1733         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1734         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1735         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1736         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1737         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1738         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1739         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1740         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1741
1742         /* Sidetone */
1743         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1744         { "Left Sidetone", "DMIC2", "DMIC2L" },
1745         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1746         { "Right Sidetone", "DMIC2", "DMIC2R" },
1747
1748         /* Output stages */
1749         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1750         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1751
1752         { "SPKL", "DAC1 Switch", "DAC1L" },
1753         { "SPKL", "DAC2 Switch", "DAC2L" },
1754
1755         { "SPKR", "DAC1 Switch", "DAC1R" },
1756         { "SPKR", "DAC2 Switch", "DAC2R" },
1757
1758         { "Left Headphone Mux", "DAC", "DAC1L" },
1759         { "Right Headphone Mux", "DAC", "DAC1R" },
1760 };
1761
1762 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1763         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1764         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1765         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1766         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1767         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1768         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1769         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1770         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1771 };
1772
1773 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1774         { "DAC1L", NULL, "DAC1L Mixer" },
1775         { "DAC1R", NULL, "DAC1R Mixer" },
1776         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1777         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1778 };
1779
1780 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1781         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1782         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1783         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1784         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1785         { "MICBIAS1", NULL, "CLK_SYS" },
1786         { "MICBIAS1", NULL, "MICBIAS Supply" },
1787         { "MICBIAS2", NULL, "CLK_SYS" },
1788         { "MICBIAS2", NULL, "MICBIAS Supply" },
1789 };
1790
1791 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1792         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1793         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1794         { "MICBIAS1", NULL, "VMID" },
1795         { "MICBIAS2", NULL, "VMID" },
1796 };
1797
1798 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1799         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1800         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1801
1802         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1803         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1804         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1805         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1806
1807         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1808         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1809
1810         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1811 };
1812
1813 /* The size in bits of the FLL divide multiplied by 10
1814  * to allow rounding later */
1815 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1816
1817 struct fll_div {
1818         u16 outdiv;
1819         u16 n;
1820         u16 k;
1821         u16 clk_ref_div;
1822         u16 fll_fratio;
1823 };
1824
1825 static int wm8994_get_fll_config(struct fll_div *fll,
1826                                  int freq_in, int freq_out)
1827 {
1828         u64 Kpart;
1829         unsigned int K, Ndiv, Nmod;
1830
1831         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1832
1833         /* Scale the input frequency down to <= 13.5MHz */
1834         fll->clk_ref_div = 0;
1835         while (freq_in > 13500000) {
1836                 fll->clk_ref_div++;
1837                 freq_in /= 2;
1838
1839                 if (fll->clk_ref_div > 3)
1840                         return -EINVAL;
1841         }
1842         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1843
1844         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1845         fll->outdiv = 3;
1846         while (freq_out * (fll->outdiv + 1) < 90000000) {
1847                 fll->outdiv++;
1848                 if (fll->outdiv > 63)
1849                         return -EINVAL;
1850         }
1851         freq_out *= fll->outdiv + 1;
1852         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1853
1854         if (freq_in > 1000000) {
1855                 fll->fll_fratio = 0;
1856         } else if (freq_in > 256000) {
1857                 fll->fll_fratio = 1;
1858                 freq_in *= 2;
1859         } else if (freq_in > 128000) {
1860                 fll->fll_fratio = 2;
1861                 freq_in *= 4;
1862         } else if (freq_in > 64000) {
1863                 fll->fll_fratio = 3;
1864                 freq_in *= 8;
1865         } else {
1866                 fll->fll_fratio = 4;
1867                 freq_in *= 16;
1868         }
1869         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1870
1871         /* Now, calculate N.K */
1872         Ndiv = freq_out / freq_in;
1873
1874         fll->n = Ndiv;
1875         Nmod = freq_out % freq_in;
1876         pr_debug("Nmod=%d\n", Nmod);
1877
1878         /* Calculate fractional part - scale up so we can round. */
1879         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1880
1881         do_div(Kpart, freq_in);
1882
1883         K = Kpart & 0xFFFFFFFF;
1884
1885         if ((K % 10) >= 5)
1886                 K += 5;
1887
1888         /* Move down to proper range now rounding is done */
1889         fll->k = K / 10;
1890
1891         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1892
1893         return 0;
1894 }
1895
1896 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1897                           unsigned int freq_in, unsigned int freq_out)
1898 {
1899         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1900         struct wm8994 *control = wm8994->wm8994;
1901         int reg_offset, ret;
1902         struct fll_div fll;
1903         u16 reg, aif1, aif2;
1904         unsigned long timeout;
1905         bool was_enabled;
1906
1907         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1908                 & WM8994_AIF1CLK_ENA;
1909
1910         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1911                 & WM8994_AIF2CLK_ENA;
1912
1913         switch (id) {
1914         case WM8994_FLL1:
1915                 reg_offset = 0;
1916                 id = 0;
1917                 break;
1918         case WM8994_FLL2:
1919                 reg_offset = 0x20;
1920                 id = 1;
1921                 break;
1922         default:
1923                 return -EINVAL;
1924         }
1925
1926         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1927         was_enabled = reg & WM8994_FLL1_ENA;
1928
1929         switch (src) {
1930         case 0:
1931                 /* Allow no source specification when stopping */
1932                 if (freq_out)
1933                         return -EINVAL;
1934                 src = wm8994->fll[id].src;
1935                 break;
1936         case WM8994_FLL_SRC_MCLK1:
1937         case WM8994_FLL_SRC_MCLK2:
1938         case WM8994_FLL_SRC_LRCLK:
1939         case WM8994_FLL_SRC_BCLK:
1940                 break;
1941         default:
1942                 return -EINVAL;
1943         }
1944
1945         /* Are we changing anything? */
1946         if (wm8994->fll[id].src == src &&
1947             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1948                 return 0;
1949
1950         /* If we're stopping the FLL redo the old config - no
1951          * registers will actually be written but we avoid GCC flow
1952          * analysis bugs spewing warnings.
1953          */
1954         if (freq_out)
1955                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1956         else
1957                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1958                                             wm8994->fll[id].out);
1959         if (ret < 0)
1960                 return ret;
1961
1962         /* Gate the AIF clocks while we reclock */
1963         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1964                             WM8994_AIF1CLK_ENA, 0);
1965         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1966                             WM8994_AIF2CLK_ENA, 0);
1967
1968         /* We always need to disable the FLL while reconfiguring */
1969         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1970                             WM8994_FLL1_ENA, 0);
1971
1972         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1973                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1974         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1975                             WM8994_FLL1_OUTDIV_MASK |
1976                             WM8994_FLL1_FRATIO_MASK, reg);
1977
1978         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1979                             WM8994_FLL1_K_MASK, fll.k);
1980
1981         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1982                             WM8994_FLL1_N_MASK,
1983                                     fll.n << WM8994_FLL1_N_SHIFT);
1984
1985         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1986                             WM8994_FLL1_REFCLK_DIV_MASK |
1987                             WM8994_FLL1_REFCLK_SRC_MASK,
1988                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1989                             (src - 1));
1990
1991         /* Clear any pending completion from a previous failure */
1992         try_wait_for_completion(&wm8994->fll_locked[id]);
1993
1994         /* Enable (with fractional mode if required) */
1995         if (freq_out) {
1996                 /* Enable VMID if we need it */
1997                 if (!was_enabled) {
1998                         active_reference(codec);
1999
2000                         switch (control->type) {
2001                         case WM8994:
2002                                 vmid_reference(codec);
2003                                 break;
2004                         case WM8958:
2005                                 if (wm8994->revision < 1)
2006                                         vmid_reference(codec);
2007                                 break;
2008                         default:
2009                                 break;
2010                         }
2011                 }
2012
2013                 if (fll.k)
2014                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2015                 else
2016                         reg = WM8994_FLL1_ENA;
2017                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2018                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2019                                     reg);
2020
2021                 if (wm8994->fll_locked_irq) {
2022                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2023                                                               msecs_to_jiffies(10));
2024                         if (timeout == 0)
2025                                 dev_warn(codec->dev,
2026                                          "Timed out waiting for FLL lock\n");
2027                 } else {
2028                         msleep(5);
2029                 }
2030         } else {
2031                 if (was_enabled) {
2032                         switch (control->type) {
2033                         case WM8994:
2034                                 vmid_dereference(codec);
2035                                 break;
2036                         case WM8958:
2037                                 if (wm8994->revision < 1)
2038                                         vmid_dereference(codec);
2039                                 break;
2040                         default:
2041                                 break;
2042                         }
2043
2044                         active_dereference(codec);
2045                 }
2046         }
2047
2048         wm8994->fll[id].in = freq_in;
2049         wm8994->fll[id].out = freq_out;
2050         wm8994->fll[id].src = src;
2051
2052         /* Enable any gated AIF clocks */
2053         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2054                             WM8994_AIF1CLK_ENA, aif1);
2055         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2056                             WM8994_AIF2CLK_ENA, aif2);
2057
2058         configure_clock(codec);
2059
2060         return 0;
2061 }
2062
2063 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2064 {
2065         struct completion *completion = data;
2066
2067         complete(completion);
2068
2069         return IRQ_HANDLED;
2070 }
2071
2072 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2073
2074 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2075                           unsigned int freq_in, unsigned int freq_out)
2076 {
2077         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2078 }
2079
2080 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2081                 int clk_id, unsigned int freq, int dir)
2082 {
2083         struct snd_soc_codec *codec = dai->codec;
2084         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2085         int i;
2086
2087         switch (dai->id) {
2088         case 1:
2089         case 2:
2090                 break;
2091
2092         default:
2093                 /* AIF3 shares clocking with AIF1/2 */
2094                 return -EINVAL;
2095         }
2096
2097         switch (clk_id) {
2098         case WM8994_SYSCLK_MCLK1:
2099                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2100                 wm8994->mclk[0] = freq;
2101                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2102                         dai->id, freq);
2103                 break;
2104
2105         case WM8994_SYSCLK_MCLK2:
2106                 /* TODO: Set GPIO AF */
2107                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2108                 wm8994->mclk[1] = freq;
2109                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2110                         dai->id, freq);
2111                 break;
2112
2113         case WM8994_SYSCLK_FLL1:
2114                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2115                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2116                 break;
2117
2118         case WM8994_SYSCLK_FLL2:
2119                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2120                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2121                 break;
2122
2123         case WM8994_SYSCLK_OPCLK:
2124                 /* Special case - a division (times 10) is given and
2125                  * no effect on main clocking. 
2126                  */
2127                 if (freq) {
2128                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2129                                 if (opclk_divs[i] == freq)
2130                                         break;
2131                         if (i == ARRAY_SIZE(opclk_divs))
2132                                 return -EINVAL;
2133                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2134                                             WM8994_OPCLK_DIV_MASK, i);
2135                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2136                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2137                 } else {
2138                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2139                                             WM8994_OPCLK_ENA, 0);
2140                 }
2141
2142         default:
2143                 return -EINVAL;
2144         }
2145
2146         configure_clock(codec);
2147
2148         return 0;
2149 }
2150
2151 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2152                                  enum snd_soc_bias_level level)
2153 {
2154         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2155         struct wm8994 *control = wm8994->wm8994;
2156
2157         wm_hubs_set_bias_level(codec, level);
2158
2159         switch (level) {
2160         case SND_SOC_BIAS_ON:
2161                 break;
2162
2163         case SND_SOC_BIAS_PREPARE:
2164                 /* MICBIAS into regulating mode */
2165                 switch (control->type) {
2166                 case WM8958:
2167                 case WM1811:
2168                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2169                                             WM8958_MICB1_MODE, 0);
2170                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2171                                             WM8958_MICB2_MODE, 0);
2172                         break;
2173                 default:
2174                         break;
2175                 }
2176
2177                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2178                         active_reference(codec);
2179                 break;
2180
2181         case SND_SOC_BIAS_STANDBY:
2182                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2183                         switch (control->type) {
2184                         case WM8958:
2185                                 if (wm8994->revision == 0) {
2186                                         /* Optimise performance for rev A */
2187                                         snd_soc_update_bits(codec,
2188                                                             WM8958_CHARGE_PUMP_2,
2189                                                             WM8958_CP_DISCH,
2190                                                             WM8958_CP_DISCH);
2191                                 }
2192                                 break;
2193
2194                         default:
2195                                 break;
2196                         }
2197
2198                         /* Discharge LINEOUT1 & 2 */
2199                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2200                                             WM8994_LINEOUT1_DISCH |
2201                                             WM8994_LINEOUT2_DISCH,
2202                                             WM8994_LINEOUT1_DISCH |
2203                                             WM8994_LINEOUT2_DISCH);
2204                 }
2205
2206                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2207                         active_dereference(codec);
2208
2209                 /* MICBIAS into bypass mode on newer devices */
2210                 switch (control->type) {
2211                 case WM8958:
2212                 case WM1811:
2213                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2214                                             WM8958_MICB1_MODE,
2215                                             WM8958_MICB1_MODE);
2216                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2217                                             WM8958_MICB2_MODE,
2218                                             WM8958_MICB2_MODE);
2219                         break;
2220                 default:
2221                         break;
2222                 }
2223                 break;
2224
2225         case SND_SOC_BIAS_OFF:
2226                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2227                         wm8994->cur_fw = NULL;
2228                 break;
2229         }
2230
2231         codec->dapm.bias_level = level;
2232
2233         return 0;
2234 }
2235
2236 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2237 {
2238         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2239
2240         switch (mode) {
2241         case WM8994_VMID_NORMAL:
2242                 if (wm8994->hubs.lineout1_se) {
2243                         snd_soc_dapm_disable_pin(&codec->dapm,
2244                                                  "LINEOUT1N Driver");
2245                         snd_soc_dapm_disable_pin(&codec->dapm,
2246                                                  "LINEOUT1P Driver");
2247                 }
2248                 if (wm8994->hubs.lineout2_se) {
2249                         snd_soc_dapm_disable_pin(&codec->dapm,
2250                                                  "LINEOUT2N Driver");
2251                         snd_soc_dapm_disable_pin(&codec->dapm,
2252                                                  "LINEOUT2P Driver");
2253                 }
2254
2255                 /* Do the sync with the old mode to allow it to clean up */
2256                 snd_soc_dapm_sync(&codec->dapm);
2257                 wm8994->vmid_mode = mode;
2258                 break;
2259
2260         case WM8994_VMID_FORCE:
2261                 if (wm8994->hubs.lineout1_se) {
2262                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2263                                                       "LINEOUT1N Driver");
2264                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2265                                                       "LINEOUT1P Driver");
2266                 }
2267                 if (wm8994->hubs.lineout2_se) {
2268                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2269                                                       "LINEOUT2N Driver");
2270                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2271                                                       "LINEOUT2P Driver");
2272                 }
2273
2274                 wm8994->vmid_mode = mode;
2275                 snd_soc_dapm_sync(&codec->dapm);
2276                 break;
2277
2278         default:
2279                 return -EINVAL;
2280         }
2281
2282         return 0;
2283 }
2284
2285 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2286 {
2287         struct snd_soc_codec *codec = dai->codec;
2288         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2289         struct wm8994 *control = wm8994->wm8994;
2290         int ms_reg;
2291         int aif1_reg;
2292         int ms = 0;
2293         int aif1 = 0;
2294
2295         switch (dai->id) {
2296         case 1:
2297                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2298                 aif1_reg = WM8994_AIF1_CONTROL_1;
2299                 break;
2300         case 2:
2301                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2302                 aif1_reg = WM8994_AIF2_CONTROL_1;
2303                 break;
2304         default:
2305                 return -EINVAL;
2306         }
2307
2308         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2309         case SND_SOC_DAIFMT_CBS_CFS:
2310                 break;
2311         case SND_SOC_DAIFMT_CBM_CFM:
2312                 ms = WM8994_AIF1_MSTR;
2313                 break;
2314         default:
2315                 return -EINVAL;
2316         }
2317
2318         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2319         case SND_SOC_DAIFMT_DSP_B:
2320                 aif1 |= WM8994_AIF1_LRCLK_INV;
2321         case SND_SOC_DAIFMT_DSP_A:
2322                 aif1 |= 0x18;
2323                 break;
2324         case SND_SOC_DAIFMT_I2S:
2325                 aif1 |= 0x10;
2326                 break;
2327         case SND_SOC_DAIFMT_RIGHT_J:
2328                 break;
2329         case SND_SOC_DAIFMT_LEFT_J:
2330                 aif1 |= 0x8;
2331                 break;
2332         default:
2333                 return -EINVAL;
2334         }
2335
2336         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2337         case SND_SOC_DAIFMT_DSP_A:
2338         case SND_SOC_DAIFMT_DSP_B:
2339                 /* frame inversion not valid for DSP modes */
2340                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2341                 case SND_SOC_DAIFMT_NB_NF:
2342                         break;
2343                 case SND_SOC_DAIFMT_IB_NF:
2344                         aif1 |= WM8994_AIF1_BCLK_INV;
2345                         break;
2346                 default:
2347                         return -EINVAL;
2348                 }
2349                 break;
2350
2351         case SND_SOC_DAIFMT_I2S:
2352         case SND_SOC_DAIFMT_RIGHT_J:
2353         case SND_SOC_DAIFMT_LEFT_J:
2354                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2355                 case SND_SOC_DAIFMT_NB_NF:
2356                         break;
2357                 case SND_SOC_DAIFMT_IB_IF:
2358                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2359                         break;
2360                 case SND_SOC_DAIFMT_IB_NF:
2361                         aif1 |= WM8994_AIF1_BCLK_INV;
2362                         break;
2363                 case SND_SOC_DAIFMT_NB_IF:
2364                         aif1 |= WM8994_AIF1_LRCLK_INV;
2365                         break;
2366                 default:
2367                         return -EINVAL;
2368                 }
2369                 break;
2370         default:
2371                 return -EINVAL;
2372         }
2373
2374         /* The AIF2 format configuration needs to be mirrored to AIF3
2375          * on WM8958 if it's in use so just do it all the time. */
2376         switch (control->type) {
2377         case WM1811:
2378         case WM8958:
2379                 if (dai->id == 2)
2380                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2381                                             WM8994_AIF1_LRCLK_INV |
2382                                             WM8958_AIF3_FMT_MASK, aif1);
2383                 break;
2384
2385         default:
2386                 break;
2387         }
2388
2389         snd_soc_update_bits(codec, aif1_reg,
2390                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2391                             WM8994_AIF1_FMT_MASK,
2392                             aif1);
2393         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2394                             ms);
2395
2396         return 0;
2397 }
2398
2399 static struct {
2400         int val, rate;
2401 } srs[] = {
2402         { 0,   8000 },
2403         { 1,  11025 },
2404         { 2,  12000 },
2405         { 3,  16000 },
2406         { 4,  22050 },
2407         { 5,  24000 },
2408         { 6,  32000 },
2409         { 7,  44100 },
2410         { 8,  48000 },
2411         { 9,  88200 },
2412         { 10, 96000 },
2413 };
2414
2415 static int fs_ratios[] = {
2416         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2417 };
2418
2419 static int bclk_divs[] = {
2420         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2421         640, 880, 960, 1280, 1760, 1920
2422 };
2423
2424 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2425                             struct snd_pcm_hw_params *params,
2426                             struct snd_soc_dai *dai)
2427 {
2428         struct snd_soc_codec *codec = dai->codec;
2429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2430         int aif1_reg;
2431         int aif2_reg;
2432         int bclk_reg;
2433         int lrclk_reg;
2434         int rate_reg;
2435         int aif1 = 0;
2436         int aif2 = 0;
2437         int bclk = 0;
2438         int lrclk = 0;
2439         int rate_val = 0;
2440         int id = dai->id - 1;
2441
2442         int i, cur_val, best_val, bclk_rate, best;
2443
2444         switch (dai->id) {
2445         case 1:
2446                 aif1_reg = WM8994_AIF1_CONTROL_1;
2447                 aif2_reg = WM8994_AIF1_CONTROL_2;
2448                 bclk_reg = WM8994_AIF1_BCLK;
2449                 rate_reg = WM8994_AIF1_RATE;
2450                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2451                     wm8994->lrclk_shared[0]) {
2452                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2453                 } else {
2454                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2455                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2456                 }
2457                 break;
2458         case 2:
2459                 aif1_reg = WM8994_AIF2_CONTROL_1;
2460                 aif2_reg = WM8994_AIF2_CONTROL_2;
2461                 bclk_reg = WM8994_AIF2_BCLK;
2462                 rate_reg = WM8994_AIF2_RATE;
2463                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2464                     wm8994->lrclk_shared[1]) {
2465                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2466                 } else {
2467                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2468                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2469                 }
2470                 break;
2471         default:
2472                 return -EINVAL;
2473         }
2474
2475         bclk_rate = params_rate(params) * 2;
2476         switch (params_format(params)) {
2477         case SNDRV_PCM_FORMAT_S16_LE:
2478                 bclk_rate *= 16;
2479                 break;
2480         case SNDRV_PCM_FORMAT_S20_3LE:
2481                 bclk_rate *= 20;
2482                 aif1 |= 0x20;
2483                 break;
2484         case SNDRV_PCM_FORMAT_S24_LE:
2485                 bclk_rate *= 24;
2486                 aif1 |= 0x40;
2487                 break;
2488         case SNDRV_PCM_FORMAT_S32_LE:
2489                 bclk_rate *= 32;
2490                 aif1 |= 0x60;
2491                 break;
2492         default:
2493                 return -EINVAL;
2494         }
2495
2496         /* Try to find an appropriate sample rate; look for an exact match. */
2497         for (i = 0; i < ARRAY_SIZE(srs); i++)
2498                 if (srs[i].rate == params_rate(params))
2499                         break;
2500         if (i == ARRAY_SIZE(srs))
2501                 return -EINVAL;
2502         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2503
2504         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2505         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2506                 dai->id, wm8994->aifclk[id], bclk_rate);
2507
2508         if (params_channels(params) == 1 &&
2509             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2510                 aif2 |= WM8994_AIF1_MONO;
2511
2512         if (wm8994->aifclk[id] == 0) {
2513                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2514                 return -EINVAL;
2515         }
2516
2517         /* AIFCLK/fs ratio; look for a close match in either direction */
2518         best = 0;
2519         best_val = abs((fs_ratios[0] * params_rate(params))
2520                        - wm8994->aifclk[id]);
2521         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2522                 cur_val = abs((fs_ratios[i] * params_rate(params))
2523                               - wm8994->aifclk[id]);
2524                 if (cur_val >= best_val)
2525                         continue;
2526                 best = i;
2527                 best_val = cur_val;
2528         }
2529         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2530                 dai->id, fs_ratios[best]);
2531         rate_val |= best;
2532
2533         /* We may not get quite the right frequency if using
2534          * approximate clocks so look for the closest match that is
2535          * higher than the target (we need to ensure that there enough
2536          * BCLKs to clock out the samples).
2537          */
2538         best = 0;
2539         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2540                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2541                 if (cur_val < 0) /* BCLK table is sorted */
2542                         break;
2543                 best = i;
2544         }
2545         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2546         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2547                 bclk_divs[best], bclk_rate);
2548         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2549
2550         lrclk = bclk_rate / params_rate(params);
2551         if (!lrclk) {
2552                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2553                         bclk_rate);
2554                 return -EINVAL;
2555         }
2556         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2557                 lrclk, bclk_rate / lrclk);
2558
2559         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2560         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2561         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2562         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2563                             lrclk);
2564         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2565                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2566
2567         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2568                 switch (dai->id) {
2569                 case 1:
2570                         wm8994->dac_rates[0] = params_rate(params);
2571                         wm8994_set_retune_mobile(codec, 0);
2572                         wm8994_set_retune_mobile(codec, 1);
2573                         break;
2574                 case 2:
2575                         wm8994->dac_rates[1] = params_rate(params);
2576                         wm8994_set_retune_mobile(codec, 2);
2577                         break;
2578                 }
2579         }
2580
2581         return 0;
2582 }
2583
2584 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2585                                  struct snd_pcm_hw_params *params,
2586                                  struct snd_soc_dai *dai)
2587 {
2588         struct snd_soc_codec *codec = dai->codec;
2589         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2590         struct wm8994 *control = wm8994->wm8994;
2591         int aif1_reg;
2592         int aif1 = 0;
2593
2594         switch (dai->id) {
2595         case 3:
2596                 switch (control->type) {
2597                 case WM1811:
2598                 case WM8958:
2599                         aif1_reg = WM8958_AIF3_CONTROL_1;
2600                         break;
2601                 default:
2602                         return 0;
2603                 }
2604         default:
2605                 return 0;
2606         }
2607
2608         switch (params_format(params)) {
2609         case SNDRV_PCM_FORMAT_S16_LE:
2610                 break;
2611         case SNDRV_PCM_FORMAT_S20_3LE:
2612                 aif1 |= 0x20;
2613                 break;
2614         case SNDRV_PCM_FORMAT_S24_LE:
2615                 aif1 |= 0x40;
2616                 break;
2617         case SNDRV_PCM_FORMAT_S32_LE:
2618                 aif1 |= 0x60;
2619                 break;
2620         default:
2621                 return -EINVAL;
2622         }
2623
2624         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2625 }
2626
2627 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2628                                 struct snd_soc_dai *dai)
2629 {
2630         struct snd_soc_codec *codec = dai->codec;
2631         int rate_reg = 0;
2632
2633         switch (dai->id) {
2634         case 1:
2635                 rate_reg = WM8994_AIF1_RATE;
2636                 break;
2637         case 2:
2638                 rate_reg = WM8994_AIF2_RATE;
2639                 break;
2640         default:
2641                 break;
2642         }
2643
2644         /* If the DAI is idle then configure the divider tree for the
2645          * lowest output rate to save a little power if the clock is
2646          * still active (eg, because it is system clock).
2647          */
2648         if (rate_reg && !dai->playback_active && !dai->capture_active)
2649                 snd_soc_update_bits(codec, rate_reg,
2650                                     WM8994_AIF1_SR_MASK |
2651                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2652 }
2653
2654 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2655 {
2656         struct snd_soc_codec *codec = codec_dai->codec;
2657         int mute_reg;
2658         int reg;
2659
2660         switch (codec_dai->id) {
2661         case 1:
2662                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2663                 break;
2664         case 2:
2665                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2666                 break;
2667         default:
2668                 return -EINVAL;
2669         }
2670
2671         if (mute)
2672                 reg = WM8994_AIF1DAC1_MUTE;
2673         else
2674                 reg = 0;
2675
2676         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2677
2678         return 0;
2679 }
2680
2681 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2682 {
2683         struct snd_soc_codec *codec = codec_dai->codec;
2684         int reg, val, mask;
2685
2686         switch (codec_dai->id) {
2687         case 1:
2688                 reg = WM8994_AIF1_MASTER_SLAVE;
2689                 mask = WM8994_AIF1_TRI;
2690                 break;
2691         case 2:
2692                 reg = WM8994_AIF2_MASTER_SLAVE;
2693                 mask = WM8994_AIF2_TRI;
2694                 break;
2695         case 3:
2696                 reg = WM8994_POWER_MANAGEMENT_6;
2697                 mask = WM8994_AIF3_TRI;
2698                 break;
2699         default:
2700                 return -EINVAL;
2701         }
2702
2703         if (tristate)
2704                 val = mask;
2705         else
2706                 val = 0;
2707
2708         return snd_soc_update_bits(codec, reg, mask, val);
2709 }
2710
2711 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2712 {
2713         struct snd_soc_codec *codec = dai->codec;
2714
2715         /* Disable the pulls on the AIF if we're using it to save power. */
2716         snd_soc_update_bits(codec, WM8994_GPIO_3,
2717                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2718         snd_soc_update_bits(codec, WM8994_GPIO_4,
2719                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2720         snd_soc_update_bits(codec, WM8994_GPIO_5,
2721                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2722
2723         return 0;
2724 }
2725
2726 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2727
2728 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2729                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2730
2731 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2732         .set_sysclk     = wm8994_set_dai_sysclk,
2733         .set_fmt        = wm8994_set_dai_fmt,
2734         .hw_params      = wm8994_hw_params,
2735         .shutdown       = wm8994_aif_shutdown,
2736         .digital_mute   = wm8994_aif_mute,
2737         .set_pll        = wm8994_set_fll,
2738         .set_tristate   = wm8994_set_tristate,
2739 };
2740
2741 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2742         .set_sysclk     = wm8994_set_dai_sysclk,
2743         .set_fmt        = wm8994_set_dai_fmt,
2744         .hw_params      = wm8994_hw_params,
2745         .shutdown       = wm8994_aif_shutdown,
2746         .digital_mute   = wm8994_aif_mute,
2747         .set_pll        = wm8994_set_fll,
2748         .set_tristate   = wm8994_set_tristate,
2749 };
2750
2751 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2752         .hw_params      = wm8994_aif3_hw_params,
2753         .set_tristate   = wm8994_set_tristate,
2754 };
2755
2756 static struct snd_soc_dai_driver wm8994_dai[] = {
2757         {
2758                 .name = "wm8994-aif1",
2759                 .id = 1,
2760                 .playback = {
2761                         .stream_name = "AIF1 Playback",
2762                         .channels_min = 1,
2763                         .channels_max = 2,
2764                         .rates = WM8994_RATES,
2765                         .formats = WM8994_FORMATS,
2766                         .sig_bits = 24,
2767                 },
2768                 .capture = {
2769                         .stream_name = "AIF1 Capture",
2770                         .channels_min = 1,
2771                         .channels_max = 2,
2772                         .rates = WM8994_RATES,
2773                         .formats = WM8994_FORMATS,
2774                         .sig_bits = 24,
2775                  },
2776                 .ops = &wm8994_aif1_dai_ops,
2777         },
2778         {
2779                 .name = "wm8994-aif2",
2780                 .id = 2,
2781                 .playback = {
2782                         .stream_name = "AIF2 Playback",
2783                         .channels_min = 1,
2784                         .channels_max = 2,
2785                         .rates = WM8994_RATES,
2786                         .formats = WM8994_FORMATS,
2787                         .sig_bits = 24,
2788                 },
2789                 .capture = {
2790                         .stream_name = "AIF2 Capture",
2791                         .channels_min = 1,
2792                         .channels_max = 2,
2793                         .rates = WM8994_RATES,
2794                         .formats = WM8994_FORMATS,
2795                         .sig_bits = 24,
2796                 },
2797                 .probe = wm8994_aif2_probe,
2798                 .ops = &wm8994_aif2_dai_ops,
2799         },
2800         {
2801                 .name = "wm8994-aif3",
2802                 .id = 3,
2803                 .playback = {
2804                         .stream_name = "AIF3 Playback",
2805                         .channels_min = 1,
2806                         .channels_max = 2,
2807                         .rates = WM8994_RATES,
2808                         .formats = WM8994_FORMATS,
2809                         .sig_bits = 24,
2810                 },
2811                 .capture = {
2812                         .stream_name = "AIF3 Capture",
2813                         .channels_min = 1,
2814                         .channels_max = 2,
2815                         .rates = WM8994_RATES,
2816                         .formats = WM8994_FORMATS,
2817                         .sig_bits = 24,
2818                  },
2819                 .ops = &wm8994_aif3_dai_ops,
2820         }
2821 };
2822
2823 #ifdef CONFIG_PM
2824 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2825 {
2826         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2827         struct wm8994 *control = wm8994->wm8994;
2828         int i, ret;
2829
2830         switch (control->type) {
2831         case WM8994:
2832                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2833                 break;
2834         case WM1811:
2835                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2836                                     WM1811_JACKDET_MODE_MASK, 0);
2837                 /* Fall through */
2838         case WM8958:
2839                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2840                                     WM8958_MICD_ENA, 0);
2841                 break;
2842         }
2843
2844         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2845                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2846                        sizeof(struct wm8994_fll_config));
2847                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2848                 if (ret < 0)
2849                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2850                                  i + 1, ret);
2851         }
2852
2853         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2854
2855         return 0;
2856 }
2857
2858 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2859 {
2860         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2861         struct wm8994 *control = wm8994->wm8994;
2862         int i, ret;
2863         unsigned int val, mask;
2864
2865         if (wm8994->revision < 4) {
2866                 /* force a HW read */
2867                 ret = regmap_read(control->regmap,
2868                                   WM8994_POWER_MANAGEMENT_5, &val);
2869
2870                 /* modify the cache only */
2871                 codec->cache_only = 1;
2872                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2873                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2874                 val &= mask;
2875                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2876                                     mask, val);
2877                 codec->cache_only = 0;
2878         }
2879
2880         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2881                 if (!wm8994->fll_suspend[i].out)
2882                         continue;
2883
2884                 ret = _wm8994_set_fll(codec, i + 1,
2885                                      wm8994->fll_suspend[i].src,
2886                                      wm8994->fll_suspend[i].in,
2887                                      wm8994->fll_suspend[i].out);
2888                 if (ret < 0)
2889                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2890                                  i + 1, ret);
2891         }
2892
2893         switch (control->type) {
2894         case WM8994:
2895                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2896                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2897                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2898                 break;
2899         case WM1811:
2900                 if (wm8994->jackdet && wm8994->jack_cb) {
2901                         /* Restart from idle */
2902                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2903                                             WM1811_JACKDET_MODE_MASK,
2904                                             WM1811_JACKDET_MODE_JACK);
2905                         break;
2906                 }
2907                 break;
2908         case WM8958:
2909                 if (wm8994->jack_cb)
2910                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2911                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2912                 break;
2913         }
2914
2915         return 0;
2916 }
2917 #else
2918 #define wm8994_codec_suspend NULL
2919 #define wm8994_codec_resume NULL
2920 #endif
2921
2922 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2923 {
2924         struct snd_soc_codec *codec = wm8994->codec;
2925         struct wm8994_pdata *pdata = wm8994->pdata;
2926         struct snd_kcontrol_new controls[] = {
2927                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2928                              wm8994->retune_mobile_enum,
2929                              wm8994_get_retune_mobile_enum,
2930                              wm8994_put_retune_mobile_enum),
2931                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2932                              wm8994->retune_mobile_enum,
2933                              wm8994_get_retune_mobile_enum,
2934                              wm8994_put_retune_mobile_enum),
2935                 SOC_ENUM_EXT("AIF2 EQ Mode",
2936                              wm8994->retune_mobile_enum,
2937                              wm8994_get_retune_mobile_enum,
2938                              wm8994_put_retune_mobile_enum),
2939         };
2940         int ret, i, j;
2941         const char **t;
2942
2943         /* We need an array of texts for the enum API but the number
2944          * of texts is likely to be less than the number of
2945          * configurations due to the sample rate dependency of the
2946          * configurations. */
2947         wm8994->num_retune_mobile_texts = 0;
2948         wm8994->retune_mobile_texts = NULL;
2949         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2950                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2951                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2952                                    wm8994->retune_mobile_texts[j]) == 0)
2953                                 break;
2954                 }
2955
2956                 if (j != wm8994->num_retune_mobile_texts)
2957                         continue;
2958
2959                 /* Expand the array... */
2960                 t = krealloc(wm8994->retune_mobile_texts,
2961                              sizeof(char *) * 
2962                              (wm8994->num_retune_mobile_texts + 1),
2963                              GFP_KERNEL);
2964                 if (t == NULL)
2965                         continue;
2966
2967                 /* ...store the new entry... */
2968                 t[wm8994->num_retune_mobile_texts] = 
2969                         pdata->retune_mobile_cfgs[i].name;
2970
2971                 /* ...and remember the new version. */
2972                 wm8994->num_retune_mobile_texts++;
2973                 wm8994->retune_mobile_texts = t;
2974         }
2975
2976         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2977                 wm8994->num_retune_mobile_texts);
2978
2979         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2980         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2981
2982         ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2983                                    ARRAY_SIZE(controls));
2984         if (ret != 0)
2985                 dev_err(wm8994->codec->dev,
2986                         "Failed to add ReTune Mobile controls: %d\n", ret);
2987 }
2988
2989 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2990 {
2991         struct snd_soc_codec *codec = wm8994->codec;
2992         struct wm8994_pdata *pdata = wm8994->pdata;
2993         int ret, i;
2994
2995         if (!pdata)
2996                 return;
2997
2998         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2999                                       pdata->lineout2_diff,
3000                                       pdata->lineout1fb,
3001                                       pdata->lineout2fb,
3002                                       pdata->jd_scthr,
3003                                       pdata->jd_thr,
3004                                       pdata->micbias1_lvl,
3005                                       pdata->micbias2_lvl);
3006
3007         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3008
3009         if (pdata->num_drc_cfgs) {
3010                 struct snd_kcontrol_new controls[] = {
3011                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3012                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3013                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3014                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3015                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3016                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3017                 };
3018
3019                 /* We need an array of texts for the enum API */
3020                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3021                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3022                 if (!wm8994->drc_texts) {
3023                         dev_err(wm8994->codec->dev,
3024                                 "Failed to allocate %d DRC config texts\n",
3025                                 pdata->num_drc_cfgs);
3026                         return;
3027                 }
3028
3029                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3030                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3031
3032                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3033                 wm8994->drc_enum.texts = wm8994->drc_texts;
3034
3035                 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
3036                                            ARRAY_SIZE(controls));
3037                 if (ret != 0)
3038                         dev_err(wm8994->codec->dev,
3039                                 "Failed to add DRC mode controls: %d\n", ret);
3040
3041                 for (i = 0; i < WM8994_NUM_DRC; i++)
3042                         wm8994_set_drc(codec, i);
3043         }
3044
3045         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3046                 pdata->num_retune_mobile_cfgs);
3047
3048         if (pdata->num_retune_mobile_cfgs)
3049                 wm8994_handle_retune_mobile_pdata(wm8994);
3050         else
3051                 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
3052                                      ARRAY_SIZE(wm8994_eq_controls));
3053
3054         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3055                 if (pdata->micbias[i]) {
3056                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3057                                 pdata->micbias[i] & 0xffff);
3058                 }
3059         }
3060 }
3061
3062 /**
3063  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3064  *
3065  * @codec:   WM8994 codec
3066  * @jack:    jack to report detection events on
3067  * @micbias: microphone bias to detect on
3068  *
3069  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3070  * being used to bring out signals to the processor then only platform
3071  * data configuration is needed for WM8994 and processor GPIOs should
3072  * be configured using snd_soc_jack_add_gpios() instead.
3073  *
3074  * Configuration of detection levels is available via the micbias1_lvl
3075  * and micbias2_lvl platform data members.
3076  */
3077 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3078                       int micbias)
3079 {
3080         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3081         struct wm8994_micdet *micdet;
3082         struct wm8994 *control = wm8994->wm8994;
3083         int reg, ret;
3084
3085         if (control->type != WM8994) {
3086                 dev_warn(codec->dev, "Not a WM8994\n");
3087                 return -EINVAL;
3088         }
3089
3090         switch (micbias) {
3091         case 1:
3092                 micdet = &wm8994->micdet[0];
3093                 if (jack)
3094                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3095                                                             "MICBIAS1");
3096                 else
3097                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3098                                                        "MICBIAS1");
3099                 break;
3100         case 2:
3101                 micdet = &wm8994->micdet[1];
3102                 if (jack)
3103                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3104                                                             "MICBIAS1");
3105                 else
3106                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3107                                                        "MICBIAS1");
3108                 break;
3109         default:
3110                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3111                 return -EINVAL;
3112         }
3113
3114         if (ret != 0)
3115                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3116                          micbias, ret);
3117
3118         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3119                 micbias, jack);
3120
3121         /* Store the configuration */
3122         micdet->jack = jack;
3123         micdet->detecting = true;
3124
3125         /* If either of the jacks is set up then enable detection */
3126         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3127                 reg = WM8994_MICD_ENA;
3128         else
3129                 reg = 0;
3130
3131         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3132
3133         snd_soc_dapm_sync(&codec->dapm);
3134
3135         return 0;
3136 }
3137 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3138
3139 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3140 {
3141         struct wm8994_priv *priv = data;
3142         struct snd_soc_codec *codec = priv->codec;
3143         int reg;
3144         int report;
3145
3146 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3147         trace_snd_soc_jack_irq(dev_name(codec->dev));
3148 #endif
3149
3150         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3151         if (reg < 0) {
3152                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3153                         reg);
3154                 return IRQ_HANDLED;
3155         }
3156
3157         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3158
3159         report = 0;
3160         if (reg & WM8994_MIC1_DET_STS) {
3161                 if (priv->micdet[0].detecting)
3162                         report = SND_JACK_HEADSET;
3163         }
3164         if (reg & WM8994_MIC1_SHRT_STS) {
3165                 if (priv->micdet[0].detecting)
3166                         report = SND_JACK_HEADPHONE;
3167                 else
3168                         report |= SND_JACK_BTN_0;
3169         }
3170         if (report)
3171                 priv->micdet[0].detecting = false;
3172         else
3173                 priv->micdet[0].detecting = true;
3174
3175         snd_soc_jack_report(priv->micdet[0].jack, report,
3176                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3177
3178         report = 0;
3179         if (reg & WM8994_MIC2_DET_STS) {
3180                 if (priv->micdet[1].detecting)
3181                         report = SND_JACK_HEADSET;
3182         }
3183         if (reg & WM8994_MIC2_SHRT_STS) {
3184                 if (priv->micdet[1].detecting)
3185                         report = SND_JACK_HEADPHONE;
3186                 else
3187                         report |= SND_JACK_BTN_0;
3188         }
3189         if (report)
3190                 priv->micdet[1].detecting = false;
3191         else
3192                 priv->micdet[1].detecting = true;
3193
3194         snd_soc_jack_report(priv->micdet[1].jack, report,
3195                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3196
3197         return IRQ_HANDLED;
3198 }
3199
3200 /* Default microphone detection handler for WM8958 - the user can
3201  * override this if they wish.
3202  */
3203 static void wm8958_default_micdet(u16 status, void *data)
3204 {
3205         struct snd_soc_codec *codec = data;
3206         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3207         int report;
3208
3209         dev_dbg(codec->dev, "MICDET %x\n", status);
3210
3211         /* Either nothing present or just starting detection */
3212         if (!(status & WM8958_MICD_STS)) {
3213                 if (!wm8994->jackdet) {
3214                         /* If nothing present then clear our statuses */
3215                         dev_dbg(codec->dev, "Detected open circuit\n");
3216                         wm8994->jack_mic = false;
3217                         wm8994->mic_detecting = true;
3218
3219                         wm8958_micd_set_rate(codec);
3220
3221                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3222                                             wm8994->btn_mask |
3223                                              SND_JACK_HEADSET);
3224                 }
3225                 return;
3226         }
3227
3228         /* If the measurement is showing a high impedence we've got a
3229          * microphone.
3230          */
3231         if (wm8994->mic_detecting && (status & 0x600)) {
3232                 dev_dbg(codec->dev, "Detected microphone\n");
3233
3234                 wm8994->mic_detecting = false;
3235                 wm8994->jack_mic = true;
3236
3237                 wm8958_micd_set_rate(codec);
3238
3239                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3240                                     SND_JACK_HEADSET);
3241         }
3242
3243
3244         if (wm8994->mic_detecting && status & 0xfc) {
3245                 dev_dbg(codec->dev, "Detected headphone\n");
3246                 wm8994->mic_detecting = false;
3247
3248                 wm8958_micd_set_rate(codec);
3249
3250                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3251                                     SND_JACK_HEADSET);
3252
3253                 /* If we have jackdet that will detect removal */
3254                 if (wm8994->jackdet) {
3255                         mutex_lock(&wm8994->accdet_lock);
3256
3257                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3258                                             WM8958_MICD_ENA, 0);
3259
3260                         wm1811_jackdet_set_mode(codec,
3261                                                 WM1811_JACKDET_MODE_JACK);
3262
3263                         mutex_unlock(&wm8994->accdet_lock);
3264
3265                         if (wm8994->pdata->jd_ext_cap) {
3266                                 mutex_lock(&codec->mutex);
3267                                 snd_soc_dapm_disable_pin(&codec->dapm,
3268                                                          "MICBIAS2");
3269                                 snd_soc_dapm_sync(&codec->dapm);
3270                                 mutex_unlock(&codec->mutex);
3271                         }
3272                 }
3273         }
3274
3275         /* Report short circuit as a button */
3276         if (wm8994->jack_mic) {
3277                 report = 0;
3278                 if (status & 0x4)
3279                         report |= SND_JACK_BTN_0;
3280
3281                 if (status & 0x8)
3282                         report |= SND_JACK_BTN_1;
3283
3284                 if (status & 0x10)
3285                         report |= SND_JACK_BTN_2;
3286
3287                 if (status & 0x20)
3288                         report |= SND_JACK_BTN_3;
3289
3290                 if (status & 0x40)
3291                         report |= SND_JACK_BTN_4;
3292
3293                 if (status & 0x80)
3294                         report |= SND_JACK_BTN_5;
3295
3296                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3297                                     wm8994->btn_mask);
3298         }
3299 }
3300
3301 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3302 {
3303         struct wm8994_priv *wm8994 = data;
3304         struct snd_soc_codec *codec = wm8994->codec;
3305         int reg;
3306         bool present;
3307
3308         mutex_lock(&wm8994->accdet_lock);
3309
3310         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3311         if (reg < 0) {
3312                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3313                 mutex_unlock(&wm8994->accdet_lock);
3314                 return IRQ_NONE;
3315         }
3316
3317         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3318
3319         present = reg & WM1811_JACKDET_LVL;
3320
3321         if (present) {
3322                 dev_dbg(codec->dev, "Jack detected\n");
3323
3324                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3325                                     WM8958_MICB2_DISCH, 0);
3326
3327                 /* Disable debounce while inserted */
3328                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3329                                     WM1811_JACKDET_DB, 0);
3330
3331                 /*
3332                  * Start off measument of microphone impedence to find
3333                  * out what's actually there.
3334                  */
3335                 wm8994->mic_detecting = true;
3336                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3337
3338                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3339                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3340         } else {
3341                 dev_dbg(codec->dev, "Jack not detected\n");
3342
3343                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3344                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3345
3346                 /* Enable debounce while removed */
3347                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3348                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3349
3350                 wm8994->mic_detecting = false;
3351                 wm8994->jack_mic = false;
3352                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3353                                     WM8958_MICD_ENA, 0);
3354                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3355         }
3356
3357         mutex_unlock(&wm8994->accdet_lock);
3358
3359         /* If required for an external cap force MICBIAS on */
3360         if (wm8994->pdata->jd_ext_cap) {
3361                 mutex_lock(&codec->mutex);
3362
3363                 if (present)
3364                         snd_soc_dapm_force_enable_pin(&codec->dapm,
3365                                                       "MICBIAS2");
3366                 else
3367                         snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3368
3369                 snd_soc_dapm_sync(&codec->dapm);
3370                 mutex_unlock(&codec->mutex);
3371         }
3372
3373         if (present)
3374                 snd_soc_jack_report(wm8994->micdet[0].jack,
3375                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3376         else
3377                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3378                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3379                                     wm8994->btn_mask);
3380
3381         return IRQ_HANDLED;
3382 }
3383
3384 /**
3385  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3386  *
3387  * @codec:   WM8958 codec
3388  * @jack:    jack to report detection events on
3389  *
3390  * Enable microphone detection functionality for the WM8958.  By
3391  * default simple detection which supports the detection of up to 6
3392  * buttons plus video and microphone functionality is supported.
3393  *
3394  * The WM8958 has an advanced jack detection facility which is able to
3395  * support complex accessory detection, especially when used in
3396  * conjunction with external circuitry.  In order to provide maximum
3397  * flexiblity a callback is provided which allows a completely custom
3398  * detection algorithm.
3399  */
3400 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3401                       wm8958_micdet_cb cb, void *cb_data)
3402 {
3403         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3404         struct wm8994 *control = wm8994->wm8994;
3405         u16 micd_lvl_sel;
3406
3407         switch (control->type) {
3408         case WM1811:
3409         case WM8958:
3410                 break;
3411         default:
3412                 return -EINVAL;
3413         }
3414
3415         if (jack) {
3416                 if (!cb) {
3417                         dev_dbg(codec->dev, "Using default micdet callback\n");
3418                         cb = wm8958_default_micdet;
3419                         cb_data = codec;
3420                 }
3421
3422                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3423                 snd_soc_dapm_sync(&codec->dapm);
3424
3425                 wm8994->micdet[0].jack = jack;
3426                 wm8994->jack_cb = cb;
3427                 wm8994->jack_cb_data = cb_data;
3428
3429                 wm8994->mic_detecting = true;
3430                 wm8994->jack_mic = false;
3431
3432                 wm8958_micd_set_rate(codec);
3433
3434                 /* Detect microphones and short circuits by default */
3435                 if (wm8994->pdata->micd_lvl_sel)
3436                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3437                 else
3438                         micd_lvl_sel = 0x41;
3439
3440                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3441                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3442                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3443
3444                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3445                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3446
3447                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3448
3449                 /*
3450                  * If we can use jack detection start off with that,
3451                  * otherwise jump straight to microphone detection.
3452                  */
3453                 if (wm8994->jackdet) {
3454                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3455                                             WM8958_MICB2_DISCH,
3456                                             WM8958_MICB2_DISCH);
3457                         snd_soc_update_bits(codec, WM8994_LDO_1,
3458                                             WM8994_LDO1_DISCH, 0);
3459                         wm1811_jackdet_set_mode(codec,
3460                                                 WM1811_JACKDET_MODE_JACK);
3461                 } else {
3462                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3463                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3464                 }
3465
3466         } else {
3467                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3468                                     WM8958_MICD_ENA, 0);
3469                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3470                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3471                 snd_soc_dapm_sync(&codec->dapm);
3472         }
3473
3474         return 0;
3475 }
3476 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3477
3478 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3479 {
3480         struct wm8994_priv *wm8994 = data;
3481         struct snd_soc_codec *codec = wm8994->codec;
3482         int reg, count;
3483
3484         /*
3485          * Jack detection may have detected a removal simulataneously
3486          * with an update of the MICDET status; if so it will have
3487          * stopped detection and we can ignore this interrupt.
3488          */
3489         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3490                 return IRQ_HANDLED;
3491
3492         /* We may occasionally read a detection without an impedence
3493          * range being provided - if that happens loop again.
3494          */
3495         count = 10;
3496         do {
3497                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3498                 if (reg < 0) {
3499                         dev_err(codec->dev,
3500                                 "Failed to read mic detect status: %d\n",
3501                                 reg);
3502                         return IRQ_NONE;
3503                 }
3504
3505                 if (!(reg & WM8958_MICD_VALID)) {
3506                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3507                         goto out;
3508                 }
3509
3510                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3511                         break;
3512
3513                 msleep(1);
3514         } while (count--);
3515
3516         if (count == 0)
3517                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3518
3519 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3520         trace_snd_soc_jack_irq(dev_name(codec->dev));
3521 #endif
3522
3523         if (wm8994->jack_cb)
3524                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3525         else
3526                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3527
3528 out:
3529         return IRQ_HANDLED;
3530 }
3531
3532 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3533 {
3534         struct snd_soc_codec *codec = data;
3535
3536         dev_err(codec->dev, "FIFO error\n");
3537
3538         return IRQ_HANDLED;
3539 }
3540
3541 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3542 {
3543         struct snd_soc_codec *codec = data;
3544
3545         dev_err(codec->dev, "Thermal warning\n");
3546
3547         return IRQ_HANDLED;
3548 }
3549
3550 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3551 {
3552         struct snd_soc_codec *codec = data;
3553
3554         dev_crit(codec->dev, "Thermal shutdown\n");
3555
3556         return IRQ_HANDLED;
3557 }
3558
3559 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3560 {
3561         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3562         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3563         struct snd_soc_dapm_context *dapm = &codec->dapm;
3564         unsigned int reg;
3565         int ret, i;
3566
3567         wm8994->codec = codec;
3568         codec->control_data = control->regmap;
3569
3570         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3571
3572         wm8994->codec = codec;
3573
3574         mutex_init(&wm8994->accdet_lock);
3575
3576         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3577                 init_completion(&wm8994->fll_locked[i]);
3578
3579         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3580                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3581         else if (wm8994->pdata && wm8994->pdata->irq_base)
3582                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3583                                      WM8994_IRQ_MIC1_DET;
3584
3585         pm_runtime_enable(codec->dev);
3586         pm_runtime_idle(codec->dev);
3587
3588         /* By default use idle_bias_off, will override for WM8994 */
3589         codec->dapm.idle_bias_off = 1;
3590
3591         /* Set revision-specific configuration */
3592         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3593         switch (control->type) {
3594         case WM8994:
3595                 /* Single ended line outputs should have VMID on. */
3596                 if (!wm8994->pdata->lineout1_diff ||
3597                     !wm8994->pdata->lineout2_diff)
3598                         codec->dapm.idle_bias_off = 0;
3599
3600                 switch (wm8994->revision) {
3601                 case 2:
3602                 case 3:
3603                         wm8994->hubs.dcs_codes_l = -5;
3604                         wm8994->hubs.dcs_codes_r = -5;
3605                         wm8994->hubs.hp_startup_mode = 1;
3606                         wm8994->hubs.dcs_readback_mode = 1;
3607                         wm8994->hubs.series_startup = 1;
3608                         break;
3609                 default:
3610                         wm8994->hubs.dcs_readback_mode = 2;
3611                         break;
3612                 }
3613                 break;
3614
3615         case WM8958:
3616                 wm8994->hubs.dcs_readback_mode = 1;
3617                 wm8994->hubs.hp_startup_mode = 1;
3618                 break;
3619
3620         case WM1811:
3621                 wm8994->hubs.dcs_readback_mode = 2;
3622                 wm8994->hubs.no_series_update = 1;
3623                 wm8994->hubs.hp_startup_mode = 1;
3624                 wm8994->hubs.no_cache_class_w = true;
3625
3626                 switch (wm8994->revision) {
3627                 case 0:
3628                 case 1:
3629                 case 2:
3630                 case 3:
3631                         wm8994->hubs.dcs_codes_l = -9;
3632                         wm8994->hubs.dcs_codes_r = -7;
3633                         break;
3634                 default:
3635                         break;
3636                 }
3637
3638                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3639                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3640                 break;
3641
3642         default:
3643                 break;
3644         }
3645
3646         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3647                            wm8994_fifo_error, "FIFO error", codec);
3648         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3649                            wm8994_temp_warn, "Thermal warning", codec);
3650         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3651                            wm8994_temp_shut, "Thermal shutdown", codec);
3652
3653         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3654                                  wm_hubs_dcs_done, "DC servo done",
3655                                  &wm8994->hubs);
3656         if (ret == 0)
3657                 wm8994->hubs.dcs_done_irq = true;
3658
3659         switch (control->type) {
3660         case WM8994:
3661                 if (wm8994->micdet_irq) {
3662                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3663                                                    wm8994_mic_irq,
3664                                                    IRQF_TRIGGER_RISING,
3665                                                    "Mic1 detect",
3666                                                    wm8994);
3667                         if (ret != 0)
3668                                 dev_warn(codec->dev,
3669                                          "Failed to request Mic1 detect IRQ: %d\n",
3670                                          ret);
3671                 }
3672
3673                 ret = wm8994_request_irq(wm8994->wm8994,
3674                                          WM8994_IRQ_MIC1_SHRT,
3675                                          wm8994_mic_irq, "Mic 1 short",
3676                                          wm8994);
3677                 if (ret != 0)
3678                         dev_warn(codec->dev,
3679                                  "Failed to request Mic1 short IRQ: %d\n",
3680                                  ret);
3681
3682                 ret = wm8994_request_irq(wm8994->wm8994,
3683                                          WM8994_IRQ_MIC2_DET,
3684                                          wm8994_mic_irq, "Mic 2 detect",
3685                                          wm8994);
3686                 if (ret != 0)
3687                         dev_warn(codec->dev,
3688                                  "Failed to request Mic2 detect IRQ: %d\n",
3689                                  ret);
3690
3691                 ret = wm8994_request_irq(wm8994->wm8994,
3692                                          WM8994_IRQ_MIC2_SHRT,
3693                                          wm8994_mic_irq, "Mic 2 short",
3694                                          wm8994);
3695                 if (ret != 0)
3696                         dev_warn(codec->dev,
3697                                  "Failed to request Mic2 short IRQ: %d\n",
3698                                  ret);
3699                 break;
3700
3701         case WM8958:
3702         case WM1811:
3703                 if (wm8994->micdet_irq) {
3704                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3705                                                    wm8958_mic_irq,
3706                                                    IRQF_TRIGGER_RISING,
3707                                                    "Mic detect",
3708                                                    wm8994);
3709                         if (ret != 0)
3710                                 dev_warn(codec->dev,
3711                                          "Failed to request Mic detect IRQ: %d\n",
3712                                          ret);
3713                 }
3714         }
3715
3716         switch (control->type) {
3717         case WM1811:
3718                 if (wm8994->revision > 1) {
3719                         ret = wm8994_request_irq(wm8994->wm8994,
3720                                                  WM8994_IRQ_GPIO(6),
3721                                                  wm1811_jackdet_irq, "JACKDET",
3722                                                  wm8994);
3723                         if (ret == 0)
3724                                 wm8994->jackdet = true;
3725                 }
3726                 break;
3727         default:
3728                 break;
3729         }
3730
3731         wm8994->fll_locked_irq = true;
3732         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3733                 ret = wm8994_request_irq(wm8994->wm8994,
3734                                          WM8994_IRQ_FLL1_LOCK + i,
3735                                          wm8994_fll_locked_irq, "FLL lock",
3736                                          &wm8994->fll_locked[i]);
3737                 if (ret != 0)
3738                         wm8994->fll_locked_irq = false;
3739         }
3740
3741         /* Make sure we can read from the GPIOs if they're inputs */
3742         pm_runtime_get_sync(codec->dev);
3743
3744         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3745          * configured on init - if a system wants to do this dynamically
3746          * at runtime we can deal with that then.
3747          */
3748         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3749         if (ret < 0) {
3750                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3751                 goto err_irq;
3752         }
3753         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3754                 wm8994->lrclk_shared[0] = 1;
3755                 wm8994_dai[0].symmetric_rates = 1;
3756         } else {
3757                 wm8994->lrclk_shared[0] = 0;
3758         }
3759
3760         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3761         if (ret < 0) {
3762                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3763                 goto err_irq;
3764         }
3765         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3766                 wm8994->lrclk_shared[1] = 1;
3767                 wm8994_dai[1].symmetric_rates = 1;
3768         } else {
3769                 wm8994->lrclk_shared[1] = 0;
3770         }
3771
3772         pm_runtime_put(codec->dev);
3773
3774         /* Latch volume updates (right only; we always do left then right). */
3775         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3776                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3777         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3778                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3779         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3780                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3781         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3782                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3783         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3784                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3785         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3786                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3787         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3788                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3789         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3790                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3791         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3792                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3793         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3794                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3795         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3796                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3797         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3798                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3799         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3800                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3801         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3802                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3803         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3804                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3805         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3806                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3807
3808         /* Set the low bit of the 3D stereo depth so TLV matches */
3809         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3810                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3811                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3812         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3813                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3814                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3815         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3816                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3817                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3818
3819         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3820          * use this; it only affects behaviour on idle TDM clock
3821          * cycles. */
3822         switch (control->type) {
3823         case WM8994:
3824         case WM8958:
3825                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3826                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3827                 break;
3828         default:
3829                 break;
3830         }
3831
3832         /* Put MICBIAS into bypass mode by default on newer devices */
3833         switch (control->type) {
3834         case WM8958:
3835         case WM1811:
3836                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3837                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3838                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3839                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3840                 break;
3841         default:
3842                 break;
3843         }
3844
3845         wm8994_update_class_w(codec);
3846
3847         wm8994_handle_pdata(wm8994);
3848
3849         wm_hubs_add_analogue_controls(codec);
3850         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3851                              ARRAY_SIZE(wm8994_snd_controls));
3852         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3853                                   ARRAY_SIZE(wm8994_dapm_widgets));
3854
3855         switch (control->type) {
3856         case WM8994:
3857                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3858                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3859                 if (wm8994->revision < 4) {
3860                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3861                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3862                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3863                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3864                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3865                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3866                 } else {
3867                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3868                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3869                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3870                                                   ARRAY_SIZE(wm8994_adc_widgets));
3871                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3872                                                   ARRAY_SIZE(wm8994_dac_widgets));
3873                 }
3874                 break;
3875         case WM8958:
3876                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3877                                      ARRAY_SIZE(wm8958_snd_controls));
3878                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3879                                           ARRAY_SIZE(wm8958_dapm_widgets));
3880                 if (wm8994->revision < 1) {
3881                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3882                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3883                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3884                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3885                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3886                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3887                 } else {
3888                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3889                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3890                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3891                                                   ARRAY_SIZE(wm8994_adc_widgets));
3892                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3893                                                   ARRAY_SIZE(wm8994_dac_widgets));
3894                 }
3895                 break;
3896
3897         case WM1811:
3898                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3899                                      ARRAY_SIZE(wm8958_snd_controls));
3900                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3901                                           ARRAY_SIZE(wm8958_dapm_widgets));
3902                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3903                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3904                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3905                                           ARRAY_SIZE(wm8994_adc_widgets));
3906                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3907                                           ARRAY_SIZE(wm8994_dac_widgets));
3908                 break;
3909         }
3910                 
3911
3912         wm_hubs_add_analogue_routes(codec, 0, 0);
3913         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3914
3915         switch (control->type) {
3916         case WM8994:
3917                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3918                                         ARRAY_SIZE(wm8994_intercon));
3919
3920                 if (wm8994->revision < 4) {
3921                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3922                                                 ARRAY_SIZE(wm8994_revd_intercon));
3923                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3924                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3925                 } else {
3926                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3927                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3928                 }
3929                 break;
3930         case WM8958:
3931                 if (wm8994->revision < 1) {
3932                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3933                                                 ARRAY_SIZE(wm8994_revd_intercon));
3934                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3935                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3936                 } else {
3937                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3938                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3939                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3940                                                 ARRAY_SIZE(wm8958_intercon));
3941                 }
3942
3943                 wm8958_dsp2_init(codec);
3944                 break;
3945         case WM1811:
3946                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3947                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3948                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3949                                         ARRAY_SIZE(wm8958_intercon));
3950                 break;
3951         }
3952
3953         return 0;
3954
3955 err_irq:
3956         if (wm8994->jackdet)
3957                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3958         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3959         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3960         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3961         if (wm8994->micdet_irq)
3962                 free_irq(wm8994->micdet_irq, wm8994);
3963         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3964                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3965                                 &wm8994->fll_locked[i]);
3966         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3967                         &wm8994->hubs);
3968         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3969         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3970         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3971
3972         return ret;
3973 }
3974
3975 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3976 {
3977         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3978         struct wm8994 *control = wm8994->wm8994;
3979         int i;
3980
3981         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3982
3983         pm_runtime_disable(codec->dev);
3984
3985         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3986                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3987                                 &wm8994->fll_locked[i]);
3988
3989         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3990                         &wm8994->hubs);
3991         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3992         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3993         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3994
3995         if (wm8994->jackdet)
3996                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3997
3998         switch (control->type) {
3999         case WM8994:
4000                 if (wm8994->micdet_irq)
4001                         free_irq(wm8994->micdet_irq, wm8994);
4002                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4003                                 wm8994);
4004                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4005                                 wm8994);
4006                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4007                                 wm8994);
4008                 break;
4009
4010         case WM1811:
4011         case WM8958:
4012                 if (wm8994->micdet_irq)
4013                         free_irq(wm8994->micdet_irq, wm8994);
4014                 break;
4015         }
4016         if (wm8994->mbc)
4017                 release_firmware(wm8994->mbc);
4018         if (wm8994->mbc_vss)
4019                 release_firmware(wm8994->mbc_vss);
4020         if (wm8994->enh_eq)
4021                 release_firmware(wm8994->enh_eq);
4022         kfree(wm8994->retune_mobile_texts);
4023
4024         return 0;
4025 }
4026
4027 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4028         .probe =        wm8994_codec_probe,
4029         .remove =       wm8994_codec_remove,
4030         .suspend =      wm8994_codec_suspend,
4031         .resume =       wm8994_codec_resume,
4032         .set_bias_level = wm8994_set_bias_level,
4033 };
4034
4035 static int __devinit wm8994_probe(struct platform_device *pdev)
4036 {
4037         struct wm8994_priv *wm8994;
4038
4039         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4040                               GFP_KERNEL);
4041         if (wm8994 == NULL)
4042                 return -ENOMEM;
4043         platform_set_drvdata(pdev, wm8994);
4044
4045         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4046         wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4047
4048         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4049                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4050 }
4051
4052 static int __devexit wm8994_remove(struct platform_device *pdev)
4053 {
4054         snd_soc_unregister_codec(&pdev->dev);
4055         return 0;
4056 }
4057
4058 #ifdef CONFIG_PM_SLEEP
4059 static int wm8994_suspend(struct device *dev)
4060 {
4061         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4062
4063         /* Drop down to power saving mode when system is suspended */
4064         if (wm8994->jackdet && !wm8994->active_refcount)
4065                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4066                                    WM1811_JACKDET_MODE_MASK,
4067                                    wm8994->jackdet_mode);
4068
4069         return 0;
4070 }
4071
4072 static int wm8994_resume(struct device *dev)
4073 {
4074         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4075
4076         if (wm8994->jackdet && wm8994->jack_cb)
4077                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4078                                    WM1811_JACKDET_MODE_MASK,
4079                                    WM1811_JACKDET_MODE_AUDIO);
4080
4081         return 0;
4082 }
4083 #endif
4084
4085 static const struct dev_pm_ops wm8994_pm_ops = {
4086         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4087 };
4088
4089 static struct platform_driver wm8994_codec_driver = {
4090         .driver = {
4091                 .name = "wm8994-codec",
4092                 .owner = THIS_MODULE,
4093                 .pm = &wm8994_pm_ops,
4094         },
4095         .probe = wm8994_probe,
4096         .remove = __devexit_p(wm8994_remove),
4097 };
4098
4099 module_platform_driver(wm8994_codec_driver);
4100
4101 MODULE_DESCRIPTION("ASoC WM8994 driver");
4102 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4103 MODULE_LICENSE("GPL");
4104 MODULE_ALIAS("platform:wm8994-codec");