ASoC: Add WM8993 CODEC driver
[linux-2.6.git] / sound / soc / codecs / wm8993.h
1 #ifndef WM8993_H
2 #define WM8993_H
3
4 extern struct snd_soc_dai wm8993_dai;
5 extern struct snd_soc_codec_device soc_codec_dev_wm8993;
6
7 #define WM8993_SYSCLK_MCLK     1
8 #define WM8993_SYSCLK_FLL      2
9
10 #define WM8993_FLL_MCLK  1
11 #define WM8993_FLL_BCLK  2
12 #define WM8993_FLL_LRCLK 3
13
14 /*
15  * Register values.
16  */
17 #define WM8993_SOFTWARE_RESET                   0x00
18 #define WM8993_POWER_MANAGEMENT_1               0x01
19 #define WM8993_POWER_MANAGEMENT_2               0x02
20 #define WM8993_POWER_MANAGEMENT_3               0x03
21 #define WM8993_AUDIO_INTERFACE_1                0x04
22 #define WM8993_AUDIO_INTERFACE_2                0x05
23 #define WM8993_CLOCKING_1                       0x06
24 #define WM8993_CLOCKING_2                       0x07
25 #define WM8993_AUDIO_INTERFACE_3                0x08
26 #define WM8993_AUDIO_INTERFACE_4                0x09
27 #define WM8993_DAC_CTRL                         0x0A
28 #define WM8993_LEFT_DAC_DIGITAL_VOLUME          0x0B
29 #define WM8993_RIGHT_DAC_DIGITAL_VOLUME         0x0C
30 #define WM8993_DIGITAL_SIDE_TONE                0x0D
31 #define WM8993_ADC_CTRL                         0x0E
32 #define WM8993_LEFT_ADC_DIGITAL_VOLUME          0x0F
33 #define WM8993_RIGHT_ADC_DIGITAL_VOLUME         0x10
34 #define WM8993_GPIO_CTRL_1                      0x12
35 #define WM8993_GPIO1                            0x13
36 #define WM8993_IRQ_DEBOUNCE                     0x14
37 #define WM8993_GPIOCTRL_2                       0x16
38 #define WM8993_GPIO_POL                         0x17
39 #define WM8993_LEFT_LINE_INPUT_1_2_VOLUME       0x18
40 #define WM8993_LEFT_LINE_INPUT_3_4_VOLUME       0x19
41 #define WM8993_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
42 #define WM8993_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
43 #define WM8993_LEFT_OUTPUT_VOLUME               0x1C
44 #define WM8993_RIGHT_OUTPUT_VOLUME              0x1D
45 #define WM8993_LINE_OUTPUTS_VOLUME              0x1E
46 #define WM8993_HPOUT2_VOLUME                    0x1F
47 #define WM8993_LEFT_OPGA_VOLUME                 0x20
48 #define WM8993_RIGHT_OPGA_VOLUME                0x21
49 #define WM8993_SPKMIXL_ATTENUATION              0x22
50 #define WM8993_SPKMIXR_ATTENUATION              0x23
51 #define WM8993_SPKOUT_MIXERS                    0x24
52 #define WM8993_SPKOUT_BOOST                     0x25
53 #define WM8993_SPEAKER_VOLUME_LEFT              0x26
54 #define WM8993_SPEAKER_VOLUME_RIGHT             0x27
55 #define WM8993_INPUT_MIXER2                     0x28
56 #define WM8993_INPUT_MIXER3                     0x29
57 #define WM8993_INPUT_MIXER4                     0x2A
58 #define WM8993_INPUT_MIXER5                     0x2B
59 #define WM8993_INPUT_MIXER6                     0x2C
60 #define WM8993_OUTPUT_MIXER1                    0x2D
61 #define WM8993_OUTPUT_MIXER2                    0x2E
62 #define WM8993_OUTPUT_MIXER3                    0x2F
63 #define WM8993_OUTPUT_MIXER4                    0x30
64 #define WM8993_OUTPUT_MIXER5                    0x31
65 #define WM8993_OUTPUT_MIXER6                    0x32
66 #define WM8993_HPOUT2_MIXER                     0x33
67 #define WM8993_LINE_MIXER1                      0x34
68 #define WM8993_LINE_MIXER2                      0x35
69 #define WM8993_SPEAKER_MIXER                    0x36
70 #define WM8993_ADDITIONAL_CONTROL               0x37
71 #define WM8993_ANTIPOP1                         0x38
72 #define WM8993_ANTIPOP2                         0x39
73 #define WM8993_MICBIAS                          0x3A
74 #define WM8993_FLL_CONTROL_1                    0x3C
75 #define WM8993_FLL_CONTROL_2                    0x3D
76 #define WM8993_FLL_CONTROL_3                    0x3E
77 #define WM8993_FLL_CONTROL_4                    0x3F
78 #define WM8993_FLL_CONTROL_5                    0x40
79 #define WM8993_CLOCKING_3                       0x41
80 #define WM8993_CLOCKING_4                       0x42
81 #define WM8993_MW_SLAVE_CONTROL                 0x43
82 #define WM8993_BUS_CONTROL_1                    0x45
83 #define WM8993_WRITE_SEQUENCER_0                0x46
84 #define WM8993_WRITE_SEQUENCER_1                0x47
85 #define WM8993_WRITE_SEQUENCER_2                0x48
86 #define WM8993_WRITE_SEQUENCER_3                0x49
87 #define WM8993_WRITE_SEQUENCER_4                0x4A
88 #define WM8993_WRITE_SEQUENCER_5                0x4B
89 #define WM8993_CHARGE_PUMP_1                    0x4C
90 #define WM8993_CLASS_W_0                        0x51
91 #define WM8993_DC_SERVO_0                       0x54
92 #define WM8993_DC_SERVO_1                       0x55
93 #define WM8993_DC_SERVO_3                       0x57
94 #define WM8993_DC_SERVO_READBACK_0              0x58
95 #define WM8993_DC_SERVO_READBACK_1              0x59
96 #define WM8993_DC_SERVO_READBACK_2              0x5A
97 #define WM8993_ANALOGUE_HP_0                    0x60
98 #define WM8993_EQ1                              0x62
99 #define WM8993_EQ2                              0x63
100 #define WM8993_EQ3                              0x64
101 #define WM8993_EQ4                              0x65
102 #define WM8993_EQ5                              0x66
103 #define WM8993_EQ6                              0x67
104 #define WM8993_EQ7                              0x68
105 #define WM8993_EQ8                              0x69
106 #define WM8993_EQ9                              0x6A
107 #define WM8993_EQ10                             0x6B
108 #define WM8993_EQ11                             0x6C
109 #define WM8993_EQ12                             0x6D
110 #define WM8993_EQ13                             0x6E
111 #define WM8993_EQ14                             0x6F
112 #define WM8993_EQ15                             0x70
113 #define WM8993_EQ16                             0x71
114 #define WM8993_EQ17                             0x72
115 #define WM8993_EQ18                             0x73
116 #define WM8993_EQ19                             0x74
117 #define WM8993_EQ20                             0x75
118 #define WM8993_EQ21                             0x76
119 #define WM8993_EQ22                             0x77
120 #define WM8993_EQ23                             0x78
121 #define WM8993_EQ24                             0x79
122 #define WM8993_DIGITAL_PULLS                    0x7A
123 #define WM8993_DRC_CONTROL_1                    0x7B
124 #define WM8993_DRC_CONTROL_2                    0x7C
125 #define WM8993_DRC_CONTROL_3                    0x7D
126 #define WM8993_DRC_CONTROL_4                    0x7E
127
128 #define WM8993_REGISTER_COUNT                   0x7F
129 #define WM8993_MAX_REGISTER                     0x7E
130
131 /*
132  * Field Definitions.
133  */
134
135 /*
136  * R0 (0x00) - Software Reset
137  */
138 #define WM8993_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
139 #define WM8993_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
140 #define WM8993_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
141
142 /*
143  * R1 (0x01) - Power Management (1)
144  */
145 #define WM8993_SPKOUTR_ENA                      0x2000  /* SPKOUTR_ENA */
146 #define WM8993_SPKOUTR_ENA_MASK                 0x2000  /* SPKOUTR_ENA */
147 #define WM8993_SPKOUTR_ENA_SHIFT                    13  /* SPKOUTR_ENA */
148 #define WM8993_SPKOUTR_ENA_WIDTH                     1  /* SPKOUTR_ENA */
149 #define WM8993_SPKOUTL_ENA                      0x1000  /* SPKOUTL_ENA */
150 #define WM8993_SPKOUTL_ENA_MASK                 0x1000  /* SPKOUTL_ENA */
151 #define WM8993_SPKOUTL_ENA_SHIFT                    12  /* SPKOUTL_ENA */
152 #define WM8993_SPKOUTL_ENA_WIDTH                     1  /* SPKOUTL_ENA */
153 #define WM8993_HPOUT2_ENA                       0x0800  /* HPOUT2_ENA */
154 #define WM8993_HPOUT2_ENA_MASK                  0x0800  /* HPOUT2_ENA */
155 #define WM8993_HPOUT2_ENA_SHIFT                     11  /* HPOUT2_ENA */
156 #define WM8993_HPOUT2_ENA_WIDTH                      1  /* HPOUT2_ENA */
157 #define WM8993_HPOUT1L_ENA                      0x0200  /* HPOUT1L_ENA */
158 #define WM8993_HPOUT1L_ENA_MASK                 0x0200  /* HPOUT1L_ENA */
159 #define WM8993_HPOUT1L_ENA_SHIFT                     9  /* HPOUT1L_ENA */
160 #define WM8993_HPOUT1L_ENA_WIDTH                     1  /* HPOUT1L_ENA */
161 #define WM8993_HPOUT1R_ENA                      0x0100  /* HPOUT1R_ENA */
162 #define WM8993_HPOUT1R_ENA_MASK                 0x0100  /* HPOUT1R_ENA */
163 #define WM8993_HPOUT1R_ENA_SHIFT                     8  /* HPOUT1R_ENA */
164 #define WM8993_HPOUT1R_ENA_WIDTH                     1  /* HPOUT1R_ENA */
165 #define WM8993_MICB2_ENA                        0x0020  /* MICB2_ENA */
166 #define WM8993_MICB2_ENA_MASK                   0x0020  /* MICB2_ENA */
167 #define WM8993_MICB2_ENA_SHIFT                       5  /* MICB2_ENA */
168 #define WM8993_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
169 #define WM8993_MICB1_ENA                        0x0010  /* MICB1_ENA */
170 #define WM8993_MICB1_ENA_MASK                   0x0010  /* MICB1_ENA */
171 #define WM8993_MICB1_ENA_SHIFT                       4  /* MICB1_ENA */
172 #define WM8993_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
173 #define WM8993_VMID_SEL_MASK                    0x0006  /* VMID_SEL - [2:1] */
174 #define WM8993_VMID_SEL_SHIFT                        1  /* VMID_SEL - [2:1] */
175 #define WM8993_VMID_SEL_WIDTH                        2  /* VMID_SEL - [2:1] */
176 #define WM8993_BIAS_ENA                         0x0001  /* BIAS_ENA */
177 #define WM8993_BIAS_ENA_MASK                    0x0001  /* BIAS_ENA */
178 #define WM8993_BIAS_ENA_SHIFT                        0  /* BIAS_ENA */
179 #define WM8993_BIAS_ENA_WIDTH                        1  /* BIAS_ENA */
180
181 /*
182  * R2 (0x02) - Power Management (2)
183  */
184 #define WM8993_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
185 #define WM8993_TSHUT_ENA_MASK                   0x4000  /* TSHUT_ENA */
186 #define WM8993_TSHUT_ENA_SHIFT                      14  /* TSHUT_ENA */
187 #define WM8993_TSHUT_ENA_WIDTH                       1  /* TSHUT_ENA */
188 #define WM8993_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
189 #define WM8993_TSHUT_OPDIS_MASK                 0x2000  /* TSHUT_OPDIS */
190 #define WM8993_TSHUT_OPDIS_SHIFT                    13  /* TSHUT_OPDIS */
191 #define WM8993_TSHUT_OPDIS_WIDTH                     1  /* TSHUT_OPDIS */
192 #define WM8993_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
193 #define WM8993_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
194 #define WM8993_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
195 #define WM8993_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
196 #define WM8993_MIXINL_ENA                       0x0200  /* MIXINL_ENA */
197 #define WM8993_MIXINL_ENA_MASK                  0x0200  /* MIXINL_ENA */
198 #define WM8993_MIXINL_ENA_SHIFT                      9  /* MIXINL_ENA */
199 #define WM8993_MIXINL_ENA_WIDTH                      1  /* MIXINL_ENA */
200 #define WM8993_MIXINR_ENA                       0x0100  /* MIXINR_ENA */
201 #define WM8993_MIXINR_ENA_MASK                  0x0100  /* MIXINR_ENA */
202 #define WM8993_MIXINR_ENA_SHIFT                      8  /* MIXINR_ENA */
203 #define WM8993_MIXINR_ENA_WIDTH                      1  /* MIXINR_ENA */
204 #define WM8993_IN2L_ENA                         0x0080  /* IN2L_ENA */
205 #define WM8993_IN2L_ENA_MASK                    0x0080  /* IN2L_ENA */
206 #define WM8993_IN2L_ENA_SHIFT                        7  /* IN2L_ENA */
207 #define WM8993_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
208 #define WM8993_IN1L_ENA                         0x0040  /* IN1L_ENA */
209 #define WM8993_IN1L_ENA_MASK                    0x0040  /* IN1L_ENA */
210 #define WM8993_IN1L_ENA_SHIFT                        6  /* IN1L_ENA */
211 #define WM8993_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
212 #define WM8993_IN2R_ENA                         0x0020  /* IN2R_ENA */
213 #define WM8993_IN2R_ENA_MASK                    0x0020  /* IN2R_ENA */
214 #define WM8993_IN2R_ENA_SHIFT                        5  /* IN2R_ENA */
215 #define WM8993_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
216 #define WM8993_IN1R_ENA                         0x0010  /* IN1R_ENA */
217 #define WM8993_IN1R_ENA_MASK                    0x0010  /* IN1R_ENA */
218 #define WM8993_IN1R_ENA_SHIFT                        4  /* IN1R_ENA */
219 #define WM8993_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
220 #define WM8993_ADCL_ENA                         0x0002  /* ADCL_ENA */
221 #define WM8993_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
222 #define WM8993_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
223 #define WM8993_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
224 #define WM8993_ADCR_ENA                         0x0001  /* ADCR_ENA */
225 #define WM8993_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
226 #define WM8993_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
227 #define WM8993_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
228
229 /*
230  * R3 (0x03) - Power Management (3)
231  */
232 #define WM8993_LINEOUT1N_ENA                    0x2000  /* LINEOUT1N_ENA */
233 #define WM8993_LINEOUT1N_ENA_MASK               0x2000  /* LINEOUT1N_ENA */
234 #define WM8993_LINEOUT1N_ENA_SHIFT                  13  /* LINEOUT1N_ENA */
235 #define WM8993_LINEOUT1N_ENA_WIDTH                   1  /* LINEOUT1N_ENA */
236 #define WM8993_LINEOUT1P_ENA                    0x1000  /* LINEOUT1P_ENA */
237 #define WM8993_LINEOUT1P_ENA_MASK               0x1000  /* LINEOUT1P_ENA */
238 #define WM8993_LINEOUT1P_ENA_SHIFT                  12  /* LINEOUT1P_ENA */
239 #define WM8993_LINEOUT1P_ENA_WIDTH                   1  /* LINEOUT1P_ENA */
240 #define WM8993_LINEOUT2N_ENA                    0x0800  /* LINEOUT2N_ENA */
241 #define WM8993_LINEOUT2N_ENA_MASK               0x0800  /* LINEOUT2N_ENA */
242 #define WM8993_LINEOUT2N_ENA_SHIFT                  11  /* LINEOUT2N_ENA */
243 #define WM8993_LINEOUT2N_ENA_WIDTH                   1  /* LINEOUT2N_ENA */
244 #define WM8993_LINEOUT2P_ENA                    0x0400  /* LINEOUT2P_ENA */
245 #define WM8993_LINEOUT2P_ENA_MASK               0x0400  /* LINEOUT2P_ENA */
246 #define WM8993_LINEOUT2P_ENA_SHIFT                  10  /* LINEOUT2P_ENA */
247 #define WM8993_LINEOUT2P_ENA_WIDTH                   1  /* LINEOUT2P_ENA */
248 #define WM8993_SPKRVOL_ENA                      0x0200  /* SPKRVOL_ENA */
249 #define WM8993_SPKRVOL_ENA_MASK                 0x0200  /* SPKRVOL_ENA */
250 #define WM8993_SPKRVOL_ENA_SHIFT                     9  /* SPKRVOL_ENA */
251 #define WM8993_SPKRVOL_ENA_WIDTH                     1  /* SPKRVOL_ENA */
252 #define WM8993_SPKLVOL_ENA                      0x0100  /* SPKLVOL_ENA */
253 #define WM8993_SPKLVOL_ENA_MASK                 0x0100  /* SPKLVOL_ENA */
254 #define WM8993_SPKLVOL_ENA_SHIFT                     8  /* SPKLVOL_ENA */
255 #define WM8993_SPKLVOL_ENA_WIDTH                     1  /* SPKLVOL_ENA */
256 #define WM8993_MIXOUTLVOL_ENA                   0x0080  /* MIXOUTLVOL_ENA */
257 #define WM8993_MIXOUTLVOL_ENA_MASK              0x0080  /* MIXOUTLVOL_ENA */
258 #define WM8993_MIXOUTLVOL_ENA_SHIFT                  7  /* MIXOUTLVOL_ENA */
259 #define WM8993_MIXOUTLVOL_ENA_WIDTH                  1  /* MIXOUTLVOL_ENA */
260 #define WM8993_MIXOUTRVOL_ENA                   0x0040  /* MIXOUTRVOL_ENA */
261 #define WM8993_MIXOUTRVOL_ENA_MASK              0x0040  /* MIXOUTRVOL_ENA */
262 #define WM8993_MIXOUTRVOL_ENA_SHIFT                  6  /* MIXOUTRVOL_ENA */
263 #define WM8993_MIXOUTRVOL_ENA_WIDTH                  1  /* MIXOUTRVOL_ENA */
264 #define WM8993_MIXOUTL_ENA                      0x0020  /* MIXOUTL_ENA */
265 #define WM8993_MIXOUTL_ENA_MASK                 0x0020  /* MIXOUTL_ENA */
266 #define WM8993_MIXOUTL_ENA_SHIFT                     5  /* MIXOUTL_ENA */
267 #define WM8993_MIXOUTL_ENA_WIDTH                     1  /* MIXOUTL_ENA */
268 #define WM8993_MIXOUTR_ENA                      0x0010  /* MIXOUTR_ENA */
269 #define WM8993_MIXOUTR_ENA_MASK                 0x0010  /* MIXOUTR_ENA */
270 #define WM8993_MIXOUTR_ENA_SHIFT                     4  /* MIXOUTR_ENA */
271 #define WM8993_MIXOUTR_ENA_WIDTH                     1  /* MIXOUTR_ENA */
272 #define WM8993_DACL_ENA                         0x0002  /* DACL_ENA */
273 #define WM8993_DACL_ENA_MASK                    0x0002  /* DACL_ENA */
274 #define WM8993_DACL_ENA_SHIFT                        1  /* DACL_ENA */
275 #define WM8993_DACL_ENA_WIDTH                        1  /* DACL_ENA */
276 #define WM8993_DACR_ENA                         0x0001  /* DACR_ENA */
277 #define WM8993_DACR_ENA_MASK                    0x0001  /* DACR_ENA */
278 #define WM8993_DACR_ENA_SHIFT                        0  /* DACR_ENA */
279 #define WM8993_DACR_ENA_WIDTH                        1  /* DACR_ENA */
280
281 /*
282  * R4 (0x04) - Audio Interface (1)
283  */
284 #define WM8993_AIFADCL_SRC                      0x8000  /* AIFADCL_SRC */
285 #define WM8993_AIFADCL_SRC_MASK                 0x8000  /* AIFADCL_SRC */
286 #define WM8993_AIFADCL_SRC_SHIFT                    15  /* AIFADCL_SRC */
287 #define WM8993_AIFADCL_SRC_WIDTH                     1  /* AIFADCL_SRC */
288 #define WM8993_AIFADCR_SRC                      0x4000  /* AIFADCR_SRC */
289 #define WM8993_AIFADCR_SRC_MASK                 0x4000  /* AIFADCR_SRC */
290 #define WM8993_AIFADCR_SRC_SHIFT                    14  /* AIFADCR_SRC */
291 #define WM8993_AIFADCR_SRC_WIDTH                     1  /* AIFADCR_SRC */
292 #define WM8993_AIFADC_TDM                       0x2000  /* AIFADC_TDM */
293 #define WM8993_AIFADC_TDM_MASK                  0x2000  /* AIFADC_TDM */
294 #define WM8993_AIFADC_TDM_SHIFT                     13  /* AIFADC_TDM */
295 #define WM8993_AIFADC_TDM_WIDTH                      1  /* AIFADC_TDM */
296 #define WM8993_AIFADC_TDM_CHAN                  0x1000  /* AIFADC_TDM_CHAN */
297 #define WM8993_AIFADC_TDM_CHAN_MASK             0x1000  /* AIFADC_TDM_CHAN */
298 #define WM8993_AIFADC_TDM_CHAN_SHIFT                12  /* AIFADC_TDM_CHAN */
299 #define WM8993_AIFADC_TDM_CHAN_WIDTH                 1  /* AIFADC_TDM_CHAN */
300 #define WM8993_BCLK_DIR                         0x0200  /* BCLK_DIR */
301 #define WM8993_BCLK_DIR_MASK                    0x0200  /* BCLK_DIR */
302 #define WM8993_BCLK_DIR_SHIFT                        9  /* BCLK_DIR */
303 #define WM8993_BCLK_DIR_WIDTH                        1  /* BCLK_DIR */
304 #define WM8993_AIF_BCLK_INV                     0x0100  /* AIF_BCLK_INV */
305 #define WM8993_AIF_BCLK_INV_MASK                0x0100  /* AIF_BCLK_INV */
306 #define WM8993_AIF_BCLK_INV_SHIFT                    8  /* AIF_BCLK_INV */
307 #define WM8993_AIF_BCLK_INV_WIDTH                    1  /* AIF_BCLK_INV */
308 #define WM8993_AIF_LRCLK_INV                    0x0080  /* AIF_LRCLK_INV */
309 #define WM8993_AIF_LRCLK_INV_MASK               0x0080  /* AIF_LRCLK_INV */
310 #define WM8993_AIF_LRCLK_INV_SHIFT                   7  /* AIF_LRCLK_INV */
311 #define WM8993_AIF_LRCLK_INV_WIDTH                   1  /* AIF_LRCLK_INV */
312 #define WM8993_AIF_WL_MASK                      0x0060  /* AIF_WL - [6:5] */
313 #define WM8993_AIF_WL_SHIFT                          5  /* AIF_WL - [6:5] */
314 #define WM8993_AIF_WL_WIDTH                          2  /* AIF_WL - [6:5] */
315 #define WM8993_AIF_FMT_MASK                     0x0018  /* AIF_FMT - [4:3] */
316 #define WM8993_AIF_FMT_SHIFT                         3  /* AIF_FMT - [4:3] */
317 #define WM8993_AIF_FMT_WIDTH                         2  /* AIF_FMT - [4:3] */
318
319 /*
320  * R5 (0x05) - Audio Interface (2)
321  */
322 #define WM8993_AIFDACL_SRC                      0x8000  /* AIFDACL_SRC */
323 #define WM8993_AIFDACL_SRC_MASK                 0x8000  /* AIFDACL_SRC */
324 #define WM8993_AIFDACL_SRC_SHIFT                    15  /* AIFDACL_SRC */
325 #define WM8993_AIFDACL_SRC_WIDTH                     1  /* AIFDACL_SRC */
326 #define WM8993_AIFDACR_SRC                      0x4000  /* AIFDACR_SRC */
327 #define WM8993_AIFDACR_SRC_MASK                 0x4000  /* AIFDACR_SRC */
328 #define WM8993_AIFDACR_SRC_SHIFT                    14  /* AIFDACR_SRC */
329 #define WM8993_AIFDACR_SRC_WIDTH                     1  /* AIFDACR_SRC */
330 #define WM8993_AIFDAC_TDM                       0x2000  /* AIFDAC_TDM */
331 #define WM8993_AIFDAC_TDM_MASK                  0x2000  /* AIFDAC_TDM */
332 #define WM8993_AIFDAC_TDM_SHIFT                     13  /* AIFDAC_TDM */
333 #define WM8993_AIFDAC_TDM_WIDTH                      1  /* AIFDAC_TDM */
334 #define WM8993_AIFDAC_TDM_CHAN                  0x1000  /* AIFDAC_TDM_CHAN */
335 #define WM8993_AIFDAC_TDM_CHAN_MASK             0x1000  /* AIFDAC_TDM_CHAN */
336 #define WM8993_AIFDAC_TDM_CHAN_SHIFT                12  /* AIFDAC_TDM_CHAN */
337 #define WM8993_AIFDAC_TDM_CHAN_WIDTH                 1  /* AIFDAC_TDM_CHAN */
338 #define WM8993_DAC_BOOST_MASK                   0x0C00  /* DAC_BOOST - [11:10] */
339 #define WM8993_DAC_BOOST_SHIFT                      10  /* DAC_BOOST - [11:10] */
340 #define WM8993_DAC_BOOST_WIDTH                       2  /* DAC_BOOST - [11:10] */
341 #define WM8993_DAC_COMP                         0x0010  /* DAC_COMP */
342 #define WM8993_DAC_COMP_MASK                    0x0010  /* DAC_COMP */
343 #define WM8993_DAC_COMP_SHIFT                        4  /* DAC_COMP */
344 #define WM8993_DAC_COMP_WIDTH                        1  /* DAC_COMP */
345 #define WM8993_DAC_COMPMODE                     0x0008  /* DAC_COMPMODE */
346 #define WM8993_DAC_COMPMODE_MASK                0x0008  /* DAC_COMPMODE */
347 #define WM8993_DAC_COMPMODE_SHIFT                    3  /* DAC_COMPMODE */
348 #define WM8993_DAC_COMPMODE_WIDTH                    1  /* DAC_COMPMODE */
349 #define WM8993_ADC_COMP                         0x0004  /* ADC_COMP */
350 #define WM8993_ADC_COMP_MASK                    0x0004  /* ADC_COMP */
351 #define WM8993_ADC_COMP_SHIFT                        2  /* ADC_COMP */
352 #define WM8993_ADC_COMP_WIDTH                        1  /* ADC_COMP */
353 #define WM8993_ADC_COMPMODE                     0x0002  /* ADC_COMPMODE */
354 #define WM8993_ADC_COMPMODE_MASK                0x0002  /* ADC_COMPMODE */
355 #define WM8993_ADC_COMPMODE_SHIFT                    1  /* ADC_COMPMODE */
356 #define WM8993_ADC_COMPMODE_WIDTH                    1  /* ADC_COMPMODE */
357 #define WM8993_LOOPBACK                         0x0001  /* LOOPBACK */
358 #define WM8993_LOOPBACK_MASK                    0x0001  /* LOOPBACK */
359 #define WM8993_LOOPBACK_SHIFT                        0  /* LOOPBACK */
360 #define WM8993_LOOPBACK_WIDTH                        1  /* LOOPBACK */
361
362 /*
363  * R6 (0x06) - Clocking 1
364  */
365 #define WM8993_TOCLK_RATE                       0x8000  /* TOCLK_RATE */
366 #define WM8993_TOCLK_RATE_MASK                  0x8000  /* TOCLK_RATE */
367 #define WM8993_TOCLK_RATE_SHIFT                     15  /* TOCLK_RATE */
368 #define WM8993_TOCLK_RATE_WIDTH                      1  /* TOCLK_RATE */
369 #define WM8993_TOCLK_ENA                        0x4000  /* TOCLK_ENA */
370 #define WM8993_TOCLK_ENA_MASK                   0x4000  /* TOCLK_ENA */
371 #define WM8993_TOCLK_ENA_SHIFT                      14  /* TOCLK_ENA */
372 #define WM8993_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
373 #define WM8993_OPCLK_DIV_MASK                   0x1E00  /* OPCLK_DIV - [12:9] */
374 #define WM8993_OPCLK_DIV_SHIFT                       9  /* OPCLK_DIV - [12:9] */
375 #define WM8993_OPCLK_DIV_WIDTH                       4  /* OPCLK_DIV - [12:9] */
376 #define WM8993_DCLK_DIV_MASK                    0x01C0  /* DCLK_DIV - [8:6] */
377 #define WM8993_DCLK_DIV_SHIFT                        6  /* DCLK_DIV - [8:6] */
378 #define WM8993_DCLK_DIV_WIDTH                        3  /* DCLK_DIV - [8:6] */
379 #define WM8993_BCLK_DIV_MASK                    0x001E  /* BCLK_DIV - [4:1] */
380 #define WM8993_BCLK_DIV_SHIFT                        1  /* BCLK_DIV - [4:1] */
381 #define WM8993_BCLK_DIV_WIDTH                        4  /* BCLK_DIV - [4:1] */
382
383 /*
384  * R7 (0x07) - Clocking 2
385  */
386 #define WM8993_MCLK_SRC                         0x8000  /* MCLK_SRC */
387 #define WM8993_MCLK_SRC_MASK                    0x8000  /* MCLK_SRC */
388 #define WM8993_MCLK_SRC_SHIFT                       15  /* MCLK_SRC */
389 #define WM8993_MCLK_SRC_WIDTH                        1  /* MCLK_SRC */
390 #define WM8993_SYSCLK_SRC                       0x4000  /* SYSCLK_SRC */
391 #define WM8993_SYSCLK_SRC_MASK                  0x4000  /* SYSCLK_SRC */
392 #define WM8993_SYSCLK_SRC_SHIFT                     14  /* SYSCLK_SRC */
393 #define WM8993_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
394 #define WM8993_MCLK_DIV                         0x1000  /* MCLK_DIV */
395 #define WM8993_MCLK_DIV_MASK                    0x1000  /* MCLK_DIV */
396 #define WM8993_MCLK_DIV_SHIFT                       12  /* MCLK_DIV */
397 #define WM8993_MCLK_DIV_WIDTH                        1  /* MCLK_DIV */
398 #define WM8993_MCLK_INV                         0x0400  /* MCLK_INV */
399 #define WM8993_MCLK_INV_MASK                    0x0400  /* MCLK_INV */
400 #define WM8993_MCLK_INV_SHIFT                       10  /* MCLK_INV */
401 #define WM8993_MCLK_INV_WIDTH                        1  /* MCLK_INV */
402 #define WM8993_ADC_DIV_MASK                     0x00E0  /* ADC_DIV - [7:5] */
403 #define WM8993_ADC_DIV_SHIFT                         5  /* ADC_DIV - [7:5] */
404 #define WM8993_ADC_DIV_WIDTH                         3  /* ADC_DIV - [7:5] */
405 #define WM8993_DAC_DIV_MASK                     0x001C  /* DAC_DIV - [4:2] */
406 #define WM8993_DAC_DIV_SHIFT                         2  /* DAC_DIV - [4:2] */
407 #define WM8993_DAC_DIV_WIDTH                         3  /* DAC_DIV - [4:2] */
408
409 /*
410  * R8 (0x08) - Audio Interface (3)
411  */
412 #define WM8993_AIF_MSTR1                        0x8000  /* AIF_MSTR1 */
413 #define WM8993_AIF_MSTR1_MASK                   0x8000  /* AIF_MSTR1 */
414 #define WM8993_AIF_MSTR1_SHIFT                      15  /* AIF_MSTR1 */
415 #define WM8993_AIF_MSTR1_WIDTH                       1  /* AIF_MSTR1 */
416
417 /*
418  * R9 (0x09) - Audio Interface (4)
419  */
420 #define WM8993_AIF_TRIS                         0x2000  /* AIF_TRIS */
421 #define WM8993_AIF_TRIS_MASK                    0x2000  /* AIF_TRIS */
422 #define WM8993_AIF_TRIS_SHIFT                       13  /* AIF_TRIS */
423 #define WM8993_AIF_TRIS_WIDTH                        1  /* AIF_TRIS */
424 #define WM8993_LRCLK_DIR                        0x0800  /* LRCLK_DIR */
425 #define WM8993_LRCLK_DIR_MASK                   0x0800  /* LRCLK_DIR */
426 #define WM8993_LRCLK_DIR_SHIFT                      11  /* LRCLK_DIR */
427 #define WM8993_LRCLK_DIR_WIDTH                       1  /* LRCLK_DIR */
428 #define WM8993_LRCLK_RATE_MASK                  0x07FF  /* LRCLK_RATE - [10:0] */
429 #define WM8993_LRCLK_RATE_SHIFT                      0  /* LRCLK_RATE - [10:0] */
430 #define WM8993_LRCLK_RATE_WIDTH                     11  /* LRCLK_RATE - [10:0] */
431
432 /*
433  * R10 (0x0A) - DAC CTRL
434  */
435 #define WM8993_DAC_OSR128                       0x2000  /* DAC_OSR128 */
436 #define WM8993_DAC_OSR128_MASK                  0x2000  /* DAC_OSR128 */
437 #define WM8993_DAC_OSR128_SHIFT                     13  /* DAC_OSR128 */
438 #define WM8993_DAC_OSR128_WIDTH                      1  /* DAC_OSR128 */
439 #define WM8993_DAC_MONO                         0x0200  /* DAC_MONO */
440 #define WM8993_DAC_MONO_MASK                    0x0200  /* DAC_MONO */
441 #define WM8993_DAC_MONO_SHIFT                        9  /* DAC_MONO */
442 #define WM8993_DAC_MONO_WIDTH                        1  /* DAC_MONO */
443 #define WM8993_DAC_SB_FILT                      0x0100  /* DAC_SB_FILT */
444 #define WM8993_DAC_SB_FILT_MASK                 0x0100  /* DAC_SB_FILT */
445 #define WM8993_DAC_SB_FILT_SHIFT                     8  /* DAC_SB_FILT */
446 #define WM8993_DAC_SB_FILT_WIDTH                     1  /* DAC_SB_FILT */
447 #define WM8993_DAC_MUTERATE                     0x0080  /* DAC_MUTERATE */
448 #define WM8993_DAC_MUTERATE_MASK                0x0080  /* DAC_MUTERATE */
449 #define WM8993_DAC_MUTERATE_SHIFT                    7  /* DAC_MUTERATE */
450 #define WM8993_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
451 #define WM8993_DAC_UNMUTE_RAMP                  0x0040  /* DAC_UNMUTE_RAMP */
452 #define WM8993_DAC_UNMUTE_RAMP_MASK             0x0040  /* DAC_UNMUTE_RAMP */
453 #define WM8993_DAC_UNMUTE_RAMP_SHIFT                 6  /* DAC_UNMUTE_RAMP */
454 #define WM8993_DAC_UNMUTE_RAMP_WIDTH                 1  /* DAC_UNMUTE_RAMP */
455 #define WM8993_DEEMPH_MASK                      0x0030  /* DEEMPH - [5:4] */
456 #define WM8993_DEEMPH_SHIFT                          4  /* DEEMPH - [5:4] */
457 #define WM8993_DEEMPH_WIDTH                          2  /* DEEMPH - [5:4] */
458 #define WM8993_DAC_MUTE                         0x0004  /* DAC_MUTE */
459 #define WM8993_DAC_MUTE_MASK                    0x0004  /* DAC_MUTE */
460 #define WM8993_DAC_MUTE_SHIFT                        2  /* DAC_MUTE */
461 #define WM8993_DAC_MUTE_WIDTH                        1  /* DAC_MUTE */
462 #define WM8993_DACL_DATINV                      0x0002  /* DACL_DATINV */
463 #define WM8993_DACL_DATINV_MASK                 0x0002  /* DACL_DATINV */
464 #define WM8993_DACL_DATINV_SHIFT                     1  /* DACL_DATINV */
465 #define WM8993_DACL_DATINV_WIDTH                     1  /* DACL_DATINV */
466 #define WM8993_DACR_DATINV                      0x0001  /* DACR_DATINV */
467 #define WM8993_DACR_DATINV_MASK                 0x0001  /* DACR_DATINV */
468 #define WM8993_DACR_DATINV_SHIFT                     0  /* DACR_DATINV */
469 #define WM8993_DACR_DATINV_WIDTH                     1  /* DACR_DATINV */
470
471 /*
472  * R11 (0x0B) - Left DAC Digital Volume
473  */
474 #define WM8993_DAC_VU                           0x0100  /* DAC_VU */
475 #define WM8993_DAC_VU_MASK                      0x0100  /* DAC_VU */
476 #define WM8993_DAC_VU_SHIFT                          8  /* DAC_VU */
477 #define WM8993_DAC_VU_WIDTH                          1  /* DAC_VU */
478 #define WM8993_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
479 #define WM8993_DACL_VOL_SHIFT                        0  /* DACL_VOL - [7:0] */
480 #define WM8993_DACL_VOL_WIDTH                        8  /* DACL_VOL - [7:0] */
481
482 /*
483  * R12 (0x0C) - Right DAC Digital Volume
484  */
485 #define WM8993_DAC_VU                           0x0100  /* DAC_VU */
486 #define WM8993_DAC_VU_MASK                      0x0100  /* DAC_VU */
487 #define WM8993_DAC_VU_SHIFT                          8  /* DAC_VU */
488 #define WM8993_DAC_VU_WIDTH                          1  /* DAC_VU */
489 #define WM8993_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
490 #define WM8993_DACR_VOL_SHIFT                        0  /* DACR_VOL - [7:0] */
491 #define WM8993_DACR_VOL_WIDTH                        8  /* DACR_VOL - [7:0] */
492
493 /*
494  * R13 (0x0D) - Digital Side Tone
495  */
496 #define WM8993_ADCL_DAC_SVOL_MASK               0x1E00  /* ADCL_DAC_SVOL - [12:9] */
497 #define WM8993_ADCL_DAC_SVOL_SHIFT                   9  /* ADCL_DAC_SVOL - [12:9] */
498 #define WM8993_ADCL_DAC_SVOL_WIDTH                   4  /* ADCL_DAC_SVOL - [12:9] */
499 #define WM8993_ADCR_DAC_SVOL_MASK               0x01E0  /* ADCR_DAC_SVOL - [8:5] */
500 #define WM8993_ADCR_DAC_SVOL_SHIFT                   5  /* ADCR_DAC_SVOL - [8:5] */
501 #define WM8993_ADCR_DAC_SVOL_WIDTH                   4  /* ADCR_DAC_SVOL - [8:5] */
502 #define WM8993_ADC_TO_DACL_MASK                 0x000C  /* ADC_TO_DACL - [3:2] */
503 #define WM8993_ADC_TO_DACL_SHIFT                     2  /* ADC_TO_DACL - [3:2] */
504 #define WM8993_ADC_TO_DACL_WIDTH                     2  /* ADC_TO_DACL - [3:2] */
505 #define WM8993_ADC_TO_DACR_MASK                 0x0003  /* ADC_TO_DACR - [1:0] */
506 #define WM8993_ADC_TO_DACR_SHIFT                     0  /* ADC_TO_DACR - [1:0] */
507 #define WM8993_ADC_TO_DACR_WIDTH                     2  /* ADC_TO_DACR - [1:0] */
508
509 /*
510  * R14 (0x0E) - ADC CTRL
511  */
512 #define WM8993_ADC_OSR128                       0x0200  /* ADC_OSR128 */
513 #define WM8993_ADC_OSR128_MASK                  0x0200  /* ADC_OSR128 */
514 #define WM8993_ADC_OSR128_SHIFT                      9  /* ADC_OSR128 */
515 #define WM8993_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
516 #define WM8993_ADC_HPF                          0x0100  /* ADC_HPF */
517 #define WM8993_ADC_HPF_MASK                     0x0100  /* ADC_HPF */
518 #define WM8993_ADC_HPF_SHIFT                         8  /* ADC_HPF */
519 #define WM8993_ADC_HPF_WIDTH                         1  /* ADC_HPF */
520 #define WM8993_ADC_HPF_CUT_MASK                 0x0060  /* ADC_HPF_CUT - [6:5] */
521 #define WM8993_ADC_HPF_CUT_SHIFT                     5  /* ADC_HPF_CUT - [6:5] */
522 #define WM8993_ADC_HPF_CUT_WIDTH                     2  /* ADC_HPF_CUT - [6:5] */
523 #define WM8993_ADCL_DATINV                      0x0002  /* ADCL_DATINV */
524 #define WM8993_ADCL_DATINV_MASK                 0x0002  /* ADCL_DATINV */
525 #define WM8993_ADCL_DATINV_SHIFT                     1  /* ADCL_DATINV */
526 #define WM8993_ADCL_DATINV_WIDTH                     1  /* ADCL_DATINV */
527 #define WM8993_ADCR_DATINV                      0x0001  /* ADCR_DATINV */
528 #define WM8993_ADCR_DATINV_MASK                 0x0001  /* ADCR_DATINV */
529 #define WM8993_ADCR_DATINV_SHIFT                     0  /* ADCR_DATINV */
530 #define WM8993_ADCR_DATINV_WIDTH                     1  /* ADCR_DATINV */
531
532 /*
533  * R15 (0x0F) - Left ADC Digital Volume
534  */
535 #define WM8993_ADC_VU                           0x0100  /* ADC_VU */
536 #define WM8993_ADC_VU_MASK                      0x0100  /* ADC_VU */
537 #define WM8993_ADC_VU_SHIFT                          8  /* ADC_VU */
538 #define WM8993_ADC_VU_WIDTH                          1  /* ADC_VU */
539 #define WM8993_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
540 #define WM8993_ADCL_VOL_SHIFT                        0  /* ADCL_VOL - [7:0] */
541 #define WM8993_ADCL_VOL_WIDTH                        8  /* ADCL_VOL - [7:0] */
542
543 /*
544  * R16 (0x10) - Right ADC Digital Volume
545  */
546 #define WM8993_ADC_VU                           0x0100  /* ADC_VU */
547 #define WM8993_ADC_VU_MASK                      0x0100  /* ADC_VU */
548 #define WM8993_ADC_VU_SHIFT                          8  /* ADC_VU */
549 #define WM8993_ADC_VU_WIDTH                          1  /* ADC_VU */
550 #define WM8993_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
551 #define WM8993_ADCR_VOL_SHIFT                        0  /* ADCR_VOL - [7:0] */
552 #define WM8993_ADCR_VOL_WIDTH                        8  /* ADCR_VOL - [7:0] */
553
554 /*
555  * R18 (0x12) - GPIO CTRL 1
556  */
557 #define WM8993_JD2_SC_EINT                      0x8000  /* JD2_SC_EINT */
558 #define WM8993_JD2_SC_EINT_MASK                 0x8000  /* JD2_SC_EINT */
559 #define WM8993_JD2_SC_EINT_SHIFT                    15  /* JD2_SC_EINT */
560 #define WM8993_JD2_SC_EINT_WIDTH                     1  /* JD2_SC_EINT */
561 #define WM8993_JD2_EINT                         0x4000  /* JD2_EINT */
562 #define WM8993_JD2_EINT_MASK                    0x4000  /* JD2_EINT */
563 #define WM8993_JD2_EINT_SHIFT                       14  /* JD2_EINT */
564 #define WM8993_JD2_EINT_WIDTH                        1  /* JD2_EINT */
565 #define WM8993_WSEQ_EINT                        0x2000  /* WSEQ_EINT */
566 #define WM8993_WSEQ_EINT_MASK                   0x2000  /* WSEQ_EINT */
567 #define WM8993_WSEQ_EINT_SHIFT                      13  /* WSEQ_EINT */
568 #define WM8993_WSEQ_EINT_WIDTH                       1  /* WSEQ_EINT */
569 #define WM8993_IRQ                              0x1000  /* IRQ */
570 #define WM8993_IRQ_MASK                         0x1000  /* IRQ */
571 #define WM8993_IRQ_SHIFT                            12  /* IRQ */
572 #define WM8993_IRQ_WIDTH                             1  /* IRQ */
573 #define WM8993_TEMPOK_EINT                      0x0800  /* TEMPOK_EINT */
574 #define WM8993_TEMPOK_EINT_MASK                 0x0800  /* TEMPOK_EINT */
575 #define WM8993_TEMPOK_EINT_SHIFT                    11  /* TEMPOK_EINT */
576 #define WM8993_TEMPOK_EINT_WIDTH                     1  /* TEMPOK_EINT */
577 #define WM8993_JD1_SC_EINT                      0x0400  /* JD1_SC_EINT */
578 #define WM8993_JD1_SC_EINT_MASK                 0x0400  /* JD1_SC_EINT */
579 #define WM8993_JD1_SC_EINT_SHIFT                    10  /* JD1_SC_EINT */
580 #define WM8993_JD1_SC_EINT_WIDTH                     1  /* JD1_SC_EINT */
581 #define WM8993_JD1_EINT                         0x0200  /* JD1_EINT */
582 #define WM8993_JD1_EINT_MASK                    0x0200  /* JD1_EINT */
583 #define WM8993_JD1_EINT_SHIFT                        9  /* JD1_EINT */
584 #define WM8993_JD1_EINT_WIDTH                        1  /* JD1_EINT */
585 #define WM8993_FLL_LOCK_EINT                    0x0100  /* FLL_LOCK_EINT */
586 #define WM8993_FLL_LOCK_EINT_MASK               0x0100  /* FLL_LOCK_EINT */
587 #define WM8993_FLL_LOCK_EINT_SHIFT                   8  /* FLL_LOCK_EINT */
588 #define WM8993_FLL_LOCK_EINT_WIDTH                   1  /* FLL_LOCK_EINT */
589 #define WM8993_GPI8_EINT                        0x0080  /* GPI8_EINT */
590 #define WM8993_GPI8_EINT_MASK                   0x0080  /* GPI8_EINT */
591 #define WM8993_GPI8_EINT_SHIFT                       7  /* GPI8_EINT */
592 #define WM8993_GPI8_EINT_WIDTH                       1  /* GPI8_EINT */
593 #define WM8993_GPI7_EINT                        0x0040  /* GPI7_EINT */
594 #define WM8993_GPI7_EINT_MASK                   0x0040  /* GPI7_EINT */
595 #define WM8993_GPI7_EINT_SHIFT                       6  /* GPI7_EINT */
596 #define WM8993_GPI7_EINT_WIDTH                       1  /* GPI7_EINT */
597 #define WM8993_GPIO1_EINT                       0x0001  /* GPIO1_EINT */
598 #define WM8993_GPIO1_EINT_MASK                  0x0001  /* GPIO1_EINT */
599 #define WM8993_GPIO1_EINT_SHIFT                      0  /* GPIO1_EINT */
600 #define WM8993_GPIO1_EINT_WIDTH                      1  /* GPIO1_EINT */
601
602 /*
603  * R19 (0x13) - GPIO1
604  */
605 #define WM8993_GPIO1_PU                         0x0020  /* GPIO1_PU */
606 #define WM8993_GPIO1_PU_MASK                    0x0020  /* GPIO1_PU */
607 #define WM8993_GPIO1_PU_SHIFT                        5  /* GPIO1_PU */
608 #define WM8993_GPIO1_PU_WIDTH                        1  /* GPIO1_PU */
609 #define WM8993_GPIO1_PD                         0x0010  /* GPIO1_PD */
610 #define WM8993_GPIO1_PD_MASK                    0x0010  /* GPIO1_PD */
611 #define WM8993_GPIO1_PD_SHIFT                        4  /* GPIO1_PD */
612 #define WM8993_GPIO1_PD_WIDTH                        1  /* GPIO1_PD */
613 #define WM8993_GPIO1_SEL_MASK                   0x000F  /* GPIO1_SEL - [3:0] */
614 #define WM8993_GPIO1_SEL_SHIFT                       0  /* GPIO1_SEL - [3:0] */
615 #define WM8993_GPIO1_SEL_WIDTH                       4  /* GPIO1_SEL - [3:0] */
616
617 /*
618  * R20 (0x14) - IRQ_DEBOUNCE
619  */
620 #define WM8993_JD2_SC_DB                        0x8000  /* JD2_SC_DB */
621 #define WM8993_JD2_SC_DB_MASK                   0x8000  /* JD2_SC_DB */
622 #define WM8993_JD2_SC_DB_SHIFT                      15  /* JD2_SC_DB */
623 #define WM8993_JD2_SC_DB_WIDTH                       1  /* JD2_SC_DB */
624 #define WM8993_JD2_DB                           0x4000  /* JD2_DB */
625 #define WM8993_JD2_DB_MASK                      0x4000  /* JD2_DB */
626 #define WM8993_JD2_DB_SHIFT                         14  /* JD2_DB */
627 #define WM8993_JD2_DB_WIDTH                          1  /* JD2_DB */
628 #define WM8993_WSEQ_DB                          0x2000  /* WSEQ_DB */
629 #define WM8993_WSEQ_DB_MASK                     0x2000  /* WSEQ_DB */
630 #define WM8993_WSEQ_DB_SHIFT                        13  /* WSEQ_DB */
631 #define WM8993_WSEQ_DB_WIDTH                         1  /* WSEQ_DB */
632 #define WM8993_TEMPOK_DB                        0x0800  /* TEMPOK_DB */
633 #define WM8993_TEMPOK_DB_MASK                   0x0800  /* TEMPOK_DB */
634 #define WM8993_TEMPOK_DB_SHIFT                      11  /* TEMPOK_DB */
635 #define WM8993_TEMPOK_DB_WIDTH                       1  /* TEMPOK_DB */
636 #define WM8993_JD1_SC_DB                        0x0400  /* JD1_SC_DB */
637 #define WM8993_JD1_SC_DB_MASK                   0x0400  /* JD1_SC_DB */
638 #define WM8993_JD1_SC_DB_SHIFT                      10  /* JD1_SC_DB */
639 #define WM8993_JD1_SC_DB_WIDTH                       1  /* JD1_SC_DB */
640 #define WM8993_JD1_DB                           0x0200  /* JD1_DB */
641 #define WM8993_JD1_DB_MASK                      0x0200  /* JD1_DB */
642 #define WM8993_JD1_DB_SHIFT                          9  /* JD1_DB */
643 #define WM8993_JD1_DB_WIDTH                          1  /* JD1_DB */
644 #define WM8993_FLL_LOCK_DB                      0x0100  /* FLL_LOCK_DB */
645 #define WM8993_FLL_LOCK_DB_MASK                 0x0100  /* FLL_LOCK_DB */
646 #define WM8993_FLL_LOCK_DB_SHIFT                     8  /* FLL_LOCK_DB */
647 #define WM8993_FLL_LOCK_DB_WIDTH                     1  /* FLL_LOCK_DB */
648 #define WM8993_GPI8_DB                          0x0080  /* GPI8_DB */
649 #define WM8993_GPI8_DB_MASK                     0x0080  /* GPI8_DB */
650 #define WM8993_GPI8_DB_SHIFT                         7  /* GPI8_DB */
651 #define WM8993_GPI8_DB_WIDTH                         1  /* GPI8_DB */
652 #define WM8993_GPI7_DB                          0x0008  /* GPI7_DB */
653 #define WM8993_GPI7_DB_MASK                     0x0008  /* GPI7_DB */
654 #define WM8993_GPI7_DB_SHIFT                         3  /* GPI7_DB */
655 #define WM8993_GPI7_DB_WIDTH                         1  /* GPI7_DB */
656 #define WM8993_GPIO1_DB                         0x0001  /* GPIO1_DB */
657 #define WM8993_GPIO1_DB_MASK                    0x0001  /* GPIO1_DB */
658 #define WM8993_GPIO1_DB_SHIFT                        0  /* GPIO1_DB */
659 #define WM8993_GPIO1_DB_WIDTH                        1  /* GPIO1_DB */
660
661 /*
662  * R22 (0x16) - GPIOCTRL 2
663  */
664 #define WM8993_IM_JD2_EINT                      0x2000  /* IM_JD2_EINT */
665 #define WM8993_IM_JD2_EINT_MASK                 0x2000  /* IM_JD2_EINT */
666 #define WM8993_IM_JD2_EINT_SHIFT                    13  /* IM_JD2_EINT */
667 #define WM8993_IM_JD2_EINT_WIDTH                     1  /* IM_JD2_EINT */
668 #define WM8993_IM_JD2_SC_EINT                   0x1000  /* IM_JD2_SC_EINT */
669 #define WM8993_IM_JD2_SC_EINT_MASK              0x1000  /* IM_JD2_SC_EINT */
670 #define WM8993_IM_JD2_SC_EINT_SHIFT                 12  /* IM_JD2_SC_EINT */
671 #define WM8993_IM_JD2_SC_EINT_WIDTH                  1  /* IM_JD2_SC_EINT */
672 #define WM8993_IM_TEMPOK_EINT                   0x0800  /* IM_TEMPOK_EINT */
673 #define WM8993_IM_TEMPOK_EINT_MASK              0x0800  /* IM_TEMPOK_EINT */
674 #define WM8993_IM_TEMPOK_EINT_SHIFT                 11  /* IM_TEMPOK_EINT */
675 #define WM8993_IM_TEMPOK_EINT_WIDTH                  1  /* IM_TEMPOK_EINT */
676 #define WM8993_IM_JD1_SC_EINT                   0x0400  /* IM_JD1_SC_EINT */
677 #define WM8993_IM_JD1_SC_EINT_MASK              0x0400  /* IM_JD1_SC_EINT */
678 #define WM8993_IM_JD1_SC_EINT_SHIFT                 10  /* IM_JD1_SC_EINT */
679 #define WM8993_IM_JD1_SC_EINT_WIDTH                  1  /* IM_JD1_SC_EINT */
680 #define WM8993_IM_JD1_EINT                      0x0200  /* IM_JD1_EINT */
681 #define WM8993_IM_JD1_EINT_MASK                 0x0200  /* IM_JD1_EINT */
682 #define WM8993_IM_JD1_EINT_SHIFT                     9  /* IM_JD1_EINT */
683 #define WM8993_IM_JD1_EINT_WIDTH                     1  /* IM_JD1_EINT */
684 #define WM8993_IM_FLL_LOCK_EINT                 0x0100  /* IM_FLL_LOCK_EINT */
685 #define WM8993_IM_FLL_LOCK_EINT_MASK            0x0100  /* IM_FLL_LOCK_EINT */
686 #define WM8993_IM_FLL_LOCK_EINT_SHIFT                8  /* IM_FLL_LOCK_EINT */
687 #define WM8993_IM_FLL_LOCK_EINT_WIDTH                1  /* IM_FLL_LOCK_EINT */
688 #define WM8993_IM_GPI8_EINT                     0x0040  /* IM_GPI8_EINT */
689 #define WM8993_IM_GPI8_EINT_MASK                0x0040  /* IM_GPI8_EINT */
690 #define WM8993_IM_GPI8_EINT_SHIFT                    6  /* IM_GPI8_EINT */
691 #define WM8993_IM_GPI8_EINT_WIDTH                    1  /* IM_GPI8_EINT */
692 #define WM8993_IM_GPIO1_EINT                    0x0020  /* IM_GPIO1_EINT */
693 #define WM8993_IM_GPIO1_EINT_MASK               0x0020  /* IM_GPIO1_EINT */
694 #define WM8993_IM_GPIO1_EINT_SHIFT                   5  /* IM_GPIO1_EINT */
695 #define WM8993_IM_GPIO1_EINT_WIDTH                   1  /* IM_GPIO1_EINT */
696 #define WM8993_GPI8_ENA                         0x0010  /* GPI8_ENA */
697 #define WM8993_GPI8_ENA_MASK                    0x0010  /* GPI8_ENA */
698 #define WM8993_GPI8_ENA_SHIFT                        4  /* GPI8_ENA */
699 #define WM8993_GPI8_ENA_WIDTH                        1  /* GPI8_ENA */
700 #define WM8993_IM_GPI7_EINT                     0x0004  /* IM_GPI7_EINT */
701 #define WM8993_IM_GPI7_EINT_MASK                0x0004  /* IM_GPI7_EINT */
702 #define WM8993_IM_GPI7_EINT_SHIFT                    2  /* IM_GPI7_EINT */
703 #define WM8993_IM_GPI7_EINT_WIDTH                    1  /* IM_GPI7_EINT */
704 #define WM8993_IM_WSEQ_EINT                     0x0002  /* IM_WSEQ_EINT */
705 #define WM8993_IM_WSEQ_EINT_MASK                0x0002  /* IM_WSEQ_EINT */
706 #define WM8993_IM_WSEQ_EINT_SHIFT                    1  /* IM_WSEQ_EINT */
707 #define WM8993_IM_WSEQ_EINT_WIDTH                    1  /* IM_WSEQ_EINT */
708 #define WM8993_GPI7_ENA                         0x0001  /* GPI7_ENA */
709 #define WM8993_GPI7_ENA_MASK                    0x0001  /* GPI7_ENA */
710 #define WM8993_GPI7_ENA_SHIFT                        0  /* GPI7_ENA */
711 #define WM8993_GPI7_ENA_WIDTH                        1  /* GPI7_ENA */
712
713 /*
714  * R23 (0x17) - GPIO_POL
715  */
716 #define WM8993_JD2_SC_POL                       0x8000  /* JD2_SC_POL */
717 #define WM8993_JD2_SC_POL_MASK                  0x8000  /* JD2_SC_POL */
718 #define WM8993_JD2_SC_POL_SHIFT                     15  /* JD2_SC_POL */
719 #define WM8993_JD2_SC_POL_WIDTH                      1  /* JD2_SC_POL */
720 #define WM8993_JD2_POL                          0x4000  /* JD2_POL */
721 #define WM8993_JD2_POL_MASK                     0x4000  /* JD2_POL */
722 #define WM8993_JD2_POL_SHIFT                        14  /* JD2_POL */
723 #define WM8993_JD2_POL_WIDTH                         1  /* JD2_POL */
724 #define WM8993_WSEQ_POL                         0x2000  /* WSEQ_POL */
725 #define WM8993_WSEQ_POL_MASK                    0x2000  /* WSEQ_POL */
726 #define WM8993_WSEQ_POL_SHIFT                       13  /* WSEQ_POL */
727 #define WM8993_WSEQ_POL_WIDTH                        1  /* WSEQ_POL */
728 #define WM8993_IRQ_POL                          0x1000  /* IRQ_POL */
729 #define WM8993_IRQ_POL_MASK                     0x1000  /* IRQ_POL */
730 #define WM8993_IRQ_POL_SHIFT                        12  /* IRQ_POL */
731 #define WM8993_IRQ_POL_WIDTH                         1  /* IRQ_POL */
732 #define WM8993_TEMPOK_POL                       0x0800  /* TEMPOK_POL */
733 #define WM8993_TEMPOK_POL_MASK                  0x0800  /* TEMPOK_POL */
734 #define WM8993_TEMPOK_POL_SHIFT                     11  /* TEMPOK_POL */
735 #define WM8993_TEMPOK_POL_WIDTH                      1  /* TEMPOK_POL */
736 #define WM8993_JD1_SC_POL                       0x0400  /* JD1_SC_POL */
737 #define WM8993_JD1_SC_POL_MASK                  0x0400  /* JD1_SC_POL */
738 #define WM8993_JD1_SC_POL_SHIFT                     10  /* JD1_SC_POL */
739 #define WM8993_JD1_SC_POL_WIDTH                      1  /* JD1_SC_POL */
740 #define WM8993_JD1_POL                          0x0200  /* JD1_POL */
741 #define WM8993_JD1_POL_MASK                     0x0200  /* JD1_POL */
742 #define WM8993_JD1_POL_SHIFT                         9  /* JD1_POL */
743 #define WM8993_JD1_POL_WIDTH                         1  /* JD1_POL */
744 #define WM8993_FLL_LOCK_POL                     0x0100  /* FLL_LOCK_POL */
745 #define WM8993_FLL_LOCK_POL_MASK                0x0100  /* FLL_LOCK_POL */
746 #define WM8993_FLL_LOCK_POL_SHIFT                    8  /* FLL_LOCK_POL */
747 #define WM8993_FLL_LOCK_POL_WIDTH                    1  /* FLL_LOCK_POL */
748 #define WM8993_GPI8_POL                         0x0080  /* GPI8_POL */
749 #define WM8993_GPI8_POL_MASK                    0x0080  /* GPI8_POL */
750 #define WM8993_GPI8_POL_SHIFT                        7  /* GPI8_POL */
751 #define WM8993_GPI8_POL_WIDTH                        1  /* GPI8_POL */
752 #define WM8993_GPI7_POL                         0x0040  /* GPI7_POL */
753 #define WM8993_GPI7_POL_MASK                    0x0040  /* GPI7_POL */
754 #define WM8993_GPI7_POL_SHIFT                        6  /* GPI7_POL */
755 #define WM8993_GPI7_POL_WIDTH                        1  /* GPI7_POL */
756 #define WM8993_GPIO1_POL                        0x0001  /* GPIO1_POL */
757 #define WM8993_GPIO1_POL_MASK                   0x0001  /* GPIO1_POL */
758 #define WM8993_GPIO1_POL_SHIFT                       0  /* GPIO1_POL */
759 #define WM8993_GPIO1_POL_WIDTH                       1  /* GPIO1_POL */
760
761 /*
762  * R24 (0x18) - Left Line Input 1&2 Volume
763  */
764 #define WM8993_IN1_VU                           0x0100  /* IN1_VU */
765 #define WM8993_IN1_VU_MASK                      0x0100  /* IN1_VU */
766 #define WM8993_IN1_VU_SHIFT                          8  /* IN1_VU */
767 #define WM8993_IN1_VU_WIDTH                          1  /* IN1_VU */
768 #define WM8993_IN1L_MUTE                        0x0080  /* IN1L_MUTE */
769 #define WM8993_IN1L_MUTE_MASK                   0x0080  /* IN1L_MUTE */
770 #define WM8993_IN1L_MUTE_SHIFT                       7  /* IN1L_MUTE */
771 #define WM8993_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
772 #define WM8993_IN1L_ZC                          0x0040  /* IN1L_ZC */
773 #define WM8993_IN1L_ZC_MASK                     0x0040  /* IN1L_ZC */
774 #define WM8993_IN1L_ZC_SHIFT                         6  /* IN1L_ZC */
775 #define WM8993_IN1L_ZC_WIDTH                         1  /* IN1L_ZC */
776 #define WM8993_IN1L_VOL_MASK                    0x001F  /* IN1L_VOL - [4:0] */
777 #define WM8993_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [4:0] */
778 #define WM8993_IN1L_VOL_WIDTH                        5  /* IN1L_VOL - [4:0] */
779
780 /*
781  * R25 (0x19) - Left Line Input 3&4 Volume
782  */
783 #define WM8993_IN2_VU                           0x0100  /* IN2_VU */
784 #define WM8993_IN2_VU_MASK                      0x0100  /* IN2_VU */
785 #define WM8993_IN2_VU_SHIFT                          8  /* IN2_VU */
786 #define WM8993_IN2_VU_WIDTH                          1  /* IN2_VU */
787 #define WM8993_IN2L_MUTE                        0x0080  /* IN2L_MUTE */
788 #define WM8993_IN2L_MUTE_MASK                   0x0080  /* IN2L_MUTE */
789 #define WM8993_IN2L_MUTE_SHIFT                       7  /* IN2L_MUTE */
790 #define WM8993_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
791 #define WM8993_IN2L_ZC                          0x0040  /* IN2L_ZC */
792 #define WM8993_IN2L_ZC_MASK                     0x0040  /* IN2L_ZC */
793 #define WM8993_IN2L_ZC_SHIFT                         6  /* IN2L_ZC */
794 #define WM8993_IN2L_ZC_WIDTH                         1  /* IN2L_ZC */
795 #define WM8993_IN2L_VOL_MASK                    0x001F  /* IN2L_VOL - [4:0] */
796 #define WM8993_IN2L_VOL_SHIFT                        0  /* IN2L_VOL - [4:0] */
797 #define WM8993_IN2L_VOL_WIDTH                        5  /* IN2L_VOL - [4:0] */
798
799 /*
800  * R26 (0x1A) - Right Line Input 1&2 Volume
801  */
802 #define WM8993_IN1_VU                           0x0100  /* IN1_VU */
803 #define WM8993_IN1_VU_MASK                      0x0100  /* IN1_VU */
804 #define WM8993_IN1_VU_SHIFT                          8  /* IN1_VU */
805 #define WM8993_IN1_VU_WIDTH                          1  /* IN1_VU */
806 #define WM8993_IN1R_MUTE                        0x0080  /* IN1R_MUTE */
807 #define WM8993_IN1R_MUTE_MASK                   0x0080  /* IN1R_MUTE */
808 #define WM8993_IN1R_MUTE_SHIFT                       7  /* IN1R_MUTE */
809 #define WM8993_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
810 #define WM8993_IN1R_ZC                          0x0040  /* IN1R_ZC */
811 #define WM8993_IN1R_ZC_MASK                     0x0040  /* IN1R_ZC */
812 #define WM8993_IN1R_ZC_SHIFT                         6  /* IN1R_ZC */
813 #define WM8993_IN1R_ZC_WIDTH                         1  /* IN1R_ZC */
814 #define WM8993_IN1R_VOL_MASK                    0x001F  /* IN1R_VOL - [4:0] */
815 #define WM8993_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [4:0] */
816 #define WM8993_IN1R_VOL_WIDTH                        5  /* IN1R_VOL - [4:0] */
817
818 /*
819  * R27 (0x1B) - Right Line Input 3&4 Volume
820  */
821 #define WM8993_IN2_VU                           0x0100  /* IN2_VU */
822 #define WM8993_IN2_VU_MASK                      0x0100  /* IN2_VU */
823 #define WM8993_IN2_VU_SHIFT                          8  /* IN2_VU */
824 #define WM8993_IN2_VU_WIDTH                          1  /* IN2_VU */
825 #define WM8993_IN2R_MUTE                        0x0080  /* IN2R_MUTE */
826 #define WM8993_IN2R_MUTE_MASK                   0x0080  /* IN2R_MUTE */
827 #define WM8993_IN2R_MUTE_SHIFT                       7  /* IN2R_MUTE */
828 #define WM8993_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
829 #define WM8993_IN2R_ZC                          0x0040  /* IN2R_ZC */
830 #define WM8993_IN2R_ZC_MASK                     0x0040  /* IN2R_ZC */
831 #define WM8993_IN2R_ZC_SHIFT                         6  /* IN2R_ZC */
832 #define WM8993_IN2R_ZC_WIDTH                         1  /* IN2R_ZC */
833 #define WM8993_IN2R_VOL_MASK                    0x001F  /* IN2R_VOL - [4:0] */
834 #define WM8993_IN2R_VOL_SHIFT                        0  /* IN2R_VOL - [4:0] */
835 #define WM8993_IN2R_VOL_WIDTH                        5  /* IN2R_VOL - [4:0] */
836
837 /*
838  * R28 (0x1C) - Left Output Volume
839  */
840 #define WM8993_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
841 #define WM8993_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
842 #define WM8993_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
843 #define WM8993_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
844 #define WM8993_HPOUT1L_ZC                       0x0080  /* HPOUT1L_ZC */
845 #define WM8993_HPOUT1L_ZC_MASK                  0x0080  /* HPOUT1L_ZC */
846 #define WM8993_HPOUT1L_ZC_SHIFT                      7  /* HPOUT1L_ZC */
847 #define WM8993_HPOUT1L_ZC_WIDTH                      1  /* HPOUT1L_ZC */
848 #define WM8993_HPOUT1L_MUTE_N                   0x0040  /* HPOUT1L_MUTE_N */
849 #define WM8993_HPOUT1L_MUTE_N_MASK              0x0040  /* HPOUT1L_MUTE_N */
850 #define WM8993_HPOUT1L_MUTE_N_SHIFT                  6  /* HPOUT1L_MUTE_N */
851 #define WM8993_HPOUT1L_MUTE_N_WIDTH                  1  /* HPOUT1L_MUTE_N */
852 #define WM8993_HPOUT1L_VOL_MASK                 0x003F  /* HPOUT1L_VOL - [5:0] */
853 #define WM8993_HPOUT1L_VOL_SHIFT                     0  /* HPOUT1L_VOL - [5:0] */
854 #define WM8993_HPOUT1L_VOL_WIDTH                     6  /* HPOUT1L_VOL - [5:0] */
855
856 /*
857  * R29 (0x1D) - Right Output Volume
858  */
859 #define WM8993_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
860 #define WM8993_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
861 #define WM8993_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
862 #define WM8993_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
863 #define WM8993_HPOUT1R_ZC                       0x0080  /* HPOUT1R_ZC */
864 #define WM8993_HPOUT1R_ZC_MASK                  0x0080  /* HPOUT1R_ZC */
865 #define WM8993_HPOUT1R_ZC_SHIFT                      7  /* HPOUT1R_ZC */
866 #define WM8993_HPOUT1R_ZC_WIDTH                      1  /* HPOUT1R_ZC */
867 #define WM8993_HPOUT1R_MUTE_N                   0x0040  /* HPOUT1R_MUTE_N */
868 #define WM8993_HPOUT1R_MUTE_N_MASK              0x0040  /* HPOUT1R_MUTE_N */
869 #define WM8993_HPOUT1R_MUTE_N_SHIFT                  6  /* HPOUT1R_MUTE_N */
870 #define WM8993_HPOUT1R_MUTE_N_WIDTH                  1  /* HPOUT1R_MUTE_N */
871 #define WM8993_HPOUT1R_VOL_MASK                 0x003F  /* HPOUT1R_VOL - [5:0] */
872 #define WM8993_HPOUT1R_VOL_SHIFT                     0  /* HPOUT1R_VOL - [5:0] */
873 #define WM8993_HPOUT1R_VOL_WIDTH                     6  /* HPOUT1R_VOL - [5:0] */
874
875 /*
876  * R30 (0x1E) - Line Outputs Volume
877  */
878 #define WM8993_LINEOUT1N_MUTE                   0x0040  /* LINEOUT1N_MUTE */
879 #define WM8993_LINEOUT1N_MUTE_MASK              0x0040  /* LINEOUT1N_MUTE */
880 #define WM8993_LINEOUT1N_MUTE_SHIFT                  6  /* LINEOUT1N_MUTE */
881 #define WM8993_LINEOUT1N_MUTE_WIDTH                  1  /* LINEOUT1N_MUTE */
882 #define WM8993_LINEOUT1P_MUTE                   0x0020  /* LINEOUT1P_MUTE */
883 #define WM8993_LINEOUT1P_MUTE_MASK              0x0020  /* LINEOUT1P_MUTE */
884 #define WM8993_LINEOUT1P_MUTE_SHIFT                  5  /* LINEOUT1P_MUTE */
885 #define WM8993_LINEOUT1P_MUTE_WIDTH                  1  /* LINEOUT1P_MUTE */
886 #define WM8993_LINEOUT1_VOL                     0x0010  /* LINEOUT1_VOL */
887 #define WM8993_LINEOUT1_VOL_MASK                0x0010  /* LINEOUT1_VOL */
888 #define WM8993_LINEOUT1_VOL_SHIFT                    4  /* LINEOUT1_VOL */
889 #define WM8993_LINEOUT1_VOL_WIDTH                    1  /* LINEOUT1_VOL */
890 #define WM8993_LINEOUT2N_MUTE                   0x0004  /* LINEOUT2N_MUTE */
891 #define WM8993_LINEOUT2N_MUTE_MASK              0x0004  /* LINEOUT2N_MUTE */
892 #define WM8993_LINEOUT2N_MUTE_SHIFT                  2  /* LINEOUT2N_MUTE */
893 #define WM8993_LINEOUT2N_MUTE_WIDTH                  1  /* LINEOUT2N_MUTE */
894 #define WM8993_LINEOUT2P_MUTE                   0x0002  /* LINEOUT2P_MUTE */
895 #define WM8993_LINEOUT2P_MUTE_MASK              0x0002  /* LINEOUT2P_MUTE */
896 #define WM8993_LINEOUT2P_MUTE_SHIFT                  1  /* LINEOUT2P_MUTE */
897 #define WM8993_LINEOUT2P_MUTE_WIDTH                  1  /* LINEOUT2P_MUTE */
898 #define WM8993_LINEOUT2_VOL                     0x0001  /* LINEOUT2_VOL */
899 #define WM8993_LINEOUT2_VOL_MASK                0x0001  /* LINEOUT2_VOL */
900 #define WM8993_LINEOUT2_VOL_SHIFT                    0  /* LINEOUT2_VOL */
901 #define WM8993_LINEOUT2_VOL_WIDTH                    1  /* LINEOUT2_VOL */
902
903 /*
904  * R31 (0x1F) - HPOUT2 Volume
905  */
906 #define WM8993_HPOUT2_MUTE                      0x0020  /* HPOUT2_MUTE */
907 #define WM8993_HPOUT2_MUTE_MASK                 0x0020  /* HPOUT2_MUTE */
908 #define WM8993_HPOUT2_MUTE_SHIFT                     5  /* HPOUT2_MUTE */
909 #define WM8993_HPOUT2_MUTE_WIDTH                     1  /* HPOUT2_MUTE */
910 #define WM8993_HPOUT2_VOL                       0x0010  /* HPOUT2_VOL */
911 #define WM8993_HPOUT2_VOL_MASK                  0x0010  /* HPOUT2_VOL */
912 #define WM8993_HPOUT2_VOL_SHIFT                      4  /* HPOUT2_VOL */
913 #define WM8993_HPOUT2_VOL_WIDTH                      1  /* HPOUT2_VOL */
914
915 /*
916  * R32 (0x20) - Left OPGA Volume
917  */
918 #define WM8993_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
919 #define WM8993_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
920 #define WM8993_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
921 #define WM8993_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
922 #define WM8993_MIXOUTL_ZC                       0x0080  /* MIXOUTL_ZC */
923 #define WM8993_MIXOUTL_ZC_MASK                  0x0080  /* MIXOUTL_ZC */
924 #define WM8993_MIXOUTL_ZC_SHIFT                      7  /* MIXOUTL_ZC */
925 #define WM8993_MIXOUTL_ZC_WIDTH                      1  /* MIXOUTL_ZC */
926 #define WM8993_MIXOUTL_MUTE_N                   0x0040  /* MIXOUTL_MUTE_N */
927 #define WM8993_MIXOUTL_MUTE_N_MASK              0x0040  /* MIXOUTL_MUTE_N */
928 #define WM8993_MIXOUTL_MUTE_N_SHIFT                  6  /* MIXOUTL_MUTE_N */
929 #define WM8993_MIXOUTL_MUTE_N_WIDTH                  1  /* MIXOUTL_MUTE_N */
930 #define WM8993_MIXOUTL_VOL_MASK                 0x003F  /* MIXOUTL_VOL - [5:0] */
931 #define WM8993_MIXOUTL_VOL_SHIFT                     0  /* MIXOUTL_VOL - [5:0] */
932 #define WM8993_MIXOUTL_VOL_WIDTH                     6  /* MIXOUTL_VOL - [5:0] */
933
934 /*
935  * R33 (0x21) - Right OPGA Volume
936  */
937 #define WM8993_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
938 #define WM8993_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
939 #define WM8993_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
940 #define WM8993_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
941 #define WM8993_MIXOUTR_ZC                       0x0080  /* MIXOUTR_ZC */
942 #define WM8993_MIXOUTR_ZC_MASK                  0x0080  /* MIXOUTR_ZC */
943 #define WM8993_MIXOUTR_ZC_SHIFT                      7  /* MIXOUTR_ZC */
944 #define WM8993_MIXOUTR_ZC_WIDTH                      1  /* MIXOUTR_ZC */
945 #define WM8993_MIXOUTR_MUTE_N                   0x0040  /* MIXOUTR_MUTE_N */
946 #define WM8993_MIXOUTR_MUTE_N_MASK              0x0040  /* MIXOUTR_MUTE_N */
947 #define WM8993_MIXOUTR_MUTE_N_SHIFT                  6  /* MIXOUTR_MUTE_N */
948 #define WM8993_MIXOUTR_MUTE_N_WIDTH                  1  /* MIXOUTR_MUTE_N */
949 #define WM8993_MIXOUTR_VOL_MASK                 0x003F  /* MIXOUTR_VOL - [5:0] */
950 #define WM8993_MIXOUTR_VOL_SHIFT                     0  /* MIXOUTR_VOL - [5:0] */
951 #define WM8993_MIXOUTR_VOL_WIDTH                     6  /* MIXOUTR_VOL - [5:0] */
952
953 /*
954  * R34 (0x22) - SPKMIXL Attenuation
955  */
956 #define WM8993_MIXINL_SPKMIXL_VOL               0x0020  /* MIXINL_SPKMIXL_VOL */
957 #define WM8993_MIXINL_SPKMIXL_VOL_MASK          0x0020  /* MIXINL_SPKMIXL_VOL */
958 #define WM8993_MIXINL_SPKMIXL_VOL_SHIFT              5  /* MIXINL_SPKMIXL_VOL */
959 #define WM8993_MIXINL_SPKMIXL_VOL_WIDTH              1  /* MIXINL_SPKMIXL_VOL */
960 #define WM8993_IN1LP_SPKMIXL_VOL                0x0010  /* IN1LP_SPKMIXL_VOL */
961 #define WM8993_IN1LP_SPKMIXL_VOL_MASK           0x0010  /* IN1LP_SPKMIXL_VOL */
962 #define WM8993_IN1LP_SPKMIXL_VOL_SHIFT               4  /* IN1LP_SPKMIXL_VOL */
963 #define WM8993_IN1LP_SPKMIXL_VOL_WIDTH               1  /* IN1LP_SPKMIXL_VOL */
964 #define WM8993_MIXOUTL_SPKMIXL_VOL              0x0008  /* MIXOUTL_SPKMIXL_VOL */
965 #define WM8993_MIXOUTL_SPKMIXL_VOL_MASK         0x0008  /* MIXOUTL_SPKMIXL_VOL */
966 #define WM8993_MIXOUTL_SPKMIXL_VOL_SHIFT             3  /* MIXOUTL_SPKMIXL_VOL */
967 #define WM8993_MIXOUTL_SPKMIXL_VOL_WIDTH             1  /* MIXOUTL_SPKMIXL_VOL */
968 #define WM8993_DACL_SPKMIXL_VOL                 0x0004  /* DACL_SPKMIXL_VOL */
969 #define WM8993_DACL_SPKMIXL_VOL_MASK            0x0004  /* DACL_SPKMIXL_VOL */
970 #define WM8993_DACL_SPKMIXL_VOL_SHIFT                2  /* DACL_SPKMIXL_VOL */
971 #define WM8993_DACL_SPKMIXL_VOL_WIDTH                1  /* DACL_SPKMIXL_VOL */
972 #define WM8993_SPKMIXL_VOL_MASK                 0x0003  /* SPKMIXL_VOL - [1:0] */
973 #define WM8993_SPKMIXL_VOL_SHIFT                     0  /* SPKMIXL_VOL - [1:0] */
974 #define WM8993_SPKMIXL_VOL_WIDTH                     2  /* SPKMIXL_VOL - [1:0] */
975
976 /*
977  * R35 (0x23) - SPKMIXR Attenuation
978  */
979 #define WM8993_SPKOUT_CLASSAB_MODE              0x0100  /* SPKOUT_CLASSAB_MODE */
980 #define WM8993_SPKOUT_CLASSAB_MODE_MASK         0x0100  /* SPKOUT_CLASSAB_MODE */
981 #define WM8993_SPKOUT_CLASSAB_MODE_SHIFT             8  /* SPKOUT_CLASSAB_MODE */
982 #define WM8993_SPKOUT_CLASSAB_MODE_WIDTH             1  /* SPKOUT_CLASSAB_MODE */
983 #define WM8993_MIXINR_SPKMIXR_VOL               0x0020  /* MIXINR_SPKMIXR_VOL */
984 #define WM8993_MIXINR_SPKMIXR_VOL_MASK          0x0020  /* MIXINR_SPKMIXR_VOL */
985 #define WM8993_MIXINR_SPKMIXR_VOL_SHIFT              5  /* MIXINR_SPKMIXR_VOL */
986 #define WM8993_MIXINR_SPKMIXR_VOL_WIDTH              1  /* MIXINR_SPKMIXR_VOL */
987 #define WM8993_IN1RP_SPKMIXR_VOL                0x0010  /* IN1RP_SPKMIXR_VOL */
988 #define WM8993_IN1RP_SPKMIXR_VOL_MASK           0x0010  /* IN1RP_SPKMIXR_VOL */
989 #define WM8993_IN1RP_SPKMIXR_VOL_SHIFT               4  /* IN1RP_SPKMIXR_VOL */
990 #define WM8993_IN1RP_SPKMIXR_VOL_WIDTH               1  /* IN1RP_SPKMIXR_VOL */
991 #define WM8993_MIXOUTR_SPKMIXR_VOL              0x0008  /* MIXOUTR_SPKMIXR_VOL */
992 #define WM8993_MIXOUTR_SPKMIXR_VOL_MASK         0x0008  /* MIXOUTR_SPKMIXR_VOL */
993 #define WM8993_MIXOUTR_SPKMIXR_VOL_SHIFT             3  /* MIXOUTR_SPKMIXR_VOL */
994 #define WM8993_MIXOUTR_SPKMIXR_VOL_WIDTH             1  /* MIXOUTR_SPKMIXR_VOL */
995 #define WM8993_DACR_SPKMIXR_VOL                 0x0004  /* DACR_SPKMIXR_VOL */
996 #define WM8993_DACR_SPKMIXR_VOL_MASK            0x0004  /* DACR_SPKMIXR_VOL */
997 #define WM8993_DACR_SPKMIXR_VOL_SHIFT                2  /* DACR_SPKMIXR_VOL */
998 #define WM8993_DACR_SPKMIXR_VOL_WIDTH                1  /* DACR_SPKMIXR_VOL */
999 #define WM8993_SPKMIXR_VOL_MASK                 0x0003  /* SPKMIXR_VOL - [1:0] */
1000 #define WM8993_SPKMIXR_VOL_SHIFT                     0  /* SPKMIXR_VOL - [1:0] */
1001 #define WM8993_SPKMIXR_VOL_WIDTH                     2  /* SPKMIXR_VOL - [1:0] */
1002
1003 /*
1004  * R36 (0x24) - SPKOUT Mixers
1005  */
1006 #define WM8993_VRX_TO_SPKOUTL                   0x0020  /* VRX_TO_SPKOUTL */
1007 #define WM8993_VRX_TO_SPKOUTL_MASK              0x0020  /* VRX_TO_SPKOUTL */
1008 #define WM8993_VRX_TO_SPKOUTL_SHIFT                  5  /* VRX_TO_SPKOUTL */
1009 #define WM8993_VRX_TO_SPKOUTL_WIDTH                  1  /* VRX_TO_SPKOUTL */
1010 #define WM8993_SPKMIXL_TO_SPKOUTL               0x0010  /* SPKMIXL_TO_SPKOUTL */
1011 #define WM8993_SPKMIXL_TO_SPKOUTL_MASK          0x0010  /* SPKMIXL_TO_SPKOUTL */
1012 #define WM8993_SPKMIXL_TO_SPKOUTL_SHIFT              4  /* SPKMIXL_TO_SPKOUTL */
1013 #define WM8993_SPKMIXL_TO_SPKOUTL_WIDTH              1  /* SPKMIXL_TO_SPKOUTL */
1014 #define WM8993_SPKMIXR_TO_SPKOUTL               0x0008  /* SPKMIXR_TO_SPKOUTL */
1015 #define WM8993_SPKMIXR_TO_SPKOUTL_MASK          0x0008  /* SPKMIXR_TO_SPKOUTL */
1016 #define WM8993_SPKMIXR_TO_SPKOUTL_SHIFT              3  /* SPKMIXR_TO_SPKOUTL */
1017 #define WM8993_SPKMIXR_TO_SPKOUTL_WIDTH              1  /* SPKMIXR_TO_SPKOUTL */
1018 #define WM8993_VRX_TO_SPKOUTR                   0x0004  /* VRX_TO_SPKOUTR */
1019 #define WM8993_VRX_TO_SPKOUTR_MASK              0x0004  /* VRX_TO_SPKOUTR */
1020 #define WM8993_VRX_TO_SPKOUTR_SHIFT                  2  /* VRX_TO_SPKOUTR */
1021 #define WM8993_VRX_TO_SPKOUTR_WIDTH                  1  /* VRX_TO_SPKOUTR */
1022 #define WM8993_SPKMIXL_TO_SPKOUTR               0x0002  /* SPKMIXL_TO_SPKOUTR */
1023 #define WM8993_SPKMIXL_TO_SPKOUTR_MASK          0x0002  /* SPKMIXL_TO_SPKOUTR */
1024 #define WM8993_SPKMIXL_TO_SPKOUTR_SHIFT              1  /* SPKMIXL_TO_SPKOUTR */
1025 #define WM8993_SPKMIXL_TO_SPKOUTR_WIDTH              1  /* SPKMIXL_TO_SPKOUTR */
1026 #define WM8993_SPKMIXR_TO_SPKOUTR               0x0001  /* SPKMIXR_TO_SPKOUTR */
1027 #define WM8993_SPKMIXR_TO_SPKOUTR_MASK          0x0001  /* SPKMIXR_TO_SPKOUTR */
1028 #define WM8993_SPKMIXR_TO_SPKOUTR_SHIFT              0  /* SPKMIXR_TO_SPKOUTR */
1029 #define WM8993_SPKMIXR_TO_SPKOUTR_WIDTH              1  /* SPKMIXR_TO_SPKOUTR */
1030
1031 /*
1032  * R37 (0x25) - SPKOUT Boost
1033  */
1034 #define WM8993_SPKOUTL_BOOST_MASK               0x0038  /* SPKOUTL_BOOST - [5:3] */
1035 #define WM8993_SPKOUTL_BOOST_SHIFT                   3  /* SPKOUTL_BOOST - [5:3] */
1036 #define WM8993_SPKOUTL_BOOST_WIDTH                   3  /* SPKOUTL_BOOST - [5:3] */
1037 #define WM8993_SPKOUTR_BOOST_MASK               0x0007  /* SPKOUTR_BOOST - [2:0] */
1038 #define WM8993_SPKOUTR_BOOST_SHIFT                   0  /* SPKOUTR_BOOST - [2:0] */
1039 #define WM8993_SPKOUTR_BOOST_WIDTH                   3  /* SPKOUTR_BOOST - [2:0] */
1040
1041 /*
1042  * R38 (0x26) - Speaker Volume Left
1043  */
1044 #define WM8993_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1045 #define WM8993_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1046 #define WM8993_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1047 #define WM8993_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1048 #define WM8993_SPKOUTL_ZC                       0x0080  /* SPKOUTL_ZC */
1049 #define WM8993_SPKOUTL_ZC_MASK                  0x0080  /* SPKOUTL_ZC */
1050 #define WM8993_SPKOUTL_ZC_SHIFT                      7  /* SPKOUTL_ZC */
1051 #define WM8993_SPKOUTL_ZC_WIDTH                      1  /* SPKOUTL_ZC */
1052 #define WM8993_SPKOUTL_MUTE_N                   0x0040  /* SPKOUTL_MUTE_N */
1053 #define WM8993_SPKOUTL_MUTE_N_MASK              0x0040  /* SPKOUTL_MUTE_N */
1054 #define WM8993_SPKOUTL_MUTE_N_SHIFT                  6  /* SPKOUTL_MUTE_N */
1055 #define WM8993_SPKOUTL_MUTE_N_WIDTH                  1  /* SPKOUTL_MUTE_N */
1056 #define WM8993_SPKOUTL_VOL_MASK                 0x003F  /* SPKOUTL_VOL - [5:0] */
1057 #define WM8993_SPKOUTL_VOL_SHIFT                     0  /* SPKOUTL_VOL - [5:0] */
1058 #define WM8993_SPKOUTL_VOL_WIDTH                     6  /* SPKOUTL_VOL - [5:0] */
1059
1060 /*
1061  * R39 (0x27) - Speaker Volume Right
1062  */
1063 #define WM8993_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1064 #define WM8993_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1065 #define WM8993_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1066 #define WM8993_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1067 #define WM8993_SPKOUTR_ZC                       0x0080  /* SPKOUTR_ZC */
1068 #define WM8993_SPKOUTR_ZC_MASK                  0x0080  /* SPKOUTR_ZC */
1069 #define WM8993_SPKOUTR_ZC_SHIFT                      7  /* SPKOUTR_ZC */
1070 #define WM8993_SPKOUTR_ZC_WIDTH                      1  /* SPKOUTR_ZC */
1071 #define WM8993_SPKOUTR_MUTE_N                   0x0040  /* SPKOUTR_MUTE_N */
1072 #define WM8993_SPKOUTR_MUTE_N_MASK              0x0040  /* SPKOUTR_MUTE_N */
1073 #define WM8993_SPKOUTR_MUTE_N_SHIFT                  6  /* SPKOUTR_MUTE_N */
1074 #define WM8993_SPKOUTR_MUTE_N_WIDTH                  1  /* SPKOUTR_MUTE_N */
1075 #define WM8993_SPKOUTR_VOL_MASK                 0x003F  /* SPKOUTR_VOL - [5:0] */
1076 #define WM8993_SPKOUTR_VOL_SHIFT                     0  /* SPKOUTR_VOL - [5:0] */
1077 #define WM8993_SPKOUTR_VOL_WIDTH                     6  /* SPKOUTR_VOL - [5:0] */
1078
1079 /*
1080  * R40 (0x28) - Input Mixer2
1081  */
1082 #define WM8993_IN2LP_TO_IN2L                    0x0080  /* IN2LP_TO_IN2L */
1083 #define WM8993_IN2LP_TO_IN2L_MASK               0x0080  /* IN2LP_TO_IN2L */
1084 #define WM8993_IN2LP_TO_IN2L_SHIFT                   7  /* IN2LP_TO_IN2L */
1085 #define WM8993_IN2LP_TO_IN2L_WIDTH                   1  /* IN2LP_TO_IN2L */
1086 #define WM8993_IN2LN_TO_IN2L                    0x0040  /* IN2LN_TO_IN2L */
1087 #define WM8993_IN2LN_TO_IN2L_MASK               0x0040  /* IN2LN_TO_IN2L */
1088 #define WM8993_IN2LN_TO_IN2L_SHIFT                   6  /* IN2LN_TO_IN2L */
1089 #define WM8993_IN2LN_TO_IN2L_WIDTH                   1  /* IN2LN_TO_IN2L */
1090 #define WM8993_IN1LP_TO_IN1L                    0x0020  /* IN1LP_TO_IN1L */
1091 #define WM8993_IN1LP_TO_IN1L_MASK               0x0020  /* IN1LP_TO_IN1L */
1092 #define WM8993_IN1LP_TO_IN1L_SHIFT                   5  /* IN1LP_TO_IN1L */
1093 #define WM8993_IN1LP_TO_IN1L_WIDTH                   1  /* IN1LP_TO_IN1L */
1094 #define WM8993_IN1LN_TO_IN1L                    0x0010  /* IN1LN_TO_IN1L */
1095 #define WM8993_IN1LN_TO_IN1L_MASK               0x0010  /* IN1LN_TO_IN1L */
1096 #define WM8993_IN1LN_TO_IN1L_SHIFT                   4  /* IN1LN_TO_IN1L */
1097 #define WM8993_IN1LN_TO_IN1L_WIDTH                   1  /* IN1LN_TO_IN1L */
1098 #define WM8993_IN2RP_TO_IN2R                    0x0008  /* IN2RP_TO_IN2R */
1099 #define WM8993_IN2RP_TO_IN2R_MASK               0x0008  /* IN2RP_TO_IN2R */
1100 #define WM8993_IN2RP_TO_IN2R_SHIFT                   3  /* IN2RP_TO_IN2R */
1101 #define WM8993_IN2RP_TO_IN2R_WIDTH                   1  /* IN2RP_TO_IN2R */
1102 #define WM8993_IN2RN_TO_IN2R                    0x0004  /* IN2RN_TO_IN2R */
1103 #define WM8993_IN2RN_TO_IN2R_MASK               0x0004  /* IN2RN_TO_IN2R */
1104 #define WM8993_IN2RN_TO_IN2R_SHIFT                   2  /* IN2RN_TO_IN2R */
1105 #define WM8993_IN2RN_TO_IN2R_WIDTH                   1  /* IN2RN_TO_IN2R */
1106 #define WM8993_IN1RP_TO_IN1R                    0x0002  /* IN1RP_TO_IN1R */
1107 #define WM8993_IN1RP_TO_IN1R_MASK               0x0002  /* IN1RP_TO_IN1R */
1108 #define WM8993_IN1RP_TO_IN1R_SHIFT                   1  /* IN1RP_TO_IN1R */
1109 #define WM8993_IN1RP_TO_IN1R_WIDTH                   1  /* IN1RP_TO_IN1R */
1110 #define WM8993_IN1RN_TO_IN1R                    0x0001  /* IN1RN_TO_IN1R */
1111 #define WM8993_IN1RN_TO_IN1R_MASK               0x0001  /* IN1RN_TO_IN1R */
1112 #define WM8993_IN1RN_TO_IN1R_SHIFT                   0  /* IN1RN_TO_IN1R */
1113 #define WM8993_IN1RN_TO_IN1R_WIDTH                   1  /* IN1RN_TO_IN1R */
1114
1115 /*
1116  * R41 (0x29) - Input Mixer3
1117  */
1118 #define WM8993_IN2L_TO_MIXINL                   0x0100  /* IN2L_TO_MIXINL */
1119 #define WM8993_IN2L_TO_MIXINL_MASK              0x0100  /* IN2L_TO_MIXINL */
1120 #define WM8993_IN2L_TO_MIXINL_SHIFT                  8  /* IN2L_TO_MIXINL */
1121 #define WM8993_IN2L_TO_MIXINL_WIDTH                  1  /* IN2L_TO_MIXINL */
1122 #define WM8993_IN2L_MIXINL_VOL                  0x0080  /* IN2L_MIXINL_VOL */
1123 #define WM8993_IN2L_MIXINL_VOL_MASK             0x0080  /* IN2L_MIXINL_VOL */
1124 #define WM8993_IN2L_MIXINL_VOL_SHIFT                 7  /* IN2L_MIXINL_VOL */
1125 #define WM8993_IN2L_MIXINL_VOL_WIDTH                 1  /* IN2L_MIXINL_VOL */
1126 #define WM8993_IN1L_TO_MIXINL                   0x0020  /* IN1L_TO_MIXINL */
1127 #define WM8993_IN1L_TO_MIXINL_MASK              0x0020  /* IN1L_TO_MIXINL */
1128 #define WM8993_IN1L_TO_MIXINL_SHIFT                  5  /* IN1L_TO_MIXINL */
1129 #define WM8993_IN1L_TO_MIXINL_WIDTH                  1  /* IN1L_TO_MIXINL */
1130 #define WM8993_IN1L_MIXINL_VOL                  0x0010  /* IN1L_MIXINL_VOL */
1131 #define WM8993_IN1L_MIXINL_VOL_MASK             0x0010  /* IN1L_MIXINL_VOL */
1132 #define WM8993_IN1L_MIXINL_VOL_SHIFT                 4  /* IN1L_MIXINL_VOL */
1133 #define WM8993_IN1L_MIXINL_VOL_WIDTH                 1  /* IN1L_MIXINL_VOL */
1134 #define WM8993_MIXOUTL_MIXINL_VOL_MASK          0x0007  /* MIXOUTL_MIXINL_VOL - [2:0] */
1135 #define WM8993_MIXOUTL_MIXINL_VOL_SHIFT              0  /* MIXOUTL_MIXINL_VOL - [2:0] */
1136 #define WM8993_MIXOUTL_MIXINL_VOL_WIDTH              3  /* MIXOUTL_MIXINL_VOL - [2:0] */
1137
1138 /*
1139  * R42 (0x2A) - Input Mixer4
1140  */
1141 #define WM8993_IN2R_TO_MIXINR                   0x0100  /* IN2R_TO_MIXINR */
1142 #define WM8993_IN2R_TO_MIXINR_MASK              0x0100  /* IN2R_TO_MIXINR */
1143 #define WM8993_IN2R_TO_MIXINR_SHIFT                  8  /* IN2R_TO_MIXINR */
1144 #define WM8993_IN2R_TO_MIXINR_WIDTH                  1  /* IN2R_TO_MIXINR */
1145 #define WM8993_IN2R_MIXINR_VOL                  0x0080  /* IN2R_MIXINR_VOL */
1146 #define WM8993_IN2R_MIXINR_VOL_MASK             0x0080  /* IN2R_MIXINR_VOL */
1147 #define WM8993_IN2R_MIXINR_VOL_SHIFT                 7  /* IN2R_MIXINR_VOL */
1148 #define WM8993_IN2R_MIXINR_VOL_WIDTH                 1  /* IN2R_MIXINR_VOL */
1149 #define WM8993_IN1R_TO_MIXINR                   0x0020  /* IN1R_TO_MIXINR */
1150 #define WM8993_IN1R_TO_MIXINR_MASK              0x0020  /* IN1R_TO_MIXINR */
1151 #define WM8993_IN1R_TO_MIXINR_SHIFT                  5  /* IN1R_TO_MIXINR */
1152 #define WM8993_IN1R_TO_MIXINR_WIDTH                  1  /* IN1R_TO_MIXINR */
1153 #define WM8993_IN1R_MIXINR_VOL                  0x0010  /* IN1R_MIXINR_VOL */
1154 #define WM8993_IN1R_MIXINR_VOL_MASK             0x0010  /* IN1R_MIXINR_VOL */
1155 #define WM8993_IN1R_MIXINR_VOL_SHIFT                 4  /* IN1R_MIXINR_VOL */
1156 #define WM8993_IN1R_MIXINR_VOL_WIDTH                 1  /* IN1R_MIXINR_VOL */
1157 #define WM8993_MIXOUTR_MIXINR_VOL_MASK          0x0007  /* MIXOUTR_MIXINR_VOL - [2:0] */
1158 #define WM8993_MIXOUTR_MIXINR_VOL_SHIFT              0  /* MIXOUTR_MIXINR_VOL - [2:0] */
1159 #define WM8993_MIXOUTR_MIXINR_VOL_WIDTH              3  /* MIXOUTR_MIXINR_VOL - [2:0] */
1160
1161 /*
1162  * R43 (0x2B) - Input Mixer5
1163  */
1164 #define WM8993_IN1LP_MIXINL_VOL_MASK            0x01C0  /* IN1LP_MIXINL_VOL - [8:6] */
1165 #define WM8993_IN1LP_MIXINL_VOL_SHIFT                6  /* IN1LP_MIXINL_VOL - [8:6] */
1166 #define WM8993_IN1LP_MIXINL_VOL_WIDTH                3  /* IN1LP_MIXINL_VOL - [8:6] */
1167 #define WM8993_VRX_MIXINL_VOL_MASK              0x0007  /* VRX_MIXINL_VOL - [2:0] */
1168 #define WM8993_VRX_MIXINL_VOL_SHIFT                  0  /* VRX_MIXINL_VOL - [2:0] */
1169 #define WM8993_VRX_MIXINL_VOL_WIDTH                  3  /* VRX_MIXINL_VOL - [2:0] */
1170
1171 /*
1172  * R44 (0x2C) - Input Mixer6
1173  */
1174 #define WM8993_IN1RP_MIXINR_VOL_MASK            0x01C0  /* IN1RP_MIXINR_VOL - [8:6] */
1175 #define WM8993_IN1RP_MIXINR_VOL_SHIFT                6  /* IN1RP_MIXINR_VOL - [8:6] */
1176 #define WM8993_IN1RP_MIXINR_VOL_WIDTH                3  /* IN1RP_MIXINR_VOL - [8:6] */
1177 #define WM8993_VRX_MIXINR_VOL_MASK              0x0007  /* VRX_MIXINR_VOL - [2:0] */
1178 #define WM8993_VRX_MIXINR_VOL_SHIFT                  0  /* VRX_MIXINR_VOL - [2:0] */
1179 #define WM8993_VRX_MIXINR_VOL_WIDTH                  3  /* VRX_MIXINR_VOL - [2:0] */
1180
1181 /*
1182  * R45 (0x2D) - Output Mixer1
1183  */
1184 #define WM8993_DACL_TO_HPOUT1L                  0x0100  /* DACL_TO_HPOUT1L */
1185 #define WM8993_DACL_TO_HPOUT1L_MASK             0x0100  /* DACL_TO_HPOUT1L */
1186 #define WM8993_DACL_TO_HPOUT1L_SHIFT                 8  /* DACL_TO_HPOUT1L */
1187 #define WM8993_DACL_TO_HPOUT1L_WIDTH                 1  /* DACL_TO_HPOUT1L */
1188 #define WM8993_MIXINR_TO_MIXOUTL                0x0080  /* MIXINR_TO_MIXOUTL */
1189 #define WM8993_MIXINR_TO_MIXOUTL_MASK           0x0080  /* MIXINR_TO_MIXOUTL */
1190 #define WM8993_MIXINR_TO_MIXOUTL_SHIFT               7  /* MIXINR_TO_MIXOUTL */
1191 #define WM8993_MIXINR_TO_MIXOUTL_WIDTH               1  /* MIXINR_TO_MIXOUTL */
1192 #define WM8993_MIXINL_TO_MIXOUTL                0x0040  /* MIXINL_TO_MIXOUTL */
1193 #define WM8993_MIXINL_TO_MIXOUTL_MASK           0x0040  /* MIXINL_TO_MIXOUTL */
1194 #define WM8993_MIXINL_TO_MIXOUTL_SHIFT               6  /* MIXINL_TO_MIXOUTL */
1195 #define WM8993_MIXINL_TO_MIXOUTL_WIDTH               1  /* MIXINL_TO_MIXOUTL */
1196 #define WM8993_IN2RN_TO_MIXOUTL                 0x0020  /* IN2RN_TO_MIXOUTL */
1197 #define WM8993_IN2RN_TO_MIXOUTL_MASK            0x0020  /* IN2RN_TO_MIXOUTL */
1198 #define WM8993_IN2RN_TO_MIXOUTL_SHIFT                5  /* IN2RN_TO_MIXOUTL */
1199 #define WM8993_IN2RN_TO_MIXOUTL_WIDTH                1  /* IN2RN_TO_MIXOUTL */
1200 #define WM8993_IN2LN_TO_MIXOUTL                 0x0010  /* IN2LN_TO_MIXOUTL */
1201 #define WM8993_IN2LN_TO_MIXOUTL_MASK            0x0010  /* IN2LN_TO_MIXOUTL */
1202 #define WM8993_IN2LN_TO_MIXOUTL_SHIFT                4  /* IN2LN_TO_MIXOUTL */
1203 #define WM8993_IN2LN_TO_MIXOUTL_WIDTH                1  /* IN2LN_TO_MIXOUTL */
1204 #define WM8993_IN1R_TO_MIXOUTL                  0x0008  /* IN1R_TO_MIXOUTL */
1205 #define WM8993_IN1R_TO_MIXOUTL_MASK             0x0008  /* IN1R_TO_MIXOUTL */
1206 #define WM8993_IN1R_TO_MIXOUTL_SHIFT                 3  /* IN1R_TO_MIXOUTL */
1207 #define WM8993_IN1R_TO_MIXOUTL_WIDTH                 1  /* IN1R_TO_MIXOUTL */
1208 #define WM8993_IN1L_TO_MIXOUTL                  0x0004  /* IN1L_TO_MIXOUTL */
1209 #define WM8993_IN1L_TO_MIXOUTL_MASK             0x0004  /* IN1L_TO_MIXOUTL */
1210 #define WM8993_IN1L_TO_MIXOUTL_SHIFT                 2  /* IN1L_TO_MIXOUTL */
1211 #define WM8993_IN1L_TO_MIXOUTL_WIDTH                 1  /* IN1L_TO_MIXOUTL */
1212 #define WM8993_IN2LP_TO_MIXOUTL                 0x0002  /* IN2LP_TO_MIXOUTL */
1213 #define WM8993_IN2LP_TO_MIXOUTL_MASK            0x0002  /* IN2LP_TO_MIXOUTL */
1214 #define WM8993_IN2LP_TO_MIXOUTL_SHIFT                1  /* IN2LP_TO_MIXOUTL */
1215 #define WM8993_IN2LP_TO_MIXOUTL_WIDTH                1  /* IN2LP_TO_MIXOUTL */
1216 #define WM8993_DACL_TO_MIXOUTL                  0x0001  /* DACL_TO_MIXOUTL */
1217 #define WM8993_DACL_TO_MIXOUTL_MASK             0x0001  /* DACL_TO_MIXOUTL */
1218 #define WM8993_DACL_TO_MIXOUTL_SHIFT                 0  /* DACL_TO_MIXOUTL */
1219 #define WM8993_DACL_TO_MIXOUTL_WIDTH                 1  /* DACL_TO_MIXOUTL */
1220
1221 /*
1222  * R46 (0x2E) - Output Mixer2
1223  */
1224 #define WM8993_DACR_TO_HPOUT1R                  0x0100  /* DACR_TO_HPOUT1R */
1225 #define WM8993_DACR_TO_HPOUT1R_MASK             0x0100  /* DACR_TO_HPOUT1R */
1226 #define WM8993_DACR_TO_HPOUT1R_SHIFT                 8  /* DACR_TO_HPOUT1R */
1227 #define WM8993_DACR_TO_HPOUT1R_WIDTH                 1  /* DACR_TO_HPOUT1R */
1228 #define WM8993_MIXINL_TO_MIXOUTR                0x0080  /* MIXINL_TO_MIXOUTR */
1229 #define WM8993_MIXINL_TO_MIXOUTR_MASK           0x0080  /* MIXINL_TO_MIXOUTR */
1230 #define WM8993_MIXINL_TO_MIXOUTR_SHIFT               7  /* MIXINL_TO_MIXOUTR */
1231 #define WM8993_MIXINL_TO_MIXOUTR_WIDTH               1  /* MIXINL_TO_MIXOUTR */
1232 #define WM8993_MIXINR_TO_MIXOUTR                0x0040  /* MIXINR_TO_MIXOUTR */
1233 #define WM8993_MIXINR_TO_MIXOUTR_MASK           0x0040  /* MIXINR_TO_MIXOUTR */
1234 #define WM8993_MIXINR_TO_MIXOUTR_SHIFT               6  /* MIXINR_TO_MIXOUTR */
1235 #define WM8993_MIXINR_TO_MIXOUTR_WIDTH               1  /* MIXINR_TO_MIXOUTR */
1236 #define WM8993_IN2LN_TO_MIXOUTR                 0x0020  /* IN2LN_TO_MIXOUTR */
1237 #define WM8993_IN2LN_TO_MIXOUTR_MASK            0x0020  /* IN2LN_TO_MIXOUTR */
1238 #define WM8993_IN2LN_TO_MIXOUTR_SHIFT                5  /* IN2LN_TO_MIXOUTR */
1239 #define WM8993_IN2LN_TO_MIXOUTR_WIDTH                1  /* IN2LN_TO_MIXOUTR */
1240 #define WM8993_IN2RN_TO_MIXOUTR                 0x0010  /* IN2RN_TO_MIXOUTR */
1241 #define WM8993_IN2RN_TO_MIXOUTR_MASK            0x0010  /* IN2RN_TO_MIXOUTR */
1242 #define WM8993_IN2RN_TO_MIXOUTR_SHIFT                4  /* IN2RN_TO_MIXOUTR */
1243 #define WM8993_IN2RN_TO_MIXOUTR_WIDTH                1  /* IN2RN_TO_MIXOUTR */
1244 #define WM8993_IN1L_TO_MIXOUTR                  0x0008  /* IN1L_TO_MIXOUTR */
1245 #define WM8993_IN1L_TO_MIXOUTR_MASK             0x0008  /* IN1L_TO_MIXOUTR */
1246 #define WM8993_IN1L_TO_MIXOUTR_SHIFT                 3  /* IN1L_TO_MIXOUTR */
1247 #define WM8993_IN1L_TO_MIXOUTR_WIDTH                 1  /* IN1L_TO_MIXOUTR */
1248 #define WM8993_IN1R_TO_MIXOUTR                  0x0004  /* IN1R_TO_MIXOUTR */
1249 #define WM8993_IN1R_TO_MIXOUTR_MASK             0x0004  /* IN1R_TO_MIXOUTR */
1250 #define WM8993_IN1R_TO_MIXOUTR_SHIFT                 2  /* IN1R_TO_MIXOUTR */
1251 #define WM8993_IN1R_TO_MIXOUTR_WIDTH                 1  /* IN1R_TO_MIXOUTR */
1252 #define WM8993_IN2RP_TO_MIXOUTR                 0x0002  /* IN2RP_TO_MIXOUTR */
1253 #define WM8993_IN2RP_TO_MIXOUTR_MASK            0x0002  /* IN2RP_TO_MIXOUTR */
1254 #define WM8993_IN2RP_TO_MIXOUTR_SHIFT                1  /* IN2RP_TO_MIXOUTR */
1255 #define WM8993_IN2RP_TO_MIXOUTR_WIDTH                1  /* IN2RP_TO_MIXOUTR */
1256 #define WM8993_DACR_TO_MIXOUTR                  0x0001  /* DACR_TO_MIXOUTR */
1257 #define WM8993_DACR_TO_MIXOUTR_MASK             0x0001  /* DACR_TO_MIXOUTR */
1258 #define WM8993_DACR_TO_MIXOUTR_SHIFT                 0  /* DACR_TO_MIXOUTR */
1259 #define WM8993_DACR_TO_MIXOUTR_WIDTH                 1  /* DACR_TO_MIXOUTR */
1260
1261 /*
1262  * R47 (0x2F) - Output Mixer3
1263  */
1264 #define WM8993_IN2LP_MIXOUTL_VOL_MASK           0x0E00  /* IN2LP_MIXOUTL_VOL - [11:9] */
1265 #define WM8993_IN2LP_MIXOUTL_VOL_SHIFT               9  /* IN2LP_MIXOUTL_VOL - [11:9] */
1266 #define WM8993_IN2LP_MIXOUTL_VOL_WIDTH               3  /* IN2LP_MIXOUTL_VOL - [11:9] */
1267 #define WM8993_IN2LN_MIXOUTL_VOL_MASK           0x01C0  /* IN2LN_MIXOUTL_VOL - [8:6] */
1268 #define WM8993_IN2LN_MIXOUTL_VOL_SHIFT               6  /* IN2LN_MIXOUTL_VOL - [8:6] */
1269 #define WM8993_IN2LN_MIXOUTL_VOL_WIDTH               3  /* IN2LN_MIXOUTL_VOL - [8:6] */
1270 #define WM8993_IN1R_MIXOUTL_VOL_MASK            0x0038  /* IN1R_MIXOUTL_VOL - [5:3] */
1271 #define WM8993_IN1R_MIXOUTL_VOL_SHIFT                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1272 #define WM8993_IN1R_MIXOUTL_VOL_WIDTH                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1273 #define WM8993_IN1L_MIXOUTL_VOL_MASK            0x0007  /* IN1L_MIXOUTL_VOL - [2:0] */
1274 #define WM8993_IN1L_MIXOUTL_VOL_SHIFT                0  /* IN1L_MIXOUTL_VOL - [2:0] */
1275 #define WM8993_IN1L_MIXOUTL_VOL_WIDTH                3  /* IN1L_MIXOUTL_VOL - [2:0] */
1276
1277 /*
1278  * R48 (0x30) - Output Mixer4
1279  */
1280 #define WM8993_IN2RP_MIXOUTR_VOL_MASK           0x0E00  /* IN2RP_MIXOUTR_VOL - [11:9] */
1281 #define WM8993_IN2RP_MIXOUTR_VOL_SHIFT               9  /* IN2RP_MIXOUTR_VOL - [11:9] */
1282 #define WM8993_IN2RP_MIXOUTR_VOL_WIDTH               3  /* IN2RP_MIXOUTR_VOL - [11:9] */
1283 #define WM8993_IN2RN_MIXOUTR_VOL_MASK           0x01C0  /* IN2RN_MIXOUTR_VOL - [8:6] */
1284 #define WM8993_IN2RN_MIXOUTR_VOL_SHIFT               6  /* IN2RN_MIXOUTR_VOL - [8:6] */
1285 #define WM8993_IN2RN_MIXOUTR_VOL_WIDTH               3  /* IN2RN_MIXOUTR_VOL - [8:6] */
1286 #define WM8993_IN1L_MIXOUTR_VOL_MASK            0x0038  /* IN1L_MIXOUTR_VOL - [5:3] */
1287 #define WM8993_IN1L_MIXOUTR_VOL_SHIFT                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1288 #define WM8993_IN1L_MIXOUTR_VOL_WIDTH                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1289 #define WM8993_IN1R_MIXOUTR_VOL_MASK            0x0007  /* IN1R_MIXOUTR_VOL - [2:0] */
1290 #define WM8993_IN1R_MIXOUTR_VOL_SHIFT                0  /* IN1R_MIXOUTR_VOL - [2:0] */
1291 #define WM8993_IN1R_MIXOUTR_VOL_WIDTH                3  /* IN1R_MIXOUTR_VOL - [2:0] */
1292
1293 /*
1294  * R49 (0x31) - Output Mixer5
1295  */
1296 #define WM8993_DACL_MIXOUTL_VOL_MASK            0x0E00  /* DACL_MIXOUTL_VOL - [11:9] */
1297 #define WM8993_DACL_MIXOUTL_VOL_SHIFT                9  /* DACL_MIXOUTL_VOL - [11:9] */
1298 #define WM8993_DACL_MIXOUTL_VOL_WIDTH                3  /* DACL_MIXOUTL_VOL - [11:9] */
1299 #define WM8993_IN2RN_MIXOUTL_VOL_MASK           0x01C0  /* IN2RN_MIXOUTL_VOL - [8:6] */
1300 #define WM8993_IN2RN_MIXOUTL_VOL_SHIFT               6  /* IN2RN_MIXOUTL_VOL - [8:6] */
1301 #define WM8993_IN2RN_MIXOUTL_VOL_WIDTH               3  /* IN2RN_MIXOUTL_VOL - [8:6] */
1302 #define WM8993_MIXINR_MIXOUTL_VOL_MASK          0x0038  /* MIXINR_MIXOUTL_VOL - [5:3] */
1303 #define WM8993_MIXINR_MIXOUTL_VOL_SHIFT              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1304 #define WM8993_MIXINR_MIXOUTL_VOL_WIDTH              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1305 #define WM8993_MIXINL_MIXOUTL_VOL_MASK          0x0007  /* MIXINL_MIXOUTL_VOL - [2:0] */
1306 #define WM8993_MIXINL_MIXOUTL_VOL_SHIFT              0  /* MIXINL_MIXOUTL_VOL - [2:0] */
1307 #define WM8993_MIXINL_MIXOUTL_VOL_WIDTH              3  /* MIXINL_MIXOUTL_VOL - [2:0] */
1308
1309 /*
1310  * R50 (0x32) - Output Mixer6
1311  */
1312 #define WM8993_DACR_MIXOUTR_VOL_MASK            0x0E00  /* DACR_MIXOUTR_VOL - [11:9] */
1313 #define WM8993_DACR_MIXOUTR_VOL_SHIFT                9  /* DACR_MIXOUTR_VOL - [11:9] */
1314 #define WM8993_DACR_MIXOUTR_VOL_WIDTH                3  /* DACR_MIXOUTR_VOL - [11:9] */
1315 #define WM8993_IN2LN_MIXOUTR_VOL_MASK           0x01C0  /* IN2LN_MIXOUTR_VOL - [8:6] */
1316 #define WM8993_IN2LN_MIXOUTR_VOL_SHIFT               6  /* IN2LN_MIXOUTR_VOL - [8:6] */
1317 #define WM8993_IN2LN_MIXOUTR_VOL_WIDTH               3  /* IN2LN_MIXOUTR_VOL - [8:6] */
1318 #define WM8993_MIXINL_MIXOUTR_VOL_MASK          0x0038  /* MIXINL_MIXOUTR_VOL - [5:3] */
1319 #define WM8993_MIXINL_MIXOUTR_VOL_SHIFT              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1320 #define WM8993_MIXINL_MIXOUTR_VOL_WIDTH              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1321 #define WM8993_MIXINR_MIXOUTR_VOL_MASK          0x0007  /* MIXINR_MIXOUTR_VOL - [2:0] */
1322 #define WM8993_MIXINR_MIXOUTR_VOL_SHIFT              0  /* MIXINR_MIXOUTR_VOL - [2:0] */
1323 #define WM8993_MIXINR_MIXOUTR_VOL_WIDTH              3  /* MIXINR_MIXOUTR_VOL - [2:0] */
1324
1325 /*
1326  * R51 (0x33) - HPOUT2 Mixer
1327  */
1328 #define WM8993_VRX_TO_HPOUT2                    0x0020  /* VRX_TO_HPOUT2 */
1329 #define WM8993_VRX_TO_HPOUT2_MASK               0x0020  /* VRX_TO_HPOUT2 */
1330 #define WM8993_VRX_TO_HPOUT2_SHIFT                   5  /* VRX_TO_HPOUT2 */
1331 #define WM8993_VRX_TO_HPOUT2_WIDTH                   1  /* VRX_TO_HPOUT2 */
1332 #define WM8993_MIXOUTLVOL_TO_HPOUT2             0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1333 #define WM8993_MIXOUTLVOL_TO_HPOUT2_MASK        0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1334 #define WM8993_MIXOUTLVOL_TO_HPOUT2_SHIFT            4  /* MIXOUTLVOL_TO_HPOUT2 */
1335 #define WM8993_MIXOUTLVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTLVOL_TO_HPOUT2 */
1336 #define WM8993_MIXOUTRVOL_TO_HPOUT2             0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1337 #define WM8993_MIXOUTRVOL_TO_HPOUT2_MASK        0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1338 #define WM8993_MIXOUTRVOL_TO_HPOUT2_SHIFT            3  /* MIXOUTRVOL_TO_HPOUT2 */
1339 #define WM8993_MIXOUTRVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTRVOL_TO_HPOUT2 */
1340
1341 /*
1342  * R52 (0x34) - Line Mixer1
1343  */
1344 #define WM8993_MIXOUTL_TO_LINEOUT1N             0x0040  /* MIXOUTL_TO_LINEOUT1N */
1345 #define WM8993_MIXOUTL_TO_LINEOUT1N_MASK        0x0040  /* MIXOUTL_TO_LINEOUT1N */
1346 #define WM8993_MIXOUTL_TO_LINEOUT1N_SHIFT            6  /* MIXOUTL_TO_LINEOUT1N */
1347 #define WM8993_MIXOUTL_TO_LINEOUT1N_WIDTH            1  /* MIXOUTL_TO_LINEOUT1N */
1348 #define WM8993_MIXOUTR_TO_LINEOUT1N             0x0020  /* MIXOUTR_TO_LINEOUT1N */
1349 #define WM8993_MIXOUTR_TO_LINEOUT1N_MASK        0x0020  /* MIXOUTR_TO_LINEOUT1N */
1350 #define WM8993_MIXOUTR_TO_LINEOUT1N_SHIFT            5  /* MIXOUTR_TO_LINEOUT1N */
1351 #define WM8993_MIXOUTR_TO_LINEOUT1N_WIDTH            1  /* MIXOUTR_TO_LINEOUT1N */
1352 #define WM8993_LINEOUT1_MODE                    0x0010  /* LINEOUT1_MODE */
1353 #define WM8993_LINEOUT1_MODE_MASK               0x0010  /* LINEOUT1_MODE */
1354 #define WM8993_LINEOUT1_MODE_SHIFT                   4  /* LINEOUT1_MODE */
1355 #define WM8993_LINEOUT1_MODE_WIDTH                   1  /* LINEOUT1_MODE */
1356 #define WM8993_IN1R_TO_LINEOUT1P                0x0004  /* IN1R_TO_LINEOUT1P */
1357 #define WM8993_IN1R_TO_LINEOUT1P_MASK           0x0004  /* IN1R_TO_LINEOUT1P */
1358 #define WM8993_IN1R_TO_LINEOUT1P_SHIFT               2  /* IN1R_TO_LINEOUT1P */
1359 #define WM8993_IN1R_TO_LINEOUT1P_WIDTH               1  /* IN1R_TO_LINEOUT1P */
1360 #define WM8993_IN1L_TO_LINEOUT1P                0x0002  /* IN1L_TO_LINEOUT1P */
1361 #define WM8993_IN1L_TO_LINEOUT1P_MASK           0x0002  /* IN1L_TO_LINEOUT1P */
1362 #define WM8993_IN1L_TO_LINEOUT1P_SHIFT               1  /* IN1L_TO_LINEOUT1P */
1363 #define WM8993_IN1L_TO_LINEOUT1P_WIDTH               1  /* IN1L_TO_LINEOUT1P */
1364 #define WM8993_MIXOUTL_TO_LINEOUT1P             0x0001  /* MIXOUTL_TO_LINEOUT1P */
1365 #define WM8993_MIXOUTL_TO_LINEOUT1P_MASK        0x0001  /* MIXOUTL_TO_LINEOUT1P */
1366 #define WM8993_MIXOUTL_TO_LINEOUT1P_SHIFT            0  /* MIXOUTL_TO_LINEOUT1P */
1367 #define WM8993_MIXOUTL_TO_LINEOUT1P_WIDTH            1  /* MIXOUTL_TO_LINEOUT1P */
1368
1369 /*
1370  * R53 (0x35) - Line Mixer2
1371  */
1372 #define WM8993_MIXOUTR_TO_LINEOUT2N             0x0040  /* MIXOUTR_TO_LINEOUT2N */
1373 #define WM8993_MIXOUTR_TO_LINEOUT2N_MASK        0x0040  /* MIXOUTR_TO_LINEOUT2N */
1374 #define WM8993_MIXOUTR_TO_LINEOUT2N_SHIFT            6  /* MIXOUTR_TO_LINEOUT2N */
1375 #define WM8993_MIXOUTR_TO_LINEOUT2N_WIDTH            1  /* MIXOUTR_TO_LINEOUT2N */
1376 #define WM8993_MIXOUTL_TO_LINEOUT2N             0x0020  /* MIXOUTL_TO_LINEOUT2N */
1377 #define WM8993_MIXOUTL_TO_LINEOUT2N_MASK        0x0020  /* MIXOUTL_TO_LINEOUT2N */
1378 #define WM8993_MIXOUTL_TO_LINEOUT2N_SHIFT            5  /* MIXOUTL_TO_LINEOUT2N */
1379 #define WM8993_MIXOUTL_TO_LINEOUT2N_WIDTH            1  /* MIXOUTL_TO_LINEOUT2N */
1380 #define WM8993_LINEOUT2_MODE                    0x0010  /* LINEOUT2_MODE */
1381 #define WM8993_LINEOUT2_MODE_MASK               0x0010  /* LINEOUT2_MODE */
1382 #define WM8993_LINEOUT2_MODE_SHIFT                   4  /* LINEOUT2_MODE */
1383 #define WM8993_LINEOUT2_MODE_WIDTH                   1  /* LINEOUT2_MODE */
1384 #define WM8993_IN1L_TO_LINEOUT2P                0x0004  /* IN1L_TO_LINEOUT2P */
1385 #define WM8993_IN1L_TO_LINEOUT2P_MASK           0x0004  /* IN1L_TO_LINEOUT2P */
1386 #define WM8993_IN1L_TO_LINEOUT2P_SHIFT               2  /* IN1L_TO_LINEOUT2P */
1387 #define WM8993_IN1L_TO_LINEOUT2P_WIDTH               1  /* IN1L_TO_LINEOUT2P */
1388 #define WM8993_IN1R_TO_LINEOUT2P                0x0002  /* IN1R_TO_LINEOUT2P */
1389 #define WM8993_IN1R_TO_LINEOUT2P_MASK           0x0002  /* IN1R_TO_LINEOUT2P */
1390 #define WM8993_IN1R_TO_LINEOUT2P_SHIFT               1  /* IN1R_TO_LINEOUT2P */
1391 #define WM8993_IN1R_TO_LINEOUT2P_WIDTH               1  /* IN1R_TO_LINEOUT2P */
1392 #define WM8993_MIXOUTR_TO_LINEOUT2P             0x0001  /* MIXOUTR_TO_LINEOUT2P */
1393 #define WM8993_MIXOUTR_TO_LINEOUT2P_MASK        0x0001  /* MIXOUTR_TO_LINEOUT2P */
1394 #define WM8993_MIXOUTR_TO_LINEOUT2P_SHIFT            0  /* MIXOUTR_TO_LINEOUT2P */
1395 #define WM8993_MIXOUTR_TO_LINEOUT2P_WIDTH            1  /* MIXOUTR_TO_LINEOUT2P */
1396
1397 /*
1398  * R54 (0x36) - Speaker Mixer
1399  */
1400 #define WM8993_SPKAB_REF_SEL                    0x0100  /* SPKAB_REF_SEL */
1401 #define WM8993_SPKAB_REF_SEL_MASK               0x0100  /* SPKAB_REF_SEL */
1402 #define WM8993_SPKAB_REF_SEL_SHIFT                   8  /* SPKAB_REF_SEL */
1403 #define WM8993_SPKAB_REF_SEL_WIDTH                   1  /* SPKAB_REF_SEL */
1404 #define WM8993_MIXINL_TO_SPKMIXL                0x0080  /* MIXINL_TO_SPKMIXL */
1405 #define WM8993_MIXINL_TO_SPKMIXL_MASK           0x0080  /* MIXINL_TO_SPKMIXL */
1406 #define WM8993_MIXINL_TO_SPKMIXL_SHIFT               7  /* MIXINL_TO_SPKMIXL */
1407 #define WM8993_MIXINL_TO_SPKMIXL_WIDTH               1  /* MIXINL_TO_SPKMIXL */
1408 #define WM8993_MIXINR_TO_SPKMIXR                0x0040  /* MIXINR_TO_SPKMIXR */
1409 #define WM8993_MIXINR_TO_SPKMIXR_MASK           0x0040  /* MIXINR_TO_SPKMIXR */
1410 #define WM8993_MIXINR_TO_SPKMIXR_SHIFT               6  /* MIXINR_TO_SPKMIXR */
1411 #define WM8993_MIXINR_TO_SPKMIXR_WIDTH               1  /* MIXINR_TO_SPKMIXR */
1412 #define WM8993_IN1LP_TO_SPKMIXL                 0x0020  /* IN1LP_TO_SPKMIXL */
1413 #define WM8993_IN1LP_TO_SPKMIXL_MASK            0x0020  /* IN1LP_TO_SPKMIXL */
1414 #define WM8993_IN1LP_TO_SPKMIXL_SHIFT                5  /* IN1LP_TO_SPKMIXL */
1415 #define WM8993_IN1LP_TO_SPKMIXL_WIDTH                1  /* IN1LP_TO_SPKMIXL */
1416 #define WM8993_IN1RP_TO_SPKMIXR                 0x0010  /* IN1RP_TO_SPKMIXR */
1417 #define WM8993_IN1RP_TO_SPKMIXR_MASK            0x0010  /* IN1RP_TO_SPKMIXR */
1418 #define WM8993_IN1RP_TO_SPKMIXR_SHIFT                4  /* IN1RP_TO_SPKMIXR */
1419 #define WM8993_IN1RP_TO_SPKMIXR_WIDTH                1  /* IN1RP_TO_SPKMIXR */
1420 #define WM8993_MIXOUTL_TO_SPKMIXL               0x0008  /* MIXOUTL_TO_SPKMIXL */
1421 #define WM8993_MIXOUTL_TO_SPKMIXL_MASK          0x0008  /* MIXOUTL_TO_SPKMIXL */
1422 #define WM8993_MIXOUTL_TO_SPKMIXL_SHIFT              3  /* MIXOUTL_TO_SPKMIXL */
1423 #define WM8993_MIXOUTL_TO_SPKMIXL_WIDTH              1  /* MIXOUTL_TO_SPKMIXL */
1424 #define WM8993_MIXOUTR_TO_SPKMIXR               0x0004  /* MIXOUTR_TO_SPKMIXR */
1425 #define WM8993_MIXOUTR_TO_SPKMIXR_MASK          0x0004  /* MIXOUTR_TO_SPKMIXR */
1426 #define WM8993_MIXOUTR_TO_SPKMIXR_SHIFT              2  /* MIXOUTR_TO_SPKMIXR */
1427 #define WM8993_MIXOUTR_TO_SPKMIXR_WIDTH              1  /* MIXOUTR_TO_SPKMIXR */
1428 #define WM8993_DACL_TO_SPKMIXL                  0x0002  /* DACL_TO_SPKMIXL */
1429 #define WM8993_DACL_TO_SPKMIXL_MASK             0x0002  /* DACL_TO_SPKMIXL */
1430 #define WM8993_DACL_TO_SPKMIXL_SHIFT                 1  /* DACL_TO_SPKMIXL */
1431 #define WM8993_DACL_TO_SPKMIXL_WIDTH                 1  /* DACL_TO_SPKMIXL */
1432 #define WM8993_DACR_TO_SPKMIXR                  0x0001  /* DACR_TO_SPKMIXR */
1433 #define WM8993_DACR_TO_SPKMIXR_MASK             0x0001  /* DACR_TO_SPKMIXR */
1434 #define WM8993_DACR_TO_SPKMIXR_SHIFT                 0  /* DACR_TO_SPKMIXR */
1435 #define WM8993_DACR_TO_SPKMIXR_WIDTH                 1  /* DACR_TO_SPKMIXR */
1436
1437 /*
1438  * R55 (0x37) - Additional Control
1439  */
1440 #define WM8993_LINEOUT1_FB                      0x0080  /* LINEOUT1_FB */
1441 #define WM8993_LINEOUT1_FB_MASK                 0x0080  /* LINEOUT1_FB */
1442 #define WM8993_LINEOUT1_FB_SHIFT                     7  /* LINEOUT1_FB */
1443 #define WM8993_LINEOUT1_FB_WIDTH                     1  /* LINEOUT1_FB */
1444 #define WM8993_LINEOUT2_FB                      0x0040  /* LINEOUT2_FB */
1445 #define WM8993_LINEOUT2_FB_MASK                 0x0040  /* LINEOUT2_FB */
1446 #define WM8993_LINEOUT2_FB_SHIFT                     6  /* LINEOUT2_FB */
1447 #define WM8993_LINEOUT2_FB_WIDTH                     1  /* LINEOUT2_FB */
1448 #define WM8993_VROI                             0x0001  /* VROI */
1449 #define WM8993_VROI_MASK                        0x0001  /* VROI */
1450 #define WM8993_VROI_SHIFT                            0  /* VROI */
1451 #define WM8993_VROI_WIDTH                            1  /* VROI */
1452
1453 /*
1454  * R56 (0x38) - AntiPOP1
1455  */
1456 #define WM8993_LINEOUT_VMID_BUF_ENA             0x0080  /* LINEOUT_VMID_BUF_ENA */
1457 #define WM8993_LINEOUT_VMID_BUF_ENA_MASK        0x0080  /* LINEOUT_VMID_BUF_ENA */
1458 #define WM8993_LINEOUT_VMID_BUF_ENA_SHIFT            7  /* LINEOUT_VMID_BUF_ENA */
1459 #define WM8993_LINEOUT_VMID_BUF_ENA_WIDTH            1  /* LINEOUT_VMID_BUF_ENA */
1460 #define WM8993_HPOUT2_IN_ENA                    0x0040  /* HPOUT2_IN_ENA */
1461 #define WM8993_HPOUT2_IN_ENA_MASK               0x0040  /* HPOUT2_IN_ENA */
1462 #define WM8993_HPOUT2_IN_ENA_SHIFT                   6  /* HPOUT2_IN_ENA */
1463 #define WM8993_HPOUT2_IN_ENA_WIDTH                   1  /* HPOUT2_IN_ENA */
1464 #define WM8993_LINEOUT1_DISCH                   0x0020  /* LINEOUT1_DISCH */
1465 #define WM8993_LINEOUT1_DISCH_MASK              0x0020  /* LINEOUT1_DISCH */
1466 #define WM8993_LINEOUT1_DISCH_SHIFT                  5  /* LINEOUT1_DISCH */
1467 #define WM8993_LINEOUT1_DISCH_WIDTH                  1  /* LINEOUT1_DISCH */
1468 #define WM8993_LINEOUT2_DISCH                   0x0010  /* LINEOUT2_DISCH */
1469 #define WM8993_LINEOUT2_DISCH_MASK              0x0010  /* LINEOUT2_DISCH */
1470 #define WM8993_LINEOUT2_DISCH_SHIFT                  4  /* LINEOUT2_DISCH */
1471 #define WM8993_LINEOUT2_DISCH_WIDTH                  1  /* LINEOUT2_DISCH */
1472
1473 /*
1474  * R57 (0x39) - AntiPOP2
1475  */
1476 #define WM8993_VMID_RAMP_MASK                   0x0060  /* VMID_RAMP - [6:5] */
1477 #define WM8993_VMID_RAMP_SHIFT                       5  /* VMID_RAMP - [6:5] */
1478 #define WM8993_VMID_RAMP_WIDTH                       2  /* VMID_RAMP - [6:5] */
1479 #define WM8993_VMID_BUF_ENA                     0x0008  /* VMID_BUF_ENA */
1480 #define WM8993_VMID_BUF_ENA_MASK                0x0008  /* VMID_BUF_ENA */
1481 #define WM8993_VMID_BUF_ENA_SHIFT                    3  /* VMID_BUF_ENA */
1482 #define WM8993_VMID_BUF_ENA_WIDTH                    1  /* VMID_BUF_ENA */
1483 #define WM8993_STARTUP_BIAS_ENA                 0x0004  /* STARTUP_BIAS_ENA */
1484 #define WM8993_STARTUP_BIAS_ENA_MASK            0x0004  /* STARTUP_BIAS_ENA */
1485 #define WM8993_STARTUP_BIAS_ENA_SHIFT                2  /* STARTUP_BIAS_ENA */
1486 #define WM8993_STARTUP_BIAS_ENA_WIDTH                1  /* STARTUP_BIAS_ENA */
1487 #define WM8993_BIAS_SRC                         0x0002  /* BIAS_SRC */
1488 #define WM8993_BIAS_SRC_MASK                    0x0002  /* BIAS_SRC */
1489 #define WM8993_BIAS_SRC_SHIFT                        1  /* BIAS_SRC */
1490 #define WM8993_BIAS_SRC_WIDTH                        1  /* BIAS_SRC */
1491 #define WM8993_VMID_DISCH                       0x0001  /* VMID_DISCH */
1492 #define WM8993_VMID_DISCH_MASK                  0x0001  /* VMID_DISCH */
1493 #define WM8993_VMID_DISCH_SHIFT                      0  /* VMID_DISCH */
1494 #define WM8993_VMID_DISCH_WIDTH                      1  /* VMID_DISCH */
1495
1496 /*
1497  * R58 (0x3A) - MICBIAS
1498  */
1499 #define WM8993_JD_SCTHR_MASK                    0x00C0  /* JD_SCTHR - [7:6] */
1500 #define WM8993_JD_SCTHR_SHIFT                        6  /* JD_SCTHR - [7:6] */
1501 #define WM8993_JD_SCTHR_WIDTH                        2  /* JD_SCTHR - [7:6] */
1502 #define WM8993_JD_THR_MASK                      0x0030  /* JD_THR - [5:4] */
1503 #define WM8993_JD_THR_SHIFT                          4  /* JD_THR - [5:4] */
1504 #define WM8993_JD_THR_WIDTH                          2  /* JD_THR - [5:4] */
1505 #define WM8993_JD_ENA                           0x0004  /* JD_ENA */
1506 #define WM8993_JD_ENA_MASK                      0x0004  /* JD_ENA */
1507 #define WM8993_JD_ENA_SHIFT                          2  /* JD_ENA */
1508 #define WM8993_JD_ENA_WIDTH                          1  /* JD_ENA */
1509 #define WM8993_MICB2_LVL                        0x0002  /* MICB2_LVL */
1510 #define WM8993_MICB2_LVL_MASK                   0x0002  /* MICB2_LVL */
1511 #define WM8993_MICB2_LVL_SHIFT                       1  /* MICB2_LVL */
1512 #define WM8993_MICB2_LVL_WIDTH                       1  /* MICB2_LVL */
1513 #define WM8993_MICB1_LVL                        0x0001  /* MICB1_LVL */
1514 #define WM8993_MICB1_LVL_MASK                   0x0001  /* MICB1_LVL */
1515 #define WM8993_MICB1_LVL_SHIFT                       0  /* MICB1_LVL */
1516 #define WM8993_MICB1_LVL_WIDTH                       1  /* MICB1_LVL */
1517
1518 /*
1519  * R60 (0x3C) - FLL Control 1
1520  */
1521 #define WM8993_FLL_FRAC                         0x0004  /* FLL_FRAC */
1522 #define WM8993_FLL_FRAC_MASK                    0x0004  /* FLL_FRAC */
1523 #define WM8993_FLL_FRAC_SHIFT                        2  /* FLL_FRAC */
1524 #define WM8993_FLL_FRAC_WIDTH                        1  /* FLL_FRAC */
1525 #define WM8993_FLL_OSC_ENA                      0x0002  /* FLL_OSC_ENA */
1526 #define WM8993_FLL_OSC_ENA_MASK                 0x0002  /* FLL_OSC_ENA */
1527 #define WM8993_FLL_OSC_ENA_SHIFT                     1  /* FLL_OSC_ENA */
1528 #define WM8993_FLL_OSC_ENA_WIDTH                     1  /* FLL_OSC_ENA */
1529 #define WM8993_FLL_ENA                          0x0001  /* FLL_ENA */
1530 #define WM8993_FLL_ENA_MASK                     0x0001  /* FLL_ENA */
1531 #define WM8993_FLL_ENA_SHIFT                         0  /* FLL_ENA */
1532 #define WM8993_FLL_ENA_WIDTH                         1  /* FLL_ENA */
1533
1534 /*
1535  * R61 (0x3D) - FLL Control 2
1536  */
1537 #define WM8993_FLL_OUTDIV_MASK                  0x0700  /* FLL_OUTDIV - [10:8] */
1538 #define WM8993_FLL_OUTDIV_SHIFT                      8  /* FLL_OUTDIV - [10:8] */
1539 #define WM8993_FLL_OUTDIV_WIDTH                      3  /* FLL_OUTDIV - [10:8] */
1540 #define WM8993_FLL_CTRL_RATE_MASK               0x0070  /* FLL_CTRL_RATE - [6:4] */
1541 #define WM8993_FLL_CTRL_RATE_SHIFT                   4  /* FLL_CTRL_RATE - [6:4] */
1542 #define WM8993_FLL_CTRL_RATE_WIDTH                   3  /* FLL_CTRL_RATE - [6:4] */
1543 #define WM8993_FLL_FRATIO_MASK                  0x0007  /* FLL_FRATIO - [2:0] */
1544 #define WM8993_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [2:0] */
1545 #define WM8993_FLL_FRATIO_WIDTH                      3  /* FLL_FRATIO - [2:0] */
1546
1547 /*
1548  * R62 (0x3E) - FLL Control 3
1549  */
1550 #define WM8993_FLL_K_MASK                       0xFFFF  /* FLL_K - [15:0] */
1551 #define WM8993_FLL_K_SHIFT                           0  /* FLL_K - [15:0] */
1552 #define WM8993_FLL_K_WIDTH                          16  /* FLL_K - [15:0] */
1553
1554 /*
1555  * R63 (0x3F) - FLL Control 4
1556  */
1557 #define WM8993_FLL_N_MASK                       0x7FE0  /* FLL_N - [14:5] */
1558 #define WM8993_FLL_N_SHIFT                           5  /* FLL_N - [14:5] */
1559 #define WM8993_FLL_N_WIDTH                          10  /* FLL_N - [14:5] */
1560 #define WM8993_FLL_GAIN_MASK                    0x000F  /* FLL_GAIN - [3:0] */
1561 #define WM8993_FLL_GAIN_SHIFT                        0  /* FLL_GAIN - [3:0] */
1562 #define WM8993_FLL_GAIN_WIDTH                        4  /* FLL_GAIN - [3:0] */
1563
1564 /*
1565  * R64 (0x40) - FLL Control 5
1566  */
1567 #define WM8993_FLL_FRC_NCO_VAL_MASK             0x1F80  /* FLL_FRC_NCO_VAL - [12:7] */
1568 #define WM8993_FLL_FRC_NCO_VAL_SHIFT                 7  /* FLL_FRC_NCO_VAL - [12:7] */
1569 #define WM8993_FLL_FRC_NCO_VAL_WIDTH                 6  /* FLL_FRC_NCO_VAL - [12:7] */
1570 #define WM8993_FLL_FRC_NCO                      0x0040  /* FLL_FRC_NCO */
1571 #define WM8993_FLL_FRC_NCO_MASK                 0x0040  /* FLL_FRC_NCO */
1572 #define WM8993_FLL_FRC_NCO_SHIFT                     6  /* FLL_FRC_NCO */
1573 #define WM8993_FLL_FRC_NCO_WIDTH                     1  /* FLL_FRC_NCO */
1574 #define WM8993_FLL_CLK_REF_DIV_MASK             0x0018  /* FLL_CLK_REF_DIV - [4:3] */
1575 #define WM8993_FLL_CLK_REF_DIV_SHIFT                 3  /* FLL_CLK_REF_DIV - [4:3] */
1576 #define WM8993_FLL_CLK_REF_DIV_WIDTH                 2  /* FLL_CLK_REF_DIV - [4:3] */
1577 #define WM8993_FLL_CLK_SRC_MASK                 0x0003  /* FLL_CLK_SRC - [1:0] */
1578 #define WM8993_FLL_CLK_SRC_SHIFT                     0  /* FLL_CLK_SRC - [1:0] */
1579 #define WM8993_FLL_CLK_SRC_WIDTH                     2  /* FLL_CLK_SRC - [1:0] */
1580
1581 /*
1582  * R65 (0x41) - Clocking 3
1583  */
1584 #define WM8993_CLK_DCS_DIV_MASK                 0x3C00  /* CLK_DCS_DIV - [13:10] */
1585 #define WM8993_CLK_DCS_DIV_SHIFT                    10  /* CLK_DCS_DIV - [13:10] */
1586 #define WM8993_CLK_DCS_DIV_WIDTH                     4  /* CLK_DCS_DIV - [13:10] */
1587 #define WM8993_SAMPLE_RATE_MASK                 0x0380  /* SAMPLE_RATE - [9:7] */
1588 #define WM8993_SAMPLE_RATE_SHIFT                     7  /* SAMPLE_RATE - [9:7] */
1589 #define WM8993_SAMPLE_RATE_WIDTH                     3  /* SAMPLE_RATE - [9:7] */
1590 #define WM8993_CLK_SYS_RATE_MASK                0x001E  /* CLK_SYS_RATE - [4:1] */
1591 #define WM8993_CLK_SYS_RATE_SHIFT                    1  /* CLK_SYS_RATE - [4:1] */
1592 #define WM8993_CLK_SYS_RATE_WIDTH                    4  /* CLK_SYS_RATE - [4:1] */
1593 #define WM8993_CLK_DSP_ENA                      0x0001  /* CLK_DSP_ENA */
1594 #define WM8993_CLK_DSP_ENA_MASK                 0x0001  /* CLK_DSP_ENA */
1595 #define WM8993_CLK_DSP_ENA_SHIFT                     0  /* CLK_DSP_ENA */
1596 #define WM8993_CLK_DSP_ENA_WIDTH                     1  /* CLK_DSP_ENA */
1597
1598 /*
1599  * R66 (0x42) - Clocking 4
1600  */
1601 #define WM8993_DAC_DIV4                         0x0200  /* DAC_DIV4 */
1602 #define WM8993_DAC_DIV4_MASK                    0x0200  /* DAC_DIV4 */
1603 #define WM8993_DAC_DIV4_SHIFT                        9  /* DAC_DIV4 */
1604 #define WM8993_DAC_DIV4_WIDTH                        1  /* DAC_DIV4 */
1605 #define WM8993_CLK_256K_DIV_MASK                0x007E  /* CLK_256K_DIV - [6:1] */
1606 #define WM8993_CLK_256K_DIV_SHIFT                    1  /* CLK_256K_DIV - [6:1] */
1607 #define WM8993_CLK_256K_DIV_WIDTH                    6  /* CLK_256K_DIV - [6:1] */
1608 #define WM8993_SR_MODE                          0x0001  /* SR_MODE */
1609 #define WM8993_SR_MODE_MASK                     0x0001  /* SR_MODE */
1610 #define WM8993_SR_MODE_SHIFT                         0  /* SR_MODE */
1611 #define WM8993_SR_MODE_WIDTH                         1  /* SR_MODE */
1612
1613 /*
1614  * R67 (0x43) - MW Slave Control
1615  */
1616 #define WM8993_MASK_WRITE_ENA                   0x0001  /* MASK_WRITE_ENA */
1617 #define WM8993_MASK_WRITE_ENA_MASK              0x0001  /* MASK_WRITE_ENA */
1618 #define WM8993_MASK_WRITE_ENA_SHIFT                  0  /* MASK_WRITE_ENA */
1619 #define WM8993_MASK_WRITE_ENA_WIDTH                  1  /* MASK_WRITE_ENA */
1620
1621 /*
1622  * R69 (0x45) - Bus Control 1
1623  */
1624 #define WM8993_CLK_SYS_ENA                      0x0002  /* CLK_SYS_ENA */
1625 #define WM8993_CLK_SYS_ENA_MASK                 0x0002  /* CLK_SYS_ENA */
1626 #define WM8993_CLK_SYS_ENA_SHIFT                     1  /* CLK_SYS_ENA */
1627 #define WM8993_CLK_SYS_ENA_WIDTH                     1  /* CLK_SYS_ENA */
1628
1629 /*
1630  * R70 (0x46) - Write Sequencer 0
1631  */
1632 #define WM8993_WSEQ_ENA                         0x0100  /* WSEQ_ENA */
1633 #define WM8993_WSEQ_ENA_MASK                    0x0100  /* WSEQ_ENA */
1634 #define WM8993_WSEQ_ENA_SHIFT                        8  /* WSEQ_ENA */
1635 #define WM8993_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
1636 #define WM8993_WSEQ_WRITE_INDEX_MASK            0x001F  /* WSEQ_WRITE_INDEX - [4:0] */
1637 #define WM8993_WSEQ_WRITE_INDEX_SHIFT                0  /* WSEQ_WRITE_INDEX - [4:0] */
1638 #define WM8993_WSEQ_WRITE_INDEX_WIDTH                5  /* WSEQ_WRITE_INDEX - [4:0] */
1639
1640 /*
1641  * R71 (0x47) - Write Sequencer 1
1642  */
1643 #define WM8993_WSEQ_DATA_WIDTH_MASK             0x7000  /* WSEQ_DATA_WIDTH - [14:12] */
1644 #define WM8993_WSEQ_DATA_WIDTH_SHIFT                12  /* WSEQ_DATA_WIDTH - [14:12] */
1645 #define WM8993_WSEQ_DATA_WIDTH_WIDTH                 3  /* WSEQ_DATA_WIDTH - [14:12] */
1646 #define WM8993_WSEQ_DATA_START_MASK             0x0F00  /* WSEQ_DATA_START - [11:8] */
1647 #define WM8993_WSEQ_DATA_START_SHIFT                 8  /* WSEQ_DATA_START - [11:8] */
1648 #define WM8993_WSEQ_DATA_START_WIDTH                 4  /* WSEQ_DATA_START - [11:8] */
1649 #define WM8993_WSEQ_ADDR_MASK                   0x00FF  /* WSEQ_ADDR - [7:0] */
1650 #define WM8993_WSEQ_ADDR_SHIFT                       0  /* WSEQ_ADDR - [7:0] */
1651 #define WM8993_WSEQ_ADDR_WIDTH                       8  /* WSEQ_ADDR - [7:0] */
1652
1653 /*
1654  * R72 (0x48) - Write Sequencer 2
1655  */
1656 #define WM8993_WSEQ_EOS                         0x4000  /* WSEQ_EOS */
1657 #define WM8993_WSEQ_EOS_MASK                    0x4000  /* WSEQ_EOS */
1658 #define WM8993_WSEQ_EOS_SHIFT                       14  /* WSEQ_EOS */
1659 #define WM8993_WSEQ_EOS_WIDTH                        1  /* WSEQ_EOS */
1660 #define WM8993_WSEQ_DELAY_MASK                  0x0F00  /* WSEQ_DELAY - [11:8] */
1661 #define WM8993_WSEQ_DELAY_SHIFT                      8  /* WSEQ_DELAY - [11:8] */
1662 #define WM8993_WSEQ_DELAY_WIDTH                      4  /* WSEQ_DELAY - [11:8] */
1663 #define WM8993_WSEQ_DATA_MASK                   0x00FF  /* WSEQ_DATA - [7:0] */
1664 #define WM8993_WSEQ_DATA_SHIFT                       0  /* WSEQ_DATA - [7:0] */
1665 #define WM8993_WSEQ_DATA_WIDTH                       8  /* WSEQ_DATA - [7:0] */
1666
1667 /*
1668  * R73 (0x49) - Write Sequencer 3
1669  */
1670 #define WM8993_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
1671 #define WM8993_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
1672 #define WM8993_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
1673 #define WM8993_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
1674 #define WM8993_WSEQ_START                       0x0100  /* WSEQ_START */
1675 #define WM8993_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
1676 #define WM8993_WSEQ_START_SHIFT                      8  /* WSEQ_START */
1677 #define WM8993_WSEQ_START_WIDTH                      1  /* WSEQ_START */
1678 #define WM8993_WSEQ_START_INDEX_MASK            0x003F  /* WSEQ_START_INDEX - [5:0] */
1679 #define WM8993_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [5:0] */
1680 #define WM8993_WSEQ_START_INDEX_WIDTH                6  /* WSEQ_START_INDEX - [5:0] */
1681
1682 /*
1683  * R74 (0x4A) - Write Sequencer 4
1684  */
1685 #define WM8993_WSEQ_BUSY                        0x0001  /* WSEQ_BUSY */
1686 #define WM8993_WSEQ_BUSY_MASK                   0x0001  /* WSEQ_BUSY */
1687 #define WM8993_WSEQ_BUSY_SHIFT                       0  /* WSEQ_BUSY */
1688 #define WM8993_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
1689
1690 /*
1691  * R75 (0x4B) - Write Sequencer 5
1692  */
1693 #define WM8993_WSEQ_CURRENT_INDEX_MASK          0x003F  /* WSEQ_CURRENT_INDEX - [5:0] */
1694 #define WM8993_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [5:0] */
1695 #define WM8993_WSEQ_CURRENT_INDEX_WIDTH              6  /* WSEQ_CURRENT_INDEX - [5:0] */
1696
1697 /*
1698  * R76 (0x4C) - Charge Pump 1
1699  */
1700 #define WM8993_CP_ENA                           0x8000  /* CP_ENA */
1701 #define WM8993_CP_ENA_MASK                      0x8000  /* CP_ENA */
1702 #define WM8993_CP_ENA_SHIFT                         15  /* CP_ENA */
1703 #define WM8993_CP_ENA_WIDTH                          1  /* CP_ENA */
1704
1705 /*
1706  * R81 (0x51) - Class W 0
1707  */
1708 #define WM8993_CP_DYN_FREQ                      0x0002  /* CP_DYN_FREQ */
1709 #define WM8993_CP_DYN_FREQ_MASK                 0x0002  /* CP_DYN_FREQ */
1710 #define WM8993_CP_DYN_FREQ_SHIFT                     1  /* CP_DYN_FREQ */
1711 #define WM8993_CP_DYN_FREQ_WIDTH                     1  /* CP_DYN_FREQ */
1712 #define WM8993_CP_DYN_V                         0x0001  /* CP_DYN_V */
1713 #define WM8993_CP_DYN_V_MASK                    0x0001  /* CP_DYN_V */
1714 #define WM8993_CP_DYN_V_SHIFT                        0  /* CP_DYN_V */
1715 #define WM8993_CP_DYN_V_WIDTH                        1  /* CP_DYN_V */
1716
1717 /*
1718  * R84 (0x54) - DC Servo 0
1719  */
1720 #define WM8993_DCS_TRIG_SINGLE_1                0x2000  /* DCS_TRIG_SINGLE_1 */
1721 #define WM8993_DCS_TRIG_SINGLE_1_MASK           0x2000  /* DCS_TRIG_SINGLE_1 */
1722 #define WM8993_DCS_TRIG_SINGLE_1_SHIFT              13  /* DCS_TRIG_SINGLE_1 */
1723 #define WM8993_DCS_TRIG_SINGLE_1_WIDTH               1  /* DCS_TRIG_SINGLE_1 */
1724 #define WM8993_DCS_TRIG_SINGLE_0                0x1000  /* DCS_TRIG_SINGLE_0 */
1725 #define WM8993_DCS_TRIG_SINGLE_0_MASK           0x1000  /* DCS_TRIG_SINGLE_0 */
1726 #define WM8993_DCS_TRIG_SINGLE_0_SHIFT              12  /* DCS_TRIG_SINGLE_0 */
1727 #define WM8993_DCS_TRIG_SINGLE_0_WIDTH               1  /* DCS_TRIG_SINGLE_0 */
1728 #define WM8993_DCS_TRIG_SERIES_1                0x0200  /* DCS_TRIG_SERIES_1 */
1729 #define WM8993_DCS_TRIG_SERIES_1_MASK           0x0200  /* DCS_TRIG_SERIES_1 */
1730 #define WM8993_DCS_TRIG_SERIES_1_SHIFT               9  /* DCS_TRIG_SERIES_1 */
1731 #define WM8993_DCS_TRIG_SERIES_1_WIDTH               1  /* DCS_TRIG_SERIES_1 */
1732 #define WM8993_DCS_TRIG_SERIES_0                0x0100  /* DCS_TRIG_SERIES_0 */
1733 #define WM8993_DCS_TRIG_SERIES_0_MASK           0x0100  /* DCS_TRIG_SERIES_0 */
1734 #define WM8993_DCS_TRIG_SERIES_0_SHIFT               8  /* DCS_TRIG_SERIES_0 */
1735 #define WM8993_DCS_TRIG_SERIES_0_WIDTH               1  /* DCS_TRIG_SERIES_0 */
1736 #define WM8993_DCS_TRIG_STARTUP_1               0x0020  /* DCS_TRIG_STARTUP_1 */
1737 #define WM8993_DCS_TRIG_STARTUP_1_MASK          0x0020  /* DCS_TRIG_STARTUP_1 */
1738 #define WM8993_DCS_TRIG_STARTUP_1_SHIFT              5  /* DCS_TRIG_STARTUP_1 */
1739 #define WM8993_DCS_TRIG_STARTUP_1_WIDTH              1  /* DCS_TRIG_STARTUP_1 */
1740 #define WM8993_DCS_TRIG_STARTUP_0               0x0010  /* DCS_TRIG_STARTUP_0 */
1741 #define WM8993_DCS_TRIG_STARTUP_0_MASK          0x0010  /* DCS_TRIG_STARTUP_0 */
1742 #define WM8993_DCS_TRIG_STARTUP_0_SHIFT              4  /* DCS_TRIG_STARTUP_0 */
1743 #define WM8993_DCS_TRIG_STARTUP_0_WIDTH              1  /* DCS_TRIG_STARTUP_0 */
1744 #define WM8993_DCS_TRIG_DAC_WR_1                0x0008  /* DCS_TRIG_DAC_WR_1 */
1745 #define WM8993_DCS_TRIG_DAC_WR_1_MASK           0x0008  /* DCS_TRIG_DAC_WR_1 */
1746 #define WM8993_DCS_TRIG_DAC_WR_1_SHIFT               3  /* DCS_TRIG_DAC_WR_1 */
1747 #define WM8993_DCS_TRIG_DAC_WR_1_WIDTH               1  /* DCS_TRIG_DAC_WR_1 */
1748 #define WM8993_DCS_TRIG_DAC_WR_0                0x0004  /* DCS_TRIG_DAC_WR_0 */
1749 #define WM8993_DCS_TRIG_DAC_WR_0_MASK           0x0004  /* DCS_TRIG_DAC_WR_0 */
1750 #define WM8993_DCS_TRIG_DAC_WR_0_SHIFT               2  /* DCS_TRIG_DAC_WR_0 */
1751 #define WM8993_DCS_TRIG_DAC_WR_0_WIDTH               1  /* DCS_TRIG_DAC_WR_0 */
1752 #define WM8993_DCS_ENA_CHAN_1                   0x0002  /* DCS_ENA_CHAN_1 */
1753 #define WM8993_DCS_ENA_CHAN_1_MASK              0x0002  /* DCS_ENA_CHAN_1 */
1754 #define WM8993_DCS_ENA_CHAN_1_SHIFT                  1  /* DCS_ENA_CHAN_1 */
1755 #define WM8993_DCS_ENA_CHAN_1_WIDTH                  1  /* DCS_ENA_CHAN_1 */
1756 #define WM8993_DCS_ENA_CHAN_0                   0x0001  /* DCS_ENA_CHAN_0 */
1757 #define WM8993_DCS_ENA_CHAN_0_MASK              0x0001  /* DCS_ENA_CHAN_0 */
1758 #define WM8993_DCS_ENA_CHAN_0_SHIFT                  0  /* DCS_ENA_CHAN_0 */
1759 #define WM8993_DCS_ENA_CHAN_0_WIDTH                  1  /* DCS_ENA_CHAN_0 */
1760
1761 /*
1762  * R85 (0x55) - DC Servo 1
1763  */
1764 #define WM8993_DCS_SERIES_NO_01_MASK            0x0FE0  /* DCS_SERIES_NO_01 - [11:5] */
1765 #define WM8993_DCS_SERIES_NO_01_SHIFT                5  /* DCS_SERIES_NO_01 - [11:5] */
1766 #define WM8993_DCS_SERIES_NO_01_WIDTH                7  /* DCS_SERIES_NO_01 - [11:5] */
1767 #define WM8993_DCS_TIMER_PERIOD_01_MASK         0x000F  /* DCS_TIMER_PERIOD_01 - [3:0] */
1768 #define WM8993_DCS_TIMER_PERIOD_01_SHIFT             0  /* DCS_TIMER_PERIOD_01 - [3:0] */
1769 #define WM8993_DCS_TIMER_PERIOD_01_WIDTH             4  /* DCS_TIMER_PERIOD_01 - [3:0] */
1770
1771 /*
1772  * R87 (0x57) - DC Servo 3
1773  */
1774 #define WM8993_DCS_DAC_WR_VAL_1_MASK            0xFF00  /* DCS_DAC_WR_VAL_1 - [15:8] */
1775 #define WM8993_DCS_DAC_WR_VAL_1_SHIFT                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
1776 #define WM8993_DCS_DAC_WR_VAL_1_WIDTH                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
1777 #define WM8993_DCS_DAC_WR_VAL_0_MASK            0x00FF  /* DCS_DAC_WR_VAL_0 - [7:0] */
1778 #define WM8993_DCS_DAC_WR_VAL_0_SHIFT                0  /* DCS_DAC_WR_VAL_0 - [7:0] */
1779 #define WM8993_DCS_DAC_WR_VAL_0_WIDTH                8  /* DCS_DAC_WR_VAL_0 - [7:0] */
1780
1781 /*
1782  * R88 (0x58) - DC Servo Readback 0
1783  */
1784 #define WM8993_DCS_DATAPATH_BUSY                0x4000  /* DCS_DATAPATH_BUSY */
1785 #define WM8993_DCS_DATAPATH_BUSY_MASK           0x4000  /* DCS_DATAPATH_BUSY */
1786 #define WM8993_DCS_DATAPATH_BUSY_SHIFT              14  /* DCS_DATAPATH_BUSY */
1787 #define WM8993_DCS_DATAPATH_BUSY_WIDTH               1  /* DCS_DATAPATH_BUSY */
1788 #define WM8993_DCS_CHANNEL_MASK                 0x3000  /* DCS_CHANNEL - [13:12] */
1789 #define WM8993_DCS_CHANNEL_SHIFT                    12  /* DCS_CHANNEL - [13:12] */
1790 #define WM8993_DCS_CHANNEL_WIDTH                     2  /* DCS_CHANNEL - [13:12] */
1791 #define WM8993_DCS_CAL_COMPLETE_MASK            0x0300  /* DCS_CAL_COMPLETE - [9:8] */
1792 #define WM8993_DCS_CAL_COMPLETE_SHIFT                8  /* DCS_CAL_COMPLETE - [9:8] */
1793 #define WM8993_DCS_CAL_COMPLETE_WIDTH                2  /* DCS_CAL_COMPLETE - [9:8] */
1794 #define WM8993_DCS_DAC_WR_COMPLETE_MASK         0x0030  /* DCS_DAC_WR_COMPLETE - [5:4] */
1795 #define WM8993_DCS_DAC_WR_COMPLETE_SHIFT             4  /* DCS_DAC_WR_COMPLETE - [5:4] */
1796 #define WM8993_DCS_DAC_WR_COMPLETE_WIDTH             2  /* DCS_DAC_WR_COMPLETE - [5:4] */
1797 #define WM8993_DCS_STARTUP_COMPLETE_MASK        0x0003  /* DCS_STARTUP_COMPLETE - [1:0] */
1798 #define WM8993_DCS_STARTUP_COMPLETE_SHIFT            0  /* DCS_STARTUP_COMPLETE - [1:0] */
1799 #define WM8993_DCS_STARTUP_COMPLETE_WIDTH            2  /* DCS_STARTUP_COMPLETE - [1:0] */
1800
1801 /*
1802  * R89 (0x59) - DC Servo Readback 1
1803  */
1804 #define WM8993_DCS_INTEG_CHAN_1_MASK            0x00FF  /* DCS_INTEG_CHAN_1 - [7:0] */
1805 #define WM8993_DCS_INTEG_CHAN_1_SHIFT                0  /* DCS_INTEG_CHAN_1 - [7:0] */
1806 #define WM8993_DCS_INTEG_CHAN_1_WIDTH                8  /* DCS_INTEG_CHAN_1 - [7:0] */
1807
1808 /*
1809  * R90 (0x5A) - DC Servo Readback 2
1810  */
1811 #define WM8993_DCS_INTEG_CHAN_0_MASK            0x00FF  /* DCS_INTEG_CHAN_0 - [7:0] */
1812 #define WM8993_DCS_INTEG_CHAN_0_SHIFT                0  /* DCS_INTEG_CHAN_0 - [7:0] */
1813 #define WM8993_DCS_INTEG_CHAN_0_WIDTH                8  /* DCS_INTEG_CHAN_0 - [7:0] */
1814
1815 /*
1816  * R96 (0x60) - Analogue HP 0
1817  */
1818 #define WM8993_HPOUT1_AUTO_PU                   0x0100  /* HPOUT1_AUTO_PU */
1819 #define WM8993_HPOUT1_AUTO_PU_MASK              0x0100  /* HPOUT1_AUTO_PU */
1820 #define WM8993_HPOUT1_AUTO_PU_SHIFT                  8  /* HPOUT1_AUTO_PU */
1821 #define WM8993_HPOUT1_AUTO_PU_WIDTH                  1  /* HPOUT1_AUTO_PU */
1822 #define WM8993_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
1823 #define WM8993_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
1824 #define WM8993_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
1825 #define WM8993_HPOUT1L_RMV_SHORT_WIDTH               1  /* HPOUT1L_RMV_SHORT */
1826 #define WM8993_HPOUT1L_OUTP                     0x0040  /* HPOUT1L_OUTP */
1827 #define WM8993_HPOUT1L_OUTP_MASK                0x0040  /* HPOUT1L_OUTP */
1828 #define WM8993_HPOUT1L_OUTP_SHIFT                    6  /* HPOUT1L_OUTP */
1829 #define WM8993_HPOUT1L_OUTP_WIDTH                    1  /* HPOUT1L_OUTP */
1830 #define WM8993_HPOUT1L_DLY                      0x0020  /* HPOUT1L_DLY */
1831 #define WM8993_HPOUT1L_DLY_MASK                 0x0020  /* HPOUT1L_DLY */
1832 #define WM8993_HPOUT1L_DLY_SHIFT                     5  /* HPOUT1L_DLY */
1833 #define WM8993_HPOUT1L_DLY_WIDTH                     1  /* HPOUT1L_DLY */
1834 #define WM8993_HPOUT1R_RMV_SHORT                0x0008  /* HPOUT1R_RMV_SHORT */
1835 #define WM8993_HPOUT1R_RMV_SHORT_MASK           0x0008  /* HPOUT1R_RMV_SHORT */
1836 #define WM8993_HPOUT1R_RMV_SHORT_SHIFT               3  /* HPOUT1R_RMV_SHORT */
1837 #define WM8993_HPOUT1R_RMV_SHORT_WIDTH               1  /* HPOUT1R_RMV_SHORT */
1838 #define WM8993_HPOUT1R_OUTP                     0x0004  /* HPOUT1R_OUTP */
1839 #define WM8993_HPOUT1R_OUTP_MASK                0x0004  /* HPOUT1R_OUTP */
1840 #define WM8993_HPOUT1R_OUTP_SHIFT                    2  /* HPOUT1R_OUTP */
1841 #define WM8993_HPOUT1R_OUTP_WIDTH                    1  /* HPOUT1R_OUTP */
1842 #define WM8993_HPOUT1R_DLY                      0x0002  /* HPOUT1R_DLY */
1843 #define WM8993_HPOUT1R_DLY_MASK                 0x0002  /* HPOUT1R_DLY */
1844 #define WM8993_HPOUT1R_DLY_SHIFT                     1  /* HPOUT1R_DLY */
1845 #define WM8993_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
1846
1847 /*
1848  * R98 (0x62) - EQ1
1849  */
1850 #define WM8993_EQ_ENA                           0x0001  /* EQ_ENA */
1851 #define WM8993_EQ_ENA_MASK                      0x0001  /* EQ_ENA */
1852 #define WM8993_EQ_ENA_SHIFT                          0  /* EQ_ENA */
1853 #define WM8993_EQ_ENA_WIDTH                          1  /* EQ_ENA */
1854
1855 /*
1856  * R99 (0x63) - EQ2
1857  */
1858 #define WM8993_EQ_B1_GAIN_MASK                  0x001F  /* EQ_B1_GAIN - [4:0] */
1859 #define WM8993_EQ_B1_GAIN_SHIFT                      0  /* EQ_B1_GAIN - [4:0] */
1860 #define WM8993_EQ_B1_GAIN_WIDTH                      5  /* EQ_B1_GAIN - [4:0] */
1861
1862 /*
1863  * R100 (0x64) - EQ3
1864  */
1865 #define WM8993_EQ_B2_GAIN_MASK                  0x001F  /* EQ_B2_GAIN - [4:0] */
1866 #define WM8993_EQ_B2_GAIN_SHIFT                      0  /* EQ_B2_GAIN - [4:0] */
1867 #define WM8993_EQ_B2_GAIN_WIDTH                      5  /* EQ_B2_GAIN - [4:0] */
1868
1869 /*
1870  * R101 (0x65) - EQ4
1871  */
1872 #define WM8993_EQ_B3_GAIN_MASK                  0x001F  /* EQ_B3_GAIN - [4:0] */
1873 #define WM8993_EQ_B3_GAIN_SHIFT                      0  /* EQ_B3_GAIN - [4:0] */
1874 #define WM8993_EQ_B3_GAIN_WIDTH                      5  /* EQ_B3_GAIN - [4:0] */
1875
1876 /*
1877  * R102 (0x66) - EQ5
1878  */
1879 #define WM8993_EQ_B4_GAIN_MASK                  0x001F  /* EQ_B4_GAIN - [4:0] */
1880 #define WM8993_EQ_B4_GAIN_SHIFT                      0  /* EQ_B4_GAIN - [4:0] */
1881 #define WM8993_EQ_B4_GAIN_WIDTH                      5  /* EQ_B4_GAIN - [4:0] */
1882
1883 /*
1884  * R103 (0x67) - EQ6
1885  */
1886 #define WM8993_EQ_B5_GAIN_MASK                  0x001F  /* EQ_B5_GAIN - [4:0] */
1887 #define WM8993_EQ_B5_GAIN_SHIFT                      0  /* EQ_B5_GAIN - [4:0] */
1888 #define WM8993_EQ_B5_GAIN_WIDTH                      5  /* EQ_B5_GAIN - [4:0] */
1889
1890 /*
1891  * R104 (0x68) - EQ7
1892  */
1893 #define WM8993_EQ_B1_A_MASK                     0xFFFF  /* EQ_B1_A - [15:0] */
1894 #define WM8993_EQ_B1_A_SHIFT                         0  /* EQ_B1_A - [15:0] */
1895 #define WM8993_EQ_B1_A_WIDTH                        16  /* EQ_B1_A - [15:0] */
1896
1897 /*
1898  * R105 (0x69) - EQ8
1899  */
1900 #define WM8993_EQ_B1_B_MASK                     0xFFFF  /* EQ_B1_B - [15:0] */
1901 #define WM8993_EQ_B1_B_SHIFT                         0  /* EQ_B1_B - [15:0] */
1902 #define WM8993_EQ_B1_B_WIDTH                        16  /* EQ_B1_B - [15:0] */
1903
1904 /*
1905  * R106 (0x6A) - EQ9
1906  */
1907 #define WM8993_EQ_B1_PG_MASK                    0xFFFF  /* EQ_B1_PG - [15:0] */
1908 #define WM8993_EQ_B1_PG_SHIFT                        0  /* EQ_B1_PG - [15:0] */
1909 #define WM8993_EQ_B1_PG_WIDTH                       16  /* EQ_B1_PG - [15:0] */
1910
1911 /*
1912  * R107 (0x6B) - EQ10
1913  */
1914 #define WM8993_EQ_B2_A_MASK                     0xFFFF  /* EQ_B2_A - [15:0] */
1915 #define WM8993_EQ_B2_A_SHIFT                         0  /* EQ_B2_A - [15:0] */
1916 #define WM8993_EQ_B2_A_WIDTH                        16  /* EQ_B2_A - [15:0] */
1917
1918 /*
1919  * R108 (0x6C) - EQ11
1920  */
1921 #define WM8993_EQ_B2_B_MASK                     0xFFFF  /* EQ_B2_B - [15:0] */
1922 #define WM8993_EQ_B2_B_SHIFT                         0  /* EQ_B2_B - [15:0] */
1923 #define WM8993_EQ_B2_B_WIDTH                        16  /* EQ_B2_B - [15:0] */
1924
1925 /*
1926  * R109 (0x6D) - EQ12
1927  */
1928 #define WM8993_EQ_B2_C_MASK                     0xFFFF  /* EQ_B2_C - [15:0] */
1929 #define WM8993_EQ_B2_C_SHIFT                         0  /* EQ_B2_C - [15:0] */
1930 #define WM8993_EQ_B2_C_WIDTH                        16  /* EQ_B2_C - [15:0] */
1931
1932 /*
1933  * R110 (0x6E) - EQ13
1934  */
1935 #define WM8993_EQ_B2_PG_MASK                    0xFFFF  /* EQ_B2_PG - [15:0] */
1936 #define WM8993_EQ_B2_PG_SHIFT                        0  /* EQ_B2_PG - [15:0] */
1937 #define WM8993_EQ_B2_PG_WIDTH                       16  /* EQ_B2_PG - [15:0] */
1938
1939 /*
1940  * R111 (0x6F) - EQ14
1941  */
1942 #define WM8993_EQ_B3_A_MASK                     0xFFFF  /* EQ_B3_A - [15:0] */
1943 #define WM8993_EQ_B3_A_SHIFT                         0  /* EQ_B3_A - [15:0] */
1944 #define WM8993_EQ_B3_A_WIDTH                        16  /* EQ_B3_A - [15:0] */
1945
1946 /*
1947  * R112 (0x70) - EQ15
1948  */
1949 #define WM8993_EQ_B3_B_MASK                     0xFFFF  /* EQ_B3_B - [15:0] */
1950 #define WM8993_EQ_B3_B_SHIFT                         0  /* EQ_B3_B - [15:0] */
1951 #define WM8993_EQ_B3_B_WIDTH                        16  /* EQ_B3_B - [15:0] */
1952
1953 /*
1954  * R113 (0x71) - EQ16
1955  */
1956 #define WM8993_EQ_B3_C_MASK                     0xFFFF  /* EQ_B3_C - [15:0] */
1957 #define WM8993_EQ_B3_C_SHIFT                         0  /* EQ_B3_C - [15:0] */
1958 #define WM8993_EQ_B3_C_WIDTH                        16  /* EQ_B3_C - [15:0] */
1959
1960 /*
1961  * R114 (0x72) - EQ17
1962  */
1963 #define WM8993_EQ_B3_PG_MASK                    0xFFFF  /* EQ_B3_PG - [15:0] */
1964 #define WM8993_EQ_B3_PG_SHIFT                        0  /* EQ_B3_PG - [15:0] */
1965 #define WM8993_EQ_B3_PG_WIDTH                       16  /* EQ_B3_PG - [15:0] */
1966
1967 /*
1968  * R115 (0x73) - EQ18
1969  */
1970 #define WM8993_EQ_B4_A_MASK                     0xFFFF  /* EQ_B4_A - [15:0] */
1971 #define WM8993_EQ_B4_A_SHIFT                         0  /* EQ_B4_A - [15:0] */
1972 #define WM8993_EQ_B4_A_WIDTH                        16  /* EQ_B4_A - [15:0] */
1973
1974 /*
1975  * R116 (0x74) - EQ19
1976  */
1977 #define WM8993_EQ_B4_B_MASK                     0xFFFF  /* EQ_B4_B - [15:0] */
1978 #define WM8993_EQ_B4_B_SHIFT                         0  /* EQ_B4_B - [15:0] */
1979 #define WM8993_EQ_B4_B_WIDTH                        16  /* EQ_B4_B - [15:0] */
1980
1981 /*
1982  * R117 (0x75) - EQ20
1983  */
1984 #define WM8993_EQ_B4_C_MASK                     0xFFFF  /* EQ_B4_C - [15:0] */
1985 #define WM8993_EQ_B4_C_SHIFT                         0  /* EQ_B4_C - [15:0] */
1986 #define WM8993_EQ_B4_C_WIDTH                        16  /* EQ_B4_C - [15:0] */
1987
1988 /*
1989  * R118 (0x76) - EQ21
1990  */
1991 #define WM8993_EQ_B4_PG_MASK                    0xFFFF  /* EQ_B4_PG - [15:0] */
1992 #define WM8993_EQ_B4_PG_SHIFT                        0  /* EQ_B4_PG - [15:0] */
1993 #define WM8993_EQ_B4_PG_WIDTH                       16  /* EQ_B4_PG - [15:0] */
1994
1995 /*
1996  * R119 (0x77) - EQ22
1997  */
1998 #define WM8993_EQ_B5_A_MASK                     0xFFFF  /* EQ_B5_A - [15:0] */
1999 #define WM8993_EQ_B5_A_SHIFT                         0  /* EQ_B5_A - [15:0] */
2000 #define WM8993_EQ_B5_A_WIDTH                        16  /* EQ_B5_A - [15:0] */
2001
2002 /*
2003  * R120 (0x78) - EQ23
2004  */
2005 #define WM8993_EQ_B5_B_MASK                     0xFFFF  /* EQ_B5_B - [15:0] */
2006 #define WM8993_EQ_B5_B_SHIFT                         0  /* EQ_B5_B - [15:0] */
2007 #define WM8993_EQ_B5_B_WIDTH                        16  /* EQ_B5_B - [15:0] */
2008
2009 /*
2010  * R121 (0x79) - EQ24
2011  */
2012 #define WM8993_EQ_B5_PG_MASK                    0xFFFF  /* EQ_B5_PG - [15:0] */
2013 #define WM8993_EQ_B5_PG_SHIFT                        0  /* EQ_B5_PG - [15:0] */
2014 #define WM8993_EQ_B5_PG_WIDTH                       16  /* EQ_B5_PG - [15:0] */
2015
2016 /*
2017  * R122 (0x7A) - Digital Pulls
2018  */
2019 #define WM8993_MCLK_PU                          0x0080  /* MCLK_PU */
2020 #define WM8993_MCLK_PU_MASK                     0x0080  /* MCLK_PU */
2021 #define WM8993_MCLK_PU_SHIFT                         7  /* MCLK_PU */
2022 #define WM8993_MCLK_PU_WIDTH                         1  /* MCLK_PU */
2023 #define WM8993_MCLK_PD                          0x0040  /* MCLK_PD */
2024 #define WM8993_MCLK_PD_MASK                     0x0040  /* MCLK_PD */
2025 #define WM8993_MCLK_PD_SHIFT                         6  /* MCLK_PD */
2026 #define WM8993_MCLK_PD_WIDTH                         1  /* MCLK_PD */
2027 #define WM8993_DACDAT_PU                        0x0020  /* DACDAT_PU */
2028 #define WM8993_DACDAT_PU_MASK                   0x0020  /* DACDAT_PU */
2029 #define WM8993_DACDAT_PU_SHIFT                       5  /* DACDAT_PU */
2030 #define WM8993_DACDAT_PU_WIDTH                       1  /* DACDAT_PU */
2031 #define WM8993_DACDAT_PD                        0x0010  /* DACDAT_PD */
2032 #define WM8993_DACDAT_PD_MASK                   0x0010  /* DACDAT_PD */
2033 #define WM8993_DACDAT_PD_SHIFT                       4  /* DACDAT_PD */
2034 #define WM8993_DACDAT_PD_WIDTH                       1  /* DACDAT_PD */
2035 #define WM8993_LRCLK_PU                         0x0008  /* LRCLK_PU */
2036 #define WM8993_LRCLK_PU_MASK                    0x0008  /* LRCLK_PU */
2037 #define WM8993_LRCLK_PU_SHIFT                        3  /* LRCLK_PU */
2038 #define WM8993_LRCLK_PU_WIDTH                        1  /* LRCLK_PU */
2039 #define WM8993_LRCLK_PD                         0x0004  /* LRCLK_PD */
2040 #define WM8993_LRCLK_PD_MASK                    0x0004  /* LRCLK_PD */
2041 #define WM8993_LRCLK_PD_SHIFT                        2  /* LRCLK_PD */
2042 #define WM8993_LRCLK_PD_WIDTH                        1  /* LRCLK_PD */
2043 #define WM8993_BCLK_PU                          0x0002  /* BCLK_PU */
2044 #define WM8993_BCLK_PU_MASK                     0x0002  /* BCLK_PU */
2045 #define WM8993_BCLK_PU_SHIFT                         1  /* BCLK_PU */
2046 #define WM8993_BCLK_PU_WIDTH                         1  /* BCLK_PU */
2047 #define WM8993_BCLK_PD                          0x0001  /* BCLK_PD */
2048 #define WM8993_BCLK_PD_MASK                     0x0001  /* BCLK_PD */
2049 #define WM8993_BCLK_PD_SHIFT                         0  /* BCLK_PD */
2050 #define WM8993_BCLK_PD_WIDTH                         1  /* BCLK_PD */
2051
2052 /*
2053  * R123 (0x7B) - DRC Control 1
2054  */
2055 #define WM8993_DRC_ENA                          0x8000  /* DRC_ENA */
2056 #define WM8993_DRC_ENA_MASK                     0x8000  /* DRC_ENA */
2057 #define WM8993_DRC_ENA_SHIFT                        15  /* DRC_ENA */
2058 #define WM8993_DRC_ENA_WIDTH                         1  /* DRC_ENA */
2059 #define WM8993_DRC_DAC_PATH                     0x4000  /* DRC_DAC_PATH */
2060 #define WM8993_DRC_DAC_PATH_MASK                0x4000  /* DRC_DAC_PATH */
2061 #define WM8993_DRC_DAC_PATH_SHIFT                   14  /* DRC_DAC_PATH */
2062 #define WM8993_DRC_DAC_PATH_WIDTH                    1  /* DRC_DAC_PATH */
2063 #define WM8993_DRC_SMOOTH_ENA                   0x0800  /* DRC_SMOOTH_ENA */
2064 #define WM8993_DRC_SMOOTH_ENA_MASK              0x0800  /* DRC_SMOOTH_ENA */
2065 #define WM8993_DRC_SMOOTH_ENA_SHIFT                 11  /* DRC_SMOOTH_ENA */
2066 #define WM8993_DRC_SMOOTH_ENA_WIDTH                  1  /* DRC_SMOOTH_ENA */
2067 #define WM8993_DRC_QR_ENA                       0x0400  /* DRC_QR_ENA */
2068 #define WM8993_DRC_QR_ENA_MASK                  0x0400  /* DRC_QR_ENA */
2069 #define WM8993_DRC_QR_ENA_SHIFT                     10  /* DRC_QR_ENA */
2070 #define WM8993_DRC_QR_ENA_WIDTH                      1  /* DRC_QR_ENA */
2071 #define WM8993_DRC_ANTICLIP_ENA                 0x0200  /* DRC_ANTICLIP_ENA */
2072 #define WM8993_DRC_ANTICLIP_ENA_MASK            0x0200  /* DRC_ANTICLIP_ENA */
2073 #define WM8993_DRC_ANTICLIP_ENA_SHIFT                9  /* DRC_ANTICLIP_ENA */
2074 #define WM8993_DRC_ANTICLIP_ENA_WIDTH                1  /* DRC_ANTICLIP_ENA */
2075 #define WM8993_DRC_HYST_ENA                     0x0100  /* DRC_HYST_ENA */
2076 #define WM8993_DRC_HYST_ENA_MASK                0x0100  /* DRC_HYST_ENA */
2077 #define WM8993_DRC_HYST_ENA_SHIFT                    8  /* DRC_HYST_ENA */
2078 #define WM8993_DRC_HYST_ENA_WIDTH                    1  /* DRC_HYST_ENA */
2079 #define WM8993_DRC_THRESH_HYST_MASK             0x0030  /* DRC_THRESH_HYST - [5:4] */
2080 #define WM8993_DRC_THRESH_HYST_SHIFT                 4  /* DRC_THRESH_HYST - [5:4] */
2081 #define WM8993_DRC_THRESH_HYST_WIDTH                 2  /* DRC_THRESH_HYST - [5:4] */
2082 #define WM8993_DRC_MINGAIN_MASK                 0x000C  /* DRC_MINGAIN - [3:2] */
2083 #define WM8993_DRC_MINGAIN_SHIFT                     2  /* DRC_MINGAIN - [3:2] */
2084 #define WM8993_DRC_MINGAIN_WIDTH                     2  /* DRC_MINGAIN - [3:2] */
2085 #define WM8993_DRC_MAXGAIN_MASK                 0x0003  /* DRC_MAXGAIN - [1:0] */
2086 #define WM8993_DRC_MAXGAIN_SHIFT                     0  /* DRC_MAXGAIN - [1:0] */
2087 #define WM8993_DRC_MAXGAIN_WIDTH                     2  /* DRC_MAXGAIN - [1:0] */
2088
2089 /*
2090  * R124 (0x7C) - DRC Control 2
2091  */
2092 #define WM8993_DRC_ATTACK_RATE_MASK             0xF000  /* DRC_ATTACK_RATE - [15:12] */
2093 #define WM8993_DRC_ATTACK_RATE_SHIFT                12  /* DRC_ATTACK_RATE - [15:12] */
2094 #define WM8993_DRC_ATTACK_RATE_WIDTH                 4  /* DRC_ATTACK_RATE - [15:12] */
2095 #define WM8993_DRC_DECAY_RATE_MASK              0x0F00  /* DRC_DECAY_RATE - [11:8] */
2096 #define WM8993_DRC_DECAY_RATE_SHIFT                  8  /* DRC_DECAY_RATE - [11:8] */
2097 #define WM8993_DRC_DECAY_RATE_WIDTH                  4  /* DRC_DECAY_RATE - [11:8] */
2098 #define WM8993_DRC_THRESH_COMP_MASK             0x00FC  /* DRC_THRESH_COMP - [7:2] */
2099 #define WM8993_DRC_THRESH_COMP_SHIFT                 2  /* DRC_THRESH_COMP - [7:2] */
2100 #define WM8993_DRC_THRESH_COMP_WIDTH                 6  /* DRC_THRESH_COMP - [7:2] */
2101
2102 /*
2103  * R125 (0x7D) - DRC Control 3
2104  */
2105 #define WM8993_DRC_AMP_COMP_MASK                0xF800  /* DRC_AMP_COMP - [15:11] */
2106 #define WM8993_DRC_AMP_COMP_SHIFT                   11  /* DRC_AMP_COMP - [15:11] */
2107 #define WM8993_DRC_AMP_COMP_WIDTH                    5  /* DRC_AMP_COMP - [15:11] */
2108 #define WM8993_DRC_R0_SLOPE_COMP_MASK           0x0700  /* DRC_R0_SLOPE_COMP - [10:8] */
2109 #define WM8993_DRC_R0_SLOPE_COMP_SHIFT               8  /* DRC_R0_SLOPE_COMP - [10:8] */
2110 #define WM8993_DRC_R0_SLOPE_COMP_WIDTH               3  /* DRC_R0_SLOPE_COMP - [10:8] */
2111 #define WM8993_DRC_FF_DELAY                     0x0080  /* DRC_FF_DELAY */
2112 #define WM8993_DRC_FF_DELAY_MASK                0x0080  /* DRC_FF_DELAY */
2113 #define WM8993_DRC_FF_DELAY_SHIFT                    7  /* DRC_FF_DELAY */
2114 #define WM8993_DRC_FF_DELAY_WIDTH                    1  /* DRC_FF_DELAY */
2115 #define WM8993_DRC_THRESH_QR_MASK               0x000C  /* DRC_THRESH_QR - [3:2] */
2116 #define WM8993_DRC_THRESH_QR_SHIFT                   2  /* DRC_THRESH_QR - [3:2] */
2117 #define WM8993_DRC_THRESH_QR_WIDTH                   2  /* DRC_THRESH_QR - [3:2] */
2118 #define WM8993_DRC_RATE_QR_MASK                 0x0003  /* DRC_RATE_QR - [1:0] */
2119 #define WM8993_DRC_RATE_QR_SHIFT                     0  /* DRC_RATE_QR - [1:0] */
2120 #define WM8993_DRC_RATE_QR_WIDTH                     2  /* DRC_RATE_QR - [1:0] */
2121
2122 /*
2123  * R126 (0x7E) - DRC Control 4
2124  */
2125 #define WM8993_DRC_R1_SLOPE_COMP_MASK           0xE000  /* DRC_R1_SLOPE_COMP - [15:13] */
2126 #define WM8993_DRC_R1_SLOPE_COMP_SHIFT              13  /* DRC_R1_SLOPE_COMP - [15:13] */
2127 #define WM8993_DRC_R1_SLOPE_COMP_WIDTH               3  /* DRC_R1_SLOPE_COMP - [15:13] */
2128 #define WM8993_DRC_STARTUP_GAIN_MASK            0x1F00  /* DRC_STARTUP_GAIN - [12:8] */
2129 #define WM8993_DRC_STARTUP_GAIN_SHIFT                8  /* DRC_STARTUP_GAIN - [12:8] */
2130 #define WM8993_DRC_STARTUP_GAIN_WIDTH                5  /* DRC_STARTUP_GAIN - [12:8] */
2131
2132 #endif