ASoC: Initial WM8993 regulator API hookup
[linux-2.6.git] / sound / soc / codecs / wm8993.c
1 /*
2  * wm8993.c -- WM8993 ALSA SoC audio driver
3  *
4  * Copyright 2009, 2010 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/tlv.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/wm8993.h>
29
30 #include "wm8993.h"
31 #include "wm_hubs.h"
32
33 #define WM8993_NUM_SUPPLIES 6
34 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
35         "DCVDD",
36         "DBVDD",
37         "AVDD1",
38         "AVDD2",
39         "CPVDD",
40         "SPKVDD",
41 };
42
43 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
44         0x8993,     /* R0   - Software Reset */
45         0x0000,     /* R1   - Power Management (1) */
46         0x6000,     /* R2   - Power Management (2) */
47         0x0000,     /* R3   - Power Management (3) */
48         0x4050,     /* R4   - Audio Interface (1) */
49         0x4000,     /* R5   - Audio Interface (2) */
50         0x01C8,     /* R6   - Clocking 1 */
51         0x0000,     /* R7   - Clocking 2 */
52         0x0000,     /* R8   - Audio Interface (3) */
53         0x0040,     /* R9   - Audio Interface (4) */
54         0x0004,     /* R10  - DAC CTRL */
55         0x00C0,     /* R11  - Left DAC Digital Volume */
56         0x00C0,     /* R12  - Right DAC Digital Volume */
57         0x0000,     /* R13  - Digital Side Tone */
58         0x0300,     /* R14  - ADC CTRL */
59         0x00C0,     /* R15  - Left ADC Digital Volume */
60         0x00C0,     /* R16  - Right ADC Digital Volume */
61         0x0000,     /* R17 */
62         0x0000,     /* R18  - GPIO CTRL 1 */
63         0x0010,     /* R19  - GPIO1 */
64         0x0000,     /* R20  - IRQ_DEBOUNCE */
65         0x0000,     /* R21 */
66         0x8000,     /* R22  - GPIOCTRL 2 */
67         0x0800,     /* R23  - GPIO_POL */
68         0x008B,     /* R24  - Left Line Input 1&2 Volume */
69         0x008B,     /* R25  - Left Line Input 3&4 Volume */
70         0x008B,     /* R26  - Right Line Input 1&2 Volume */
71         0x008B,     /* R27  - Right Line Input 3&4 Volume */
72         0x006D,     /* R28  - Left Output Volume */
73         0x006D,     /* R29  - Right Output Volume */
74         0x0066,     /* R30  - Line Outputs Volume */
75         0x0020,     /* R31  - HPOUT2 Volume */
76         0x0079,     /* R32  - Left OPGA Volume */
77         0x0079,     /* R33  - Right OPGA Volume */
78         0x0003,     /* R34  - SPKMIXL Attenuation */
79         0x0003,     /* R35  - SPKMIXR Attenuation */
80         0x0011,     /* R36  - SPKOUT Mixers */
81         0x0100,     /* R37  - SPKOUT Boost */
82         0x0079,     /* R38  - Speaker Volume Left */
83         0x0079,     /* R39  - Speaker Volume Right */
84         0x0000,     /* R40  - Input Mixer2 */
85         0x0000,     /* R41  - Input Mixer3 */
86         0x0000,     /* R42  - Input Mixer4 */
87         0x0000,     /* R43  - Input Mixer5 */
88         0x0000,     /* R44  - Input Mixer6 */
89         0x0000,     /* R45  - Output Mixer1 */
90         0x0000,     /* R46  - Output Mixer2 */
91         0x0000,     /* R47  - Output Mixer3 */
92         0x0000,     /* R48  - Output Mixer4 */
93         0x0000,     /* R49  - Output Mixer5 */
94         0x0000,     /* R50  - Output Mixer6 */
95         0x0000,     /* R51  - HPOUT2 Mixer */
96         0x0000,     /* R52  - Line Mixer1 */
97         0x0000,     /* R53  - Line Mixer2 */
98         0x0000,     /* R54  - Speaker Mixer */
99         0x0000,     /* R55  - Additional Control */
100         0x0000,     /* R56  - AntiPOP1 */
101         0x0000,     /* R57  - AntiPOP2 */
102         0x0000,     /* R58  - MICBIAS */
103         0x0000,     /* R59 */
104         0x0000,     /* R60  - FLL Control 1 */
105         0x0000,     /* R61  - FLL Control 2 */
106         0x0000,     /* R62  - FLL Control 3 */
107         0x2EE0,     /* R63  - FLL Control 4 */
108         0x0002,     /* R64  - FLL Control 5 */
109         0x2287,     /* R65  - Clocking 3 */
110         0x025F,     /* R66  - Clocking 4 */
111         0x0000,     /* R67  - MW Slave Control */
112         0x0000,     /* R68 */
113         0x0002,     /* R69  - Bus Control 1 */
114         0x0000,     /* R70  - Write Sequencer 0 */
115         0x0000,     /* R71  - Write Sequencer 1 */
116         0x0000,     /* R72  - Write Sequencer 2 */
117         0x0000,     /* R73  - Write Sequencer 3 */
118         0x0000,     /* R74  - Write Sequencer 4 */
119         0x0000,     /* R75  - Write Sequencer 5 */
120         0x1F25,     /* R76  - Charge Pump 1 */
121         0x0000,     /* R77 */
122         0x0000,     /* R78 */
123         0x0000,     /* R79 */
124         0x0000,     /* R80 */
125         0x0000,     /* R81  - Class W 0 */
126         0x0000,     /* R82 */
127         0x0000,     /* R83 */
128         0x0000,     /* R84  - DC Servo 0 */
129         0x054A,     /* R85  - DC Servo 1 */
130         0x0000,     /* R86 */
131         0x0000,     /* R87  - DC Servo 3 */
132         0x0000,     /* R88  - DC Servo Readback 0 */
133         0x0000,     /* R89  - DC Servo Readback 1 */
134         0x0000,     /* R90  - DC Servo Readback 2 */
135         0x0000,     /* R91 */
136         0x0000,     /* R92 */
137         0x0000,     /* R93 */
138         0x0000,     /* R94 */
139         0x0000,     /* R95 */
140         0x0100,     /* R96  - Analogue HP 0 */
141         0x0000,     /* R97 */
142         0x0000,     /* R98  - EQ1 */
143         0x000C,     /* R99  - EQ2 */
144         0x000C,     /* R100 - EQ3 */
145         0x000C,     /* R101 - EQ4 */
146         0x000C,     /* R102 - EQ5 */
147         0x000C,     /* R103 - EQ6 */
148         0x0FCA,     /* R104 - EQ7 */
149         0x0400,     /* R105 - EQ8 */
150         0x00D8,     /* R106 - EQ9 */
151         0x1EB5,     /* R107 - EQ10 */
152         0xF145,     /* R108 - EQ11 */
153         0x0B75,     /* R109 - EQ12 */
154         0x01C5,     /* R110 - EQ13 */
155         0x1C58,     /* R111 - EQ14 */
156         0xF373,     /* R112 - EQ15 */
157         0x0A54,     /* R113 - EQ16 */
158         0x0558,     /* R114 - EQ17 */
159         0x168E,     /* R115 - EQ18 */
160         0xF829,     /* R116 - EQ19 */
161         0x07AD,     /* R117 - EQ20 */
162         0x1103,     /* R118 - EQ21 */
163         0x0564,     /* R119 - EQ22 */
164         0x0559,     /* R120 - EQ23 */
165         0x4000,     /* R121 - EQ24 */
166         0x0000,     /* R122 - Digital Pulls */
167         0x0F08,     /* R123 - DRC Control 1 */
168         0x0000,     /* R124 - DRC Control 2 */
169         0x0080,     /* R125 - DRC Control 3 */
170         0x0000,     /* R126 - DRC Control 4 */
171 };
172
173 static struct {
174         int ratio;
175         int clk_sys_rate;
176 } clk_sys_rates[] = {
177         { 64,   0 },
178         { 128,  1 },
179         { 192,  2 },
180         { 256,  3 },
181         { 384,  4 },
182         { 512,  5 },
183         { 768,  6 },
184         { 1024, 7 },
185         { 1408, 8 },
186         { 1536, 9 },
187 };
188
189 static struct {
190         int rate;
191         int sample_rate;
192 } sample_rates[] = {
193         { 8000,  0  },
194         { 11025, 1  },
195         { 12000, 1  },
196         { 16000, 2  },
197         { 22050, 3  },
198         { 24000, 3  },
199         { 32000, 4  },
200         { 44100, 5  },
201         { 48000, 5  },
202 };
203
204 static struct {
205         int div; /* *10 due to .5s */
206         int bclk_div;
207 } bclk_divs[] = {
208         { 10,  0  },
209         { 15,  1  },
210         { 20,  2  },
211         { 30,  3  },
212         { 40,  4  },
213         { 55,  5  },
214         { 60,  6  },
215         { 80,  7  },
216         { 110, 8  },
217         { 120, 9  },
218         { 160, 10 },
219         { 220, 11 },
220         { 240, 12 },
221         { 320, 13 },
222         { 440, 14 },
223         { 480, 15 },
224 };
225
226 struct wm8993_priv {
227         struct wm_hubs_data hubs_data;
228         u16 reg_cache[WM8993_REGISTER_COUNT];
229         struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
230         struct wm8993_platform_data pdata;
231         struct snd_soc_codec codec;
232         int master;
233         int sysclk_source;
234         int tdm_slots;
235         int tdm_width;
236         unsigned int mclk_rate;
237         unsigned int sysclk_rate;
238         unsigned int fs;
239         unsigned int bclk;
240         int class_w_users;
241         unsigned int fll_fref;
242         unsigned int fll_fout;
243         int fll_src;
244 };
245
246 static int wm8993_volatile(unsigned int reg)
247 {
248         switch (reg) {
249         case WM8993_SOFTWARE_RESET:
250         case WM8993_DC_SERVO_0:
251         case WM8993_DC_SERVO_READBACK_0:
252         case WM8993_DC_SERVO_READBACK_1:
253         case WM8993_DC_SERVO_READBACK_2:
254                 return 1;
255         default:
256                 return 0;
257         }
258 }
259
260 struct _fll_div {
261         u16 fll_fratio;
262         u16 fll_outdiv;
263         u16 fll_clk_ref_div;
264         u16 n;
265         u16 k;
266 };
267
268 /* The size in bits of the FLL divide multiplied by 10
269  * to allow rounding later */
270 #define FIXED_FLL_SIZE ((1 << 16) * 10)
271
272 static struct {
273         unsigned int min;
274         unsigned int max;
275         u16 fll_fratio;
276         int ratio;
277 } fll_fratios[] = {
278         {       0,    64000, 4, 16 },
279         {   64000,   128000, 3,  8 },
280         {  128000,   256000, 2,  4 },
281         {  256000,  1000000, 1,  2 },
282         { 1000000, 13500000, 0,  1 },
283 };
284
285 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
286                        unsigned int Fout)
287 {
288         u64 Kpart;
289         unsigned int K, Ndiv, Nmod, target;
290         unsigned int div;
291         int i;
292
293         /* Fref must be <=13.5MHz */
294         div = 1;
295         fll_div->fll_clk_ref_div = 0;
296         while ((Fref / div) > 13500000) {
297                 div *= 2;
298                 fll_div->fll_clk_ref_div++;
299
300                 if (div > 8) {
301                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
302                                Fref);
303                         return -EINVAL;
304                 }
305         }
306
307         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
308
309         /* Apply the division for our remaining calculations */
310         Fref /= div;
311
312         /* Fvco should be 90-100MHz; don't check the upper bound */
313         div = 0;
314         target = Fout * 2;
315         while (target < 90000000) {
316                 div++;
317                 target *= 2;
318                 if (div > 7) {
319                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
320                                Fout);
321                         return -EINVAL;
322                 }
323         }
324         fll_div->fll_outdiv = div;
325
326         pr_debug("Fvco=%dHz\n", target);
327
328         /* Find an appropraite FLL_FRATIO and factor it out of the target */
329         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
330                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
331                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
332                         target /= fll_fratios[i].ratio;
333                         break;
334                 }
335         }
336         if (i == ARRAY_SIZE(fll_fratios)) {
337                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
338                 return -EINVAL;
339         }
340
341         /* Now, calculate N.K */
342         Ndiv = target / Fref;
343
344         fll_div->n = Ndiv;
345         Nmod = target % Fref;
346         pr_debug("Nmod=%d\n", Nmod);
347
348         /* Calculate fractional part - scale up so we can round. */
349         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
350
351         do_div(Kpart, Fref);
352
353         K = Kpart & 0xFFFFFFFF;
354
355         if ((K % 10) >= 5)
356                 K += 5;
357
358         /* Move down to proper range now rounding is done */
359         fll_div->k = K / 10;
360
361         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
362                  fll_div->n, fll_div->k,
363                  fll_div->fll_fratio, fll_div->fll_outdiv,
364                  fll_div->fll_clk_ref_div);
365
366         return 0;
367 }
368
369 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
370                           unsigned int Fref, unsigned int Fout)
371 {
372         struct snd_soc_codec *codec = dai->codec;
373         struct wm8993_priv *wm8993 = codec->private_data;
374         u16 reg1, reg4, reg5;
375         struct _fll_div fll_div;
376         int ret;
377
378         /* Any change? */
379         if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
380                 return 0;
381
382         /* Disable the FLL */
383         if (Fout == 0) {
384                 dev_dbg(codec->dev, "FLL disabled\n");
385                 wm8993->fll_fref = 0;
386                 wm8993->fll_fout = 0;
387
388                 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
389                 reg1 &= ~WM8993_FLL_ENA;
390                 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
391
392                 return 0;
393         }
394
395         ret = fll_factors(&fll_div, Fref, Fout);
396         if (ret != 0)
397                 return ret;
398
399         reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
400         reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
401
402         switch (fll_id) {
403         case WM8993_FLL_MCLK:
404                 break;
405
406         case WM8993_FLL_LRCLK:
407                 reg5 |= 1;
408                 break;
409
410         case WM8993_FLL_BCLK:
411                 reg5 |= 2;
412                 break;
413
414         default:
415                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
416                 return -EINVAL;
417         }
418
419         /* Any FLL configuration change requires that the FLL be
420          * disabled first. */
421         reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
422         reg1 &= ~WM8993_FLL_ENA;
423         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
424
425         /* Apply the configuration */
426         if (fll_div.k)
427                 reg1 |= WM8993_FLL_FRAC_MASK;
428         else
429                 reg1 &= ~WM8993_FLL_FRAC_MASK;
430         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
431
432         snd_soc_write(codec, WM8993_FLL_CONTROL_2,
433                       (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
434                       (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
435         snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
436
437         reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
438         reg4 &= ~WM8993_FLL_N_MASK;
439         reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
440         snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
441
442         reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
443         reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
444         snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
445
446         /* Enable the FLL */
447         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
448
449         dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
450
451         wm8993->fll_fref = Fref;
452         wm8993->fll_fout = Fout;
453         wm8993->fll_src = source;
454
455         return 0;
456 }
457
458 static int configure_clock(struct snd_soc_codec *codec)
459 {
460         struct wm8993_priv *wm8993 = codec->private_data;
461         unsigned int reg;
462
463         /* This should be done on init() for bypass paths */
464         switch (wm8993->sysclk_source) {
465         case WM8993_SYSCLK_MCLK:
466                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
467
468                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
469                 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
470                 if (wm8993->mclk_rate > 13500000) {
471                         reg |= WM8993_MCLK_DIV;
472                         wm8993->sysclk_rate = wm8993->mclk_rate / 2;
473                 } else {
474                         reg &= ~WM8993_MCLK_DIV;
475                         wm8993->sysclk_rate = wm8993->mclk_rate;
476                 }
477                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
478                 break;
479
480         case WM8993_SYSCLK_FLL:
481                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
482                         wm8993->fll_fout);
483
484                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
485                 reg |= WM8993_SYSCLK_SRC;
486                 if (wm8993->fll_fout > 13500000) {
487                         reg |= WM8993_MCLK_DIV;
488                         wm8993->sysclk_rate = wm8993->fll_fout / 2;
489                 } else {
490                         reg &= ~WM8993_MCLK_DIV;
491                         wm8993->sysclk_rate = wm8993->fll_fout;
492                 }
493                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
494                 break;
495
496         default:
497                 dev_err(codec->dev, "System clock not configured\n");
498                 return -EINVAL;
499         }
500
501         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
502
503         return 0;
504 }
505
506 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
507 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
508 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
509 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
510 static const unsigned int drc_max_tlv[] = {
511         TLV_DB_RANGE_HEAD(4),
512         0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
513         3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
514 };
515 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
516 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
517 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
518 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
519 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
520
521 static const char *dac_deemph_text[] = {
522         "None",
523         "32kHz",
524         "44.1kHz",
525         "48kHz",
526 };
527
528 static const struct soc_enum dac_deemph =
529         SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
530
531 static const char *adc_hpf_text[] = {
532         "Hi-Fi",
533         "Voice 1",
534         "Voice 2",
535         "Voice 3",
536 };
537
538 static const struct soc_enum adc_hpf =
539         SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
540
541 static const char *drc_path_text[] = {
542         "ADC",
543         "DAC"
544 };
545
546 static const struct soc_enum drc_path =
547         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
548
549 static const char *drc_r0_text[] = {
550         "1",
551         "1/2",
552         "1/4",
553         "1/8",
554         "1/16",
555         "0",
556 };
557
558 static const struct soc_enum drc_r0 =
559         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
560
561 static const char *drc_r1_text[] = {
562         "1",
563         "1/2",
564         "1/4",
565         "1/8",
566         "0",
567 };
568
569 static const struct soc_enum drc_r1 =
570         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
571
572 static const char *drc_attack_text[] = {
573         "Reserved",
574         "181us",
575         "363us",
576         "726us",
577         "1.45ms",
578         "2.9ms",
579         "5.8ms",
580         "11.6ms",
581         "23.2ms",
582         "46.4ms",
583         "92.8ms",
584         "185.6ms",
585 };
586
587 static const struct soc_enum drc_attack =
588         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
589
590 static const char *drc_decay_text[] = {
591         "186ms",
592         "372ms",
593         "743ms",
594         "1.49s",
595         "2.97ms",
596         "5.94ms",
597         "11.89ms",
598         "23.78ms",
599         "47.56ms",
600 };
601
602 static const struct soc_enum drc_decay =
603         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
604
605 static const char *drc_ff_text[] = {
606         "5 samples",
607         "9 samples",
608 };
609
610 static const struct soc_enum drc_ff =
611         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
612
613 static const char *drc_qr_rate_text[] = {
614         "0.725ms",
615         "1.45ms",
616         "5.8ms",
617 };
618
619 static const struct soc_enum drc_qr_rate =
620         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
621
622 static const char *drc_smooth_text[] = {
623         "Low",
624         "Medium",
625         "High",
626 };
627
628 static const struct soc_enum drc_smooth =
629         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
630
631 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
632 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
633                5, 9, 12, 0, sidetone_tlv),
634
635 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
636 SOC_ENUM("DRC Path", drc_path),
637 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
638                2, 60, 1, drc_comp_threash),
639 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
640                11, 30, 1, drc_comp_amp),
641 SOC_ENUM("DRC R0", drc_r0),
642 SOC_ENUM("DRC R1", drc_r1),
643 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
644                drc_min_tlv),
645 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
646                drc_max_tlv),
647 SOC_ENUM("DRC Attack Rate", drc_attack),
648 SOC_ENUM("DRC Decay Rate", drc_decay),
649 SOC_ENUM("DRC FF Delay", drc_ff),
650 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
651 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
652 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
653                drc_qr_tlv),
654 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
655 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
656 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
657 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
658 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
659                drc_startup_tlv),
660
661 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
662
663 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
664                  WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
665 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
666 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
667
668 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
669                  WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
670 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
671                dac_boost_tlv),
672 SOC_ENUM("DAC Deemphasis", dac_deemph),
673
674 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
675                2, 1, 1, wm_hubs_spkmix_tlv),
676
677 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
678                2, 1, 1, wm_hubs_spkmix_tlv),
679 };
680
681 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
682 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
683 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
684 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
685 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
686 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
687 };
688
689 static int clk_sys_event(struct snd_soc_dapm_widget *w,
690                          struct snd_kcontrol *kcontrol, int event)
691 {
692         struct snd_soc_codec *codec = w->codec;
693
694         switch (event) {
695         case SND_SOC_DAPM_PRE_PMU:
696                 return configure_clock(codec);
697
698         case SND_SOC_DAPM_POST_PMD:
699                 break;
700         }
701
702         return 0;
703 }
704
705 /*
706  * When used with DAC outputs only the WM8993 charge pump supports
707  * operation in class W mode, providing very low power consumption
708  * when used with digital sources.  Enable and disable this mode
709  * automatically depending on the mixer configuration.
710  *
711  * Currently the only supported paths are the direct DAC->headphone
712  * paths (which provide minimum power consumption anyway).
713  */
714 static int class_w_put(struct snd_kcontrol *kcontrol,
715                        struct snd_ctl_elem_value *ucontrol)
716 {
717         struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
718         struct snd_soc_codec *codec = widget->codec;
719         struct wm8993_priv *wm8993 = codec->private_data;
720         int ret;
721
722         /* Turn it off if we're using the main output mixer */
723         if (ucontrol->value.integer.value[0] == 0) {
724                 if (wm8993->class_w_users == 0) {
725                         dev_dbg(codec->dev, "Disabling Class W\n");
726                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
727                                             WM8993_CP_DYN_FREQ |
728                                             WM8993_CP_DYN_V,
729                                             0);
730                 }
731                 wm8993->class_w_users++;
732         }
733
734         /* Implement the change */
735         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
736
737         /* Enable it if we're using the direct DAC path */
738         if (ucontrol->value.integer.value[0] == 1) {
739                 if (wm8993->class_w_users == 1) {
740                         dev_dbg(codec->dev, "Enabling Class W\n");
741                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
742                                             WM8993_CP_DYN_FREQ |
743                                             WM8993_CP_DYN_V,
744                                             WM8993_CP_DYN_FREQ |
745                                             WM8993_CP_DYN_V);
746                 }
747                 wm8993->class_w_users--;
748         }
749
750         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
751                 wm8993->class_w_users);
752
753         return ret;
754 }
755
756 #define SOC_DAPM_ENUM_W(xname, xenum) \
757 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
758         .info = snd_soc_info_enum_double, \
759         .get = snd_soc_dapm_get_enum_double, \
760         .put = class_w_put, \
761         .private_value = (unsigned long)&xenum }
762
763 static const char *hp_mux_text[] = {
764         "Mixer",
765         "DAC",
766 };
767
768 static const struct soc_enum hpl_enum =
769         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
770
771 static const struct snd_kcontrol_new hpl_mux =
772         SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
773
774 static const struct soc_enum hpr_enum =
775         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
776
777 static const struct snd_kcontrol_new hpr_mux =
778         SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
779
780 static const struct snd_kcontrol_new left_speaker_mixer[] = {
781 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
782 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
783 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
784 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
785 };
786
787 static const struct snd_kcontrol_new right_speaker_mixer[] = {
788 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
789 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
790 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
791 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
792 };
793
794 static const char *aif_text[] = {
795         "Left", "Right"
796 };
797
798 static const struct soc_enum aifoutl_enum =
799         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
800
801 static const struct snd_kcontrol_new aifoutl_mux =
802         SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
803
804 static const struct soc_enum aifoutr_enum =
805         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
806
807 static const struct snd_kcontrol_new aifoutr_mux =
808         SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
809
810 static const struct soc_enum aifinl_enum =
811         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
812
813 static const struct snd_kcontrol_new aifinl_mux =
814         SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
815
816 static const struct soc_enum aifinr_enum =
817         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
818
819 static const struct snd_kcontrol_new aifinr_mux =
820         SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
821
822 static const char *sidetone_text[] = {
823         "None", "Left", "Right"
824 };
825
826 static const struct soc_enum sidetonel_enum =
827         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
828
829 static const struct snd_kcontrol_new sidetonel_mux =
830         SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
831
832 static const struct soc_enum sidetoner_enum =
833         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
834
835 static const struct snd_kcontrol_new sidetoner_mux =
836         SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
837
838 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
839 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
840                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
841 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
842 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
843
844 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
845 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
846
847 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
848 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
849
850 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
851 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
852
853 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
854 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
855
856 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
857 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
858
859 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
860 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
861
862 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
863 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
864
865 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
866 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
867
868 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
869                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
870 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
871                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
872
873 };
874
875 static const struct snd_soc_dapm_route routes[] = {
876         { "ADCL", NULL, "CLK_SYS" },
877         { "ADCL", NULL, "CLK_DSP" },
878         { "ADCR", NULL, "CLK_SYS" },
879         { "ADCR", NULL, "CLK_DSP" },
880
881         { "AIFOUTL Mux", "Left", "ADCL" },
882         { "AIFOUTL Mux", "Right", "ADCR" },
883         { "AIFOUTR Mux", "Left", "ADCL" },
884         { "AIFOUTR Mux", "Right", "ADCR" },
885
886         { "AIFOUTL", NULL, "AIFOUTL Mux" },
887         { "AIFOUTR", NULL, "AIFOUTR Mux" },
888
889         { "DACL Mux", "Left", "AIFINL" },
890         { "DACL Mux", "Right", "AIFINR" },
891         { "DACR Mux", "Left", "AIFINL" },
892         { "DACR Mux", "Right", "AIFINR" },
893
894         { "DACL Sidetone", "Left", "ADCL" },
895         { "DACL Sidetone", "Right", "ADCR" },
896         { "DACR Sidetone", "Left", "ADCL" },
897         { "DACR Sidetone", "Right", "ADCR" },
898
899         { "DACL", NULL, "CLK_SYS" },
900         { "DACL", NULL, "CLK_DSP" },
901         { "DACL", NULL, "DACL Mux" },
902         { "DACL", NULL, "DACL Sidetone" },
903         { "DACR", NULL, "CLK_SYS" },
904         { "DACR", NULL, "CLK_DSP" },
905         { "DACR", NULL, "DACR Mux" },
906         { "DACR", NULL, "DACR Sidetone" },
907
908         { "Left Output Mixer", "DAC Switch", "DACL" },
909
910         { "Right Output Mixer", "DAC Switch", "DACR" },
911
912         { "Left Output PGA", NULL, "CLK_SYS" },
913
914         { "Right Output PGA", NULL, "CLK_SYS" },
915
916         { "SPKL", "DAC Switch", "DACL" },
917         { "SPKL", NULL, "CLK_SYS" },
918
919         { "SPKR", "DAC Switch", "DACR" },
920         { "SPKR", NULL, "CLK_SYS" },
921
922         { "Left Headphone Mux", "DAC", "DACL" },
923         { "Right Headphone Mux", "DAC", "DACR" },
924 };
925
926 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
927                                  enum snd_soc_bias_level level)
928 {
929         struct wm8993_priv *wm8993 = codec->private_data;
930
931         switch (level) {
932         case SND_SOC_BIAS_ON:
933         case SND_SOC_BIAS_PREPARE:
934                 /* VMID=2*40k */
935                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
936                                     WM8993_VMID_SEL_MASK, 0x2);
937                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
938                                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
939                 break;
940
941         case SND_SOC_BIAS_STANDBY:
942                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
943                         /* Tune DC servo configuration */
944                         snd_soc_write(codec, 0x44, 3);
945                         snd_soc_write(codec, 0x56, 3);
946                         snd_soc_write(codec, 0x44, 0);
947
948                         /* Bring up VMID with fast soft start */
949                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
950                                             WM8993_STARTUP_BIAS_ENA |
951                                             WM8993_VMID_BUF_ENA |
952                                             WM8993_VMID_RAMP_MASK |
953                                             WM8993_BIAS_SRC,
954                                             WM8993_STARTUP_BIAS_ENA |
955                                             WM8993_VMID_BUF_ENA |
956                                             WM8993_VMID_RAMP_MASK |
957                                             WM8993_BIAS_SRC);
958
959                         /* If either line output is single ended we
960                          * need the VMID buffer */
961                         if (!wm8993->pdata.lineout1_diff ||
962                             !wm8993->pdata.lineout2_diff)
963                                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
964                                                  WM8993_LINEOUT_VMID_BUF_ENA,
965                                                  WM8993_LINEOUT_VMID_BUF_ENA);
966
967                         /* VMID=2*40k */
968                         snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
969                                             WM8993_VMID_SEL_MASK |
970                                             WM8993_BIAS_ENA,
971                                             WM8993_BIAS_ENA | 0x2);
972                         msleep(32);
973
974                         /* Switch to normal bias */
975                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
976                                             WM8993_BIAS_SRC |
977                                             WM8993_STARTUP_BIAS_ENA, 0);
978                 }
979
980                 /* VMID=2*240k */
981                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
982                                     WM8993_VMID_SEL_MASK, 0x4);
983
984                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
985                                     WM8993_TSHUT_ENA, 0);
986                 break;
987
988         case SND_SOC_BIAS_OFF:
989                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
990                                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
991
992                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
993                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
994                                     0);
995                 break;
996         }
997
998         codec->bias_level = level;
999
1000         return 0;
1001 }
1002
1003 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1004                              int clk_id, unsigned int freq, int dir)
1005 {
1006         struct snd_soc_codec *codec = codec_dai->codec;
1007         struct wm8993_priv *wm8993 = codec->private_data;
1008
1009         switch (clk_id) {
1010         case WM8993_SYSCLK_MCLK:
1011                 wm8993->mclk_rate = freq;
1012         case WM8993_SYSCLK_FLL:
1013                 wm8993->sysclk_source = clk_id;
1014                 break;
1015
1016         default:
1017                 return -EINVAL;
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1024                               unsigned int fmt)
1025 {
1026         struct snd_soc_codec *codec = dai->codec;
1027         struct wm8993_priv *wm8993 = codec->private_data;
1028         unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1029         unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1030
1031         aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1032                   WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1033         aif4 &= ~WM8993_LRCLK_DIR;
1034
1035         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1036         case SND_SOC_DAIFMT_CBS_CFS:
1037                 wm8993->master = 0;
1038                 break;
1039         case SND_SOC_DAIFMT_CBS_CFM:
1040                 aif4 |= WM8993_LRCLK_DIR;
1041                 wm8993->master = 1;
1042                 break;
1043         case SND_SOC_DAIFMT_CBM_CFS:
1044                 aif1 |= WM8993_BCLK_DIR;
1045                 wm8993->master = 1;
1046                 break;
1047         case SND_SOC_DAIFMT_CBM_CFM:
1048                 aif1 |= WM8993_BCLK_DIR;
1049                 aif4 |= WM8993_LRCLK_DIR;
1050                 wm8993->master = 1;
1051                 break;
1052         default:
1053                 return -EINVAL;
1054         }
1055
1056         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1057         case SND_SOC_DAIFMT_DSP_B:
1058                 aif1 |= WM8993_AIF_LRCLK_INV;
1059         case SND_SOC_DAIFMT_DSP_A:
1060                 aif1 |= 0x18;
1061                 break;
1062         case SND_SOC_DAIFMT_I2S:
1063                 aif1 |= 0x10;
1064                 break;
1065         case SND_SOC_DAIFMT_RIGHT_J:
1066                 break;
1067         case SND_SOC_DAIFMT_LEFT_J:
1068                 aif1 |= 0x8;
1069                 break;
1070         default:
1071                 return -EINVAL;
1072         }
1073
1074         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1075         case SND_SOC_DAIFMT_DSP_A:
1076         case SND_SOC_DAIFMT_DSP_B:
1077                 /* frame inversion not valid for DSP modes */
1078                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1079                 case SND_SOC_DAIFMT_NB_NF:
1080                         break;
1081                 case SND_SOC_DAIFMT_IB_NF:
1082                         aif1 |= WM8993_AIF_BCLK_INV;
1083                         break;
1084                 default:
1085                         return -EINVAL;
1086                 }
1087                 break;
1088
1089         case SND_SOC_DAIFMT_I2S:
1090         case SND_SOC_DAIFMT_RIGHT_J:
1091         case SND_SOC_DAIFMT_LEFT_J:
1092                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1093                 case SND_SOC_DAIFMT_NB_NF:
1094                         break;
1095                 case SND_SOC_DAIFMT_IB_IF:
1096                         aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1097                         break;
1098                 case SND_SOC_DAIFMT_IB_NF:
1099                         aif1 |= WM8993_AIF_BCLK_INV;
1100                         break;
1101                 case SND_SOC_DAIFMT_NB_IF:
1102                         aif1 |= WM8993_AIF_LRCLK_INV;
1103                         break;
1104                 default:
1105                         return -EINVAL;
1106                 }
1107                 break;
1108         default:
1109                 return -EINVAL;
1110         }
1111
1112         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1113         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1114
1115         return 0;
1116 }
1117
1118 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1119                             struct snd_pcm_hw_params *params,
1120                             struct snd_soc_dai *dai)
1121 {
1122         struct snd_soc_codec *codec = dai->codec;
1123         struct wm8993_priv *wm8993 = codec->private_data;
1124         int ret, i, best, best_val, cur_val;
1125         unsigned int clocking1, clocking3, aif1, aif4;
1126
1127         clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1128         clocking1 &= ~WM8993_BCLK_DIV_MASK;
1129
1130         clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1131         clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1132
1133         aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1134         aif1 &= ~WM8993_AIF_WL_MASK;
1135
1136         aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1137         aif4 &= ~WM8993_LRCLK_RATE_MASK;
1138
1139         /* What BCLK do we need? */
1140         wm8993->fs = params_rate(params);
1141         wm8993->bclk = 2 * wm8993->fs;
1142         if (wm8993->tdm_slots) {
1143                 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1144                         wm8993->tdm_slots, wm8993->tdm_width);
1145                 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1146         } else {
1147                 switch (params_format(params)) {
1148                 case SNDRV_PCM_FORMAT_S16_LE:
1149                         wm8993->bclk *= 16;
1150                         break;
1151                 case SNDRV_PCM_FORMAT_S20_3LE:
1152                         wm8993->bclk *= 20;
1153                         aif1 |= 0x8;
1154                         break;
1155                 case SNDRV_PCM_FORMAT_S24_LE:
1156                         wm8993->bclk *= 24;
1157                         aif1 |= 0x10;
1158                         break;
1159                 case SNDRV_PCM_FORMAT_S32_LE:
1160                         wm8993->bclk *= 32;
1161                         aif1 |= 0x18;
1162                         break;
1163                 default:
1164                         return -EINVAL;
1165                 }
1166         }
1167
1168         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1169
1170         ret = configure_clock(codec);
1171         if (ret != 0)
1172                 return ret;
1173
1174         /* Select nearest CLK_SYS_RATE */
1175         best = 0;
1176         best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1177                        - wm8993->fs);
1178         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1179                 cur_val = abs((wm8993->sysclk_rate /
1180                                clk_sys_rates[i].ratio) - wm8993->fs);;
1181                 if (cur_val < best_val) {
1182                         best = i;
1183                         best_val = cur_val;
1184                 }
1185         }
1186         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1187                 clk_sys_rates[best].ratio);
1188         clocking3 |= (clk_sys_rates[best].clk_sys_rate
1189                       << WM8993_CLK_SYS_RATE_SHIFT);
1190
1191         /* SAMPLE_RATE */
1192         best = 0;
1193         best_val = abs(wm8993->fs - sample_rates[0].rate);
1194         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1195                 /* Closest match */
1196                 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1197                 if (cur_val < best_val) {
1198                         best = i;
1199                         best_val = cur_val;
1200                 }
1201         }
1202         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1203                 sample_rates[best].rate);
1204         clocking3 |= (sample_rates[best].sample_rate
1205                       << WM8993_SAMPLE_RATE_SHIFT);
1206
1207         /* BCLK_DIV */
1208         best = 0;
1209         best_val = INT_MAX;
1210         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1211                 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1212                         - wm8993->bclk;
1213                 if (cur_val < 0) /* Table is sorted */
1214                         break;
1215                 if (cur_val < best_val) {
1216                         best = i;
1217                         best_val = cur_val;
1218                 }
1219         }
1220         wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1221         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1222                 bclk_divs[best].div, wm8993->bclk);
1223         clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1224
1225         /* LRCLK is a simple fraction of BCLK */
1226         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1227         aif4 |= wm8993->bclk / wm8993->fs;
1228
1229         snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1230         snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1231         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1232         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1233
1234         /* ReTune Mobile? */
1235         if (wm8993->pdata.num_retune_configs) {
1236                 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1237                 struct wm8993_retune_mobile_setting *s;
1238
1239                 best = 0;
1240                 best_val = abs(wm8993->pdata.retune_configs[0].rate
1241                                - wm8993->fs);
1242                 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1243                         cur_val = abs(wm8993->pdata.retune_configs[i].rate
1244                                       - wm8993->fs);
1245                         if (cur_val < best_val) {
1246                                 best_val = cur_val;
1247                                 best = i;
1248                         }
1249                 }
1250                 s = &wm8993->pdata.retune_configs[best];
1251
1252                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1253                         s->name, s->rate);
1254
1255                 /* Disable EQ while we reconfigure */
1256                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1257
1258                 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1259                         snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1260
1261                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1262         }
1263
1264         return 0;
1265 }
1266
1267 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1268 {
1269         struct snd_soc_codec *codec = codec_dai->codec;
1270         unsigned int reg;
1271
1272         reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1273
1274         if (mute)
1275                 reg |= WM8993_DAC_MUTE;
1276         else
1277                 reg &= ~WM8993_DAC_MUTE;
1278
1279         snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1280
1281         return 0;
1282 }
1283
1284 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1285                                unsigned int rx_mask, int slots, int slot_width)
1286 {
1287         struct snd_soc_codec *codec = dai->codec;
1288         struct wm8993_priv *wm8993 = codec->private_data;
1289         int aif1 = 0;
1290         int aif2 = 0;
1291
1292         /* Don't need to validate anything if we're turning off TDM */
1293         if (slots == 0) {
1294                 wm8993->tdm_slots = 0;
1295                 goto out;
1296         }
1297
1298         /* Note that we allow configurations we can't handle ourselves - 
1299          * for example, we can generate clocks for slots 2 and up even if
1300          * we can't use those slots ourselves.
1301          */
1302         aif1 |= WM8993_AIFADC_TDM;
1303         aif2 |= WM8993_AIFDAC_TDM;
1304
1305         switch (rx_mask) {
1306         case 3:
1307                 break;
1308         case 0xc:
1309                 aif1 |= WM8993_AIFADC_TDM_CHAN;
1310                 break;
1311         default:
1312                 return -EINVAL;
1313         }
1314
1315
1316         switch (tx_mask) {
1317         case 3:
1318                 break;
1319         case 0xc:
1320                 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1321                 break;
1322         default:
1323                 return -EINVAL;
1324         }
1325
1326 out:
1327         wm8993->tdm_width = slot_width;
1328         wm8993->tdm_slots = slots / 2;
1329
1330         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1331                             WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1332         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1333                             WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1334
1335         return 0;
1336 }
1337
1338 static struct snd_soc_dai_ops wm8993_ops = {
1339         .set_sysclk = wm8993_set_sysclk,
1340         .set_fmt = wm8993_set_dai_fmt,
1341         .hw_params = wm8993_hw_params,
1342         .digital_mute = wm8993_digital_mute,
1343         .set_pll = wm8993_set_fll,
1344         .set_tdm_slot = wm8993_set_tdm_slot,
1345 };
1346
1347 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1348
1349 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1350                         SNDRV_PCM_FMTBIT_S20_3LE |\
1351                         SNDRV_PCM_FMTBIT_S24_LE |\
1352                         SNDRV_PCM_FMTBIT_S32_LE)
1353
1354 struct snd_soc_dai wm8993_dai = {
1355         .name = "WM8993",
1356         .playback = {
1357                 .stream_name = "Playback",
1358                 .channels_min = 1,
1359                 .channels_max = 2,
1360                 .rates = WM8993_RATES,
1361                 .formats = WM8993_FORMATS,
1362         },
1363         .capture = {
1364                  .stream_name = "Capture",
1365                  .channels_min = 1,
1366                  .channels_max = 2,
1367                  .rates = WM8993_RATES,
1368                  .formats = WM8993_FORMATS,
1369          },
1370         .ops = &wm8993_ops,
1371         .symmetric_rates = 1,
1372 };
1373 EXPORT_SYMBOL_GPL(wm8993_dai);
1374
1375 static struct snd_soc_codec *wm8993_codec;
1376
1377 static int wm8993_probe(struct platform_device *pdev)
1378 {
1379         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1380         struct snd_soc_codec *codec;
1381         struct wm8993_priv *wm8993;
1382         int ret = 0;
1383
1384         if (!wm8993_codec) {
1385                 dev_err(&pdev->dev, "I2C device not yet probed\n");
1386                 goto err;
1387         }
1388
1389         socdev->card->codec = wm8993_codec;
1390         codec = wm8993_codec;
1391         wm8993 = codec->private_data;
1392
1393         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1394         if (ret < 0) {
1395                 dev_err(codec->dev, "failed to create pcms\n");
1396                 goto err;
1397         }
1398
1399         snd_soc_add_controls(codec, wm8993_snd_controls,
1400                              ARRAY_SIZE(wm8993_snd_controls));
1401         if (wm8993->pdata.num_retune_configs != 0) {
1402                 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1403         } else {
1404                 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1405                 snd_soc_add_controls(codec, wm8993_eq_controls,
1406                                      ARRAY_SIZE(wm8993_eq_controls));
1407         }
1408
1409         snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1410                                   ARRAY_SIZE(wm8993_dapm_widgets));
1411         wm_hubs_add_analogue_controls(codec);
1412
1413         snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1414         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1415                                     wm8993->pdata.lineout2_diff);
1416
1417         return ret;
1418
1419 err:
1420         return ret;
1421 }
1422
1423 static int wm8993_remove(struct platform_device *pdev)
1424 {
1425         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1426
1427         snd_soc_free_pcms(socdev);
1428         snd_soc_dapm_free(socdev);
1429
1430         return 0;
1431 }
1432
1433 #ifdef CONFIG_PM
1434 static int wm8993_suspend(struct platform_device *pdev, pm_message_t state)
1435 {
1436         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1437         struct snd_soc_codec *codec = socdev->card->codec;
1438         struct wm8993_priv *wm8993 = codec->private_data;
1439         int fll_fout = wm8993->fll_fout;
1440         int fll_fref  = wm8993->fll_fref;
1441         int ret;
1442
1443         /* Stop the FLL in an orderly fashion */
1444         ret = wm8993_set_fll(codec->dai, 0, 0, 0, 0);
1445         if (ret != 0) {
1446                 dev_err(&pdev->dev, "Failed to stop FLL\n");
1447                 return ret;
1448         }
1449
1450         wm8993->fll_fout = fll_fout;
1451         wm8993->fll_fref = fll_fref;
1452
1453         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1454
1455         return 0;
1456 }
1457
1458 static int wm8993_resume(struct platform_device *pdev)
1459 {
1460         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1461         struct snd_soc_codec *codec = socdev->card->codec;
1462         struct wm8993_priv *wm8993 = codec->private_data;
1463         u16 *cache = wm8993->reg_cache;
1464         int i, ret;
1465
1466         /* Restore the register settings */
1467         for (i = 1; i < WM8993_MAX_REGISTER; i++) {
1468                 if (cache[i] == wm8993_reg_defaults[i])
1469                         continue;
1470                 snd_soc_write(codec, i, cache[i]);
1471         }
1472
1473         wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1474
1475         /* Restart the FLL? */
1476         if (wm8993->fll_fout) {
1477                 int fll_fout = wm8993->fll_fout;
1478                 int fll_fref  = wm8993->fll_fref;
1479
1480                 wm8993->fll_fref = 0;
1481                 wm8993->fll_fout = 0;
1482
1483                 ret = wm8993_set_fll(codec->dai, 0, wm8993->fll_src,
1484                                      fll_fref, fll_fout);
1485                 if (ret != 0)
1486                         dev_err(codec->dev, "Failed to restart FLL\n");
1487         }
1488
1489         return 0;
1490 }
1491 #else
1492 #define wm8993_suspend NULL
1493 #define wm8993_resume NULL
1494 #endif
1495
1496 struct snd_soc_codec_device soc_codec_dev_wm8993 = {
1497         .probe =        wm8993_probe,
1498         .remove =       wm8993_remove,
1499         .suspend =      wm8993_suspend,
1500         .resume =       wm8993_resume,
1501 };
1502 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
1503
1504 static int wm8993_i2c_probe(struct i2c_client *i2c,
1505                             const struct i2c_device_id *id)
1506 {
1507         struct wm8993_priv *wm8993;
1508         struct snd_soc_codec *codec;
1509         unsigned int val;
1510         int ret;
1511         int i;
1512
1513         if (wm8993_codec) {
1514                 dev_err(&i2c->dev, "A WM8993 is already registered\n");
1515                 return -EINVAL;
1516         }
1517
1518         wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1519         if (wm8993 == NULL)
1520                 return -ENOMEM;
1521
1522         codec = &wm8993->codec;
1523         if (i2c->dev.platform_data)
1524                 memcpy(&wm8993->pdata, i2c->dev.platform_data,
1525                        sizeof(wm8993->pdata));
1526
1527         mutex_init(&codec->mutex);
1528         INIT_LIST_HEAD(&codec->dapm_widgets);
1529         INIT_LIST_HEAD(&codec->dapm_paths);
1530
1531         codec->name = "WM8993";
1532         codec->volatile_register = wm8993_volatile;
1533         codec->reg_cache = wm8993->reg_cache;
1534         codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
1535         codec->bias_level = SND_SOC_BIAS_OFF;
1536         codec->set_bias_level = wm8993_set_bias_level;
1537         codec->dai = &wm8993_dai;
1538         codec->num_dai = 1;
1539         codec->private_data = wm8993;
1540
1541         wm8993->hubs_data.hp_startup_mode = 1;
1542         wm8993->hubs_data.dcs_codes = -2;
1543
1544         memcpy(wm8993->reg_cache, wm8993_reg_defaults,
1545                sizeof(wm8993->reg_cache));
1546
1547         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1548         if (ret != 0) {
1549                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1550                 goto err;
1551         }
1552
1553         i2c_set_clientdata(i2c, wm8993);
1554         codec->control_data = i2c;
1555         wm8993_codec = codec;
1556
1557         codec->dev = &i2c->dev;
1558
1559         for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1560                 wm8993->supplies[i].supply = wm8993_supply_names[i];
1561
1562         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies),
1563                                  wm8993->supplies);
1564         if (ret != 0) {
1565                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1566                 goto err;
1567         }
1568
1569         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1570                                     wm8993->supplies);
1571         if (ret != 0) {
1572                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1573                 goto err_get;
1574         }
1575
1576         val = snd_soc_read(codec, WM8993_SOFTWARE_RESET);
1577         if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1578                 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1579                 ret = -EINVAL;
1580                 goto err_enable;
1581         }
1582
1583         ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1584         if (ret != 0)
1585                 goto err_enable;
1586
1587         /* By default we're using the output mixers */
1588         wm8993->class_w_users = 2;
1589
1590         /* Latch volume update bits and default ZC on */
1591         snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1592                             WM8993_DAC_VU, WM8993_DAC_VU);
1593         snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1594                             WM8993_ADC_VU, WM8993_ADC_VU);
1595
1596         /* Manualy manage the HPOUT sequencing for independent stereo
1597          * control. */
1598         snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1599                             WM8993_HPOUT1_AUTO_PU, 0);
1600
1601         /* Use automatic clock configuration */
1602         snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1603
1604         wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1605                                       wm8993->pdata.lineout2_diff,
1606                                       wm8993->pdata.lineout1fb,
1607                                       wm8993->pdata.lineout2fb,
1608                                       wm8993->pdata.jd_scthr,
1609                                       wm8993->pdata.jd_thr,
1610                                       wm8993->pdata.micbias1_lvl,
1611                                       wm8993->pdata.micbias2_lvl);
1612                              
1613         ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1614         if (ret != 0)
1615                 goto err_enable;
1616
1617         wm8993_dai.dev = codec->dev;
1618
1619         ret = snd_soc_register_dai(&wm8993_dai);
1620         if (ret != 0)
1621                 goto err_bias;
1622
1623         ret = snd_soc_register_codec(codec);
1624
1625         return 0;
1626
1627 err_bias:
1628         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1629 err_enable:
1630         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1631 err_get:
1632         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1633 err:
1634         wm8993_codec = NULL;
1635         kfree(wm8993);
1636         return ret;
1637 }
1638
1639 static int wm8993_i2c_remove(struct i2c_client *client)
1640 {
1641         struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
1642
1643         snd_soc_unregister_codec(&wm8993->codec);
1644         snd_soc_unregister_dai(&wm8993_dai);
1645
1646         wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
1647         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1648         kfree(wm8993);
1649
1650         return 0;
1651 }
1652
1653 static const struct i2c_device_id wm8993_i2c_id[] = {
1654         { "wm8993", 0 },
1655         { }
1656 };
1657 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1658
1659 static struct i2c_driver wm8993_i2c_driver = {
1660         .driver = {
1661                 .name = "WM8993",
1662                 .owner = THIS_MODULE,
1663         },
1664         .probe = wm8993_i2c_probe,
1665         .remove = wm8993_i2c_remove,
1666         .id_table = wm8993_i2c_id,
1667 };
1668
1669
1670 static int __init wm8993_modinit(void)
1671 {
1672         int ret;
1673
1674         ret = i2c_add_driver(&wm8993_i2c_driver);
1675         if (ret != 0)
1676                 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
1677
1678         return ret;
1679 }
1680 module_init(wm8993_modinit);
1681
1682 static void __exit wm8993_exit(void)
1683 {
1684         i2c_del_driver(&wm8993_i2c_driver);
1685 }
1686 module_exit(wm8993_exit);
1687
1688
1689 MODULE_DESCRIPTION("ASoC WM8993 driver");
1690 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1691 MODULE_LICENSE("GPL");