ASoC: WM8993 digital mixing support
[linux-2.6.git] / sound / soc / codecs / wm8993.c
1 /*
2  * wm8993.c -- WM8993 ALSA SoC audio driver
3  *
4  * Copyright 2009 Wolfson Microelectronics plc
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/spi/spi.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/tlv.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/wm8993.h>
28
29 #include "wm8993.h"
30 #include "wm_hubs.h"
31
32 static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
33         0x8993,     /* R0   - Software Reset */
34         0x0000,     /* R1   - Power Management (1) */
35         0x6000,     /* R2   - Power Management (2) */
36         0x0000,     /* R3   - Power Management (3) */
37         0x4050,     /* R4   - Audio Interface (1) */
38         0x4000,     /* R5   - Audio Interface (2) */
39         0x01C8,     /* R6   - Clocking 1 */
40         0x0000,     /* R7   - Clocking 2 */
41         0x0000,     /* R8   - Audio Interface (3) */
42         0x0040,     /* R9   - Audio Interface (4) */
43         0x0004,     /* R10  - DAC CTRL */
44         0x00C0,     /* R11  - Left DAC Digital Volume */
45         0x00C0,     /* R12  - Right DAC Digital Volume */
46         0x0000,     /* R13  - Digital Side Tone */
47         0x0300,     /* R14  - ADC CTRL */
48         0x00C0,     /* R15  - Left ADC Digital Volume */
49         0x00C0,     /* R16  - Right ADC Digital Volume */
50         0x0000,     /* R17 */
51         0x0000,     /* R18  - GPIO CTRL 1 */
52         0x0010,     /* R19  - GPIO1 */
53         0x0000,     /* R20  - IRQ_DEBOUNCE */
54         0x0000,     /* R21 */
55         0x8000,     /* R22  - GPIOCTRL 2 */
56         0x0800,     /* R23  - GPIO_POL */
57         0x008B,     /* R24  - Left Line Input 1&2 Volume */
58         0x008B,     /* R25  - Left Line Input 3&4 Volume */
59         0x008B,     /* R26  - Right Line Input 1&2 Volume */
60         0x008B,     /* R27  - Right Line Input 3&4 Volume */
61         0x006D,     /* R28  - Left Output Volume */
62         0x006D,     /* R29  - Right Output Volume */
63         0x0066,     /* R30  - Line Outputs Volume */
64         0x0020,     /* R31  - HPOUT2 Volume */
65         0x0079,     /* R32  - Left OPGA Volume */
66         0x0079,     /* R33  - Right OPGA Volume */
67         0x0003,     /* R34  - SPKMIXL Attenuation */
68         0x0003,     /* R35  - SPKMIXR Attenuation */
69         0x0011,     /* R36  - SPKOUT Mixers */
70         0x0100,     /* R37  - SPKOUT Boost */
71         0x0079,     /* R38  - Speaker Volume Left */
72         0x0079,     /* R39  - Speaker Volume Right */
73         0x0000,     /* R40  - Input Mixer2 */
74         0x0000,     /* R41  - Input Mixer3 */
75         0x0000,     /* R42  - Input Mixer4 */
76         0x0000,     /* R43  - Input Mixer5 */
77         0x0000,     /* R44  - Input Mixer6 */
78         0x0000,     /* R45  - Output Mixer1 */
79         0x0000,     /* R46  - Output Mixer2 */
80         0x0000,     /* R47  - Output Mixer3 */
81         0x0000,     /* R48  - Output Mixer4 */
82         0x0000,     /* R49  - Output Mixer5 */
83         0x0000,     /* R50  - Output Mixer6 */
84         0x0000,     /* R51  - HPOUT2 Mixer */
85         0x0000,     /* R52  - Line Mixer1 */
86         0x0000,     /* R53  - Line Mixer2 */
87         0x0000,     /* R54  - Speaker Mixer */
88         0x0000,     /* R55  - Additional Control */
89         0x0000,     /* R56  - AntiPOP1 */
90         0x0000,     /* R57  - AntiPOP2 */
91         0x0000,     /* R58  - MICBIAS */
92         0x0000,     /* R59 */
93         0x0000,     /* R60  - FLL Control 1 */
94         0x0000,     /* R61  - FLL Control 2 */
95         0x0000,     /* R62  - FLL Control 3 */
96         0x2EE0,     /* R63  - FLL Control 4 */
97         0x0002,     /* R64  - FLL Control 5 */
98         0x2287,     /* R65  - Clocking 3 */
99         0x025F,     /* R66  - Clocking 4 */
100         0x0000,     /* R67  - MW Slave Control */
101         0x0000,     /* R68 */
102         0x0002,     /* R69  - Bus Control 1 */
103         0x0000,     /* R70  - Write Sequencer 0 */
104         0x0000,     /* R71  - Write Sequencer 1 */
105         0x0000,     /* R72  - Write Sequencer 2 */
106         0x0000,     /* R73  - Write Sequencer 3 */
107         0x0000,     /* R74  - Write Sequencer 4 */
108         0x0000,     /* R75  - Write Sequencer 5 */
109         0x1F25,     /* R76  - Charge Pump 1 */
110         0x0000,     /* R77 */
111         0x0000,     /* R78 */
112         0x0000,     /* R79 */
113         0x0000,     /* R80 */
114         0x0000,     /* R81  - Class W 0 */
115         0x0000,     /* R82 */
116         0x0000,     /* R83 */
117         0x0000,     /* R84  - DC Servo 0 */
118         0x054A,     /* R85  - DC Servo 1 */
119         0x0000,     /* R86 */
120         0x0000,     /* R87  - DC Servo 3 */
121         0x0000,     /* R88  - DC Servo Readback 0 */
122         0x0000,     /* R89  - DC Servo Readback 1 */
123         0x0000,     /* R90  - DC Servo Readback 2 */
124         0x0000,     /* R91 */
125         0x0000,     /* R92 */
126         0x0000,     /* R93 */
127         0x0000,     /* R94 */
128         0x0000,     /* R95 */
129         0x0100,     /* R96  - Analogue HP 0 */
130         0x0000,     /* R97 */
131         0x0000,     /* R98  - EQ1 */
132         0x000C,     /* R99  - EQ2 */
133         0x000C,     /* R100 - EQ3 */
134         0x000C,     /* R101 - EQ4 */
135         0x000C,     /* R102 - EQ5 */
136         0x000C,     /* R103 - EQ6 */
137         0x0FCA,     /* R104 - EQ7 */
138         0x0400,     /* R105 - EQ8 */
139         0x00D8,     /* R106 - EQ9 */
140         0x1EB5,     /* R107 - EQ10 */
141         0xF145,     /* R108 - EQ11 */
142         0x0B75,     /* R109 - EQ12 */
143         0x01C5,     /* R110 - EQ13 */
144         0x1C58,     /* R111 - EQ14 */
145         0xF373,     /* R112 - EQ15 */
146         0x0A54,     /* R113 - EQ16 */
147         0x0558,     /* R114 - EQ17 */
148         0x168E,     /* R115 - EQ18 */
149         0xF829,     /* R116 - EQ19 */
150         0x07AD,     /* R117 - EQ20 */
151         0x1103,     /* R118 - EQ21 */
152         0x0564,     /* R119 - EQ22 */
153         0x0559,     /* R120 - EQ23 */
154         0x4000,     /* R121 - EQ24 */
155         0x0000,     /* R122 - Digital Pulls */
156         0x0F08,     /* R123 - DRC Control 1 */
157         0x0000,     /* R124 - DRC Control 2 */
158         0x0080,     /* R125 - DRC Control 3 */
159         0x0000,     /* R126 - DRC Control 4 */
160 };
161
162 static struct {
163         int ratio;
164         int clk_sys_rate;
165 } clk_sys_rates[] = {
166         { 64,   0 },
167         { 128,  1 },
168         { 192,  2 },
169         { 256,  3 },
170         { 384,  4 },
171         { 512,  5 },
172         { 768,  6 },
173         { 1024, 7 },
174         { 1408, 8 },
175         { 1536, 9 },
176 };
177
178 static struct {
179         int rate;
180         int sample_rate;
181 } sample_rates[] = {
182         { 8000,  0  },
183         { 11025, 1  },
184         { 12000, 1  },
185         { 16000, 2  },
186         { 22050, 3  },
187         { 24000, 3  },
188         { 32000, 4  },
189         { 44100, 5  },
190         { 48000, 5  },
191 };
192
193 static struct {
194         int div; /* *10 due to .5s */
195         int bclk_div;
196 } bclk_divs[] = {
197         { 10,  0  },
198         { 15,  1  },
199         { 20,  2  },
200         { 30,  3  },
201         { 40,  4  },
202         { 55,  5  },
203         { 60,  6  },
204         { 80,  7  },
205         { 110, 8  },
206         { 120, 9  },
207         { 160, 10 },
208         { 220, 11 },
209         { 240, 12 },
210         { 320, 13 },
211         { 440, 14 },
212         { 480, 15 },
213 };
214
215 struct wm8993_priv {
216         u16 reg_cache[WM8993_REGISTER_COUNT];
217         struct wm8993_platform_data pdata;
218         struct snd_soc_codec codec;
219         int master;
220         int sysclk_source;
221         unsigned int mclk_rate;
222         unsigned int sysclk_rate;
223         unsigned int fs;
224         unsigned int bclk;
225         int class_w_users;
226         unsigned int fll_fref;
227         unsigned int fll_fout;
228 };
229
230 static unsigned int wm8993_read_hw(struct snd_soc_codec *codec, u8 reg)
231 {
232         struct i2c_msg xfer[2];
233         u16 data;
234         int ret;
235         struct i2c_client *i2c = codec->control_data;
236
237         /* Write register */
238         xfer[0].addr = i2c->addr;
239         xfer[0].flags = 0;
240         xfer[0].len = 1;
241         xfer[0].buf = &reg;
242
243         /* Read data */
244         xfer[1].addr = i2c->addr;
245         xfer[1].flags = I2C_M_RD;
246         xfer[1].len = 2;
247         xfer[1].buf = (u8 *)&data;
248
249         ret = i2c_transfer(i2c->adapter, xfer, 2);
250         if (ret != 2) {
251                 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
252                 return 0;
253         }
254
255         return (data >> 8) | ((data & 0xff) << 8);
256 }
257
258 static int wm8993_volatile(unsigned int reg)
259 {
260         switch (reg) {
261         case WM8993_SOFTWARE_RESET:
262         case WM8993_DC_SERVO_0:
263         case WM8993_DC_SERVO_READBACK_0:
264         case WM8993_DC_SERVO_READBACK_1:
265         case WM8993_DC_SERVO_READBACK_2:
266                 return 1;
267         default:
268                 return 0;
269         }
270 }
271
272 static unsigned int wm8993_read(struct snd_soc_codec *codec,
273                                 unsigned int reg)
274 {
275         u16 *reg_cache = codec->reg_cache;
276
277         BUG_ON(reg > WM8993_MAX_REGISTER);
278
279         if (wm8993_volatile(reg))
280                 return wm8993_read_hw(codec, reg);
281         else
282                 return reg_cache[reg];
283 }
284
285 static int wm8993_write(struct snd_soc_codec *codec, unsigned int reg,
286                         unsigned int value)
287 {
288         u16 *reg_cache = codec->reg_cache;
289         u8 data[3];
290         int ret;
291
292         BUG_ON(reg > WM8993_MAX_REGISTER);
293
294         /* data is
295          *   D15..D9 WM8993 register offset
296          *   D8...D0 register data
297          */
298         data[0] = reg;
299         data[1] = value >> 8;
300         data[2] = value & 0x00ff;
301
302         if (!wm8993_volatile(reg))
303                 reg_cache[reg] = value;
304
305         ret = codec->hw_write(codec->control_data, data, 3);
306
307         if (ret == 3)
308                 return 0;
309         if (ret < 0)
310                 return ret;
311         return -EIO;
312 }
313
314 struct _fll_div {
315         u16 fll_fratio;
316         u16 fll_outdiv;
317         u16 fll_clk_ref_div;
318         u16 n;
319         u16 k;
320 };
321
322 /* The size in bits of the FLL divide multiplied by 10
323  * to allow rounding later */
324 #define FIXED_FLL_SIZE ((1 << 16) * 10)
325
326 static struct {
327         unsigned int min;
328         unsigned int max;
329         u16 fll_fratio;
330         int ratio;
331 } fll_fratios[] = {
332         {       0,    64000, 4, 16 },
333         {   64000,   128000, 3,  8 },
334         {  128000,   256000, 2,  4 },
335         {  256000,  1000000, 1,  2 },
336         { 1000000, 13500000, 0,  1 },
337 };
338
339 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
340                        unsigned int Fout)
341 {
342         u64 Kpart;
343         unsigned int K, Ndiv, Nmod, target;
344         unsigned int div;
345         int i;
346
347         /* Fref must be <=13.5MHz */
348         div = 1;
349         fll_div->fll_clk_ref_div = 0;
350         while ((Fref / div) > 13500000) {
351                 div *= 2;
352                 fll_div->fll_clk_ref_div++;
353
354                 if (div > 8) {
355                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
356                                Fref);
357                         return -EINVAL;
358                 }
359         }
360
361         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
362
363         /* Apply the division for our remaining calculations */
364         Fref /= div;
365
366         /* Fvco should be 90-100MHz; don't check the upper bound */
367         div = 0;
368         target = Fout * 2;
369         while (target < 90000000) {
370                 div++;
371                 target *= 2;
372                 if (div > 7) {
373                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
374                                Fout);
375                         return -EINVAL;
376                 }
377         }
378         fll_div->fll_outdiv = div;
379
380         pr_debug("Fvco=%dHz\n", target);
381
382         /* Find an appropraite FLL_FRATIO and factor it out of the target */
383         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
384                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
385                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
386                         target /= fll_fratios[i].ratio;
387                         break;
388                 }
389         }
390         if (i == ARRAY_SIZE(fll_fratios)) {
391                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
392                 return -EINVAL;
393         }
394
395         /* Now, calculate N.K */
396         Ndiv = target / Fref;
397
398         fll_div->n = Ndiv;
399         Nmod = target % Fref;
400         pr_debug("Nmod=%d\n", Nmod);
401
402         /* Calculate fractional part - scale up so we can round. */
403         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
404
405         do_div(Kpart, Fref);
406
407         K = Kpart & 0xFFFFFFFF;
408
409         if ((K % 10) >= 5)
410                 K += 5;
411
412         /* Move down to proper range now rounding is done */
413         fll_div->k = K / 10;
414
415         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
416                  fll_div->n, fll_div->k,
417                  fll_div->fll_fratio, fll_div->fll_outdiv,
418                  fll_div->fll_clk_ref_div);
419
420         return 0;
421 }
422
423 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id,
424                           unsigned int Fref, unsigned int Fout)
425 {
426         struct snd_soc_codec *codec = dai->codec;
427         struct wm8993_priv *wm8993 = codec->private_data;
428         u16 reg1, reg4, reg5;
429         struct _fll_div fll_div;
430         int ret;
431
432         /* Any change? */
433         if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
434                 return 0;
435
436         /* Disable the FLL */
437         if (Fout == 0) {
438                 dev_dbg(codec->dev, "FLL disabled\n");
439                 wm8993->fll_fref = 0;
440                 wm8993->fll_fout = 0;
441
442                 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
443                 reg1 &= ~WM8993_FLL_ENA;
444                 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
445
446                 return 0;
447         }
448
449         ret = fll_factors(&fll_div, Fref, Fout);
450         if (ret != 0)
451                 return ret;
452
453         reg5 = wm8993_read(codec, WM8993_FLL_CONTROL_5);
454         reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
455
456         switch (fll_id) {
457         case WM8993_FLL_MCLK:
458                 break;
459
460         case WM8993_FLL_LRCLK:
461                 reg5 |= 1;
462                 break;
463
464         case WM8993_FLL_BCLK:
465                 reg5 |= 2;
466                 break;
467
468         default:
469                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
470                 return -EINVAL;
471         }
472
473         /* Any FLL configuration change requires that the FLL be
474          * disabled first. */
475         reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
476         reg1 &= ~WM8993_FLL_ENA;
477         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
478
479         /* Apply the configuration */
480         if (fll_div.k)
481                 reg1 |= WM8993_FLL_FRAC_MASK;
482         else
483                 reg1 &= ~WM8993_FLL_FRAC_MASK;
484         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
485
486         wm8993_write(codec, WM8993_FLL_CONTROL_2,
487                      (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
488                      (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
489         wm8993_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
490
491         reg4 = wm8993_read(codec, WM8993_FLL_CONTROL_4);
492         reg4 &= ~WM8993_FLL_N_MASK;
493         reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
494         wm8993_write(codec, WM8993_FLL_CONTROL_4, reg4);
495
496         reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
497         reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
498         wm8993_write(codec, WM8993_FLL_CONTROL_5, reg5);
499
500         /* Enable the FLL */
501         wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
502
503         dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
504
505         wm8993->fll_fref = Fref;
506         wm8993->fll_fout = Fout;
507
508         return 0;
509 }
510
511 static int configure_clock(struct snd_soc_codec *codec)
512 {
513         struct wm8993_priv *wm8993 = codec->private_data;
514         unsigned int reg;
515
516         /* This should be done on init() for bypass paths */
517         switch (wm8993->sysclk_source) {
518         case WM8993_SYSCLK_MCLK:
519                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
520
521                 reg = wm8993_read(codec, WM8993_CLOCKING_2);
522                 reg &= ~WM8993_SYSCLK_SRC;
523                 if (wm8993->mclk_rate > 13500000) {
524                         reg |= WM8993_MCLK_DIV;
525                         wm8993->sysclk_rate = wm8993->mclk_rate / 2;
526                 } else {
527                         reg &= ~WM8993_MCLK_DIV;
528                         wm8993->sysclk_rate = wm8993->mclk_rate;
529                 }
530                 reg &= ~WM8993_MCLK_DIV;
531                 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
532                 wm8993_write(codec, WM8993_CLOCKING_2, reg);
533                 break;
534
535         case WM8993_SYSCLK_FLL:
536                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
537                         wm8993->fll_fout);
538
539                 reg = wm8993_read(codec, WM8993_CLOCKING_2);
540                 reg |= WM8993_SYSCLK_SRC;
541                 if (wm8993->fll_fout > 13500000) {
542                         reg |= WM8993_MCLK_DIV;
543                         wm8993->sysclk_rate = wm8993->fll_fout / 2;
544                 } else {
545                         reg &= ~WM8993_MCLK_DIV;
546                         wm8993->sysclk_rate = wm8993->fll_fout;
547                 }
548                 wm8993_write(codec, WM8993_CLOCKING_2, reg);
549                 break;
550
551         default:
552                 dev_err(codec->dev, "System clock not configured\n");
553                 return -EINVAL;
554         }
555
556         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
557
558         return 0;
559 }
560
561 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
562 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
563 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
564 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
565 static const unsigned int drc_max_tlv[] = {
566         TLV_DB_RANGE_HEAD(4),
567         0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
568         3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
569 };
570 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
571 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
572 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
573 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
574 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
575
576 static const char *dac_deemph_text[] = {
577         "None",
578         "32kHz",
579         "44.1kHz",
580         "48kHz",
581 };
582
583 static const struct soc_enum dac_deemph =
584         SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
585
586 static const char *adc_hpf_text[] = {
587         "Hi-Fi",
588         "Voice 1",
589         "Voice 2",
590         "Voice 3",
591 };
592
593 static const struct soc_enum adc_hpf =
594         SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
595
596 static const char *drc_path_text[] = {
597         "ADC",
598         "DAC"
599 };
600
601 static const struct soc_enum drc_path =
602         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
603
604 static const char *drc_r0_text[] = {
605         "1",
606         "1/2",
607         "1/4",
608         "1/8",
609         "1/16",
610         "0",
611 };
612
613 static const struct soc_enum drc_r0 =
614         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
615
616 static const char *drc_r1_text[] = {
617         "1",
618         "1/2",
619         "1/4",
620         "1/8",
621         "0",
622 };
623
624 static const struct soc_enum drc_r1 =
625         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
626
627 static const char *drc_attack_text[] = {
628         "Reserved",
629         "181us",
630         "363us",
631         "726us",
632         "1.45ms",
633         "2.9ms",
634         "5.8ms",
635         "11.6ms",
636         "23.2ms",
637         "46.4ms",
638         "92.8ms",
639         "185.6ms",
640 };
641
642 static const struct soc_enum drc_attack =
643         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
644
645 static const char *drc_decay_text[] = {
646         "186ms",
647         "372ms",
648         "743ms",
649         "1.49s",
650         "2.97ms",
651         "5.94ms",
652         "11.89ms",
653         "23.78ms",
654         "47.56ms",
655 };
656
657 static const struct soc_enum drc_decay =
658         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
659
660 static const char *drc_ff_text[] = {
661         "5 samples",
662         "9 samples",
663 };
664
665 static const struct soc_enum drc_ff =
666         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
667
668 static const char *drc_qr_rate_text[] = {
669         "0.725ms",
670         "1.45ms",
671         "5.8ms",
672 };
673
674 static const struct soc_enum drc_qr_rate =
675         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
676
677 static const char *drc_smooth_text[] = {
678         "Low",
679         "Medium",
680         "High",
681 };
682
683 static const struct soc_enum drc_smooth =
684         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
685
686 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
687 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
688                5, 9, 12, 0, sidetone_tlv),
689
690 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
691 SOC_ENUM("DRC Path", drc_path),
692 SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8993_DRC_CONTROL_2,
693                2, 60, 1, drc_comp_threash),
694 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
695                11, 30, 1, drc_comp_amp),
696 SOC_ENUM("DRC R0", drc_r0),
697 SOC_ENUM("DRC R1", drc_r1),
698 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
699                drc_min_tlv),
700 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
701                drc_max_tlv),
702 SOC_ENUM("DRC Attack Rate", drc_attack),
703 SOC_ENUM("DRC Decay Rate", drc_decay),
704 SOC_ENUM("DRC FF Delay", drc_ff),
705 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
706 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
707 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
708                drc_qr_tlv),
709 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
710 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
711 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
712 SOC_ENUM("DRC Smoothing Hysteresis Threashold", drc_smooth),
713 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
714                drc_startup_tlv),
715
716 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
717
718 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
719                  WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
720 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
721 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
722
723 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
724                  WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
725 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
726                dac_boost_tlv),
727 SOC_ENUM("DAC Deemphasis", dac_deemph),
728
729 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
730                2, 1, 1, wm_hubs_spkmix_tlv),
731
732 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
733                2, 1, 1, wm_hubs_spkmix_tlv),
734 };
735
736 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
737 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
738 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
739 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
740 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
741 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
742 };
743
744 static int clk_sys_event(struct snd_soc_dapm_widget *w,
745                          struct snd_kcontrol *kcontrol, int event)
746 {
747         struct snd_soc_codec *codec = w->codec;
748
749         switch (event) {
750         case SND_SOC_DAPM_PRE_PMU:
751                 return configure_clock(codec);
752
753         case SND_SOC_DAPM_POST_PMD:
754                 break;
755         }
756
757         return 0;
758 }
759
760 /*
761  * When used with DAC outputs only the WM8993 charge pump supports
762  * operation in class W mode, providing very low power consumption
763  * when used with digital sources.  Enable and disable this mode
764  * automatically depending on the mixer configuration.
765  *
766  * Currently the only supported paths are the direct DAC->headphone
767  * paths (which provide minimum power consumption anyway).
768  */
769 static int class_w_put(struct snd_kcontrol *kcontrol,
770                        struct snd_ctl_elem_value *ucontrol)
771 {
772         struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
773         struct snd_soc_codec *codec = widget->codec;
774         struct wm8993_priv *wm8993 = codec->private_data;
775         int ret;
776
777         /* Turn it off if we're using the main output mixer */
778         if (ucontrol->value.integer.value[0] == 0) {
779                 if (wm8993->class_w_users == 0) {
780                         dev_dbg(codec->dev, "Disabling Class W\n");
781                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
782                                             WM8993_CP_DYN_FREQ |
783                                             WM8993_CP_DYN_V,
784                                             0);
785                 }
786                 wm8993->class_w_users++;
787         }
788
789         /* Implement the change */
790         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
791
792         /* Enable it if we're using the direct DAC path */
793         if (ucontrol->value.integer.value[0] == 1) {
794                 if (wm8993->class_w_users == 1) {
795                         dev_dbg(codec->dev, "Enabling Class W\n");
796                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
797                                             WM8993_CP_DYN_FREQ |
798                                             WM8993_CP_DYN_V,
799                                             WM8993_CP_DYN_FREQ |
800                                             WM8993_CP_DYN_V);
801                 }
802                 wm8993->class_w_users--;
803         }
804
805         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
806                 wm8993->class_w_users);
807
808         return ret;
809 }
810
811 #define SOC_DAPM_ENUM_W(xname, xenum) \
812 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
813         .info = snd_soc_info_enum_double, \
814         .get = snd_soc_dapm_get_enum_double, \
815         .put = class_w_put, \
816         .private_value = (unsigned long)&xenum }
817
818 static const char *hp_mux_text[] = {
819         "Mixer",
820         "DAC",
821 };
822
823 static const struct soc_enum hpl_enum =
824         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
825
826 static const struct snd_kcontrol_new hpl_mux =
827         SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
828
829 static const struct soc_enum hpr_enum =
830         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
831
832 static const struct snd_kcontrol_new hpr_mux =
833         SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
834
835 static const struct snd_kcontrol_new left_speaker_mixer[] = {
836 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
837 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
838 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
839 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
840 };
841
842 static const struct snd_kcontrol_new right_speaker_mixer[] = {
843 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
844 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
845 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
846 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
847 };
848
849 static const char *aif_text[] = {
850         "Left", "Right"
851 };
852
853 static const struct soc_enum aifoutl_enum =
854         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
855
856 static const struct snd_kcontrol_new aifoutl_mux =
857         SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
858
859 static const struct soc_enum aifoutr_enum =
860         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
861
862 static const struct snd_kcontrol_new aifoutr_mux =
863         SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
864
865 static const struct soc_enum aifinl_enum =
866         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
867
868 static const struct snd_kcontrol_new aifinl_mux =
869         SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
870
871 static const struct soc_enum aifinr_enum =
872         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
873
874 static const struct snd_kcontrol_new aifinr_mux =
875         SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
876
877 static const char *sidetone_text[] = {
878         "None", "Left", "Right"
879 };
880
881 static const struct soc_enum sidetonel_enum =
882         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
883
884 static const struct snd_kcontrol_new sidetonel_mux =
885         SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
886
887 static const struct soc_enum sidetoner_enum =
888         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
889
890 static const struct snd_kcontrol_new sidetoner_mux =
891         SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
892
893 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
894 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
895                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
896 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
897 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
898
899 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
900 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
901
902 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
903 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
904
905 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
906 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
907
908 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
909 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
910
911 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
912 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
913
914 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
915 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
916
917 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
918 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
919
920 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
921 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
922
923 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
924                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
925 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
926                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
927
928 };
929
930 static const struct snd_soc_dapm_route routes[] = {
931         { "ADCL", NULL, "CLK_SYS" },
932         { "ADCL", NULL, "CLK_DSP" },
933         { "ADCR", NULL, "CLK_SYS" },
934         { "ADCR", NULL, "CLK_DSP" },
935
936         { "AIFOUTL Mux", "Left", "ADCL" },
937         { "AIFOUTL Mux", "Right", "ADCR" },
938         { "AIFOUTR Mux", "Left", "ADCL" },
939         { "AIFOUTR Mux", "Right", "ADCR" },
940
941         { "AIFOUTL", NULL, "AIFOUTL Mux" },
942         { "AIFOUTR", NULL, "AIFOUTR Mux" },
943
944         { "DACL Mux", "Left", "AIFINL" },
945         { "DACL Mux", "Right", "AIFINR" },
946         { "DACR Mux", "Left", "AIFINL" },
947         { "DACR Mux", "Right", "AIFINR" },
948
949         { "DACL Sidetone", "Left", "ADCL" },
950         { "DACL Sidetone", "Right", "ADCR" },
951         { "DACR Sidetone", "Left", "ADCL" },
952         { "DACR Sidetone", "Right", "ADCR" },
953
954         { "DACL", NULL, "CLK_SYS" },
955         { "DACL", NULL, "CLK_DSP" },
956         { "DACL", NULL, "DACL Mux" },
957         { "DACL", NULL, "DACL Sidetone" },
958         { "DACR", NULL, "CLK_SYS" },
959         { "DACR", NULL, "CLK_DSP" },
960         { "DACR", NULL, "DACR Mux" },
961         { "DACR", NULL, "DACR Sidetone" },
962
963         { "Left Output Mixer", "DAC Switch", "DACL" },
964
965         { "Right Output Mixer", "DAC Switch", "DACR" },
966
967         { "Left Output PGA", NULL, "CLK_SYS" },
968
969         { "Right Output PGA", NULL, "CLK_SYS" },
970
971         { "SPKL", "DAC Switch", "DACL" },
972         { "SPKL", NULL, "CLK_SYS" },
973
974         { "SPKR", "DAC Switch", "DACR" },
975         { "SPKR", NULL, "CLK_SYS" },
976
977         { "Left Headphone Mux", "DAC", "DACL" },
978         { "Right Headphone Mux", "DAC", "DACR" },
979 };
980
981 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
982                                  enum snd_soc_bias_level level)
983 {
984         struct wm8993_priv *wm8993 = codec->private_data;
985
986         switch (level) {
987         case SND_SOC_BIAS_ON:
988         case SND_SOC_BIAS_PREPARE:
989                 /* VMID=2*40k */
990                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
991                                     WM8993_VMID_SEL_MASK, 0x2);
992                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
993                                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
994                 break;
995
996         case SND_SOC_BIAS_STANDBY:
997                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
998                         /* Bring up VMID with fast soft start */
999                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1000                                             WM8993_STARTUP_BIAS_ENA |
1001                                             WM8993_VMID_BUF_ENA |
1002                                             WM8993_VMID_RAMP_MASK |
1003                                             WM8993_BIAS_SRC,
1004                                             WM8993_STARTUP_BIAS_ENA |
1005                                             WM8993_VMID_BUF_ENA |
1006                                             WM8993_VMID_RAMP_MASK |
1007                                             WM8993_BIAS_SRC);
1008
1009                         /* If either line output is single ended we
1010                          * need the VMID buffer */
1011                         if (!wm8993->pdata.lineout1_diff ||
1012                             !wm8993->pdata.lineout2_diff)
1013                                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1014                                                  WM8993_LINEOUT_VMID_BUF_ENA,
1015                                                  WM8993_LINEOUT_VMID_BUF_ENA);
1016
1017                         /* VMID=2*40k */
1018                         snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1019                                             WM8993_VMID_SEL_MASK |
1020                                             WM8993_BIAS_ENA,
1021                                             WM8993_BIAS_ENA | 0x2);
1022                         msleep(32);
1023
1024                         /* Switch to normal bias */
1025                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1026                                             WM8993_BIAS_SRC |
1027                                             WM8993_STARTUP_BIAS_ENA, 0);
1028                 }
1029
1030                 /* VMID=2*240k */
1031                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1032                                     WM8993_VMID_SEL_MASK, 0x4);
1033
1034                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1035                                     WM8993_TSHUT_ENA, 0);
1036                 break;
1037
1038         case SND_SOC_BIAS_OFF:
1039                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1040                                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
1041
1042                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1043                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1044                                     0);
1045                 break;
1046         }
1047
1048         codec->bias_level = level;
1049
1050         return 0;
1051 }
1052
1053 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1054                              int clk_id, unsigned int freq, int dir)
1055 {
1056         struct snd_soc_codec *codec = codec_dai->codec;
1057         struct wm8993_priv *wm8993 = codec->private_data;
1058
1059         switch (clk_id) {
1060         case WM8993_SYSCLK_MCLK:
1061                 wm8993->mclk_rate = freq;
1062         case WM8993_SYSCLK_FLL:
1063                 wm8993->sysclk_source = clk_id;
1064                 break;
1065
1066         default:
1067                 return -EINVAL;
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1074                               unsigned int fmt)
1075 {
1076         struct snd_soc_codec *codec = dai->codec;
1077         struct wm8993_priv *wm8993 = codec->private_data;
1078         unsigned int aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1079         unsigned int aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1080
1081         aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1082                   WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1083         aif4 &= ~WM8993_LRCLK_DIR;
1084
1085         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1086         case SND_SOC_DAIFMT_CBS_CFS:
1087                 wm8993->master = 0;
1088                 break;
1089         case SND_SOC_DAIFMT_CBS_CFM:
1090                 aif4 |= WM8993_LRCLK_DIR;
1091                 wm8993->master = 1;
1092                 break;
1093         case SND_SOC_DAIFMT_CBM_CFS:
1094                 aif1 |= WM8993_BCLK_DIR;
1095                 wm8993->master = 1;
1096                 break;
1097         case SND_SOC_DAIFMT_CBM_CFM:
1098                 aif1 |= WM8993_BCLK_DIR;
1099                 aif4 |= WM8993_LRCLK_DIR;
1100                 wm8993->master = 1;
1101                 break;
1102         default:
1103                 return -EINVAL;
1104         }
1105
1106         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1107         case SND_SOC_DAIFMT_DSP_B:
1108                 aif1 |= WM8993_AIF_LRCLK_INV;
1109         case SND_SOC_DAIFMT_DSP_A:
1110                 aif1 |= 0x18;
1111                 break;
1112         case SND_SOC_DAIFMT_I2S:
1113                 aif1 |= 0x10;
1114                 break;
1115         case SND_SOC_DAIFMT_RIGHT_J:
1116                 break;
1117         case SND_SOC_DAIFMT_LEFT_J:
1118                 aif1 |= 0x8;
1119                 break;
1120         default:
1121                 return -EINVAL;
1122         }
1123
1124         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1125         case SND_SOC_DAIFMT_DSP_A:
1126         case SND_SOC_DAIFMT_DSP_B:
1127                 /* frame inversion not valid for DSP modes */
1128                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1129                 case SND_SOC_DAIFMT_NB_NF:
1130                         break;
1131                 case SND_SOC_DAIFMT_IB_NF:
1132                         aif1 |= WM8993_AIF_BCLK_INV;
1133                         break;
1134                 default:
1135                         return -EINVAL;
1136                 }
1137                 break;
1138
1139         case SND_SOC_DAIFMT_I2S:
1140         case SND_SOC_DAIFMT_RIGHT_J:
1141         case SND_SOC_DAIFMT_LEFT_J:
1142                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1143                 case SND_SOC_DAIFMT_NB_NF:
1144                         break;
1145                 case SND_SOC_DAIFMT_IB_IF:
1146                         aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1147                         break;
1148                 case SND_SOC_DAIFMT_IB_NF:
1149                         aif1 |= WM8993_AIF_BCLK_INV;
1150                         break;
1151                 case SND_SOC_DAIFMT_NB_IF:
1152                         aif1 |= WM8993_AIF_LRCLK_INV;
1153                         break;
1154                 default:
1155                         return -EINVAL;
1156                 }
1157                 break;
1158         default:
1159                 return -EINVAL;
1160         }
1161
1162         wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1163         wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1164
1165         return 0;
1166 }
1167
1168 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1169                             struct snd_pcm_hw_params *params,
1170                             struct snd_soc_dai *dai)
1171 {
1172         struct snd_soc_codec *codec = dai->codec;
1173         struct wm8993_priv *wm8993 = codec->private_data;
1174         int ret, i, best, best_val, cur_val;
1175         unsigned int clocking1, clocking3, aif1, aif4;
1176
1177         clocking1 = wm8993_read(codec, WM8993_CLOCKING_1);
1178         clocking1 &= ~WM8993_BCLK_DIV_MASK;
1179
1180         clocking3 = wm8993_read(codec, WM8993_CLOCKING_3);
1181         clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1182
1183         aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1184         aif1 &= ~WM8993_AIF_WL_MASK;
1185
1186         aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1187         aif4 &= ~WM8993_LRCLK_RATE_MASK;
1188
1189         /* What BCLK do we need? */
1190         wm8993->fs = params_rate(params);
1191         wm8993->bclk = 2 * wm8993->fs;
1192         switch (params_format(params)) {
1193         case SNDRV_PCM_FORMAT_S16_LE:
1194                 wm8993->bclk *= 16;
1195                 break;
1196         case SNDRV_PCM_FORMAT_S20_3LE:
1197                 wm8993->bclk *= 20;
1198                 aif1 |= 0x8;
1199                 break;
1200         case SNDRV_PCM_FORMAT_S24_LE:
1201                 wm8993->bclk *= 24;
1202                 aif1 |= 0x10;
1203                 break;
1204         case SNDRV_PCM_FORMAT_S32_LE:
1205                 wm8993->bclk *= 32;
1206                 aif1 |= 0x18;
1207                 break;
1208         default:
1209                 return -EINVAL;
1210         }
1211
1212         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1213
1214         ret = configure_clock(codec);
1215         if (ret != 0)
1216                 return ret;
1217
1218         /* Select nearest CLK_SYS_RATE */
1219         best = 0;
1220         best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1221                        - wm8993->fs);
1222         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1223                 cur_val = abs((wm8993->sysclk_rate /
1224                                clk_sys_rates[i].ratio) - wm8993->fs);;
1225                 if (cur_val < best_val) {
1226                         best = i;
1227                         best_val = cur_val;
1228                 }
1229         }
1230         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1231                 clk_sys_rates[best].ratio);
1232         clocking3 |= (clk_sys_rates[best].clk_sys_rate
1233                       << WM8993_CLK_SYS_RATE_SHIFT);
1234
1235         /* SAMPLE_RATE */
1236         best = 0;
1237         best_val = abs(wm8993->fs - sample_rates[0].rate);
1238         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1239                 /* Closest match */
1240                 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1241                 if (cur_val < best_val) {
1242                         best = i;
1243                         best_val = cur_val;
1244                 }
1245         }
1246         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1247                 sample_rates[best].rate);
1248         clocking3 |= (sample_rates[best].sample_rate
1249                       << WM8993_SAMPLE_RATE_SHIFT);
1250
1251         /* BCLK_DIV */
1252         best = 0;
1253         best_val = INT_MAX;
1254         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1255                 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1256                         - wm8993->bclk;
1257                 if (cur_val < 0) /* Table is sorted */
1258                         break;
1259                 if (cur_val < best_val) {
1260                         best = i;
1261                         best_val = cur_val;
1262                 }
1263         }
1264         wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1265         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1266                 bclk_divs[best].div, wm8993->bclk);
1267         clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1268
1269         /* LRCLK is a simple fraction of BCLK */
1270         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1271         aif4 |= wm8993->bclk / wm8993->fs;
1272
1273         wm8993_write(codec, WM8993_CLOCKING_1, clocking1);
1274         wm8993_write(codec, WM8993_CLOCKING_3, clocking3);
1275         wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1276         wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1277
1278         /* ReTune Mobile? */
1279         if (wm8993->pdata.num_retune_configs) {
1280                 u16 eq1 = wm8993_read(codec, WM8993_EQ1);
1281                 struct wm8993_retune_mobile_setting *s;
1282
1283                 best = 0;
1284                 best_val = abs(wm8993->pdata.retune_configs[0].rate
1285                                - wm8993->fs);
1286                 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1287                         cur_val = abs(wm8993->pdata.retune_configs[i].rate
1288                                       - wm8993->fs);
1289                         if (cur_val < best_val) {
1290                                 best_val = cur_val;
1291                                 best = i;
1292                         }
1293                 }
1294                 s = &wm8993->pdata.retune_configs[best];
1295
1296                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1297                         s->name, s->rate);
1298
1299                 /* Disable EQ while we reconfigure */
1300                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1301
1302                 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1303                         wm8993_write(codec, WM8993_EQ1 + i, s->config[i]);
1304
1305                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1312 {
1313         struct snd_soc_codec *codec = codec_dai->codec;
1314         unsigned int reg;
1315
1316         reg = wm8993_read(codec, WM8993_DAC_CTRL);
1317
1318         if (mute)
1319                 reg |= WM8993_DAC_MUTE;
1320         else
1321                 reg &= ~WM8993_DAC_MUTE;
1322
1323         wm8993_write(codec, WM8993_DAC_CTRL, reg);
1324
1325         return 0;
1326 }
1327
1328 static struct snd_soc_dai_ops wm8993_ops = {
1329         .set_sysclk = wm8993_set_sysclk,
1330         .set_fmt = wm8993_set_dai_fmt,
1331         .hw_params = wm8993_hw_params,
1332         .digital_mute = wm8993_digital_mute,
1333         .set_pll = wm8993_set_fll,
1334 };
1335
1336 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1337
1338 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1339                         SNDRV_PCM_FMTBIT_S20_3LE |\
1340                         SNDRV_PCM_FMTBIT_S24_LE |\
1341                         SNDRV_PCM_FMTBIT_S32_LE)
1342
1343 struct snd_soc_dai wm8993_dai = {
1344         .name = "WM8993",
1345         .playback = {
1346                 .stream_name = "Playback",
1347                 .channels_min = 1,
1348                 .channels_max = 2,
1349                 .rates = WM8993_RATES,
1350                 .formats = WM8993_FORMATS,
1351         },
1352         .capture = {
1353                  .stream_name = "Capture",
1354                  .channels_min = 1,
1355                  .channels_max = 2,
1356                  .rates = WM8993_RATES,
1357                  .formats = WM8993_FORMATS,
1358          },
1359         .ops = &wm8993_ops,
1360         .symmetric_rates = 1,
1361 };
1362 EXPORT_SYMBOL_GPL(wm8993_dai);
1363
1364 static struct snd_soc_codec *wm8993_codec;
1365
1366 static int wm8993_probe(struct platform_device *pdev)
1367 {
1368         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1369         struct snd_soc_codec *codec;
1370         struct wm8993_priv *wm8993;
1371         int ret = 0;
1372
1373         if (!wm8993_codec) {
1374                 dev_err(&pdev->dev, "I2C device not yet probed\n");
1375                 goto err;
1376         }
1377
1378         socdev->card->codec = wm8993_codec;
1379         codec = wm8993_codec;
1380         wm8993 = codec->private_data;
1381
1382         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1383         if (ret < 0) {
1384                 dev_err(codec->dev, "failed to create pcms\n");
1385                 goto err;
1386         }
1387
1388         snd_soc_add_controls(codec, wm8993_snd_controls,
1389                              ARRAY_SIZE(wm8993_snd_controls));
1390         if (wm8993->pdata.num_retune_configs != 0) {
1391                 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1392         } else {
1393                 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1394                 snd_soc_add_controls(codec, wm8993_eq_controls,
1395                                      ARRAY_SIZE(wm8993_eq_controls));
1396         }
1397
1398         snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1399                                   ARRAY_SIZE(wm8993_dapm_widgets));
1400         wm_hubs_add_analogue_controls(codec);
1401
1402         snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1403         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1404                                     wm8993->pdata.lineout2_diff);
1405
1406         snd_soc_dapm_new_widgets(codec);
1407
1408         ret = snd_soc_init_card(socdev);
1409         if (ret < 0) {
1410                 dev_err(codec->dev, "failed to register card\n");
1411                 goto card_err;
1412         }
1413
1414         return ret;
1415
1416 card_err:
1417         snd_soc_free_pcms(socdev);
1418         snd_soc_dapm_free(socdev);
1419 err:
1420         return ret;
1421 }
1422
1423 static int wm8993_remove(struct platform_device *pdev)
1424 {
1425         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1426
1427         snd_soc_free_pcms(socdev);
1428         snd_soc_dapm_free(socdev);
1429
1430         return 0;
1431 }
1432
1433 struct snd_soc_codec_device soc_codec_dev_wm8993 = {
1434         .probe =        wm8993_probe,
1435         .remove =       wm8993_remove,
1436 };
1437 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
1438
1439 static int wm8993_i2c_probe(struct i2c_client *i2c,
1440                             const struct i2c_device_id *id)
1441 {
1442         struct wm8993_priv *wm8993;
1443         struct snd_soc_codec *codec;
1444         unsigned int val;
1445         int ret;
1446
1447         if (wm8993_codec) {
1448                 dev_err(&i2c->dev, "A WM8993 is already registered\n");
1449                 return -EINVAL;
1450         }
1451
1452         wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
1453         if (wm8993 == NULL)
1454                 return -ENOMEM;
1455
1456         codec = &wm8993->codec;
1457         if (i2c->dev.platform_data)
1458                 memcpy(&wm8993->pdata, i2c->dev.platform_data,
1459                        sizeof(wm8993->pdata));
1460
1461         mutex_init(&codec->mutex);
1462         INIT_LIST_HEAD(&codec->dapm_widgets);
1463         INIT_LIST_HEAD(&codec->dapm_paths);
1464
1465         codec->name = "WM8993";
1466         codec->read = wm8993_read;
1467         codec->write = wm8993_write;
1468         codec->hw_write = (hw_write_t)i2c_master_send;
1469         codec->reg_cache = wm8993->reg_cache;
1470         codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
1471         codec->bias_level = SND_SOC_BIAS_OFF;
1472         codec->set_bias_level = wm8993_set_bias_level;
1473         codec->dai = &wm8993_dai;
1474         codec->num_dai = 1;
1475         codec->private_data = wm8993;
1476
1477         memcpy(wm8993->reg_cache, wm8993_reg_defaults,
1478                sizeof(wm8993->reg_cache));
1479
1480         i2c_set_clientdata(i2c, wm8993);
1481         codec->control_data = i2c;
1482         wm8993_codec = codec;
1483
1484         codec->dev = &i2c->dev;
1485
1486         val = wm8993_read_hw(codec, WM8993_SOFTWARE_RESET);
1487         if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
1488                 dev_err(codec->dev, "Invalid ID register value %x\n", val);
1489                 ret = -EINVAL;
1490                 goto err;
1491         }
1492
1493         ret = wm8993_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
1494         if (ret != 0)
1495                 goto err;
1496
1497         /* By default we're using the output mixers */
1498         wm8993->class_w_users = 2;
1499
1500         /* Latch volume update bits and default ZC on */
1501         snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1502                             WM8993_DAC_VU, WM8993_DAC_VU);
1503         snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1504                             WM8993_ADC_VU, WM8993_ADC_VU);
1505
1506         /* Manualy manage the HPOUT sequencing for independent stereo
1507          * control. */
1508         snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1509                             WM8993_HPOUT1_AUTO_PU, 0);
1510
1511         /* Use automatic clock configuration */
1512         snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1513
1514         if (!wm8993->pdata.lineout1_diff)
1515                 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
1516                                     WM8993_LINEOUT1_MODE,
1517                                     WM8993_LINEOUT1_MODE);
1518         if (!wm8993->pdata.lineout2_diff)
1519                 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
1520                                     WM8993_LINEOUT2_MODE,
1521                                     WM8993_LINEOUT2_MODE);
1522
1523         if (wm8993->pdata.lineout1fb)
1524                 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1525                                     WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
1526
1527         if (wm8993->pdata.lineout2fb)
1528                 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
1529                                     WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
1530
1531         /* Apply the microphone bias/detection configuration - the
1532          * platform data is directly applicable to the register. */
1533         snd_soc_update_bits(codec, WM8993_MICBIAS,
1534                             WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
1535                             WM8993_MICB1_LVL | WM8993_MICB2_LVL,
1536                             wm8993->pdata.jd_scthr << WM8993_JD_SCTHR_SHIFT |
1537                             wm8993->pdata.jd_thr << WM8993_JD_THR_SHIFT |
1538                             wm8993->pdata.micbias1_lvl |
1539                             wm8993->pdata.micbias1_lvl << 1);
1540
1541         ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1542         if (ret != 0)
1543                 goto err;
1544
1545         wm8993_dai.dev = codec->dev;
1546
1547         ret = snd_soc_register_dai(&wm8993_dai);
1548         if (ret != 0)
1549                 goto err_bias;
1550
1551         ret = snd_soc_register_codec(codec);
1552
1553         return 0;
1554
1555 err_bias:
1556         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1557 err:
1558         wm8993_codec = NULL;
1559         kfree(wm8993);
1560         return ret;
1561 }
1562
1563 static int wm8993_i2c_remove(struct i2c_client *client)
1564 {
1565         struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
1566
1567         snd_soc_unregister_codec(&wm8993->codec);
1568         snd_soc_unregister_dai(&wm8993_dai);
1569
1570         wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
1571         kfree(wm8993);
1572
1573         return 0;
1574 }
1575
1576 static const struct i2c_device_id wm8993_i2c_id[] = {
1577         { "wm8993", 0 },
1578         { }
1579 };
1580 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1581
1582 static struct i2c_driver wm8993_i2c_driver = {
1583         .driver = {
1584                 .name = "WM8993",
1585                 .owner = THIS_MODULE,
1586         },
1587         .probe = wm8993_i2c_probe,
1588         .remove = wm8993_i2c_remove,
1589         .id_table = wm8993_i2c_id,
1590 };
1591
1592
1593 static int __init wm8993_modinit(void)
1594 {
1595         int ret;
1596
1597         ret = i2c_add_driver(&wm8993_i2c_driver);
1598         if (ret != 0)
1599                 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
1600
1601         return ret;
1602 }
1603 module_init(wm8993_modinit);
1604
1605 static void __exit wm8993_exit(void)
1606 {
1607         i2c_del_driver(&wm8993_i2c_driver);
1608 }
1609 module_exit(wm8993_exit);
1610
1611
1612 MODULE_DESCRIPTION("ASoC WM8993 driver");
1613 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1614 MODULE_LICENSE("GPL");