796621de5009bfa3f82284093edc526364def850
[linux-2.6.git] / sound / pci / rme9652 / hdsp.c
1 /*
2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
3  *
4  *      Copyright (c) 2002  Paul Davis
5  *                          Marcus Andersson
6  *                          Thomas Charbonnel
7  *
8  *   This program is free software; you can redistribute it and/or modify
9  *   it under the terms of the GNU General Public License as published by
10  *   the Free Software Foundation; either version 2 of the License, or
11  *   (at your option) any later version.
12  *
13  *   This program is distributed in the hope that it will be useful,
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *   GNU General Public License for more details.
17  *
18  *   You should have received a copy of the GNU General Public License
19  *   along with this program; if not, write to the Free Software
20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21  *
22  */
23
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61                 "{RME HDSP-9652},"
62                 "{RME HDSP-9632}}");
63
64 #define HDSP_MAX_CHANNELS        26
65 #define HDSP_MAX_DS_CHANNELS     14
66 #define HDSP_MAX_QS_CHANNELS     8
67 #define DIGIFACE_SS_CHANNELS     26
68 #define DIGIFACE_DS_CHANNELS     14
69 #define MULTIFACE_SS_CHANNELS    18
70 #define MULTIFACE_DS_CHANNELS    14
71 #define H9652_SS_CHANNELS        26
72 #define H9652_DS_CHANNELS        14
73 /* This does not include possible Analog Extension Boards
74    AEBs are detected at card initialization
75 */
76 #define H9632_SS_CHANNELS        12
77 #define H9632_DS_CHANNELS        8
78 #define H9632_QS_CHANNELS        4
79
80 /* Write registers. These are defined as byte-offsets from the iobase value.
81  */
82 #define HDSP_resetPointer               0
83 #define HDSP_outputBufferAddress        32
84 #define HDSP_inputBufferAddress         36
85 #define HDSP_controlRegister            64
86 #define HDSP_interruptConfirmation      96
87 #define HDSP_outputEnable               128
88 #define HDSP_control2Reg                256
89 #define HDSP_midiDataOut0               352
90 #define HDSP_midiDataOut1               356
91 #define HDSP_fifoData                   368
92 #define HDSP_inputEnable                384
93
94 /* Read registers. These are defined as byte-offsets from the iobase value
95  */
96
97 #define HDSP_statusRegister    0
98 #define HDSP_timecode        128
99 #define HDSP_status2Register 192
100 #define HDSP_midiDataOut0    352
101 #define HDSP_midiDataOut1    356
102 #define HDSP_midiDataIn0     360
103 #define HDSP_midiDataIn1     364
104 #define HDSP_midiStatusOut0  384
105 #define HDSP_midiStatusOut1  388
106 #define HDSP_midiStatusIn0   392
107 #define HDSP_midiStatusIn1   396
108 #define HDSP_fifoStatus      400
109
110 /* the meters are regular i/o-mapped registers, but offset
111    considerably from the rest. the peak registers are reset
112    when read; the least-significant 4 bits are full-scale counters; 
113    the actual peak value is in the most-significant 24 bits.
114 */
115
116 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
117 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
118 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
119 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
120 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
121
122
123 /* This is for H9652 cards
124    Peak values are read downward from the base
125    Rms values are read upward
126    There are rms values for the outputs too
127    26*3 values are read in ss mode
128    14*3 in ds mode, with no gap between values
129 */
130 #define HDSP_9652_peakBase      7164    
131 #define HDSP_9652_rmsBase       4096
132
133 /* c.f. the hdsp_9632_meters_t struct */
134 #define HDSP_9632_metersBase    4096
135
136 #define HDSP_IO_EXTENT     7168
137
138 /* control2 register bits */
139
140 #define HDSP_TMS                0x01
141 #define HDSP_TCK                0x02
142 #define HDSP_TDI                0x04
143 #define HDSP_JTAG               0x08
144 #define HDSP_PWDN               0x10
145 #define HDSP_PROGRAM            0x020
146 #define HDSP_CONFIG_MODE_0      0x040
147 #define HDSP_CONFIG_MODE_1      0x080
148 #define HDSP_VERSION_BIT        0x100
149 #define HDSP_BIGENDIAN_MODE     0x200
150 #define HDSP_RD_MULTIPLE        0x400
151 #define HDSP_9652_ENABLE_MIXER  0x800
152 #define HDSP_TDO                0x10000000
153
154 #define HDSP_S_PROGRAM          (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
155 #define HDSP_S_LOAD             (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
156
157 /* Control Register bits */
158
159 #define HDSP_Start                (1<<0)  /* start engine */
160 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
161 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
162 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
163 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
164 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
165 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
166 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
167 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
168 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
169 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
170 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
171 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
172 #define HDSP_SyncRef2             (1<<13) 
173 #define HDSP_SPDIFInputSelect0    (1<<14) 
174 #define HDSP_SPDIFInputSelect1    (1<<15) 
175 #define HDSP_SyncRef0             (1<<16) 
176 #define HDSP_SyncRef1             (1<<17)
177 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 
178 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
179 #define HDSP_Midi0InterruptEnable (1<<22)
180 #define HDSP_Midi1InterruptEnable (1<<23)
181 #define HDSP_LineOut              (1<<24)
182 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
183 #define HDSP_ADGain1              (1<<26)
184 #define HDSP_DAGain0              (1<<27)
185 #define HDSP_DAGain1              (1<<28)
186 #define HDSP_PhoneGain0           (1<<29)
187 #define HDSP_PhoneGain1           (1<<30)
188 #define HDSP_QuadSpeed            (1<<31)
189
190 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
191 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
192 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
193 #define HDSP_ADGainLowGain     0
194
195 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
196 #define HDSP_DAGainHighGain      HDSP_DAGainMask
197 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
198 #define HDSP_DAGainMinus10dBV    0
199
200 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
201 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
202 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
203 #define HDSP_PhoneGainMinus12dB  0
204
205 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
206 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
207
208 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
209 #define HDSP_SPDIFInputADAT1    0
210 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
211 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
212 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
213
214 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
215 #define HDSP_SyncRef_ADAT1       0
216 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
217 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
218 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
219 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
220 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
221
222 /* Sample Clock Sources */
223
224 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
225 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
226 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
227 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
228 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
229 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
230 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
231 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
232 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
233 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
234
235 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
236
237 #define HDSP_SYNC_FROM_WORD      0
238 #define HDSP_SYNC_FROM_SPDIF     1
239 #define HDSP_SYNC_FROM_ADAT1     2
240 #define HDSP_SYNC_FROM_ADAT_SYNC 3
241 #define HDSP_SYNC_FROM_ADAT2     4
242 #define HDSP_SYNC_FROM_ADAT3     5
243
244 /* SyncCheck status */
245
246 #define HDSP_SYNC_CHECK_NO_LOCK 0
247 #define HDSP_SYNC_CHECK_LOCK    1
248 #define HDSP_SYNC_CHECK_SYNC    2
249
250 /* AutoSync references - used by "autosync_ref" control switch */
251
252 #define HDSP_AUTOSYNC_FROM_WORD      0
253 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
254 #define HDSP_AUTOSYNC_FROM_SPDIF     2
255 #define HDSP_AUTOSYNC_FROM_NONE      3
256 #define HDSP_AUTOSYNC_FROM_ADAT1     4
257 #define HDSP_AUTOSYNC_FROM_ADAT2     5
258 #define HDSP_AUTOSYNC_FROM_ADAT3     6
259
260 /* Possible sources of S/PDIF input */
261
262 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
263 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
264 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
265 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
266
267 #define HDSP_Frequency32KHz    HDSP_Frequency0
268 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
269 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
270 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
271 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
272 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
273 /* For H9632 cards */
274 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
275 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
276 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
277
278 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
279 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
280
281 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
282 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
283
284 /* Status Register bits */
285
286 #define HDSP_audioIRQPending    (1<<0)
287 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
288 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
289 #define HDSP_Lock1              (1<<2)
290 #define HDSP_Lock0              (1<<3)
291 #define HDSP_SPDIFSync          (1<<4)
292 #define HDSP_TimecodeLock       (1<<5)
293 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
294 #define HDSP_Sync2              (1<<16)
295 #define HDSP_Sync1              (1<<17)
296 #define HDSP_Sync0              (1<<18)
297 #define HDSP_DoubleSpeedStatus  (1<<19)
298 #define HDSP_ConfigError        (1<<20)
299 #define HDSP_DllError           (1<<21)
300 #define HDSP_spdifFrequency0    (1<<22)
301 #define HDSP_spdifFrequency1    (1<<23)
302 #define HDSP_spdifFrequency2    (1<<24)
303 #define HDSP_SPDIFErrorFlag     (1<<25)
304 #define HDSP_BufferID           (1<<26)
305 #define HDSP_TimecodeSync       (1<<27)
306 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
307 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
308 #define HDSP_midi0IRQPending    (1<<30) 
309 #define HDSP_midi1IRQPending    (1<<31)
310
311 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
312
313 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
314 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
315 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
316
317 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
318 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
319 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
320
321 /* This is for H9632 cards */
322 #define HDSP_spdifFrequency128KHz   HDSP_spdifFrequencyMask
323 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
324 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
325
326 /* Status2 Register bits */
327
328 #define HDSP_version0     (1<<0)
329 #define HDSP_version1     (1<<1)
330 #define HDSP_version2     (1<<2)
331 #define HDSP_wc_lock      (1<<3)
332 #define HDSP_wc_sync      (1<<4)
333 #define HDSP_inp_freq0    (1<<5)
334 #define HDSP_inp_freq1    (1<<6)
335 #define HDSP_inp_freq2    (1<<7)
336 #define HDSP_SelSyncRef0  (1<<8)
337 #define HDSP_SelSyncRef1  (1<<9)
338 #define HDSP_SelSyncRef2  (1<<10)
339
340 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
341
342 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
343 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
344 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
345 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
346 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
347 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
348 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
349 /* FIXME : more values for 9632 cards ? */
350
351 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
352 #define HDSP_SelSyncRef_ADAT1      0
353 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
354 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
355 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
356 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
357 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
358
359 /* Card state flags */
360
361 #define HDSP_InitializationComplete  (1<<0)
362 #define HDSP_FirmwareLoaded          (1<<1)
363 #define HDSP_FirmwareCached          (1<<2)
364
365 /* FIFO wait times, defined in terms of 1/10ths of msecs */
366
367 #define HDSP_LONG_WAIT   5000
368 #define HDSP_SHORT_WAIT  30
369
370 #define UNITY_GAIN                       32768
371 #define MINUS_INFINITY_GAIN              0
372
373 #ifndef PCI_VENDOR_ID_XILINX
374 #define PCI_VENDOR_ID_XILINX            0x10ee
375 #endif
376 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
377 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
378 #endif
379
380 /* the size of a substream (1 mono data stream) */
381
382 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
383 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
384
385 /* the size of the area we need to allocate for DMA transfers. the
386    size is the same regardless of the number of channels - the 
387    Multiface still uses the same memory area.
388
389    Note that we allocate 1 more channel than is apparently needed
390    because the h/w seems to write 1 byte beyond the end of the last
391    page. Sigh.
392 */
393
394 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
395 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
396
397 /* use hotplug firmeare loader? */
398 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
399 #ifndef HDSP_USE_HWDEP_LOADER
400 #define HDSP_FW_LOADER
401 #endif
402 #endif
403
404 typedef struct _hdsp             hdsp_t;
405 typedef struct _hdsp_midi        hdsp_midi_t;
406 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
407
408 struct _hdsp_9632_meters {
409     u32 input_peak[16];
410     u32 playback_peak[16];
411     u32 output_peak[16];
412     u32 xxx_peak[16];
413     u32 padding[64];
414     u32 input_rms_low[16];
415     u32 playback_rms_low[16];
416     u32 output_rms_low[16];
417     u32 xxx_rms_low[16];
418     u32 input_rms_high[16];
419     u32 playback_rms_high[16];
420     u32 output_rms_high[16];
421     u32 xxx_rms_high[16];
422 };
423
424 struct _hdsp_midi {
425     hdsp_t                  *hdsp;
426     int                      id;
427     snd_rawmidi_t           *rmidi;
428     snd_rawmidi_substream_t *input;
429     snd_rawmidi_substream_t *output;
430     char                     istimer; /* timer in use */
431     struct timer_list        timer;
432     spinlock_t               lock;
433     int                      pending;
434 };
435
436 struct _hdsp {
437         spinlock_t            lock;
438         snd_pcm_substream_t  *capture_substream;
439         snd_pcm_substream_t  *playback_substream;
440         hdsp_midi_t           midi[2];
441         struct tasklet_struct midi_tasklet;
442         int                   use_midi_tasklet;
443         int                   precise_ptr;
444         u32                   control_register;      /* cached value */
445         u32                   control2_register;     /* cached value */
446         u32                   creg_spdif;
447         u32                   creg_spdif_stream;
448         int                   clock_source_locked;
449         char                 *card_name;             /* digiface/multiface */
450         HDSP_IO_Type          io_type;               /* ditto, but for code use */
451         unsigned short        firmware_rev;
452         unsigned short        state;                 /* stores state bits */
453         u32                   firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
454         size_t                period_bytes;          /* guess what this is */
455         unsigned char         max_channels;
456         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
457         unsigned char         ds_in_channels;
458         unsigned char         ss_in_channels;       /* different for multiface/digiface */
459         unsigned char         qs_out_channels;      
460         unsigned char         ds_out_channels;
461         unsigned char         ss_out_channels;
462
463         struct snd_dma_buffer capture_dma_buf;
464         struct snd_dma_buffer playback_dma_buf;
465         unsigned char        *capture_buffer;       /* suitably aligned address */
466         unsigned char        *playback_buffer;      /* suitably aligned address */
467
468         pid_t                 capture_pid;
469         pid_t                 playback_pid;
470         int                   running;
471         int                   system_sample_rate;
472         char                 *channel_map;
473         int                   dev;
474         int                   irq;
475         unsigned long         port;
476         void __iomem         *iobase;
477         snd_card_t           *card;
478         snd_pcm_t            *pcm;
479         snd_hwdep_t          *hwdep;
480         struct pci_dev       *pci;
481         snd_kcontrol_t       *spdif_ctl;
482         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
483 };
484
485 /* These tables map the ALSA channels 1..N to the channels that we
486    need to use in order to find the relevant channel buffer. RME
487    refer to this kind of mapping as between "the ADAT channel and
488    the DMA channel." We index it using the logical audio channel,
489    and the value is the DMA channel (i.e. channel buffer number)
490    where the data for that channel can be read/written from/to.
491 */
492
493 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
494         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
495         18, 19, 20, 21, 22, 23, 24, 25
496 };
497
498 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
499         /* Analog */
500         0, 1, 2, 3, 4, 5, 6, 7, 
501         /* ADAT 2 */
502         16, 17, 18, 19, 20, 21, 22, 23, 
503         /* SPDIF */
504         24, 25,
505         -1, -1, -1, -1, -1, -1, -1, -1
506 };
507
508 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
509         /* ADAT channels are remapped */
510         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
511         /* channels 12 and 13 are S/PDIF */
512         24, 25,
513         /* others don't exist */
514         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
515 };
516
517 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
518         /* ADAT channels */
519         0, 1, 2, 3, 4, 5, 6, 7,
520         /* SPDIF */
521         8, 9,
522         /* Analog */
523         10, 11, 
524         /* AO4S-192 and AI4S-192 extension boards */
525         12, 13, 14, 15,
526         /* others don't exist */
527         -1, -1, -1, -1, -1, -1, -1, -1, 
528         -1, -1
529 };
530
531 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
532         /* ADAT */
533         1, 3, 5, 7,
534         /* SPDIF */
535         8, 9,
536         /* Analog */
537         10, 11, 
538         /* AO4S-192 and AI4S-192 extension boards */
539         12, 13, 14, 15,
540         /* others don't exist */
541         -1, -1, -1, -1, -1, -1, -1, -1,
542         -1, -1, -1, -1, -1, -1
543 };
544
545 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
546         /* ADAT is disabled in this mode */
547         /* SPDIF */
548         8, 9,
549         /* Analog */
550         10, 11,
551         /* AO4S-192 and AI4S-192 extension boards */
552         12, 13, 14, 15,
553         /* others don't exist */
554         -1, -1, -1, -1, -1, -1, -1, -1,
555         -1, -1, -1, -1, -1, -1, -1, -1,
556         -1, -1
557 };
558
559 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
560 {
561         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
562         dmab->dev.dev = snd_dma_pci_data(pci);
563         if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
564                 if (dmab->bytes >= size)
565                         return 0;
566         }
567         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
568                                 size, dmab) < 0)
569                 return -ENOMEM;
570         return 0;
571 }
572
573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
574 {
575         if (dmab->area) {
576                 dmab->dev.dev = NULL; /* make it anonymous */
577                 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
578         }
579 }
580
581
582 static struct pci_device_id snd_hdsp_ids[] = {
583         {
584                 .vendor = PCI_VENDOR_ID_XILINX,
585                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 
586                 .subvendor = PCI_ANY_ID,
587                 .subdevice = PCI_ANY_ID,
588         }, /* RME Hammerfall-DSP */
589         { 0, },
590 };
591
592 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
593
594 /* prototypes */
595 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
596 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
597 static int snd_hdsp_enable_io (hdsp_t *hdsp);
598 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
599 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
600 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
601 static int hdsp_autosync_ref(hdsp_t *hdsp);
602 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
603 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
604
605 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
606 {
607         switch (hdsp->firmware_rev) {
608         case 0xa:
609                 return (64 * out) + (32 + (in));
610         case 0x96:
611         case 0x97:
612                 return (32 * out) + (16 + (in));
613         default:
614                 return (52 * out) + (26 + (in));
615         }
616 }
617
618 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
619 {
620         switch (hdsp->firmware_rev) {
621         case 0xa:
622                 return (64 * out) + in;
623         case 0x96:
624         case 0x97:
625                 return (32 * out) + in;
626         default:
627                 return (52 * out) + in;
628         }
629 }
630
631 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
632 {
633         writel(val, hdsp->iobase + reg);
634 }
635
636 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
637 {
638         return readl (hdsp->iobase + reg);
639 }
640
641 static int hdsp_check_for_iobox (hdsp_t *hdsp)
642 {
643
644         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
645         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
646                 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
647                 hdsp->state &= ~HDSP_FirmwareLoaded;
648                 return -EIO;
649         }
650         return 0;
651
652 }
653
654 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
655
656         int i;
657         unsigned long flags;
658
659         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
660                 
661                 snd_printk ("Hammerfall-DSP: loading firmware\n");
662
663                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
664                 hdsp_write (hdsp, HDSP_fifoData, 0);
665                 
666                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
667                         snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
668                         return -EIO;
669                 }
670                 
671                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
672                 
673                 for (i = 0; i < 24413; ++i) {
674                         hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
675                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
676                                 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
677                                 return -EIO;
678                         }
679                 }
680
681                 if ((1000 / HZ) < 3000) {
682                         ssleep(3);
683                 } else {
684                         mdelay(3000);
685                 }
686                 
687                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
688                         snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
689                         return -EIO;
690                 }
691
692 #ifdef SNDRV_BIG_ENDIAN
693                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
694 #else
695                 hdsp->control2_register = 0;
696 #endif
697                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
698                 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
699                 
700         }
701         if (hdsp->state & HDSP_InitializationComplete) {
702                 snd_printk("Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
703                 spin_lock_irqsave(&hdsp->lock, flags);
704                 snd_hdsp_set_defaults(hdsp);
705                 spin_unlock_irqrestore(&hdsp->lock, flags); 
706         }
707         
708         hdsp->state |= HDSP_FirmwareLoaded;
709
710         return 0;
711 }
712
713 static int hdsp_get_iobox_version (hdsp_t *hdsp)
714 {
715         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
716         
717                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
718                 hdsp_write (hdsp, HDSP_fifoData, 0);
719                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
720                         return -EIO;
721                 }
722
723                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
724                 hdsp_write (hdsp, HDSP_fifoData, 0);
725
726                 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
727                         hdsp->io_type = Multiface;
728                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
729                         hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
730                         hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
731                 } else {
732                         hdsp->io_type = Digiface;
733                 } 
734         } else {
735                 /* firmware was already loaded, get iobox type */
736                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
737                         hdsp->io_type = Multiface;
738                 } else {
739                         hdsp->io_type = Digiface;
740                 }
741         }
742         return 0;
743 }
744
745
746 static int hdsp_check_for_firmware (hdsp_t *hdsp)
747 {
748         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
749         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
750                 snd_printk("Hammerfall-DSP: firmware not present.\n");
751                 hdsp->state &= ~HDSP_FirmwareLoaded;
752                 return -EIO;
753         }
754         return 0;
755 }
756
757
758 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
759 {    
760         int i;
761
762         /* the fifoStatus registers reports on how many words
763            are available in the command FIFO.
764         */
765         
766         for (i = 0; i < timeout; i++) {
767
768                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
769                         return 0;
770
771                 /* not very friendly, but we only do this during a firmware
772                    load and changing the mixer, so we just put up with it.
773                 */
774
775                 udelay (100);
776         }
777
778         snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
779                     count, timeout);
780         return -1;
781 }
782
783 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
784 {
785         if (addr >= HDSP_MATRIX_MIXER_SIZE) {
786                 return 0;
787         }
788         return hdsp->mixer_matrix[addr];
789 }
790
791 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
792 {
793         unsigned int ad;
794
795         if (addr >= HDSP_MATRIX_MIXER_SIZE)
796                 return -1;
797         
798         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
799
800                 /* from martin bjornsen:
801                    
802                    "You can only write dwords to the
803                    mixer memory which contain two
804                    mixer values in the low and high
805                    word. So if you want to change
806                    value 0 you have to read value 1
807                    from the cache and write both to
808                    the first dword in the mixer
809                    memory."
810                 */
811
812                 if (hdsp->io_type == H9632 && addr >= 512) {
813                         return 0;
814                 }
815
816                 if (hdsp->io_type == H9652 && addr >= 1352) {
817                         return 0;
818                 }
819
820                 hdsp->mixer_matrix[addr] = data;
821
822                 
823                 /* `addr' addresses a 16-bit wide address, but
824                    the address space accessed via hdsp_write
825                    uses byte offsets. put another way, addr
826                    varies from 0 to 1351, but to access the
827                    corresponding memory location, we need
828                    to access 0 to 2703 ...
829                 */
830                 ad = addr/2;
831         
832                 hdsp_write (hdsp, 4096 + (ad*4), 
833                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 
834                             hdsp->mixer_matrix[addr&0x7fe]);
835                 
836                 return 0;
837
838         } else {
839
840                 ad = (addr << 16) + data;
841                 
842                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
843                         return -1;
844                 }
845
846                 hdsp_write (hdsp, HDSP_fifoData, ad);
847                 hdsp->mixer_matrix[addr] = data;
848
849         }
850
851         return 0;
852 }
853
854 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
855 {
856         unsigned long flags;
857         int ret = 1;
858
859         spin_lock_irqsave(&hdsp->lock, flags);
860         if ((hdsp->playback_pid != hdsp->capture_pid) &&
861             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
862                 ret = 0;
863         }
864         spin_unlock_irqrestore(&hdsp->lock, flags);
865         return ret;
866 }
867
868 static int hdsp_external_sample_rate (hdsp_t *hdsp)
869 {
870         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
871         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
872
873         switch (rate_bits) {
874         case HDSP_systemFrequency32:   return 32000;
875         case HDSP_systemFrequency44_1: return 44100;
876         case HDSP_systemFrequency48:   return 48000;
877         case HDSP_systemFrequency64:   return 64000;
878         case HDSP_systemFrequency88_2: return 88200;
879         case HDSP_systemFrequency96:   return 96000;
880         default:
881                 return 0;
882         }
883 }
884
885 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
886 {
887         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
888         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
889
890         if (status & HDSP_SPDIFErrorFlag) {
891                 return 0;
892         }
893         
894         switch (rate_bits) {
895         case HDSP_spdifFrequency32KHz: return 32000;
896         case HDSP_spdifFrequency44_1KHz: return 44100;
897         case HDSP_spdifFrequency48KHz: return 48000;
898         case HDSP_spdifFrequency64KHz: return 64000;
899         case HDSP_spdifFrequency88_2KHz: return 88200;
900         case HDSP_spdifFrequency96KHz: return 96000;
901         case HDSP_spdifFrequency128KHz: 
902                 if (hdsp->io_type == H9632) return 128000;
903                 break;
904         case HDSP_spdifFrequency176_4KHz: 
905                 if (hdsp->io_type == H9632) return 176400;
906                 break;
907         case HDSP_spdifFrequency192KHz: 
908                 if (hdsp->io_type == H9632) return 192000;
909                 break;
910         default:
911                 break;
912         }
913         snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
914         return 0;
915 }
916
917 static void hdsp_compute_period_size(hdsp_t *hdsp)
918 {
919         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
920 }
921
922 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
923 {
924         int position;
925
926         position = hdsp_read(hdsp, HDSP_statusRegister);
927
928         if (!hdsp->precise_ptr) {
929                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
930         }
931
932         position &= HDSP_BufferPositionMask;
933         position /= 4;
934         position &= (hdsp->period_bytes/2) - 1;
935         return position;
936 }
937
938 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
939 {
940         hdsp_write (hdsp, HDSP_resetPointer, 0);
941 }
942
943 static void hdsp_start_audio(hdsp_t *s)
944 {
945         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
946         hdsp_write(s, HDSP_controlRegister, s->control_register);
947 }
948
949 static void hdsp_stop_audio(hdsp_t *s)
950 {
951         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
952         hdsp_write(s, HDSP_controlRegister, s->control_register);
953 }
954
955 static void hdsp_silence_playback(hdsp_t *hdsp)
956 {
957         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
958 }
959
960 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
961 {
962         int n;
963
964         spin_lock_irq(&s->lock);
965
966         frames >>= 7;
967         n = 0;
968         while (frames) {
969                 n++;
970                 frames >>= 1;
971         }
972
973         s->control_register &= ~HDSP_LatencyMask;
974         s->control_register |= hdsp_encode_latency(n);
975
976         hdsp_write(s, HDSP_controlRegister, s->control_register);
977
978         hdsp_compute_period_size(s);
979
980         spin_unlock_irq(&s->lock);
981
982         return 0;
983 }
984
985 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
986 {
987         int reject_if_open = 0;
988         int current_rate;
989         int rate_bits;
990
991         /* ASSUMPTION: hdsp->lock is either held, or
992            there is no need for it (e.g. during module
993            initialization).
994         */
995         
996         if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 
997                 if (called_internally) {
998                         /* request from ctl or card initialization */
999                         snd_printk("Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1000                         return -1;
1001                 } else {                
1002                         /* hw_param request while in AutoSync mode */
1003                         int external_freq = hdsp_external_sample_rate(hdsp);
1004                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1005                 
1006                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1007                                 snd_printk("Hammerfall-DSP: Detected ADAT in double speed mode\n");
1008                         } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1009                                 snd_printk("Hammerfall-DSP: Detected ADAT in quad speed mode\n");                       
1010                         } else if (rate != external_freq) {
1011                                 snd_printk("Hammerfall-DSP: No AutoSync source for requested rate\n");
1012                                 return -1;
1013                         }               
1014                 }       
1015         }
1016
1017         current_rate = hdsp->system_sample_rate;
1018
1019         /* Changing from a "single speed" to a "double speed" rate is
1020            not allowed if any substreams are open. This is because
1021            such a change causes a shift in the location of 
1022            the DMA buffers and a reduction in the number of available
1023            buffers. 
1024
1025            Note that a similar but essentially insoluble problem
1026            exists for externally-driven rate changes. All we can do
1027            is to flag rate changes in the read/write routines.  */
1028
1029         if (rate > 96000 && hdsp->io_type != H9632) {
1030                 return -EINVAL;
1031         }
1032         
1033         switch (rate) {
1034         case 32000:
1035                 if (current_rate > 48000) {
1036                         reject_if_open = 1;
1037                 }
1038                 rate_bits = HDSP_Frequency32KHz;
1039                 break;
1040         case 44100:
1041                 if (current_rate > 48000) {
1042                         reject_if_open = 1;
1043                 }
1044                 rate_bits = HDSP_Frequency44_1KHz;
1045                 break;
1046         case 48000:
1047                 if (current_rate > 48000) {
1048                         reject_if_open = 1;
1049                 }
1050                 rate_bits = HDSP_Frequency48KHz;
1051                 break;
1052         case 64000:
1053                 if (current_rate <= 48000 || current_rate > 96000) {
1054                         reject_if_open = 1;
1055                 }
1056                 rate_bits = HDSP_Frequency64KHz;
1057                 break;
1058         case 88200:
1059                 if (current_rate <= 48000 || current_rate > 96000) {
1060                         reject_if_open = 1;
1061                 }
1062                 rate_bits = HDSP_Frequency88_2KHz;
1063                 break;
1064         case 96000:
1065                 if (current_rate <= 48000 || current_rate > 96000) {
1066                         reject_if_open = 1;
1067                 }
1068                 rate_bits = HDSP_Frequency96KHz;
1069                 break;
1070         case 128000:
1071                 if (current_rate < 128000) {
1072                         reject_if_open = 1;
1073                 }
1074                 rate_bits = HDSP_Frequency128KHz;
1075                 break;
1076         case 176400:
1077                 if (current_rate < 128000) {
1078                         reject_if_open = 1;
1079                 }
1080                 rate_bits = HDSP_Frequency176_4KHz;
1081                 break;
1082         case 192000:
1083                 if (current_rate < 128000) {
1084                         reject_if_open = 1;
1085                 }
1086                 rate_bits = HDSP_Frequency192KHz;
1087                 break;
1088         default:
1089                 return -EINVAL;
1090         }
1091
1092         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1093                 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1094                             hdsp->capture_pid,
1095                             hdsp->playback_pid);
1096                 return -EBUSY;
1097         }
1098
1099         hdsp->control_register &= ~HDSP_FrequencyMask;
1100         hdsp->control_register |= rate_bits;
1101         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1102
1103         if (rate >= 128000) {
1104                 hdsp->channel_map = channel_map_H9632_qs;
1105         } else if (rate > 48000) {
1106                 if (hdsp->io_type == H9632) {
1107                         hdsp->channel_map = channel_map_H9632_ds;
1108                 } else {
1109                         hdsp->channel_map = channel_map_ds;
1110                 }
1111         } else {
1112                 switch (hdsp->io_type) {
1113                 case Multiface:
1114                         hdsp->channel_map = channel_map_mf_ss;
1115                         break;
1116                 case Digiface:
1117                 case H9652:
1118                         hdsp->channel_map = channel_map_df_ss;
1119                         break;
1120                 case H9632:
1121                         hdsp->channel_map = channel_map_H9632_ss;
1122                         break;
1123                 default:
1124                         /* should never happen */
1125                         break;
1126                 }
1127         }
1128         
1129         hdsp->system_sample_rate = rate;
1130
1131         return 0;
1132 }
1133
1134 /*----------------------------------------------------------------------------
1135    MIDI
1136   ----------------------------------------------------------------------------*/
1137
1138 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1139 {
1140         /* the hardware already does the relevant bit-mask with 0xff */
1141         if (id) {
1142                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1143         } else {
1144                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1145         }
1146 }
1147
1148 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1149 {
1150         /* the hardware already does the relevant bit-mask with 0xff */
1151         if (id) {
1152                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1153         } else {
1154                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1155         }
1156 }
1157
1158 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1159 {
1160         if (id) {
1161                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1162         } else {
1163                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1164         }
1165 }
1166
1167 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1168 {
1169         int fifo_bytes_used;
1170
1171         if (id) {
1172                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1173         } else {
1174                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1175         }
1176
1177         if (fifo_bytes_used < 128) {
1178                 return  128 - fifo_bytes_used;
1179         } else {
1180                 return 0;
1181         }
1182 }
1183
1184 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1185 {
1186         while (snd_hdsp_midi_input_available (hdsp, id)) {
1187                 snd_hdsp_midi_read_byte (hdsp, id);
1188         }
1189 }
1190
1191 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1192 {
1193         unsigned long flags;
1194         int n_pending;
1195         int to_write;
1196         int i;
1197         unsigned char buf[128];
1198
1199         /* Output is not interrupt driven */
1200                 
1201         spin_lock_irqsave (&hmidi->lock, flags);
1202         if (hmidi->output) {
1203                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1204                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1205                                 if (n_pending > (int)sizeof (buf))
1206                                         n_pending = sizeof (buf);
1207                                 
1208                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1209                                         for (i = 0; i < to_write; ++i) 
1210                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1211                                 }
1212                         }
1213                 }
1214         }
1215         spin_unlock_irqrestore (&hmidi->lock, flags);
1216         return 0;
1217 }
1218
1219 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1220 {
1221         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1222         unsigned long flags;
1223         int n_pending;
1224         int i;
1225
1226         spin_lock_irqsave (&hmidi->lock, flags);
1227         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1228                 if (hmidi->input) {
1229                         if (n_pending > (int)sizeof (buf)) {
1230                                 n_pending = sizeof (buf);
1231                         }
1232                         for (i = 0; i < n_pending; ++i) {
1233                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1234                         }
1235                         if (n_pending) {
1236                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1237                         }
1238                 } else {
1239                         /* flush the MIDI input FIFO */
1240                         while (--n_pending) {
1241                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1242                         }
1243                 }
1244         }
1245         hmidi->pending = 0;
1246         if (hmidi->id) {
1247                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1248         } else {
1249                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1250         }
1251         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1252         spin_unlock_irqrestore (&hmidi->lock, flags);
1253         return snd_hdsp_midi_output_write (hmidi);
1254 }
1255
1256 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1257 {
1258         hdsp_t *hdsp;
1259         hdsp_midi_t *hmidi;
1260         unsigned long flags;
1261         u32 ie;
1262
1263         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1264         hdsp = hmidi->hdsp;
1265         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1266         spin_lock_irqsave (&hdsp->lock, flags);
1267         if (up) {
1268                 if (!(hdsp->control_register & ie)) {
1269                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1270                         hdsp->control_register |= ie;
1271                 }
1272         } else {
1273                 hdsp->control_register &= ~ie;
1274                 tasklet_kill(&hdsp->midi_tasklet);
1275         }
1276
1277         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1278         spin_unlock_irqrestore (&hdsp->lock, flags);
1279 }
1280
1281 static void snd_hdsp_midi_output_timer(unsigned long data)
1282 {
1283         hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1284         unsigned long flags;
1285         
1286         snd_hdsp_midi_output_write(hmidi);
1287         spin_lock_irqsave (&hmidi->lock, flags);
1288
1289         /* this does not bump hmidi->istimer, because the
1290            kernel automatically removed the timer when it
1291            expired, and we are now adding it back, thus
1292            leaving istimer wherever it was set before.  
1293         */
1294
1295         if (hmidi->istimer) {
1296                 hmidi->timer.expires = 1 + jiffies;
1297                 add_timer(&hmidi->timer);
1298         }
1299
1300         spin_unlock_irqrestore (&hmidi->lock, flags);
1301 }
1302
1303 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1304 {
1305         hdsp_midi_t *hmidi;
1306         unsigned long flags;
1307
1308         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1309         spin_lock_irqsave (&hmidi->lock, flags);
1310         if (up) {
1311                 if (!hmidi->istimer) {
1312                         init_timer(&hmidi->timer);
1313                         hmidi->timer.function = snd_hdsp_midi_output_timer;
1314                         hmidi->timer.data = (unsigned long) hmidi;
1315                         hmidi->timer.expires = 1 + jiffies;
1316                         add_timer(&hmidi->timer);
1317                         hmidi->istimer++;
1318                 }
1319         } else {
1320                 if (hmidi->istimer && --hmidi->istimer <= 0) {
1321                         del_timer (&hmidi->timer);
1322                 }
1323         }
1324         spin_unlock_irqrestore (&hmidi->lock, flags);
1325         if (up)
1326                 snd_hdsp_midi_output_write(hmidi);
1327 }
1328
1329 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1330 {
1331         hdsp_midi_t *hmidi;
1332
1333         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1334         spin_lock_irq (&hmidi->lock);
1335         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1336         hmidi->input = substream;
1337         spin_unlock_irq (&hmidi->lock);
1338
1339         return 0;
1340 }
1341
1342 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1343 {
1344         hdsp_midi_t *hmidi;
1345
1346         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1347         spin_lock_irq (&hmidi->lock);
1348         hmidi->output = substream;
1349         spin_unlock_irq (&hmidi->lock);
1350
1351         return 0;
1352 }
1353
1354 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1355 {
1356         hdsp_midi_t *hmidi;
1357
1358         snd_hdsp_midi_input_trigger (substream, 0);
1359
1360         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1361         spin_lock_irq (&hmidi->lock);
1362         hmidi->input = NULL;
1363         spin_unlock_irq (&hmidi->lock);
1364
1365         return 0;
1366 }
1367
1368 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1369 {
1370         hdsp_midi_t *hmidi;
1371
1372         snd_hdsp_midi_output_trigger (substream, 0);
1373
1374         hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1375         spin_lock_irq (&hmidi->lock);
1376         hmidi->output = NULL;
1377         spin_unlock_irq (&hmidi->lock);
1378
1379         return 0;
1380 }
1381
1382 static snd_rawmidi_ops_t snd_hdsp_midi_output =
1383 {
1384         .open =         snd_hdsp_midi_output_open,
1385         .close =        snd_hdsp_midi_output_close,
1386         .trigger =      snd_hdsp_midi_output_trigger,
1387 };
1388
1389 static snd_rawmidi_ops_t snd_hdsp_midi_input =
1390 {
1391         .open =         snd_hdsp_midi_input_open,
1392         .close =        snd_hdsp_midi_input_close,
1393         .trigger =      snd_hdsp_midi_input_trigger,
1394 };
1395
1396 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1397 {
1398         char buf[32];
1399
1400         hdsp->midi[id].id = id;
1401         hdsp->midi[id].rmidi = NULL;
1402         hdsp->midi[id].input = NULL;
1403         hdsp->midi[id].output = NULL;
1404         hdsp->midi[id].hdsp = hdsp;
1405         hdsp->midi[id].istimer = 0;
1406         hdsp->midi[id].pending = 0;
1407         spin_lock_init (&hdsp->midi[id].lock);
1408
1409         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1410         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1411                 return -1;
1412         }
1413
1414         sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1415         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1416
1417         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1418         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1419
1420         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1421                 SNDRV_RAWMIDI_INFO_INPUT |
1422                 SNDRV_RAWMIDI_INFO_DUPLEX;
1423
1424         return 0;
1425 }
1426
1427 /*-----------------------------------------------------------------------------
1428   Control Interface
1429   ----------------------------------------------------------------------------*/
1430
1431 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1432 {
1433         u32 val = 0;
1434         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1435         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1436         if (val & HDSP_SPDIFProfessional)
1437                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1438         else
1439                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1440         return val;
1441 }
1442
1443 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1444 {
1445         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1446                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1447         if (val & HDSP_SPDIFProfessional)
1448                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1449         else
1450                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1451 }
1452
1453 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1454 {
1455         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1456         uinfo->count = 1;
1457         return 0;
1458 }
1459
1460 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1461 {
1462         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1463         
1464         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1465         return 0;
1466 }
1467
1468 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1469 {
1470         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1471         int change;
1472         u32 val;
1473         
1474         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1475         spin_lock_irq(&hdsp->lock);
1476         change = val != hdsp->creg_spdif;
1477         hdsp->creg_spdif = val;
1478         spin_unlock_irq(&hdsp->lock);
1479         return change;
1480 }
1481
1482 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1483 {
1484         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1485         uinfo->count = 1;
1486         return 0;
1487 }
1488
1489 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1490 {
1491         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1492         
1493         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1494         return 0;
1495 }
1496
1497 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1498 {
1499         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1500         int change;
1501         u32 val;
1502         
1503         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1504         spin_lock_irq(&hdsp->lock);
1505         change = val != hdsp->creg_spdif_stream;
1506         hdsp->creg_spdif_stream = val;
1507         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1508         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1509         spin_unlock_irq(&hdsp->lock);
1510         return change;
1511 }
1512
1513 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1514 {
1515         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1516         uinfo->count = 1;
1517         return 0;
1518 }
1519
1520 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1521 {
1522         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1523         return 0;
1524 }
1525
1526 #define HDSP_SPDIF_IN(xname, xindex) \
1527 { .iface = SNDRV_CTL_ELEM_IFACE_PCM,  \
1528   .name = xname, \
1529   .index = xindex, \
1530   .info = snd_hdsp_info_spdif_in, \
1531   .get = snd_hdsp_get_spdif_in, \
1532   .put = snd_hdsp_put_spdif_in }
1533
1534 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1535 {
1536         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1537 }
1538
1539 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1540 {
1541         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1542         hdsp->control_register |= hdsp_encode_spdif_in(in);
1543         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1544         return 0;
1545 }
1546
1547 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1548 {
1549         static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1550         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1551
1552         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1553         uinfo->count = 1;
1554         uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1555         if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1556                 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1557         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1558         return 0;
1559 }
1560
1561 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1562 {
1563         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1564         
1565         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1566         return 0;
1567 }
1568
1569 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1570 {
1571         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1572         int change;
1573         unsigned int val;
1574         
1575         if (!snd_hdsp_use_is_exclusive(hdsp))
1576                 return -EBUSY;
1577         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1578         spin_lock_irq(&hdsp->lock);
1579         change = val != hdsp_spdif_in(hdsp);
1580         if (change)
1581                 hdsp_set_spdif_input(hdsp, val);
1582         spin_unlock_irq(&hdsp->lock);
1583         return change;
1584 }
1585
1586 #define HDSP_SPDIF_OUT(xname, xindex) \
1587 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1588   .info = snd_hdsp_info_spdif_bits, \
1589   .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1590
1591 static int hdsp_spdif_out(hdsp_t *hdsp)
1592 {
1593         return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1594 }
1595
1596 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1597 {
1598         if (out) {
1599                 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1600         } else {
1601                 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1602         }
1603         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1604         return 0;
1605 }
1606
1607 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1608 {
1609         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1610         uinfo->count = 1;
1611         uinfo->value.integer.min = 0;
1612         uinfo->value.integer.max = 1;
1613         return 0;
1614 }
1615
1616 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1617 {
1618         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1619         
1620         ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1621         return 0;
1622 }
1623
1624 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1625 {
1626         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1627         int change;
1628         unsigned int val;
1629         
1630         if (!snd_hdsp_use_is_exclusive(hdsp))
1631                 return -EBUSY;
1632         val = ucontrol->value.integer.value[0] & 1;
1633         spin_lock_irq(&hdsp->lock);
1634         change = (int)val != hdsp_spdif_out(hdsp);
1635         hdsp_set_spdif_output(hdsp, val);
1636         spin_unlock_irq(&hdsp->lock);
1637         return change;
1638 }
1639
1640 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1641 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1642   .info = snd_hdsp_info_spdif_bits, \
1643   .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1644
1645 static int hdsp_spdif_professional(hdsp_t *hdsp)
1646 {
1647         return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1648 }
1649
1650 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1651 {
1652         if (val) {
1653                 hdsp->control_register |= HDSP_SPDIFProfessional;
1654         } else {
1655                 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1656         }
1657         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1658         return 0;
1659 }
1660
1661 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1662 {
1663         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1664         
1665         ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1666         return 0;
1667 }
1668
1669 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1670 {
1671         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1672         int change;
1673         unsigned int val;
1674         
1675         if (!snd_hdsp_use_is_exclusive(hdsp))
1676                 return -EBUSY;
1677         val = ucontrol->value.integer.value[0] & 1;
1678         spin_lock_irq(&hdsp->lock);
1679         change = (int)val != hdsp_spdif_professional(hdsp);
1680         hdsp_set_spdif_professional(hdsp, val);
1681         spin_unlock_irq(&hdsp->lock);
1682         return change;
1683 }
1684
1685 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1686 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1687   .info = snd_hdsp_info_spdif_bits, \
1688   .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1689
1690 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1691 {
1692         return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1693 }
1694
1695 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1696 {
1697         if (val) {
1698                 hdsp->control_register |= HDSP_SPDIFEmphasis;
1699         } else {
1700                 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1701         }
1702         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1703         return 0;
1704 }
1705
1706 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1707 {
1708         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1709         
1710         ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1711         return 0;
1712 }
1713
1714 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1715 {
1716         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1717         int change;
1718         unsigned int val;
1719         
1720         if (!snd_hdsp_use_is_exclusive(hdsp))
1721                 return -EBUSY;
1722         val = ucontrol->value.integer.value[0] & 1;
1723         spin_lock_irq(&hdsp->lock);
1724         change = (int)val != hdsp_spdif_emphasis(hdsp);
1725         hdsp_set_spdif_emphasis(hdsp, val);
1726         spin_unlock_irq(&hdsp->lock);
1727         return change;
1728 }
1729
1730 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1731 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1732   .info = snd_hdsp_info_spdif_bits, \
1733   .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1734
1735 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1736 {
1737         return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1738 }
1739
1740 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1741 {
1742         if (val) {
1743                 hdsp->control_register |= HDSP_SPDIFNonAudio;
1744         } else {
1745                 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1746         }
1747         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1748         return 0;
1749 }
1750
1751 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1752 {
1753         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1754         
1755         ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1756         return 0;
1757 }
1758
1759 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1760 {
1761         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1762         int change;
1763         unsigned int val;
1764         
1765         if (!snd_hdsp_use_is_exclusive(hdsp))
1766                 return -EBUSY;
1767         val = ucontrol->value.integer.value[0] & 1;
1768         spin_lock_irq(&hdsp->lock);
1769         change = (int)val != hdsp_spdif_nonaudio(hdsp);
1770         hdsp_set_spdif_nonaudio(hdsp, val);
1771         spin_unlock_irq(&hdsp->lock);
1772         return change;
1773 }
1774
1775 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1776 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1777   .name = xname, \
1778   .index = xindex, \
1779   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1780   .info = snd_hdsp_info_spdif_sample_rate, \
1781   .get = snd_hdsp_get_spdif_sample_rate \
1782 }
1783
1784 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1785 {
1786         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1787         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1788
1789         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1790         uinfo->count = 1;
1791         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1792         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1793                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1794         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1795         return 0;
1796 }
1797
1798 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1799 {
1800         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1801         
1802         switch (hdsp_spdif_sample_rate(hdsp)) {
1803         case 32000:
1804                 ucontrol->value.enumerated.item[0] = 0;
1805                 break;
1806         case 44100:
1807                 ucontrol->value.enumerated.item[0] = 1;
1808                 break;
1809         case 48000:
1810                 ucontrol->value.enumerated.item[0] = 2;
1811                 break;
1812         case 64000:
1813                 ucontrol->value.enumerated.item[0] = 3;
1814                 break;
1815         case 88200:
1816                 ucontrol->value.enumerated.item[0] = 4;
1817                 break;
1818         case 96000:
1819                 ucontrol->value.enumerated.item[0] = 5;
1820                 break;
1821         case 128000:
1822                 ucontrol->value.enumerated.item[0] = 7;
1823                 break;
1824         case 176400:
1825                 ucontrol->value.enumerated.item[0] = 8;
1826                 break;
1827         case 192000:
1828                 ucontrol->value.enumerated.item[0] = 9;
1829                 break;
1830         default:
1831                 ucontrol->value.enumerated.item[0] = 6;         
1832         }
1833         return 0;
1834 }
1835
1836 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1837 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1838   .name = xname, \
1839   .index = xindex, \
1840   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1841   .info = snd_hdsp_info_system_sample_rate, \
1842   .get = snd_hdsp_get_system_sample_rate \
1843 }
1844
1845 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1846 {
1847         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1848         uinfo->count = 1;
1849         return 0;
1850 }
1851
1852 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1853 {
1854         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1855         
1856         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1857         return 0;
1858 }
1859
1860 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1861 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1862   .name = xname, \
1863   .index = xindex, \
1864   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1865   .info = snd_hdsp_info_autosync_sample_rate, \
1866   .get = snd_hdsp_get_autosync_sample_rate \
1867 }
1868
1869 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1870 {
1871         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1872         static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};    
1873         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1874         uinfo->count = 1;
1875         uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1876         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1877                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1878         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1879         return 0;
1880 }
1881
1882 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1883 {
1884         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1885         
1886         switch (hdsp_external_sample_rate(hdsp)) {
1887         case 32000:
1888                 ucontrol->value.enumerated.item[0] = 0;
1889                 break;
1890         case 44100:
1891                 ucontrol->value.enumerated.item[0] = 1;
1892                 break;
1893         case 48000:
1894                 ucontrol->value.enumerated.item[0] = 2;
1895                 break;
1896         case 64000:
1897                 ucontrol->value.enumerated.item[0] = 3;
1898                 break;
1899         case 88200:
1900                 ucontrol->value.enumerated.item[0] = 4;
1901                 break;
1902         case 96000:
1903                 ucontrol->value.enumerated.item[0] = 5;
1904                 break;
1905         case 128000:
1906                 ucontrol->value.enumerated.item[0] = 7;
1907                 break;
1908         case 176400:
1909                 ucontrol->value.enumerated.item[0] = 8;
1910                 break;
1911         case 192000:
1912                 ucontrol->value.enumerated.item[0] = 9;
1913                 break;  
1914         default:
1915                 ucontrol->value.enumerated.item[0] = 6;         
1916         }
1917         return 0;
1918 }
1919
1920 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1921 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1922   .name = xname, \
1923   .index = xindex, \
1924   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1925   .info = snd_hdsp_info_system_clock_mode, \
1926   .get = snd_hdsp_get_system_clock_mode \
1927 }
1928
1929 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1930 {
1931         if (hdsp->control_register & HDSP_ClockModeMaster) {
1932                 return 0;
1933         } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
1934                         return 0;
1935         }
1936         return 1;
1937 }
1938
1939 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1940 {
1941         static char *texts[] = {"Master", "Slave" };
1942         
1943         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1944         uinfo->count = 1;
1945         uinfo->value.enumerated.items = 2;
1946         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1947                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1948         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1949         return 0;
1950 }
1951
1952 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1953 {
1954         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1955         
1956         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1957         return 0;
1958 }
1959
1960 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1961 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1962   .name = xname, \
1963   .index = xindex, \
1964   .info = snd_hdsp_info_clock_source, \
1965   .get = snd_hdsp_get_clock_source, \
1966   .put = snd_hdsp_put_clock_source \
1967 }
1968
1969 static int hdsp_clock_source(hdsp_t *hdsp)
1970 {
1971         if (hdsp->control_register & HDSP_ClockModeMaster) {
1972                 switch (hdsp->system_sample_rate) {
1973                 case 32000:
1974                         return 1;
1975                 case 44100:
1976                         return 2;
1977                 case 48000:
1978                         return 3;
1979                 case 64000:
1980                         return 4;
1981                 case 88200:
1982                         return 5;
1983                 case 96000:
1984                         return 6;
1985                 case 128000:
1986                         return 7;
1987                 case 176400:
1988                         return 8;
1989                 case 192000:
1990                         return 9;
1991                 default:
1992                         return 3;       
1993                 }
1994         } else {
1995                 return 0;
1996         }
1997 }
1998
1999 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2000 {
2001         int rate;
2002         switch (mode) {
2003         case HDSP_CLOCK_SOURCE_AUTOSYNC:
2004                 if (hdsp_external_sample_rate(hdsp) != 0) {
2005                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2006                         hdsp->control_register &= ~HDSP_ClockModeMaster;                
2007                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2008                         return 0;
2009                     }
2010                 }
2011                 return -1;
2012         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2013                 rate = 32000;
2014                 break;
2015         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2016                 rate = 44100;
2017                 break;      
2018         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2019                 rate = 48000;
2020                 break;
2021         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2022                 rate = 64000;
2023                 break;
2024         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2025                 rate = 88200;
2026                 break;
2027         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2028                 rate = 96000;
2029                 break;
2030         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2031                 rate = 128000;
2032                 break;
2033         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2034                 rate = 176400;
2035                 break;
2036         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2037                 rate = 192000;
2038                 break;
2039         default:
2040                 rate = 48000;
2041         }
2042         hdsp->control_register |= HDSP_ClockModeMaster;
2043         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2044         hdsp_set_rate(hdsp, rate, 1);
2045         return 0;
2046 }
2047
2048 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2049 {
2050         static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2051         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2052         
2053         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2054         uinfo->count = 1;
2055         if (hdsp->io_type == H9632)
2056             uinfo->value.enumerated.items = 10;
2057         else
2058             uinfo->value.enumerated.items = 7;  
2059         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2060                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2061         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2062         return 0;
2063 }
2064
2065 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2066 {
2067         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2068         
2069         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2070         return 0;
2071 }
2072
2073 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2074 {
2075         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2076         int change;
2077         int val;
2078         
2079         if (!snd_hdsp_use_is_exclusive(hdsp))
2080                 return -EBUSY;
2081         val = ucontrol->value.enumerated.item[0];
2082         if (val < 0) val = 0;
2083         if (hdsp->io_type == H9632) {
2084             if (val > 9) val = 9;
2085         } else {
2086             if (val > 6) val = 6;
2087         }
2088         spin_lock_irq(&hdsp->lock);
2089         if (val != hdsp_clock_source(hdsp)) {
2090                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2091         } else {
2092                 change = 0;
2093         }
2094         spin_unlock_irq(&hdsp->lock);
2095         return change;
2096 }
2097
2098 static int snd_hdsp_info_clock_source_lock(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2099 {
2100         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2101         uinfo->count = 1;
2102         uinfo->value.integer.min = 0;
2103         uinfo->value.integer.max = 1;
2104         return 0;
2105 }
2106
2107 static int snd_hdsp_get_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2108 {
2109         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2110         
2111         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2112         return 0;
2113 }
2114
2115 static int snd_hdsp_put_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2116 {
2117         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2118         int change;
2119
2120         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2121         if (change)
2122                 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2123         return change;
2124 }
2125
2126 #define HDSP_DA_GAIN(xname, xindex) \
2127 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2128   .name = xname, \
2129   .index = xindex, \
2130   .info = snd_hdsp_info_da_gain, \
2131   .get = snd_hdsp_get_da_gain, \
2132   .put = snd_hdsp_put_da_gain \
2133 }
2134
2135 static int hdsp_da_gain(hdsp_t *hdsp)
2136 {
2137         switch (hdsp->control_register & HDSP_DAGainMask) {
2138         case HDSP_DAGainHighGain:
2139                 return 0;
2140         case HDSP_DAGainPlus4dBu:
2141                 return 1;
2142         case HDSP_DAGainMinus10dBV:
2143                 return 2;
2144         default:
2145                 return 1;       
2146         }
2147 }
2148
2149 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2150 {
2151         hdsp->control_register &= ~HDSP_DAGainMask;
2152         switch (mode) {
2153         case 0:
2154                 hdsp->control_register |= HDSP_DAGainHighGain;
2155                 break;
2156         case 1:
2157                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2158                 break;
2159         case 2:
2160                 hdsp->control_register |= HDSP_DAGainMinus10dBV;                
2161                 break;      
2162         default:
2163                 return -1;
2164
2165         }
2166         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2167         return 0;
2168 }
2169
2170 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2171 {
2172         static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2173         
2174         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2175         uinfo->count = 1;
2176         uinfo->value.enumerated.items = 3;
2177         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2178                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2179         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2180         return 0;
2181 }
2182
2183 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2184 {
2185         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2186         
2187         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2188         return 0;
2189 }
2190
2191 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2192 {
2193         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2194         int change;
2195         int val;
2196         
2197         if (!snd_hdsp_use_is_exclusive(hdsp))
2198                 return -EBUSY;
2199         val = ucontrol->value.enumerated.item[0];
2200         if (val < 0) val = 0;
2201         if (val > 2) val = 2;
2202         spin_lock_irq(&hdsp->lock);
2203         if (val != hdsp_da_gain(hdsp)) {
2204                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2205         } else {
2206                 change = 0;
2207         }
2208         spin_unlock_irq(&hdsp->lock);
2209         return change;
2210 }
2211
2212 #define HDSP_AD_GAIN(xname, xindex) \
2213 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2214   .name = xname, \
2215   .index = xindex, \
2216   .info = snd_hdsp_info_ad_gain, \
2217   .get = snd_hdsp_get_ad_gain, \
2218   .put = snd_hdsp_put_ad_gain \
2219 }
2220
2221 static int hdsp_ad_gain(hdsp_t *hdsp)
2222 {
2223         switch (hdsp->control_register & HDSP_ADGainMask) {
2224         case HDSP_ADGainMinus10dBV:
2225                 return 0;
2226         case HDSP_ADGainPlus4dBu:
2227                 return 1;
2228         case HDSP_ADGainLowGain:
2229                 return 2;
2230         default:
2231                 return 1;       
2232         }
2233 }
2234
2235 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2236 {
2237         hdsp->control_register &= ~HDSP_ADGainMask;
2238         switch (mode) {
2239         case 0:
2240                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2241                 break;
2242         case 1:
2243                 hdsp->control_register |= HDSP_ADGainPlus4dBu;          
2244                 break;
2245         case 2:
2246                 hdsp->control_register |= HDSP_ADGainLowGain;           
2247                 break;      
2248         default:
2249                 return -1;
2250
2251         }
2252         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2253         return 0;
2254 }
2255
2256 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2257 {
2258         static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2259         
2260         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2261         uinfo->count = 1;
2262         uinfo->value.enumerated.items = 3;
2263         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2264                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2265         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2266         return 0;
2267 }
2268
2269 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2270 {
2271         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2272         
2273         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2274         return 0;
2275 }
2276
2277 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2278 {
2279         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2280         int change;
2281         int val;
2282         
2283         if (!snd_hdsp_use_is_exclusive(hdsp))
2284                 return -EBUSY;
2285         val = ucontrol->value.enumerated.item[0];
2286         if (val < 0) val = 0;
2287         if (val > 2) val = 2;
2288         spin_lock_irq(&hdsp->lock);
2289         if (val != hdsp_ad_gain(hdsp)) {
2290                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2291         } else {
2292                 change = 0;
2293         }
2294         spin_unlock_irq(&hdsp->lock);
2295         return change;
2296 }
2297
2298 #define HDSP_PHONE_GAIN(xname, xindex) \
2299 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2300   .name = xname, \
2301   .index = xindex, \
2302   .info = snd_hdsp_info_phone_gain, \
2303   .get = snd_hdsp_get_phone_gain, \
2304   .put = snd_hdsp_put_phone_gain \
2305 }
2306
2307 static int hdsp_phone_gain(hdsp_t *hdsp)
2308 {
2309         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2310         case HDSP_PhoneGain0dB:
2311                 return 0;
2312         case HDSP_PhoneGainMinus6dB:
2313                 return 1;
2314         case HDSP_PhoneGainMinus12dB:
2315                 return 2;
2316         default:
2317                 return 0;       
2318         }
2319 }
2320
2321 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2322 {
2323         hdsp->control_register &= ~HDSP_PhoneGainMask;
2324         switch (mode) {
2325         case 0:
2326                 hdsp->control_register |= HDSP_PhoneGain0dB;
2327                 break;
2328         case 1:
2329                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;               
2330                 break;
2331         case 2:
2332                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;              
2333                 break;      
2334         default:
2335                 return -1;
2336
2337         }
2338         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2339         return 0;
2340 }
2341
2342 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2343 {
2344         static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2345         
2346         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2347         uinfo->count = 1;
2348         uinfo->value.enumerated.items = 3;
2349         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2350                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2351         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2352         return 0;
2353 }
2354
2355 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2356 {
2357         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2358         
2359         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2360         return 0;
2361 }
2362
2363 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2364 {
2365         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2366         int change;
2367         int val;
2368         
2369         if (!snd_hdsp_use_is_exclusive(hdsp))
2370                 return -EBUSY;
2371         val = ucontrol->value.enumerated.item[0];
2372         if (val < 0) val = 0;
2373         if (val > 2) val = 2;
2374         spin_lock_irq(&hdsp->lock);
2375         if (val != hdsp_phone_gain(hdsp)) {
2376                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2377         } else {
2378                 change = 0;
2379         }
2380         spin_unlock_irq(&hdsp->lock);
2381         return change;
2382 }
2383
2384 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2385 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2386   .name = xname, \
2387   .index = xindex, \
2388   .info = snd_hdsp_info_xlr_breakout_cable, \
2389   .get = snd_hdsp_get_xlr_breakout_cable, \
2390   .put = snd_hdsp_put_xlr_breakout_cable \
2391 }
2392
2393 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2394 {
2395         if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2396                 return 1;
2397         }
2398         return 0;
2399 }
2400
2401 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2402 {
2403         if (mode) {
2404                 hdsp->control_register |= HDSP_XLRBreakoutCable;
2405         } else {
2406                 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2407         }
2408         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2409         return 0;
2410 }
2411
2412 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2413 {
2414         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2415         uinfo->count = 1;
2416         uinfo->value.integer.min = 0;
2417         uinfo->value.integer.max = 1;
2418         return 0;
2419 }
2420
2421 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2422 {
2423         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2424         
2425         ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2426         return 0;
2427 }
2428
2429 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2430 {
2431         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2432         int change;
2433         int val;
2434         
2435         if (!snd_hdsp_use_is_exclusive(hdsp))
2436                 return -EBUSY;
2437         val = ucontrol->value.integer.value[0] & 1;
2438         spin_lock_irq(&hdsp->lock);
2439         change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2440         hdsp_set_xlr_breakout_cable(hdsp, val);
2441         spin_unlock_irq(&hdsp->lock);
2442         return change;
2443 }
2444
2445 /* (De)activates old RME Analog Extension Board
2446    These are connected to the internal ADAT connector
2447    Switching this on desactivates external ADAT
2448 */
2449 #define HDSP_AEB(xname, xindex) \
2450 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2451   .name = xname, \
2452   .index = xindex, \
2453   .info = snd_hdsp_info_aeb, \
2454   .get = snd_hdsp_get_aeb, \
2455   .put = snd_hdsp_put_aeb \
2456 }
2457
2458 static int hdsp_aeb(hdsp_t *hdsp)
2459 {
2460         if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2461                 return 1;
2462         }
2463         return 0;
2464 }
2465
2466 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2467 {
2468         if (mode) {
2469                 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2470         } else {
2471                 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2472         }
2473         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2474         return 0;
2475 }
2476
2477 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2478 {
2479         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2480         uinfo->count = 1;
2481         uinfo->value.integer.min = 0;
2482         uinfo->value.integer.max = 1;
2483         return 0;
2484 }
2485
2486 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2487 {
2488         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2489         
2490         ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2491         return 0;
2492 }
2493
2494 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2495 {
2496         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2497         int change;
2498         int val;
2499         
2500         if (!snd_hdsp_use_is_exclusive(hdsp))
2501                 return -EBUSY;
2502         val = ucontrol->value.integer.value[0] & 1;
2503         spin_lock_irq(&hdsp->lock);
2504         change = (int)val != hdsp_aeb(hdsp);
2505         hdsp_set_aeb(hdsp, val);
2506         spin_unlock_irq(&hdsp->lock);
2507         return change;
2508 }
2509
2510 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2511 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2512   .name = xname, \
2513   .index = xindex, \
2514   .info = snd_hdsp_info_pref_sync_ref, \
2515   .get = snd_hdsp_get_pref_sync_ref, \
2516   .put = snd_hdsp_put_pref_sync_ref \
2517 }
2518
2519 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2520 {
2521         /* Notice that this looks at the requested sync source,
2522            not the one actually in use.
2523         */
2524
2525         switch (hdsp->control_register & HDSP_SyncRefMask) {
2526         case HDSP_SyncRef_ADAT1:
2527                 return HDSP_SYNC_FROM_ADAT1;
2528         case HDSP_SyncRef_ADAT2:
2529                 return HDSP_SYNC_FROM_ADAT2;
2530         case HDSP_SyncRef_ADAT3:
2531                 return HDSP_SYNC_FROM_ADAT3;
2532         case HDSP_SyncRef_SPDIF:
2533                 return HDSP_SYNC_FROM_SPDIF;
2534         case HDSP_SyncRef_WORD:
2535                 return HDSP_SYNC_FROM_WORD;
2536         case HDSP_SyncRef_ADAT_SYNC:
2537                 return HDSP_SYNC_FROM_ADAT_SYNC;
2538         default:
2539                 return HDSP_SYNC_FROM_WORD;
2540         }
2541         return 0;
2542 }
2543
2544 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2545 {
2546         hdsp->control_register &= ~HDSP_SyncRefMask;
2547         switch (pref) {
2548         case HDSP_SYNC_FROM_ADAT1:
2549                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2550                 break;
2551         case HDSP_SYNC_FROM_ADAT2:
2552                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2553                 break;
2554         case HDSP_SYNC_FROM_ADAT3:
2555                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2556                 break;
2557         case HDSP_SYNC_FROM_SPDIF:
2558                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2559                 break;
2560         case HDSP_SYNC_FROM_WORD:
2561                 hdsp->control_register |= HDSP_SyncRef_WORD;
2562                 break;
2563         case HDSP_SYNC_FROM_ADAT_SYNC:
2564                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2565                 break;
2566         default:
2567                 return -1;
2568         }
2569         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2570         return 0;
2571 }
2572
2573 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2574 {
2575         static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2576         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2577         
2578         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2579         uinfo->count = 1;
2580
2581         switch (hdsp->io_type) {
2582         case Digiface:
2583         case H9652:
2584                 uinfo->value.enumerated.items = 6;
2585                 break;
2586         case Multiface:
2587                 uinfo->value.enumerated.items = 4;
2588                 break;
2589         case H9632:
2590                 uinfo->value.enumerated.items = 3;
2591                 break;
2592         default:
2593                 uinfo->value.enumerated.items = 0;
2594                 break;
2595         }
2596                 
2597         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2598                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2599         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2600         return 0;
2601 }
2602
2603 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2604 {
2605         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2606         
2607         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2608         return 0;
2609 }
2610
2611 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2612 {
2613         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2614         int change, max;
2615         unsigned int val;
2616         
2617         if (!snd_hdsp_use_is_exclusive(hdsp))
2618                 return -EBUSY;
2619
2620         switch (hdsp->io_type) {
2621         case Digiface:
2622         case H9652:
2623                 max = 6;
2624                 break;
2625         case Multiface:
2626                 max = 4;
2627                 break;
2628         case H9632:
2629                 max = 3;
2630                 break;
2631         default:
2632                 return -EIO;
2633         }
2634
2635         val = ucontrol->value.enumerated.item[0] % max;
2636         spin_lock_irq(&hdsp->lock);
2637         change = (int)val != hdsp_pref_sync_ref(hdsp);
2638         hdsp_set_pref_sync_ref(hdsp, val);
2639         spin_unlock_irq(&hdsp->lock);
2640         return change;
2641 }
2642
2643 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2644 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2645   .name = xname, \
2646   .index = xindex, \
2647   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2648   .info = snd_hdsp_info_autosync_ref, \
2649   .get = snd_hdsp_get_autosync_ref, \
2650 }
2651
2652 static int hdsp_autosync_ref(hdsp_t *hdsp)
2653 {
2654         /* This looks at the autosync selected sync reference */
2655         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2656
2657         switch (status2 & HDSP_SelSyncRefMask) {
2658         case HDSP_SelSyncRef_WORD:
2659                 return HDSP_AUTOSYNC_FROM_WORD;
2660         case HDSP_SelSyncRef_ADAT_SYNC:
2661                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2662         case HDSP_SelSyncRef_SPDIF:
2663                 return HDSP_AUTOSYNC_FROM_SPDIF;
2664         case HDSP_SelSyncRefMask:
2665                 return HDSP_AUTOSYNC_FROM_NONE; 
2666         case HDSP_SelSyncRef_ADAT1:
2667                 return HDSP_AUTOSYNC_FROM_ADAT1;
2668         case HDSP_SelSyncRef_ADAT2:
2669                 return HDSP_AUTOSYNC_FROM_ADAT2;
2670         case HDSP_SelSyncRef_ADAT3:
2671                 return HDSP_AUTOSYNC_FROM_ADAT3;
2672         default:
2673                 return HDSP_AUTOSYNC_FROM_WORD;
2674         }
2675         return 0;
2676 }
2677
2678 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2679 {
2680         static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2681         
2682         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2683         uinfo->count = 1;
2684         uinfo->value.enumerated.items = 7;
2685         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2686                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2687         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2688         return 0;
2689 }
2690
2691 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2692 {
2693         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2694         
2695         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2696         return 0;
2697 }
2698
2699 #define HDSP_LINE_OUT(xname, xindex) \
2700 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2701   .name = xname, \
2702   .index = xindex, \
2703   .info = snd_hdsp_info_line_out, \
2704   .get = snd_hdsp_get_line_out, \
2705   .put = snd_hdsp_put_line_out \
2706 }
2707
2708 static int hdsp_line_out(hdsp_t *hdsp)
2709 {
2710         return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2711 }
2712
2713 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2714 {
2715         if (out) {
2716                 hdsp->control_register |= HDSP_LineOut;
2717         } else {
2718                 hdsp->control_register &= ~HDSP_LineOut;
2719         }
2720         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2721         return 0;
2722 }
2723
2724 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2725 {
2726         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2727         uinfo->count = 1;
2728         uinfo->value.integer.min = 0;
2729         uinfo->value.integer.max = 1;
2730         return 0;
2731 }
2732
2733 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2734 {
2735         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2736         
2737         spin_lock_irq(&hdsp->lock);
2738         ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2739         spin_unlock_irq(&hdsp->lock);
2740         return 0;
2741 }
2742
2743 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2744 {
2745         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2746         int change;
2747         unsigned int val;
2748         
2749         if (!snd_hdsp_use_is_exclusive(hdsp))
2750                 return -EBUSY;
2751         val = ucontrol->value.integer.value[0] & 1;
2752         spin_lock_irq(&hdsp->lock);
2753         change = (int)val != hdsp_line_out(hdsp);
2754         hdsp_set_line_output(hdsp, val);
2755         spin_unlock_irq(&hdsp->lock);
2756         return change;
2757 }
2758
2759 #define HDSP_PRECISE_POINTER(xname, xindex) \
2760 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2761   .name = xname, \
2762   .index = xindex, \
2763   .info = snd_hdsp_info_precise_pointer, \
2764   .get = snd_hdsp_get_precise_pointer, \
2765   .put = snd_hdsp_put_precise_pointer \
2766 }
2767
2768 static int hdsp_set_precise_pointer(hdsp_t *hdsp, int precise)
2769 {
2770         if (precise) {
2771                 hdsp->precise_ptr = 1;
2772         } else {
2773                 hdsp->precise_ptr = 0;
2774         }
2775         return 0;
2776 }
2777
2778 static int snd_hdsp_info_precise_pointer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2779 {
2780         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2781         uinfo->count = 1;
2782         uinfo->value.integer.min = 0;
2783         uinfo->value.integer.max = 1;
2784         return 0;
2785 }
2786
2787 static int snd_hdsp_get_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2788 {
2789         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2790         
2791         spin_lock_irq(&hdsp->lock);
2792         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2793         spin_unlock_irq(&hdsp->lock);
2794         return 0;
2795 }
2796
2797 static int snd_hdsp_put_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2798 {
2799         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2800         int change;
2801         unsigned int val;
2802         
2803         if (!snd_hdsp_use_is_exclusive(hdsp))
2804                 return -EBUSY;
2805         val = ucontrol->value.integer.value[0] & 1;
2806         spin_lock_irq(&hdsp->lock);
2807         change = (int)val != hdsp->precise_ptr;
2808         hdsp_set_precise_pointer(hdsp, val);
2809         spin_unlock_irq(&hdsp->lock);
2810         return change;
2811 }
2812
2813 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2814 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2815   .name = xname, \
2816   .index = xindex, \
2817   .info = snd_hdsp_info_use_midi_tasklet, \
2818   .get = snd_hdsp_get_use_midi_tasklet, \
2819   .put = snd_hdsp_put_use_midi_tasklet \
2820 }
2821
2822 static int hdsp_set_use_midi_tasklet(hdsp_t *hdsp, int use_tasklet)
2823 {
2824         if (use_tasklet) {
2825                 hdsp->use_midi_tasklet = 1;
2826         } else {
2827                 hdsp->use_midi_tasklet = 0;
2828         }
2829         return 0;
2830 }
2831
2832 static int snd_hdsp_info_use_midi_tasklet(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2833 {
2834         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2835         uinfo->count = 1;
2836         uinfo->value.integer.min = 0;
2837         uinfo->value.integer.max = 1;
2838         return 0;
2839 }
2840
2841 static int snd_hdsp_get_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2842 {
2843         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2844         
2845         spin_lock_irq(&hdsp->lock);
2846         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2847         spin_unlock_irq(&hdsp->lock);
2848         return 0;
2849 }
2850
2851 static int snd_hdsp_put_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2852 {
2853         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2854         int change;
2855         unsigned int val;
2856         
2857         if (!snd_hdsp_use_is_exclusive(hdsp))
2858                 return -EBUSY;
2859         val = ucontrol->value.integer.value[0] & 1;
2860         spin_lock_irq(&hdsp->lock);
2861         change = (int)val != hdsp->use_midi_tasklet;
2862         hdsp_set_use_midi_tasklet(hdsp, val);
2863         spin_unlock_irq(&hdsp->lock);
2864         return change;
2865 }
2866
2867 #define HDSP_MIXER(xname, xindex) \
2868 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2869   .name = xname, \
2870   .index = xindex, \
2871   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2872                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2873   .info = snd_hdsp_info_mixer, \
2874   .get = snd_hdsp_get_mixer, \
2875   .put = snd_hdsp_put_mixer \
2876 }
2877
2878 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2879 {
2880         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2881         uinfo->count = 3;
2882         uinfo->value.integer.min = 0;
2883         uinfo->value.integer.max = 65536;
2884         uinfo->value.integer.step = 1;
2885         return 0;
2886 }
2887
2888 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2889 {
2890         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2891         int source;
2892         int destination;
2893         int addr;
2894
2895         source = ucontrol->value.integer.value[0];
2896         destination = ucontrol->value.integer.value[1];
2897         
2898         if (source >= hdsp->max_channels) {
2899                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2900         } else {
2901                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2902         }
2903         
2904         spin_lock_irq(&hdsp->lock);
2905         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2906         spin_unlock_irq(&hdsp->lock);
2907         return 0;
2908 }
2909
2910 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2911 {
2912         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2913         int change;
2914         int source;
2915         int destination;
2916         int gain;
2917         int addr;
2918
2919         if (!snd_hdsp_use_is_exclusive(hdsp))
2920                 return -EBUSY;
2921
2922         source = ucontrol->value.integer.value[0];
2923         destination = ucontrol->value.integer.value[1];
2924
2925         if (source >= hdsp->max_channels) {
2926                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2927         } else {
2928                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2929         }
2930
2931         gain = ucontrol->value.integer.value[2];
2932
2933         spin_lock_irq(&hdsp->lock);
2934         change = gain != hdsp_read_gain(hdsp, addr);
2935         if (change)
2936                 hdsp_write_gain(hdsp, addr, gain);
2937         spin_unlock_irq(&hdsp->lock);
2938         return change;
2939 }
2940
2941 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2942 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2943   .name = xname, \
2944   .index = xindex, \
2945   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2946   .info = snd_hdsp_info_sync_check, \
2947   .get = snd_hdsp_get_wc_sync_check \
2948 }
2949
2950 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2951 {
2952         static char *texts[] = {"No Lock", "Lock", "Sync" };    
2953         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2954         uinfo->count = 1;
2955         uinfo->value.enumerated.items = 3;
2956         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2957                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2958         strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2959         return 0;
2960 }
2961
2962 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2963 {
2964         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2965         if (status2 & HDSP_wc_lock) {
2966                 if (status2 & HDSP_wc_sync) {
2967                         return 2;
2968                 } else {
2969                          return 1;
2970                 }
2971         } else {                
2972                 return 0;
2973         }
2974         return 0;
2975 }
2976
2977 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2978 {
2979         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2980
2981         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2982         return 0;
2983 }
2984
2985 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2986 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2987   .name = xname, \
2988   .index = xindex, \
2989   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2990   .info = snd_hdsp_info_sync_check, \
2991   .get = snd_hdsp_get_spdif_sync_check \
2992 }
2993
2994 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2995 {
2996         int status = hdsp_read(hdsp, HDSP_statusRegister);
2997         if (status & HDSP_SPDIFErrorFlag) {
2998                 return 0;
2999         } else {        
3000                 if (status & HDSP_SPDIFSync) {
3001                         return 2;
3002                 } else {
3003                         return 1;
3004                 }
3005         }
3006         return 0;
3007 }
3008
3009 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3010 {
3011         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3012
3013         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3014         return 0;
3015 }
3016
3017 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3018 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3019   .name = xname, \
3020   .index = xindex, \
3021   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3022   .info = snd_hdsp_info_sync_check, \
3023   .get = snd_hdsp_get_adatsync_sync_check \
3024 }
3025
3026 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3027 {
3028         int status = hdsp_read(hdsp, HDSP_statusRegister);
3029         if (status & HDSP_TimecodeLock) {
3030                 if (status & HDSP_TimecodeSync) {
3031                         return 2;
3032                 } else {
3033                         return 1;
3034                 }
3035         } else {
3036                 return 0;
3037         }
3038 }       
3039
3040 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3041 {
3042         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3043
3044         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3045         return 0;
3046 }
3047
3048 #define HDSP_ADAT_SYNC_CHECK \
3049 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3050   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3051   .info = snd_hdsp_info_sync_check, \
3052   .get = snd_hdsp_get_adat_sync_check \
3053 }
3054
3055 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3056 {       
3057         int status = hdsp_read(hdsp, HDSP_statusRegister);
3058         
3059         if (status & (HDSP_Lock0>>idx)) {
3060                 if (status & (HDSP_Sync0>>idx)) {
3061                         return 2;
3062                 } else {
3063                         return 1;               
3064                 }
3065         } else {
3066                 return 0;
3067         }               
3068
3069
3070 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3071 {
3072         int offset;
3073         hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3074
3075         offset = ucontrol->id.index - 1;
3076         snd_assert(offset >= 0);
3077
3078         switch (hdsp->io_type) {
3079         case Digiface:
3080         case H9652:
3081                 if (offset >= 3)
3082                         return -EINVAL;
3083                 break;
3084         case Multiface:
3085         case H9632:
3086                 if (offset >= 1) 
3087                         return -EINVAL;
3088                 break;
3089         default:
3090                 return -EIO;
3091         }
3092
3093         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3094         return 0;
3095 }
3096
3097 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3098 HDSP_DA_GAIN("DA Gain", 0),
3099 HDSP_AD_GAIN("AD Gain", 0),
3100 HDSP_PHONE_GAIN("Phones Gain", 0),
3101 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3102 };
3103
3104 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3105 {
3106         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3107         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3108         .info =         snd_hdsp_control_spdif_info,
3109         .get =          snd_hdsp_control_spdif_get,
3110         .put =          snd_hdsp_control_spdif_put,
3111 },
3112 {
3113         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3114         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
3115         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3116         .info =         snd_hdsp_control_spdif_stream_info,
3117         .get =          snd_hdsp_control_spdif_stream_get,
3118         .put =          snd_hdsp_control_spdif_stream_put,
3119 },
3120 {
3121         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3122         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3123         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3124         .info =         snd_hdsp_control_spdif_mask_info,
3125         .get =          snd_hdsp_control_spdif_mask_get,
3126         .private_value = IEC958_AES0_NONAUDIO |
3127                          IEC958_AES0_PROFESSIONAL |
3128                          IEC958_AES0_CON_EMPHASIS,                                                                                            
3129 },
3130 {
3131         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
3132         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
3133         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3134         .info =         snd_hdsp_control_spdif_mask_info,
3135         .get =          snd_hdsp_control_spdif_mask_get,
3136         .private_value = IEC958_AES0_NONAUDIO |
3137                          IEC958_AES0_PROFESSIONAL |
3138                          IEC958_AES0_PRO_EMPHASIS,
3139 },
3140 HDSP_MIXER("Mixer", 0),
3141 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3142 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3143 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3144 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3145 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3146 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 
3147 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3148 {
3149         /* FIXME: should be PCM or MIXER? */
3150         /* .iface = SNDRV_CTL_ELEM_IFACE_PCM, */
3151         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3152         .name = "Sample Clock Source Locking",
3153         .info = snd_hdsp_info_clock_source_lock,
3154         .get = snd_hdsp_get_clock_source_lock,
3155         .put = snd_hdsp_put_clock_source_lock,
3156 },
3157 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3158 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3159 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3160 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3161 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3162 /* 'External Rate' complies with the alsa control naming scheme */
3163 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3164 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3165 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3166 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3167 HDSP_LINE_OUT("Line Out", 0),
3168 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3169 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3170 };
3171
3172 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3173 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3174
3175 static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3176 {
3177         unsigned int idx;
3178         int err;
3179         snd_kcontrol_t *kctl;
3180
3181         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3182                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3183                         return err;
3184                 }
3185                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3186                         hdsp->spdif_ctl = kctl;
3187         }
3188
3189         /* ADAT SyncCheck status */
3190         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3191         snd_hdsp_adat_sync_check.index = 1;
3192         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3193                 return err;
3194         }       
3195         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3196                 for (idx = 1; idx < 3; ++idx) {
3197                         snd_hdsp_adat_sync_check.index = idx+1;
3198                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3199                                 return err;
3200                         }
3201                 }
3202         }
3203         
3204         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3205         if (hdsp->io_type == H9632) {
3206                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3207                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3208                                 return err;
3209                         }
3210                 }
3211         }
3212
3213         /* AEB control for H96xx card */
3214         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3215                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3216                                 return err;
3217                 }       
3218         }
3219
3220         return 0;
3221 }
3222
3223 /*------------------------------------------------------------
3224    /proc interface 
3225  ------------------------------------------------------------*/
3226
3227 static void
3228 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3229 {
3230         hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3231         unsigned int status;
3232         unsigned int status2;
3233         char *pref_sync_ref;
3234         char *autosync_ref;
3235         char *system_clock_mode;
3236         char *clock_source;
3237         int x;
3238
3239         if (hdsp_check_for_iobox (hdsp)) {
3240                 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3241                 return;
3242         }
3243
3244         if (hdsp_check_for_firmware(hdsp)) {
3245                 if (hdsp->state & HDSP_FirmwareCached) {
3246                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3247                                 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3248                                 return;
3249                         }
3250                 } else {
3251                         snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3252                         return;
3253                 }
3254         }
3255         
3256         status = hdsp_read(hdsp, HDSP_statusRegister);
3257         status2 = hdsp_read(hdsp, HDSP_status2Register);
3258
3259         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3260         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3261                     hdsp->capture_buffer, hdsp->playback_buffer);
3262         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3263                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3264         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3265         snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3266         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3267         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3268         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3269         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3270         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3271         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3272         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3273         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3274
3275         snd_iprintf(buffer, "\n");
3276
3277         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3278
3279         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3280         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3281         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3282         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3283
3284         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3285
3286         snd_iprintf(buffer, "\n");
3287
3288
3289         switch (hdsp_clock_source(hdsp)) {
3290         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3291                 clock_source = "AutoSync";
3292                 break;
3293         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3294                 clock_source = "Internal 32 kHz";
3295                 break;
3296         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3297                 clock_source = "Internal 44.1 kHz";
3298                 break;
3299         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3300                 clock_source = "Internal 48 kHz";
3301                 break;
3302         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3303                 clock_source = "Internal 64 kHz";
3304                 break;
3305         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3306                 clock_source = "Internal 88.2 kHz";
3307                 break;
3308         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3309                 clock_source = "Internal 96 kHz";
3310                 break;
3311         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3312                 clock_source = "Internal 128 kHz";
3313                 break;
3314         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3315                 clock_source = "Internal 176.4 kHz";
3316                 break;
3317                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3318                 clock_source = "Internal 192 kHz";
3319                 break;  
3320         default:
3321                 clock_source = "Error";         
3322         }
3323         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3324                         
3325         if (hdsp_system_clock_mode(hdsp)) {
3326                 system_clock_mode = "Slave";
3327         } else {
3328                 system_clock_mode = "Master";
3329         }
3330         
3331         switch (hdsp_pref_sync_ref (hdsp)) {
3332         case HDSP_SYNC_FROM_WORD:
3333                 pref_sync_ref = "Word Clock";
3334                 break;
3335         case HDSP_SYNC_FROM_ADAT_SYNC:
3336                 pref_sync_ref = "ADAT Sync";
3337                 break;
3338         case HDSP_SYNC_FROM_SPDIF:
3339                 pref_sync_ref = "SPDIF";
3340                 break;
3341         case HDSP_SYNC_FROM_ADAT1:
3342                 pref_sync_ref = "ADAT1";
3343                 break;
3344         case HDSP_SYNC_FROM_ADAT2:
3345                 pref_sync_ref = "ADAT2";
3346                 break;
3347         case HDSP_SYNC_FROM_ADAT3:
3348                 pref_sync_ref = "ADAT3";
3349                 break;
3350         default:
3351                 pref_sync_ref = "Word Clock";
3352                 break;
3353         }
3354         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3355         
3356         switch (hdsp_autosync_ref (hdsp)) {
3357         case HDSP_AUTOSYNC_FROM_WORD:
3358                 autosync_ref = "Word Clock";
3359                 break;
3360         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3361                 autosync_ref = "ADAT Sync";
3362                 break;
3363         case HDSP_AUTOSYNC_FROM_SPDIF:
3364                 autosync_ref = "SPDIF";
3365                 break;
3366         case HDSP_AUTOSYNC_FROM_NONE:
3367                 autosync_ref = "None";
3368                 break;  
3369         case HDSP_AUTOSYNC_FROM_ADAT1:
3370                 autosync_ref = "ADAT1";
3371                 break;
3372         case HDSP_AUTOSYNC_FROM_ADAT2:
3373                 autosync_ref = "ADAT2";
3374                 break;
3375         case HDSP_AUTOSYNC_FROM_ADAT3:
3376                 autosync_ref = "ADAT3";
3377                 break;
3378         default:
3379                 autosync_ref = "---";
3380                 break;
3381         }
3382         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3383         
3384         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3385         
3386         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3387
3388         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3389         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3390                 
3391         snd_iprintf(buffer, "\n");
3392
3393         switch (hdsp_spdif_in(hdsp)) {
3394         case HDSP_SPDIFIN_OPTICAL:
3395                 snd_iprintf(buffer, "IEC958 input: Optical\n");
3396                 break;
3397         case HDSP_SPDIFIN_COAXIAL:
3398                 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3399                 break;
3400         case HDSP_SPDIFIN_INTERNAL:
3401                 snd_iprintf(buffer, "IEC958 input: Internal\n");
3402                 break;
3403         case HDSP_SPDIFIN_AES:
3404                 snd_iprintf(buffer, "IEC958 input: AES\n");
3405                 break;
3406         default:
3407                 snd_iprintf(buffer, "IEC958 input: ???\n");
3408                 break;
3409         }
3410         
3411         if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3412                 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3413         } else {
3414                 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3415         }
3416
3417         if (hdsp->control_register & HDSP_SPDIFProfessional) {
3418                 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3419         } else {
3420                 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3421         }
3422
3423         if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3424                 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3425         } else {
3426                 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3427         }
3428
3429         if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3430                 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3431         } else {
3432                 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3433         }
3434         if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3435                 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3436         } else {
3437                 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3438         }
3439
3440         snd_iprintf(buffer, "\n");
3441
3442         /* Sync Check */
3443         x = status & HDSP_Sync0;
3444         if (status & HDSP_Lock0) {
3445                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3446         } else {
3447                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3448         }
3449
3450         switch (hdsp->io_type) {
3451         case Digiface:
3452         case H9652:
3453                 x = status & HDSP_Sync1;
3454                 if (status & HDSP_Lock1) {
3455                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3456                 } else {
3457                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3458                 }
3459                 x = status & HDSP_Sync2;
3460                 if (status & HDSP_Lock2) {
3461                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3462                 } else {
3463                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3464                 }
3465         default:
3466                 /* relax */
3467                 break;
3468         }
3469
3470         x = status & HDSP_SPDIFSync;
3471         if (status & HDSP_SPDIFErrorFlag) {
3472                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3473         } else {
3474                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3475         }
3476         
3477         x = status2 & HDSP_wc_sync;
3478         if (status2 & HDSP_wc_lock) {
3479                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3480         } else {
3481                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3482         }
3483         
3484         x = status & HDSP_TimecodeSync;
3485         if (status & HDSP_TimecodeLock) {
3486                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3487         } else {
3488                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3489         }
3490
3491         snd_iprintf(buffer, "\n");
3492         
3493         /* Informations about H9632 specific controls */
3494         if (hdsp->io_type == H9632) {
3495                 char *tmp;
3496         
3497                 switch (hdsp_ad_gain(hdsp)) {
3498                 case 0:
3499                         tmp = "-10 dBV";
3500                         break;
3501                 case 1:
3502                         tmp = "+4 dBu";
3503                         break;
3504                 default:
3505                         tmp = "Lo Gain";
3506                         break;
3507                 }
3508                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3509
3510                 switch (hdsp_da_gain(hdsp)) {
3511                 case 0:
3512                         tmp = "Hi Gain";
3513                         break;
3514                 case 1:
3515                         tmp = "+4 dBu";
3516                         break;
3517                 default:
3518                         tmp = "-10 dBV";
3519                         break;
3520                 }
3521                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3522                 
3523                 switch (hdsp_phone_gain(hdsp)) {
3524                 case 0:
3525                         tmp = "0 dB";
3526                         break;
3527                 case 1:
3528                         tmp = "-6 dB";
3529                         break;
3530                 default:
3531                         tmp = "-12 dB";
3532                         break;
3533                 }
3534                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3535
3536                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); 
3537                 
3538                 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3539                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3540                 } else {
3541                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3542                 }
3543                 snd_iprintf(buffer, "\n");
3544         }
3545
3546 }
3547
3548 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3549 {
3550         snd_info_entry_t *entry;
3551
3552         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3553                 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3554 }
3555
3556 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3557 {
3558         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3559         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3560 }
3561
3562 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3563 {
3564         unsigned long pb_bus, cb_bus;
3565
3566         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3567             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3568                 if (hdsp->capture_dma_buf.area)
3569                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3570                 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3571                 return -ENOMEM;
3572         }
3573
3574         /* Align to bus-space 64K boundary */
3575
3576         cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3577         pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3578
3579         /* Tell the card where it is */
3580
3581         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3582         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3583
3584         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3585         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3586
3587         return 0;
3588 }
3589
3590 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3591 {
3592         unsigned int i;
3593
3594         /* ASSUMPTION: hdsp->lock is either held, or
3595            there is no need to hold it (e.g. during module
3596            initalization).
3597          */
3598
3599         /* set defaults:
3600
3601            SPDIF Input via Coax 
3602            Master clock mode
3603            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3604                             which implies 2 4096 sample, 32Kbyte periods).
3605            Enable line out.                         
3606          */
3607
3608         hdsp->control_register = HDSP_ClockModeMaster | 
3609                                  HDSP_SPDIFInputCoaxial | 
3610                                  hdsp_encode_latency(7) | 
3611                                  HDSP_LineOut;
3612         
3613
3614         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3615
3616 #ifdef SNDRV_BIG_ENDIAN
3617         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3618 #else
3619         hdsp->control2_register = 0;
3620 #endif
3621         if (hdsp->io_type == H9652) {
3622                 snd_hdsp_9652_enable_mixer (hdsp);
3623         } else {
3624             hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3625         } 
3626
3627         hdsp_reset_hw_pointer(hdsp);
3628         hdsp_compute_period_size(hdsp);
3629
3630         /* silence everything */
3631         
3632         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3633                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3634         }
3635
3636         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3637                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3638                         return -EIO;
3639                 }
3640         }
3641         
3642         /* H9632 specific defaults */
3643         if (hdsp->io_type == H9632) {
3644                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3645                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3646         }
3647
3648         /* set a default rate so that the channel map is set up.
3649          */
3650
3651         hdsp_set_rate(hdsp, 48000, 1);
3652
3653         return 0;
3654 }
3655
3656 static void hdsp_midi_tasklet(unsigned long arg)
3657 {
3658         hdsp_t *hdsp = (hdsp_t *)arg;
3659         
3660         if (hdsp->midi[0].pending) {
3661                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3662         }
3663         if (hdsp->midi[1].pending) {
3664                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3665         }
3666
3667
3668 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3669 {
3670         hdsp_t *hdsp = (hdsp_t *) dev_id;
3671         unsigned int status;
3672         int audio;
3673         int midi0;
3674         int midi1;
3675         unsigned int midi0status;
3676         unsigned int midi1status;
3677         int schedule = 0;
3678         
3679         status = hdsp_read(hdsp, HDSP_statusRegister);
3680
3681         audio = status & HDSP_audioIRQPending;
3682         midi0 = status & HDSP_midi0IRQPending;
3683         midi1 = status & HDSP_midi1IRQPending;
3684
3685         if (!audio && !midi0 && !midi1) {
3686                 return IRQ_NONE;
3687         }
3688
3689         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3690
3691         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3692         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3693         
3694         if (audio) {
3695                 if (hdsp->capture_substream) {
3696                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3697                 }
3698                 
3699                 if (hdsp->playback_substream) {
3700                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3701                 }
3702         }
3703         
3704         if (midi0 && midi0status) {
3705                 if (hdsp->use_midi_tasklet) {
3706                         /* we disable interrupts for this input until processing is done */
3707                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3708                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3709                         hdsp->midi[0].pending = 1;
3710                         schedule = 1;
3711                 } else {
3712                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3713                 }
3714         }
3715         if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3716                 if (hdsp->use_midi_tasklet) {
3717                         /* we disable interrupts for this input until processing is done */
3718                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3719                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3720                         hdsp->midi[1].pending = 1;
3721                         schedule = 1;
3722                 } else {
3723                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3724                 }
3725         }
3726         if (hdsp->use_midi_tasklet && schedule)
3727                 tasklet_hi_schedule(&hdsp->midi_tasklet);
3728         return IRQ_HANDLED;
3729 }
3730
3731 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3732 {
3733         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3734         return hdsp_hw_pointer(hdsp);
3735 }
3736
3737 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3738                                              int stream,
3739                                              int channel)
3740
3741 {
3742         int mapped_channel;
3743
3744         snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3745         
3746         if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3747                 return NULL;
3748         }
3749         
3750         if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3751                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3752         } else {
3753                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3754         }
3755 }
3756
3757 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3758                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3759 {
3760         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3761         char *channel_buf;
3762
3763         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3764
3765         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3766         snd_assert(channel_buf != NULL, return -EIO);
3767         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3768                 return -EFAULT;
3769         return count;
3770 }
3771
3772 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3773                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3774 {
3775         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3776         char *channel_buf;
3777
3778         snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3779
3780         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3781         snd_assert(channel_buf != NULL, return -EIO);
3782         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3783                 return -EFAULT;
3784         return count;
3785 }
3786
3787 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3788                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3789 {
3790         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3791         char *channel_buf;
3792
3793         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3794         snd_assert(channel_buf != NULL, return -EIO);
3795         memset(channel_buf + pos * 4, 0, count * 4);
3796         return count;
3797 }
3798
3799 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3800 {
3801         snd_pcm_runtime_t *runtime = substream->runtime;
3802         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3803         snd_pcm_substream_t *other;
3804         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3805                 other = hdsp->capture_substream;
3806         else
3807                 other = hdsp->playback_substream;
3808         if (hdsp->running)
3809                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3810         else
3811                 runtime->status->hw_ptr = 0;
3812         if (other) {
3813                 struct list_head *pos;
3814                 snd_pcm_substream_t *s;
3815                 snd_pcm_runtime_t *oruntime = other->runtime;
3816                 snd_pcm_group_for_each(pos, substream) {
3817                         s = snd_pcm_group_substream_entry(pos);
3818                         if (s == other) {
3819                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3820                                 break;
3821                         }
3822                 }
3823         }
3824         return 0;
3825 }
3826
3827 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3828                                  snd_pcm_hw_params_t *params)
3829 {
3830         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3831         int err;
3832         pid_t this_pid;
3833         pid_t other_pid;
3834
3835         if (hdsp_check_for_iobox (hdsp)) {
3836                 return -EIO;
3837         }
3838
3839         if (hdsp_check_for_firmware(hdsp)) {
3840                 if (hdsp->state & HDSP_FirmwareCached) {
3841                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3842                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3843                         }
3844                 } else {
3845                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3846                 }
3847                 return -EIO;
3848         }
3849
3850         spin_lock_irq(&hdsp->lock);
3851
3852         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3853                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3854                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3855                 this_pid = hdsp->playback_pid;
3856                 other_pid = hdsp->capture_pid;
3857         } else {
3858                 this_pid = hdsp->capture_pid;
3859                 other_pid = hdsp->playback_pid;
3860         }
3861
3862         if ((other_pid > 0) && (this_pid != other_pid)) {
3863
3864                 /* The other stream is open, and not by the same
3865                    task as this one. Make sure that the parameters
3866                    that matter are the same.
3867                  */
3868
3869                 if (params_rate(params) != hdsp->system_sample_rate) {
3870                         spin_unlock_irq(&hdsp->lock);
3871                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3872                         return -EBUSY;
3873                 }
3874
3875                 if (params_period_size(params) != hdsp->period_bytes / 4) {
3876                         spin_unlock_irq(&hdsp->lock);
3877                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3878                         return -EBUSY;
3879                 }
3880
3881                 /* We're fine. */
3882
3883                 spin_unlock_irq(&hdsp->lock);
3884                 return 0;
3885
3886         } else {
3887                 spin_unlock_irq(&hdsp->lock);
3888         }
3889
3890         /* how to make sure that the rate matches an externally-set one ?
3891          */
3892
3893         spin_lock_irq(&hdsp->lock);
3894         if (! hdsp->clock_source_locked) {
3895                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3896                         spin_unlock_irq(&hdsp->lock);
3897                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3898                         return err;
3899                 }
3900         }
3901         spin_unlock_irq(&hdsp->lock);
3902
3903         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3904                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3905                 return err;
3906         }
3907
3908         return 0;
3909 }
3910
3911 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3912                                     snd_pcm_channel_info_t *info)
3913 {
3914         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3915         int mapped_channel;
3916
3917         snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3918
3919         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3920                 return -EINVAL;
3921         }
3922
3923         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3924         info->first = 0;
3925         info->step = 32;
3926         return 0;
3927 }
3928
3929 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3930                              unsigned int cmd, void *arg)
3931 {
3932         switch (cmd) {
3933         case SNDRV_PCM_IOCTL1_RESET:
3934         {
3935                 return snd_hdsp_reset(substream);
3936         }
3937         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3938         {
3939                 snd_pcm_channel_info_t *info = arg;
3940                 return snd_hdsp_channel_info(substream, info);
3941         }
3942         default:
3943                 break;
3944         }
3945
3946         return snd_pcm_lib_ioctl(substream, cmd, arg);
3947 }
3948
3949 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3950 {
3951         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3952         snd_pcm_substream_t *other;
3953         int running;
3954         
3955         if (hdsp_check_for_iobox (hdsp)) {
3956                 return -EIO;
3957         }
3958
3959         if (hdsp_check_for_firmware(hdsp)) {
3960                 if (hdsp->state & HDSP_FirmwareCached) {
3961                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3962                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3963                         }
3964                 } else {
3965                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3966                 }
3967                 return -EIO;
3968         }
3969
3970         spin_lock(&hdsp->lock);
3971         running = hdsp->running;
3972         switch (cmd) {
3973         case SNDRV_PCM_TRIGGER_START:
3974                 running |= 1 << substream->stream;
3975                 break;
3976         case SNDRV_PCM_TRIGGER_STOP:
3977                 running &= ~(1 << substream->stream);
3978                 break;
3979         default:
3980                 snd_BUG();
3981                 spin_unlock(&hdsp->lock);
3982                 return -EINVAL;
3983         }
3984         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3985                 other = hdsp->capture_substream;
3986         else
3987                 other = hdsp->playback_substream;
3988
3989         if (other) {
3990                 struct list_head *pos;
3991                 snd_pcm_substream_t *s;
3992                 snd_pcm_group_for_each(pos, substream) {
3993                         s = snd_pcm_group_substream_entry(pos);
3994                         if (s == other) {
3995                                 snd_pcm_trigger_done(s, substream);
3996                                 if (cmd == SNDRV_PCM_TRIGGER_START)
3997                                         running |= 1 << s->stream;
3998                                 else
3999                                         running &= ~(1 << s->stream);
4000                                 goto _ok;
4001                         }
4002                 }
4003                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4004                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4005                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4006                                 hdsp_silence_playback(hdsp);
4007                 } else {
4008                         if (running &&
4009                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4010                                 hdsp_silence_playback(hdsp);
4011                 }
4012         } else {
4013                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4014                                 hdsp_silence_playback(hdsp);
4015         }
4016  _ok:
4017         snd_pcm_trigger_done(substream, substream);
4018         if (!hdsp->running && running)
4019                 hdsp_start_audio(hdsp);
4020         else if (hdsp->running && !running)
4021                 hdsp_stop_audio(hdsp);
4022         hdsp->running = running;
4023         spin_unlock(&hdsp->lock);
4024
4025         return 0;
4026 }
4027
4028 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4029 {
4030         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4031         int result = 0;
4032
4033         if (hdsp_check_for_iobox (hdsp)) {
4034                 return -EIO;
4035         }
4036
4037         if (hdsp_check_for_firmware(hdsp)) {
4038                 if (hdsp->state & HDSP_FirmwareCached) {
4039                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4040                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4041                         }
4042                 } else {
4043                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4044                 }
4045                 return -EIO;
4046         }
4047
4048         spin_lock_irq(&hdsp->lock);
4049         if (!hdsp->running)
4050                 hdsp_reset_hw_pointer(hdsp);
4051         spin_unlock_irq(&hdsp->lock);
4052         return result;
4053 }
4054
4055 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4056 {
4057         .info =                 (SNDRV_PCM_INFO_MMAP |
4058                                  SNDRV_PCM_INFO_MMAP_VALID |
4059                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4060                                  SNDRV_PCM_INFO_SYNC_START |
4061                                  SNDRV_PCM_INFO_DOUBLE),
4062 #ifdef SNDRV_BIG_ENDIAN
4063         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4064 #else
4065         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4066 #endif
4067         .rates =                (SNDRV_PCM_RATE_32000 |
4068                                  SNDRV_PCM_RATE_44100 | 
4069                                  SNDRV_PCM_RATE_48000 | 
4070                                  SNDRV_PCM_RATE_64000 | 
4071                                  SNDRV_PCM_RATE_88200 | 
4072                                  SNDRV_PCM_RATE_96000),
4073         .rate_min =             32000,
4074         .rate_max =             96000,
4075         .channels_min =         14,
4076         .channels_max =         HDSP_MAX_CHANNELS,
4077         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4078         .period_bytes_min =     (64 * 4) * 10,
4079         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4080         .periods_min =          2,
4081         .periods_max =          2,
4082         .fifo_size =            0
4083 };
4084
4085 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4086 {
4087         .info =                 (SNDRV_PCM_INFO_MMAP |
4088                                  SNDRV_PCM_INFO_MMAP_VALID |
4089                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4090                                  SNDRV_PCM_INFO_SYNC_START),
4091 #ifdef SNDRV_BIG_ENDIAN
4092         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4093 #else
4094         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4095 #endif
4096         .rates =                (SNDRV_PCM_RATE_32000 |
4097                                  SNDRV_PCM_RATE_44100 | 
4098                                  SNDRV_PCM_RATE_48000 | 
4099                                  SNDRV_PCM_RATE_64000 | 
4100                                  SNDRV_PCM_RATE_88200 | 
4101                                  SNDRV_PCM_RATE_96000),
4102         .rate_min =             32000,
4103         .rate_max =             96000,
4104         .channels_min =         14,
4105         .channels_max =         HDSP_MAX_CHANNELS,
4106         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4107         .period_bytes_min =     (64 * 4) * 10,
4108         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4109         .periods_min =          2,
4110         .periods_max =          2,
4111         .fifo_size =            0
4112 };
4113
4114 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4115
4116 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4117         .count = ARRAY_SIZE(hdsp_period_sizes),
4118         .list = hdsp_period_sizes,
4119         .mask = 0
4120 };
4121
4122 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4123
4124 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4125         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4126         .list = hdsp_9632_sample_rates,
4127         .mask = 0
4128 };
4129
4130 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4131                                         snd_pcm_hw_rule_t *rule)
4132 {
4133         hdsp_t *hdsp = rule->private;
4134         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4135         if (hdsp->io_type == H9632) {
4136                 unsigned int list[3];
4137                 list[0] = hdsp->qs_in_channels;
4138                 list[1] = hdsp->ds_in_channels;
4139                 list[2] = hdsp->ss_in_channels;
4140                 return snd_interval_list(c, 3, list, 0);
4141         } else {
4142                 unsigned int list[2];
4143                 list[0] = hdsp->ds_in_channels;
4144                 list[1] = hdsp->ss_in_channels;
4145                 return snd_interval_list(c, 2, list, 0);
4146         }
4147 }
4148
4149 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4150                                         snd_pcm_hw_rule_t *rule)
4151 {
4152         unsigned int list[3];
4153         hdsp_t *hdsp = rule->private;
4154         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4155         if (hdsp->io_type == H9632) {
4156                 list[0] = hdsp->qs_out_channels;
4157                 list[1] = hdsp->ds_out_channels;
4158                 list[2] = hdsp->ss_out_channels;
4159                 return snd_interval_list(c, 3, list, 0);
4160         } else {
4161                 list[0] = hdsp->ds_out_channels;
4162                 list[1] = hdsp->ss_out_channels;
4163         }
4164         return snd_interval_list(c, 2, list, 0);
4165 }
4166
4167 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4168                                              snd_pcm_hw_rule_t *rule)
4169 {
4170         hdsp_t *hdsp = rule->private;
4171         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4172         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4173         if (r->min > 96000 && hdsp->io_type == H9632) {
4174                 snd_interval_t t = {
4175                         .min = hdsp->qs_in_channels,
4176                         .max = hdsp->qs_in_channels,
4177                         .integer = 1,
4178                 };
4179                 return snd_interval_refine(c, &t);      
4180         } else if (r->min > 48000 && r->max <= 96000) {
4181                 snd_interval_t t = {
4182                         .min = hdsp->ds_in_channels,
4183                         .max = hdsp->ds_in_channels,
4184                         .integer = 1,
4185                 };
4186                 return snd_interval_refine(c, &t);
4187         } else if (r->max < 64000) {
4188                 snd_interval_t t = {
4189                         .min = hdsp->ss_in_channels,
4190                         .max = hdsp->ss_in_channels,
4191                         .integer = 1,
4192                 };
4193                 return snd_interval_refine(c, &t);
4194         }
4195         return 0;
4196 }
4197
4198 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4199                                              snd_pcm_hw_rule_t *rule)
4200 {
4201         hdsp_t *hdsp = rule->private;
4202         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4203         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4204         if (r->min > 96000 && hdsp->io_type == H9632) {
4205                 snd_interval_t t = {
4206                         .min = hdsp->qs_out_channels,
4207                         .max = hdsp->qs_out_channels,
4208                         .integer = 1,
4209                 };
4210                 return snd_interval_refine(c, &t);      
4211         } else if (r->min > 48000 && r->max <= 96000) {
4212                 snd_interval_t t = {
4213                         .min = hdsp->ds_out_channels,
4214                         .max = hdsp->ds_out_channels,
4215                         .integer = 1,
4216                 };
4217                 return snd_interval_refine(c, &t);
4218         } else if (r->max < 64000) {
4219                 snd_interval_t t = {
4220                         .min = hdsp->ss_out_channels,
4221                         .max = hdsp->ss_out_channels,
4222                         .integer = 1,
4223                 };
4224                 return snd_interval_refine(c, &t);
4225         }
4226         return 0;
4227 }
4228
4229 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4230                                              snd_pcm_hw_rule_t *rule)
4231 {
4232         hdsp_t *hdsp = rule->private;
4233         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4234         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4235         if (c->min >= hdsp->ss_out_channels) {
4236                 snd_interval_t t = {
4237                         .min = 32000,
4238                         .max = 48000,
4239                         .integer = 1,
4240                 };
4241                 return snd_interval_refine(r, &t);
4242         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4243                 snd_interval_t t = {
4244                         .min = 128000,
4245                         .max = 192000,
4246                         .integer = 1,
4247                 };
4248                 return snd_interval_refine(r, &t);
4249         } else if (c->max <= hdsp->ds_out_channels) {
4250                 snd_interval_t t = {
4251                         .min = 64000,
4252                         .max = 96000,
4253                         .integer = 1,
4254                 };
4255                 return snd_interval_refine(r, &t);
4256         }
4257         return 0;
4258 }
4259
4260 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4261                                              snd_pcm_hw_rule_t *rule)
4262 {
4263         hdsp_t *hdsp = rule->private;
4264         snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4265         snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4266         if (c->min >= hdsp->ss_in_channels) {
4267                 snd_interval_t t = {
4268                         .min = 32000,
4269                         .max = 48000,
4270                         .integer = 1,
4271                 };
4272                 return snd_interval_refine(r, &t);
4273         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4274                 snd_interval_t t = {
4275                         .min = 128000,
4276                         .max = 192000,
4277                         .integer = 1,
4278                 };
4279                 return snd_interval_refine(r, &t);
4280         } else if (c->max <= hdsp->ds_in_channels) {
4281                 snd_interval_t t = {
4282                         .min = 64000,
4283                         .max = 96000,
4284                         .integer = 1,
4285                 };
4286                 return snd_interval_refine(r, &t);
4287         }
4288         return 0;
4289 }
4290
4291 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4292 {
4293         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4294         snd_pcm_runtime_t *runtime = substream->runtime;
4295
4296         if (hdsp_check_for_iobox (hdsp)) {
4297                 return -EIO;
4298         }
4299
4300         if (hdsp_check_for_firmware(hdsp)) {
4301                 if (hdsp->state & HDSP_FirmwareCached) {
4302                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4303                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4304                         }
4305                 } else {
4306                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4307                 }
4308                 return -EIO;
4309         }
4310
4311         spin_lock_irq(&hdsp->lock);
4312
4313         snd_pcm_set_sync(substream);
4314
4315         runtime->hw = snd_hdsp_playback_subinfo;
4316         runtime->dma_area = hdsp->playback_buffer;
4317         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4318
4319         hdsp->playback_pid = current->pid;
4320         hdsp->playback_substream = substream;
4321
4322         spin_unlock_irq(&hdsp->lock);
4323
4324         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4325         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4326         if (hdsp->clock_source_locked) {
4327                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4328         } else if (hdsp->io_type == H9632) {
4329                 runtime->hw.rate_max = 192000;
4330                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4331                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4332         }
4333         if (hdsp->io_type == H9632) {
4334                 runtime->hw.channels_min = hdsp->qs_out_channels;
4335                 runtime->hw.channels_max = hdsp->ss_out_channels;
4336         }       
4337         
4338         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4339                              snd_hdsp_hw_rule_out_channels, hdsp,
4340                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4341         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4342                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4343                              SNDRV_PCM_HW_PARAM_RATE, -1);
4344         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4345                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4346                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4347
4348         hdsp->creg_spdif_stream = hdsp->creg_spdif;
4349         hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4350         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4351                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4352         return 0;
4353 }
4354
4355 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4356 {
4357         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4358
4359         spin_lock_irq(&hdsp->lock);
4360
4361         hdsp->playback_pid = -1;
4362         hdsp->playback_substream = NULL;
4363
4364         spin_unlock_irq(&hdsp->lock);
4365
4366         hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4367         snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4368                        SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4369         return 0;
4370 }
4371
4372
4373 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4374 {
4375         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4376         snd_pcm_runtime_t *runtime = substream->runtime;
4377
4378         if (hdsp_check_for_iobox (hdsp)) {
4379                 return -EIO;
4380         }
4381
4382         if (hdsp_check_for_firmware(hdsp)) {
4383                 if (hdsp->state & HDSP_FirmwareCached) {
4384                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4385                                 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4386                         }
4387                 } else {
4388                         snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4389                 }
4390                 return -EIO;
4391         }
4392
4393         spin_lock_irq(&hdsp->lock);
4394
4395         snd_pcm_set_sync(substream);
4396
4397         runtime->hw = snd_hdsp_capture_subinfo;
4398         runtime->dma_area = hdsp->capture_buffer;
4399         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4400
4401         hdsp->capture_pid = current->pid;
4402         hdsp->capture_substream = substream;
4403
4404         spin_unlock_irq(&hdsp->lock);
4405
4406         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4407         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4408         if (hdsp->io_type == H9632) {
4409                 runtime->hw.channels_min = hdsp->qs_in_channels;
4410                 runtime->hw.channels_max = hdsp->ss_in_channels;
4411                 runtime->hw.rate_max = 192000;
4412                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4413                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4414         }
4415         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4416                              snd_hdsp_hw_rule_in_channels, hdsp,
4417                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4418         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4419                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4420                              SNDRV_PCM_HW_PARAM_RATE, -1);
4421         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4422                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4423                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4424         return 0;
4425 }
4426
4427 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4428 {
4429         hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4430
4431         spin_lock_irq(&hdsp->lock);
4432
4433         hdsp->capture_pid = -1;
4434         hdsp->capture_substream = NULL;
4435
4436         spin_unlock_irq(&hdsp->lock);
4437         return 0;
4438 }
4439
4440 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4441 {
4442         /* we have nothing to initialize but the call is required */
4443         return 0;
4444 }
4445
4446
4447 /* helper functions for copying meter values */
4448 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4449 {
4450         u32 val = readl(src);
4451         return copy_to_user(dest, &val, 4);
4452 }
4453
4454 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4455 {
4456         u32 rms_low, rms_high;
4457         u64 rms;
4458         rms_low = readl(src_low);
4459         rms_high = readl(src_high);
4460         rms = ((u64)rms_high << 32) | rms_low;
4461         return copy_to_user(dest, &rms, 8);
4462 }
4463
4464 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4465 {
4466         u32 rms_low, rms_high;
4467         u64 rms;
4468         rms_low = readl(src_low) & 0xffffff00;
4469         rms_high = readl(src_high) & 0xffffff00;
4470         rms = ((u64)rms_high << 32) | rms_low;
4471         return copy_to_user(dest, &rms, 8);
4472 }
4473
4474 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4475 {
4476         int doublespeed = 0;
4477         int i, j, channels, ofs;
4478
4479         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4480                 doublespeed = 1;
4481         channels = doublespeed ? 14 : 26;
4482         for (i = 0, j = 0; i < 26; ++i) {
4483                 if (doublespeed && (i & 4))
4484                         continue;
4485                 ofs = HDSP_9652_peakBase - j * 4;
4486                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4487                         return -EFAULT;
4488                 ofs -= channels * 4;
4489                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4490                         return -EFAULT;
4491                 ofs -= channels * 4;
4492                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4493                         return -EFAULT;
4494                 ofs = HDSP_9652_rmsBase + j * 8;
4495                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4496                                 hdsp->iobase + ofs + 4))
4497                         return -EFAULT;
4498                 ofs += channels * 8;
4499                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4500                                 hdsp->iobase + ofs + 4))
4501                         return -EFAULT;
4502                 ofs += channels * 8;
4503                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4504                                 hdsp->iobase + ofs + 4))
4505                         return -EFAULT;
4506                 j++;
4507         }
4508         return 0;
4509 }
4510
4511 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4512 {
4513         int i, j;
4514         hdsp_9632_meters_t __iomem *m;
4515         int doublespeed = 0;
4516
4517         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4518                 doublespeed = 1;
4519         m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4520         for (i = 0, j = 0; i < 16; ++i, ++j) {
4521                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4522                         return -EFAULT;
4523                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4524                         return -EFAULT;
4525                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4526                         return -EFAULT;
4527                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4528                                 &m->input_rms_high[j]))
4529                         return -EFAULT;
4530                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4531                                 &m->playback_rms_high[j]))
4532                         return -EFAULT;
4533                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4534                                 &m->output_rms_high[j]))
4535                         return -EFAULT;
4536                 if (doublespeed && i == 3) i += 4;
4537         }
4538         return 0;
4539 }
4540
4541 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4542 {
4543         int i;
4544
4545         for (i = 0; i < 26; i++) {
4546                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4547                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4548                         return -EFAULT;
4549                 if (copy_u32_le(&peak_rms->input_peaks[i],
4550                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4551                         return -EFAULT;
4552         }
4553         for (i = 0; i < 28; i++) {
4554                 if (copy_u32_le(&peak_rms->output_peaks[i],
4555                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4556                         return -EFAULT;
4557         }
4558         for (i = 0; i < 26; ++i) {
4559                 if (copy_u64_le(&peak_rms->playback_rms[i],
4560                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4561                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4562                         return -EFAULT;
4563                 if (copy_u64_le(&peak_rms->input_rms[i], 
4564                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4565                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4566                         return -EFAULT;
4567         }
4568         return 0;
4569 }
4570
4571 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4572 {
4573         hdsp_t *hdsp = (hdsp_t *)hw->private_data;      
4574         void __user *argp = (void __user *)arg;
4575
4576         switch (cmd) {
4577         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4578                 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4579
4580                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4581                         snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4582                         return -EINVAL;
4583                 }
4584
4585                 switch (hdsp->io_type) {
4586                 case H9652:
4587                         return hdsp_9652_get_peak(hdsp, peak_rms);
4588                 case H9632:
4589                         return hdsp_9632_get_peak(hdsp, peak_rms);
4590                 default:
4591                         return hdsp_get_peak(hdsp, peak_rms);
4592                 }
4593         }
4594         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4595                 hdsp_config_info_t info;
4596                 unsigned long flags;
4597                 int i;
4598                 
4599                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4600                         snd_printk("Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");     
4601                         return -EINVAL;
4602                 }
4603                 spin_lock_irqsave(&hdsp->lock, flags);
4604                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4605                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4606                 if (hdsp->io_type != H9632) {
4607                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4608                 }
4609                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4610                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4611                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4612                 }
4613                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4614                 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4615                 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4616                 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4617                 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4618                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4619                 info.system_sample_rate = hdsp->system_sample_rate;
4620                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4621                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4622                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4623                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4624                 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4625                 if (hdsp->io_type == H9632) {
4626                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4627                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4628                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4629                         info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4630                 
4631                 }
4632                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4633                         info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4634                 }
4635                 spin_unlock_irqrestore(&hdsp->lock, flags);
4636                 if (copy_to_user(argp, &info, sizeof(info)))
4637                         return -EFAULT;
4638                 break;
4639         }
4640         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4641                 hdsp_9632_aeb_t h9632_aeb;
4642                 
4643                 if (hdsp->io_type != H9632) return -EINVAL;
4644                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4645                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4646                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4647                         return -EFAULT;
4648                 break;
4649         }
4650         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4651                 hdsp_version_t hdsp_version;
4652                 int err;
4653                 
4654                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4655                 if (hdsp->io_type == Undefined) {
4656                         if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4657                                 return err;
4658                         }
4659                 }
4660                 hdsp_version.io_type = hdsp->io_type;
4661                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4662                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4663                         return -EFAULT;
4664                 }
4665                 break;
4666         }
4667         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4668                 hdsp_firmware_t __user *firmware;
4669                 u32 __user *firmware_data;
4670                 int err;
4671                 
4672                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4673                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4674                 if (hdsp->io_type == Undefined) return -EINVAL;
4675
4676                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4677                         return -EBUSY;
4678
4679                 snd_printk("Hammerfall-DSP: initializing firmware upload\n");
4680                 firmware = (hdsp_firmware_t __user *)argp;
4681
4682                 if (get_user(firmware_data, &firmware->firmware_data)) {
4683                         return -EFAULT;
4684                 }
4685                 
4686                 if (hdsp_check_for_iobox (hdsp)) {
4687                         return -EIO;
4688                 }
4689
4690                 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4691                         return -EFAULT;
4692                 }
4693                 
4694                 hdsp->state |= HDSP_FirmwareCached;
4695
4696                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4697                         return err;
4698                 }
4699                 
4700                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4701                         if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4702                                 return err;
4703                         }
4704                         
4705                         snd_hdsp_initialize_channels(hdsp);             
4706                         snd_hdsp_initialize_midi_flush(hdsp);
4707             
4708                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4709                                 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4710                             return err;
4711                         }
4712                 }
4713                 break;
4714         }
4715         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4716                 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4717                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4718                         return -EFAULT;
4719                 break;
4720         }
4721         default:
4722                 return -EINVAL;
4723         }
4724         return 0;
4725 }
4726
4727 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4728         .open =         snd_hdsp_playback_open,
4729         .close =        snd_hdsp_playback_release,
4730         .ioctl =        snd_hdsp_ioctl,
4731         .hw_params =    snd_hdsp_hw_params,
4732         .prepare =      snd_hdsp_prepare,
4733         .trigger =      snd_hdsp_trigger,
4734         .pointer =      snd_hdsp_hw_pointer,
4735         .copy =         snd_hdsp_playback_copy,
4736         .silence =      snd_hdsp_hw_silence,
4737 };
4738
4739 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4740         .open =         snd_hdsp_capture_open,
4741         .close =        snd_hdsp_capture_release,
4742         .ioctl =        snd_hdsp_ioctl,
4743         .hw_params =    snd_hdsp_hw_params,
4744         .prepare =      snd_hdsp_prepare,
4745         .trigger =      snd_hdsp_trigger,
4746         .pointer =      snd_hdsp_hw_pointer,
4747         .copy =         snd_hdsp_capture_copy,
4748 };
4749
4750 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4751                                            hdsp_t *hdsp)
4752 {
4753         snd_hwdep_t *hw;
4754         int err;
4755         
4756         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4757                 return err;
4758                 
4759         hdsp->hwdep = hw;
4760         hw->private_data = hdsp;
4761         strcpy(hw->name, "HDSP hwdep interface");
4762
4763         hw->ops.open = snd_hdsp_hwdep_dummy_op;
4764         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4765         hw->ops.release = snd_hdsp_hwdep_dummy_op;
4766                 
4767         return 0;
4768 }
4769
4770 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp)
4771 {
4772         snd_pcm_t *pcm;
4773         int err;
4774
4775         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4776                 return err;
4777
4778         hdsp->pcm = pcm;
4779         pcm->private_data = hdsp;
4780         strcpy(pcm->name, hdsp->card_name);
4781
4782         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4783         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4784
4785         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4786
4787         return 0;
4788 }
4789
4790 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4791 {
4792         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4793         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4794 }
4795
4796 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4797 {
4798         int i;
4799         
4800         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4801                 snd_printk("Hammerfall-DSP: enable_io fifo_wait failed\n");
4802                 return -EIO;
4803         }
4804         
4805         for (i = 0; i < hdsp->max_channels; ++i) {
4806                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4807                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4808         }
4809         
4810         return 0;
4811 }
4812
4813 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4814 {
4815         int status, aebi_channels, aebo_channels;
4816         
4817         switch (hdsp->io_type) {
4818         case Digiface:
4819                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4820                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4821                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4822                 break;
4823
4824         case H9652:
4825                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4826                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4827                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4828                 break;
4829         
4830         case H9632:
4831                 status = hdsp_read(hdsp, HDSP_statusRegister);
4832                 /* HDSP_AEBx bits are low when AEB are connected */
4833                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4834                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4835                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4836                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4837                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4838                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4839                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4840                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4841                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4842                 break;
4843
4844         case Multiface:
4845                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4846                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4847                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4848                 break;
4849                 
4850         default:
4851                 /* should never get here */
4852                 break;
4853         }
4854 }
4855
4856 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4857 {
4858         snd_hdsp_flush_midi_input (hdsp, 0);
4859         snd_hdsp_flush_midi_input (hdsp, 1);
4860 }
4861
4862 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4863 {
4864         int err;
4865         
4866         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4867                 snd_printk("Hammerfall-DSP: Error creating pcm interface\n");
4868                 return err;
4869         }
4870         
4871
4872         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4873                 snd_printk("Hammerfall-DSP: Error creating first midi interface\n");
4874                 return err;
4875         }
4876
4877         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4878                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4879                         snd_printk("Hammerfall-DSP: Error creating second midi interface\n");
4880                         return err;
4881                 }
4882         }
4883
4884         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4885                 snd_printk("Hammerfall-DSP: Error creating ctl interface\n");
4886                 return err;
4887         }
4888
4889         snd_hdsp_proc_init(hdsp);
4890
4891         hdsp->system_sample_rate = -1;
4892         hdsp->playback_pid = -1;
4893         hdsp->capture_pid = -1;
4894         hdsp->capture_substream = NULL;
4895         hdsp->playback_substream = NULL;
4896
4897         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4898                 snd_printk("Hammerfall-DSP: Error setting default values\n");
4899                 return err;
4900         }
4901         
4902         if (!(hdsp->state & HDSP_InitializationComplete)) {
4903                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 
4904                         hdsp->port, hdsp->irq);
4905             
4906                 if ((err = snd_card_register(card)) < 0) {
4907                         snd_printk("Hammerfall-DSP: error registering card\n");
4908                         return err;
4909                 }
4910                 hdsp->state |= HDSP_InitializationComplete;
4911         }
4912         
4913         return 0;
4914 }
4915
4916 #ifdef HDSP_FW_LOADER
4917 /* load firmware via hotplug fw loader */
4918 static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp)
4919 {
4920         const char *fwfile;
4921         const struct firmware *fw;
4922         int err;
4923                 
4924         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4925                 return 0;
4926         if (hdsp->io_type == Undefined) {
4927                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4928                         return err;
4929                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4930                         return 0;
4931         }
4932         
4933         /* caution: max length of firmware filename is 30! */
4934         switch (hdsp->io_type) {
4935         case Multiface:
4936                 if (hdsp->firmware_rev == 0xa)
4937                         fwfile = "multiface_firmware.bin";
4938                 else
4939                         fwfile = "multiface_firmware_rev11.bin";
4940                 break;
4941         case Digiface:
4942                 if (hdsp->firmware_rev == 0xa)
4943                         fwfile = "digiface_firmware.bin";
4944                 else
4945                         fwfile = "digiface_firmware_rev11.bin";
4946                 break;
4947         default:
4948                 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4949                 return -EINVAL;
4950         }
4951
4952         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4953                 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4954                 return -ENOENT;
4955         }
4956         if (fw->size < sizeof(hdsp->firmware_cache)) {
4957                 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4958                            (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4959                 release_firmware(fw);
4960                 return -EINVAL;
4961         }
4962
4963         memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4964
4965         release_firmware(fw);
4966                 
4967         hdsp->state |= HDSP_FirmwareCached;
4968
4969         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4970                 return err;
4971                 
4972         if (!(hdsp->state & HDSP_InitializationComplete)) {
4973                 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4974                         return err;
4975                 }
4976
4977                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4978                         snd_printk("Hammerfall-DSP: error creating hwdep device\n");
4979                         return err;
4980                 }
4981                 snd_hdsp_initialize_channels(hdsp);
4982                 snd_hdsp_initialize_midi_flush(hdsp);
4983                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4984                         snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4985                         return err;
4986                 }
4987         }
4988         return 0;
4989 }
4990 #endif
4991
4992 static int __devinit snd_hdsp_create(snd_card_t *card,
4993                                      hdsp_t *hdsp)
4994 {
4995         struct pci_dev *pci = hdsp->pci;
4996         int err;
4997         int is_9652 = 0;
4998         int is_9632 = 0;
4999
5000         hdsp->irq = -1;
5001         hdsp->state = 0;
5002         hdsp->midi[0].rmidi = NULL;
5003         hdsp->midi[1].rmidi = NULL;
5004         hdsp->midi[0].input = NULL;
5005         hdsp->midi[1].input = NULL;
5006         hdsp->midi[0].output = NULL;
5007         hdsp->midi[1].output = NULL;
5008         hdsp->midi[0].pending = 0;
5009         hdsp->midi[1].pending = 0;
5010         spin_lock_init(&hdsp->midi[0].lock);
5011         spin_lock_init(&hdsp->midi[1].lock);
5012         hdsp->iobase = NULL;
5013         hdsp->control_register = 0;
5014         hdsp->control2_register = 0;
5015         hdsp->io_type = Undefined;
5016         hdsp->max_channels = 26;
5017
5018         hdsp->card = card;
5019         
5020         spin_lock_init(&hdsp->lock);
5021
5022         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5023         
5024         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5025         hdsp->firmware_rev &= 0xff;
5026         
5027         /* From Martin Bjoernsen :
5028             "It is important that the card's latency timer register in
5029             the PCI configuration space is set to a value much larger
5030             than 0 by the computer's BIOS or the driver.
5031             The windows driver always sets this 8 bit register [...]
5032             to its maximum 255 to avoid problems with some computers."
5033         */
5034         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5035         
5036         strcpy(card->driver, "H-DSP");
5037         strcpy(card->mixername, "Xilinx FPGA");
5038
5039         if (hdsp->firmware_rev < 0xa) {
5040                 return -ENODEV;
5041         } else if (hdsp->firmware_rev < 0x64) {
5042                 hdsp->card_name = "RME Hammerfall DSP";
5043         } else if (hdsp->firmware_rev < 0x96) {
5044                 hdsp->card_name = "RME HDSP 9652";
5045                 is_9652 = 1;
5046         } else {
5047                 hdsp->card_name = "RME HDSP 9632";
5048                 hdsp->max_channels = 16;
5049                 is_9632 = 1;    
5050         }
5051
5052         if ((err = pci_enable_device(pci)) < 0) {
5053                 return err;
5054         }
5055
5056         pci_set_master(hdsp->pci);
5057
5058         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5059                 return err;
5060         hdsp->port = pci_resource_start(pci, 0);
5061         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5062                 snd_printk("Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5063                 return -EBUSY;
5064         }
5065
5066         if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5067                 snd_printk("Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5068                 return -EBUSY;
5069         }
5070
5071         hdsp->irq = pci->irq;
5072         hdsp->precise_ptr = 1;
5073         hdsp->use_midi_tasklet = 1;
5074
5075         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5076                 return err;
5077         }
5078         
5079         if (!is_9652 && !is_9632) {
5080                 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5081                 if ((1000 / HZ) < 2000) {
5082                         ssleep(2);
5083                 } else {
5084                         mdelay(2000);
5085                 }
5086
5087                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5088 #ifdef HDSP_FW_LOADER
5089                         if ((err = hdsp_request_fw_loader(hdsp)) < 0) {
5090                                 /* we don't fail as this can happen
5091                                    if userspace is not ready for
5092                                    firmware upload
5093                                 */
5094                                 snd_printk("Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5095                         } else {
5096                                 /* init is complete, we return */
5097                                 return 0;
5098                         }
5099 #endif
5100                         /* no iobox connected, we defer initialization */
5101                         snd_printk("Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5102                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5103                                 return err;
5104                         }
5105                         return 0;
5106                 } else {
5107                         snd_printk("Hammerfall-DSP: Firmware already present, initializing card.\n");       
5108                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5109                                 hdsp->io_type = Multiface;
5110                         } else {
5111                                 hdsp->io_type = Digiface;
5112                         }
5113                 }
5114         }
5115         
5116         if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5117                 return err;
5118         }
5119         
5120         if (is_9652) {
5121                 hdsp->io_type = H9652;
5122         }
5123         
5124         if (is_9632) {
5125                 hdsp->io_type = H9632;
5126         }
5127
5128         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5129                 return err;
5130         }
5131         
5132         snd_hdsp_initialize_channels(hdsp);
5133         snd_hdsp_initialize_midi_flush(hdsp);
5134
5135         hdsp->state |= HDSP_FirmwareLoaded;     
5136
5137         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5138                 return err;
5139         }
5140
5141         return 0;       
5142 }
5143
5144 static int snd_hdsp_free(hdsp_t *hdsp)
5145 {
5146         if (hdsp->port) {
5147                 /* stop the audio, and cancel all interrupts */
5148                 tasklet_kill(&hdsp->midi_tasklet);
5149                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5150                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5151         }
5152
5153         if (hdsp->irq >= 0)
5154                 free_irq(hdsp->irq, (void *)hdsp);
5155
5156         snd_hdsp_free_buffers(hdsp);
5157         
5158         if (hdsp->iobase)
5159                 iounmap(hdsp->iobase);
5160
5161         if (hdsp->port)
5162                 pci_release_regions(hdsp->pci);
5163                 
5164         pci_disable_device(hdsp->pci);
5165         return 0;
5166 }
5167
5168 static void snd_hdsp_card_free(snd_card_t *card)
5169 {
5170         hdsp_t *hdsp = (hdsp_t *) card->private_data;
5171
5172         if (hdsp)
5173                 snd_hdsp_free(hdsp);
5174 }
5175
5176 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5177                                     const struct pci_device_id *pci_id)
5178 {
5179         static int dev;
5180         hdsp_t *hdsp;
5181         snd_card_t *card;
5182         int err;
5183
5184         if (dev >= SNDRV_CARDS)
5185                 return -ENODEV;
5186         if (!enable[dev]) {
5187                 dev++;
5188                 return -ENOENT;
5189         }
5190
5191         if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5192                 return -ENOMEM;
5193
5194         hdsp = (hdsp_t *) card->private_data;
5195         card->private_free = snd_hdsp_card_free;
5196         hdsp->dev = dev;
5197         hdsp->pci = pci;
5198         snd_card_set_dev(card, &pci->dev);
5199
5200         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5201                 snd_card_free(card);
5202                 return err;
5203         }
5204
5205         strcpy(card->shortname, "Hammerfall DSP");
5206         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 
5207                 hdsp->port, hdsp->irq);
5208
5209         if ((err = snd_card_register(card)) < 0) {
5210                 snd_card_free(card);
5211                 return err;
5212         }
5213         pci_set_drvdata(pci, card);
5214         dev++;
5215         return 0;
5216 }
5217
5218 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5219 {
5220         snd_card_free(pci_get_drvdata(pci));
5221         pci_set_drvdata(pci, NULL);
5222 }
5223
5224 static struct pci_driver driver = {
5225         .name =     "RME Hammerfall DSP",
5226         .id_table = snd_hdsp_ids,
5227         .probe =    snd_hdsp_probe,
5228         .remove = __devexit_p(snd_hdsp_remove),
5229 };
5230
5231 static int __init alsa_card_hdsp_init(void)
5232 {
5233         return pci_register_driver(&driver);
5234 }
5235
5236 static void __exit alsa_card_hdsp_exit(void)
5237 {
5238         pci_unregister_driver(&driver);
5239 }
5240
5241 module_init(alsa_card_hdsp_init)
5242 module_exit(alsa_card_hdsp_exit)