[ALSA] sound/pci: remove line duplications in defines
[linux-2.6.git] / sound / pci / maestro3.c
1 /*
2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4  *                       Takashi Iwai <tiwai@suse.de>
5  *
6  * Most of the hardware init stuffs are based on maestro3 driver for
7  * OSS/Free by Zach Brown.  Many thanks to Zach!
8  *
9  *   This program is free software; you can redistribute it and/or modify
10  *   it under the terms of the GNU General Public License as published by
11  *   the Free Software Foundation; either version 2 of the License, or
12  *   (at your option) any later version.
13  *
14  *   This program is distributed in the hope that it will be useful,
15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *   GNU General Public License for more details.
18  *
19  *   You should have received a copy of the GNU General Public License
20  *   along with this program; if not, write to the Free Software
21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  *
23  *
24  * ChangeLog:
25  * Aug. 27, 2001
26  *     - Fixed deadlock on capture
27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28  *
29  */
30  
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <sound/driver.h>
35 #include <asm/io.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include <linux/init.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/moduleparam.h>
44 #include <linux/firmware.h>
45 #include <sound/core.h>
46 #include <sound/info.h>
47 #include <sound/control.h>
48 #include <sound/pcm.h>
49 #include <sound/mpu401.h>
50 #include <sound/ac97_codec.h>
51 #include <sound/initval.h>
52 #include <asm/byteorder.h>
53
54 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
55 MODULE_DESCRIPTION("ESS Maestro3 PCI");
56 MODULE_LICENSE("GPL");
57 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
58                 "{ESS,ES1988},"
59                 "{ESS,Allegro PCI},"
60                 "{ESS,Allegro-1 PCI},"
61                 "{ESS,Canyon3D-2/LE PCI}}");
62 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
63 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
64 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
65 #endif
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
70 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
71 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
72
73 module_param_array(index, int, NULL, 0444);
74 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
75 module_param_array(id, charp, NULL, 0444);
76 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
77 module_param_array(enable, bool, NULL, 0444);
78 MODULE_PARM_DESC(enable, "Enable this soundcard.");
79 module_param_array(external_amp, bool, NULL, 0444);
80 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
81 module_param_array(amp_gpio, int, NULL, 0444);
82 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
83
84 #define MAX_PLAYBACKS   2
85 #define MAX_CAPTURES    1
86 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
87
88
89 /*
90  * maestro3 registers
91  */
92
93 /* Allegro PCI configuration registers */
94 #define PCI_LEGACY_AUDIO_CTRL   0x40
95 #define SOUND_BLASTER_ENABLE    0x00000001
96 #define FM_SYNTHESIS_ENABLE     0x00000002
97 #define GAME_PORT_ENABLE        0x00000004
98 #define MPU401_IO_ENABLE        0x00000008
99 #define MPU401_IRQ_ENABLE       0x00000010
100 #define ALIAS_10BIT_IO          0x00000020
101 #define SB_DMA_MASK             0x000000C0
102 #define SB_DMA_0                0x00000040
103 #define SB_DMA_1                0x00000040
104 #define SB_DMA_R                0x00000080
105 #define SB_DMA_3                0x000000C0
106 #define SB_IRQ_MASK             0x00000700
107 #define SB_IRQ_5                0x00000000
108 #define SB_IRQ_7                0x00000100
109 #define SB_IRQ_9                0x00000200
110 #define SB_IRQ_10               0x00000300
111 #define MIDI_IRQ_MASK           0x00003800
112 #define SERIAL_IRQ_ENABLE       0x00004000
113 #define DISABLE_LEGACY          0x00008000
114
115 #define PCI_ALLEGRO_CONFIG      0x50
116 #define SB_ADDR_240             0x00000004
117 #define MPU_ADDR_MASK           0x00000018
118 #define MPU_ADDR_330            0x00000000
119 #define MPU_ADDR_300            0x00000008
120 #define MPU_ADDR_320            0x00000010
121 #define MPU_ADDR_340            0x00000018
122 #define USE_PCI_TIMING          0x00000040
123 #define POSTED_WRITE_ENABLE     0x00000080
124 #define DMA_POLICY_MASK         0x00000700
125 #define DMA_DDMA                0x00000000
126 #define DMA_TDMA                0x00000100
127 #define DMA_PCPCI               0x00000200
128 #define DMA_WBDMA16             0x00000400
129 #define DMA_WBDMA4              0x00000500
130 #define DMA_WBDMA2              0x00000600
131 #define DMA_WBDMA1              0x00000700
132 #define DMA_SAFE_GUARD          0x00000800
133 #define HI_PERF_GP_ENABLE       0x00001000
134 #define PIC_SNOOP_MODE_0        0x00002000
135 #define PIC_SNOOP_MODE_1        0x00004000
136 #define SOUNDBLASTER_IRQ_MASK   0x00008000
137 #define RING_IN_ENABLE          0x00010000
138 #define SPDIF_TEST_MODE         0x00020000
139 #define CLK_MULT_MODE_SELECT_2  0x00040000
140 #define EEPROM_WRITE_ENABLE     0x00080000
141 #define CODEC_DIR_IN            0x00100000
142 #define HV_BUTTON_FROM_GD       0x00200000
143 #define REDUCED_DEBOUNCE        0x00400000
144 #define HV_CTRL_ENABLE          0x00800000
145 #define SPDIF_ENABLE            0x01000000
146 #define CLK_DIV_SELECT          0x06000000
147 #define CLK_DIV_BY_48           0x00000000
148 #define CLK_DIV_BY_49           0x02000000
149 #define CLK_DIV_BY_50           0x04000000
150 #define CLK_DIV_RESERVED        0x06000000
151 #define PM_CTRL_ENABLE          0x08000000
152 #define CLK_MULT_MODE_SELECT    0x30000000
153 #define CLK_MULT_MODE_SHIFT     28
154 #define CLK_MULT_MODE_0         0x00000000
155 #define CLK_MULT_MODE_1         0x10000000
156 #define CLK_MULT_MODE_2         0x20000000
157 #define CLK_MULT_MODE_3         0x30000000
158 #define INT_CLK_SELECT          0x40000000
159 #define INT_CLK_MULT_RESET      0x80000000
160
161 /* M3 */
162 #define INT_CLK_SRC_NOT_PCI     0x00100000
163 #define INT_CLK_MULT_ENABLE     0x80000000
164
165 #define PCI_ACPI_CONTROL        0x54
166 #define PCI_ACPI_D0             0x00000000
167 #define PCI_ACPI_D1             0xB4F70000
168 #define PCI_ACPI_D2             0xB4F7B4F7
169
170 #define PCI_USER_CONFIG         0x58
171 #define EXT_PCI_MASTER_ENABLE   0x00000001
172 #define SPDIF_OUT_SELECT        0x00000002
173 #define TEST_PIN_DIR_CTRL       0x00000004
174 #define AC97_CODEC_TEST         0x00000020
175 #define TRI_STATE_BUFFER        0x00000080
176 #define IN_CLK_12MHZ_SELECT     0x00000100
177 #define MULTI_FUNC_DISABLE      0x00000200
178 #define EXT_MASTER_PAIR_SEL     0x00000400
179 #define PCI_MASTER_SUPPORT      0x00000800
180 #define STOP_CLOCK_ENABLE       0x00001000
181 #define EAPD_DRIVE_ENABLE       0x00002000
182 #define REQ_TRI_STATE_ENABLE    0x00004000
183 #define REQ_LOW_ENABLE          0x00008000
184 #define MIDI_1_ENABLE           0x00010000
185 #define MIDI_2_ENABLE           0x00020000
186 #define SB_AUDIO_SYNC           0x00040000
187 #define HV_CTRL_TEST            0x00100000
188 #define SOUNDBLASTER_TEST       0x00400000
189
190 #define PCI_USER_CONFIG_C       0x5C
191
192 #define PCI_DDMA_CTRL           0x60
193 #define DDMA_ENABLE             0x00000001
194
195
196 /* Allegro registers */
197 #define HOST_INT_CTRL           0x18
198 #define SB_INT_ENABLE           0x0001
199 #define MPU401_INT_ENABLE       0x0002
200 #define ASSP_INT_ENABLE         0x0010
201 #define RING_INT_ENABLE         0x0020
202 #define HV_INT_ENABLE           0x0040
203 #define CLKRUN_GEN_ENABLE       0x0100
204 #define HV_CTRL_TO_PME          0x0400
205 #define SOFTWARE_RESET_ENABLE   0x8000
206
207 /*
208  * should be using the above defines, probably.
209  */
210 #define REGB_ENABLE_RESET               0x01
211 #define REGB_STOP_CLOCK                 0x10
212
213 #define HOST_INT_STATUS         0x1A
214 #define SB_INT_PENDING          0x01
215 #define MPU401_INT_PENDING      0x02
216 #define ASSP_INT_PENDING        0x10
217 #define RING_INT_PENDING        0x20
218 #define HV_INT_PENDING          0x40
219
220 #define HARDWARE_VOL_CTRL       0x1B
221 #define SHADOW_MIX_REG_VOICE    0x1C
222 #define HW_VOL_COUNTER_VOICE    0x1D
223 #define SHADOW_MIX_REG_MASTER   0x1E
224 #define HW_VOL_COUNTER_MASTER   0x1F
225
226 #define CODEC_COMMAND           0x30
227 #define CODEC_READ_B            0x80
228
229 #define CODEC_STATUS            0x30
230 #define CODEC_BUSY_B            0x01
231
232 #define CODEC_DATA              0x32
233
234 #define RING_BUS_CTRL_A         0x36
235 #define RAC_PME_ENABLE          0x0100
236 #define RAC_SDFS_ENABLE         0x0200
237 #define LAC_PME_ENABLE          0x0400
238 #define LAC_SDFS_ENABLE         0x0800
239 #define SERIAL_AC_LINK_ENABLE   0x1000
240 #define IO_SRAM_ENABLE          0x2000
241 #define IIS_INPUT_ENABLE        0x8000
242
243 #define RING_BUS_CTRL_B         0x38
244 #define SECOND_CODEC_ID_MASK    0x0003
245 #define SPDIF_FUNC_ENABLE       0x0010
246 #define SECOND_AC_ENABLE        0x0020
247 #define SB_MODULE_INTF_ENABLE   0x0040
248 #define SSPE_ENABLE             0x0040
249 #define M3I_DOCK_ENABLE         0x0080
250
251 #define SDO_OUT_DEST_CTRL       0x3A
252 #define COMMAND_ADDR_OUT        0x0003
253 #define PCM_LR_OUT_LOCAL        0x0000
254 #define PCM_LR_OUT_REMOTE       0x0004
255 #define PCM_LR_OUT_MUTE         0x0008
256 #define PCM_LR_OUT_BOTH         0x000C
257 #define LINE1_DAC_OUT_LOCAL     0x0000
258 #define LINE1_DAC_OUT_REMOTE    0x0010
259 #define LINE1_DAC_OUT_MUTE      0x0020
260 #define LINE1_DAC_OUT_BOTH      0x0030
261 #define PCM_CLS_OUT_LOCAL       0x0000
262 #define PCM_CLS_OUT_REMOTE      0x0040
263 #define PCM_CLS_OUT_MUTE        0x0080
264 #define PCM_CLS_OUT_BOTH        0x00C0
265 #define PCM_RLF_OUT_LOCAL       0x0000
266 #define PCM_RLF_OUT_REMOTE      0x0100
267 #define PCM_RLF_OUT_MUTE        0x0200
268 #define PCM_RLF_OUT_BOTH        0x0300
269 #define LINE2_DAC_OUT_LOCAL     0x0000
270 #define LINE2_DAC_OUT_REMOTE    0x0400
271 #define LINE2_DAC_OUT_MUTE      0x0800
272 #define LINE2_DAC_OUT_BOTH      0x0C00
273 #define HANDSET_OUT_LOCAL       0x0000
274 #define HANDSET_OUT_REMOTE      0x1000
275 #define HANDSET_OUT_MUTE        0x2000
276 #define HANDSET_OUT_BOTH        0x3000
277 #define IO_CTRL_OUT_LOCAL       0x0000
278 #define IO_CTRL_OUT_REMOTE      0x4000
279 #define IO_CTRL_OUT_MUTE        0x8000
280 #define IO_CTRL_OUT_BOTH        0xC000
281
282 #define SDO_IN_DEST_CTRL        0x3C
283 #define STATUS_ADDR_IN          0x0003
284 #define PCM_LR_IN_LOCAL         0x0000
285 #define PCM_LR_IN_REMOTE        0x0004
286 #define PCM_LR_RESERVED         0x0008
287 #define PCM_LR_IN_BOTH          0x000C
288 #define LINE1_ADC_IN_LOCAL      0x0000
289 #define LINE1_ADC_IN_REMOTE     0x0010
290 #define LINE1_ADC_IN_MUTE       0x0020
291 #define MIC_ADC_IN_LOCAL        0x0000
292 #define MIC_ADC_IN_REMOTE       0x0040
293 #define MIC_ADC_IN_MUTE         0x0080
294 #define LINE2_DAC_IN_LOCAL      0x0000
295 #define LINE2_DAC_IN_REMOTE     0x0400
296 #define LINE2_DAC_IN_MUTE       0x0800
297 #define HANDSET_IN_LOCAL        0x0000
298 #define HANDSET_IN_REMOTE       0x1000
299 #define HANDSET_IN_MUTE         0x2000
300 #define IO_STATUS_IN_LOCAL      0x0000
301 #define IO_STATUS_IN_REMOTE     0x4000
302
303 #define SPDIF_IN_CTRL           0x3E
304 #define SPDIF_IN_ENABLE         0x0001
305
306 #define GPIO_DATA               0x60
307 #define GPIO_DATA_MASK          0x0FFF
308 #define GPIO_HV_STATUS          0x3000
309 #define GPIO_PME_STATUS         0x4000
310
311 #define GPIO_MASK               0x64
312 #define GPIO_DIRECTION          0x68
313 #define GPO_PRIMARY_AC97        0x0001
314 #define GPI_LINEOUT_SENSE       0x0004
315 #define GPO_SECONDARY_AC97      0x0008
316 #define GPI_VOL_DOWN            0x0010
317 #define GPI_VOL_UP              0x0020
318 #define GPI_IIS_CLK             0x0040
319 #define GPI_IIS_LRCLK           0x0080
320 #define GPI_IIS_DATA            0x0100
321 #define GPI_DOCKING_STATUS      0x0100
322 #define GPI_HEADPHONE_SENSE     0x0200
323 #define GPO_EXT_AMP_SHUTDOWN    0x1000
324
325 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
326 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
327
328 /* M3 */
329 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
330
331 #define ASSP_INDEX_PORT         0x80
332 #define ASSP_MEMORY_PORT        0x82
333 #define ASSP_DATA_PORT          0x84
334
335 #define MPU401_DATA_PORT        0x98
336 #define MPU401_STATUS_PORT      0x99
337
338 #define CLK_MULT_DATA_PORT      0x9C
339
340 #define ASSP_CONTROL_A          0xA2
341 #define ASSP_0_WS_ENABLE        0x01
342 #define ASSP_CTRL_A_RESERVED1   0x02
343 #define ASSP_CTRL_A_RESERVED2   0x04
344 #define ASSP_CLK_49MHZ_SELECT   0x08
345 #define FAST_PLU_ENABLE         0x10
346 #define ASSP_CTRL_A_RESERVED3   0x20
347 #define DSP_CLK_36MHZ_SELECT    0x40
348
349 #define ASSP_CONTROL_B          0xA4
350 #define RESET_ASSP              0x00
351 #define RUN_ASSP                0x01
352 #define ENABLE_ASSP_CLOCK       0x00
353 #define STOP_ASSP_CLOCK         0x10
354 #define RESET_TOGGLE            0x40
355
356 #define ASSP_CONTROL_C          0xA6
357 #define ASSP_HOST_INT_ENABLE    0x01
358 #define FM_ADDR_REMAP_DISABLE   0x02
359 #define HOST_WRITE_PORT_ENABLE  0x08
360
361 #define ASSP_HOST_INT_STATUS    0xAC
362 #define DSP2HOST_REQ_PIORECORD  0x01
363 #define DSP2HOST_REQ_I2SRATE    0x02
364 #define DSP2HOST_REQ_TIMER      0x04
365
366 /* AC97 registers */
367 /* XXX fix this crap up */
368 /*#define AC97_RESET              0x00*/
369
370 #define AC97_VOL_MUTE_B         0x8000
371 #define AC97_VOL_M              0x1F
372 #define AC97_LEFT_VOL_S         8
373
374 #define AC97_MASTER_VOL         0x02
375 #define AC97_LINE_LEVEL_VOL     0x04
376 #define AC97_MASTER_MONO_VOL    0x06
377 #define AC97_PC_BEEP_VOL        0x0A
378 #define AC97_PC_BEEP_VOL_M      0x0F
379 #define AC97_SROUND_MASTER_VOL  0x38
380 #define AC97_PC_BEEP_VOL_S      1
381
382 /*#define AC97_PHONE_VOL          0x0C
383 #define AC97_MIC_VOL            0x0E*/
384 #define AC97_MIC_20DB_ENABLE    0x40
385
386 /*#define AC97_LINEIN_VOL         0x10
387 #define AC97_CD_VOL             0x12
388 #define AC97_VIDEO_VOL          0x14
389 #define AC97_AUX_VOL            0x16*/
390 #define AC97_PCM_OUT_VOL        0x18
391 /*#define AC97_RECORD_SELECT      0x1A*/
392 #define AC97_RECORD_MIC         0x00
393 #define AC97_RECORD_CD          0x01
394 #define AC97_RECORD_VIDEO       0x02
395 #define AC97_RECORD_AUX         0x03
396 #define AC97_RECORD_MONO_MUX    0x02
397 #define AC97_RECORD_DIGITAL     0x03
398 #define AC97_RECORD_LINE        0x04
399 #define AC97_RECORD_STEREO      0x05
400 #define AC97_RECORD_MONO        0x06
401 #define AC97_RECORD_PHONE       0x07
402
403 /*#define AC97_RECORD_GAIN        0x1C*/
404 #define AC97_RECORD_VOL_M       0x0F
405
406 /*#define AC97_GENERAL_PURPOSE    0x20*/
407 #define AC97_POWER_DOWN_CTRL    0x26
408 #define AC97_ADC_READY          0x0001
409 #define AC97_DAC_READY          0x0002
410 #define AC97_ANALOG_READY       0x0004
411 #define AC97_VREF_ON            0x0008
412 #define AC97_PR0                0x0100
413 #define AC97_PR1                0x0200
414 #define AC97_PR2                0x0400
415 #define AC97_PR3                0x0800
416 #define AC97_PR4                0x1000
417
418 #define AC97_RESERVED1          0x28
419
420 #define AC97_VENDOR_TEST        0x5A
421
422 #define AC97_CLOCK_DELAY        0x5C
423 #define AC97_LINEOUT_MUX_SEL    0x0001
424 #define AC97_MONO_MUX_SEL       0x0002
425 #define AC97_CLOCK_DELAY_SEL    0x1F
426 #define AC97_DAC_CDS_SHIFT      6
427 #define AC97_ADC_CDS_SHIFT      11
428
429 #define AC97_MULTI_CHANNEL_SEL  0x74
430
431 /*#define AC97_VENDOR_ID1         0x7C
432 #define AC97_VENDOR_ID2         0x7E*/
433
434 /*
435  * ASSP control regs
436  */
437 #define DSP_PORT_TIMER_COUNT    0x06
438
439 #define DSP_PORT_MEMORY_INDEX   0x80
440
441 #define DSP_PORT_MEMORY_TYPE    0x82
442 #define MEMTYPE_INTERNAL_CODE   0x0002
443 #define MEMTYPE_INTERNAL_DATA   0x0003
444 #define MEMTYPE_MASK            0x0003
445
446 #define DSP_PORT_MEMORY_DATA    0x84
447
448 #define DSP_PORT_CONTROL_REG_A  0xA2
449 #define DSP_PORT_CONTROL_REG_B  0xA4
450 #define DSP_PORT_CONTROL_REG_C  0xA6
451
452 #define REV_A_CODE_MEMORY_BEGIN         0x0000
453 #define REV_A_CODE_MEMORY_END           0x0FFF
454 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
455 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
456
457 #define REV_B_CODE_MEMORY_BEGIN         0x0000
458 #define REV_B_CODE_MEMORY_END           0x0BFF
459 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
460 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
461
462 #define REV_A_DATA_MEMORY_BEGIN         0x1000
463 #define REV_A_DATA_MEMORY_END           0x2FFF
464 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
465 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
466
467 #define REV_B_DATA_MEMORY_BEGIN         0x1000
468 #define REV_B_DATA_MEMORY_END           0x2BFF
469 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
470 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
471
472
473 #define NUM_UNITS_KERNEL_CODE          16
474 #define NUM_UNITS_KERNEL_DATA           2
475
476 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
477 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
478
479 /*
480  * Kernel data layout
481  */
482
483 #define DP_SHIFT_COUNT                  7
484
485 #define KDATA_BASE_ADDR                 0x1000
486 #define KDATA_BASE_ADDR2                0x1080
487
488 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
489 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
490 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
491 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
492 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
493 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
494 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
495 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
496 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
497
498 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
499 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
500
501 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
502 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
503 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
504 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
505 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
506 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
507 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
508 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
509 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
510 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
511
512 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
513 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
514
515 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
516 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
517
518 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
519 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
520
521 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
522 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
523 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
524
525 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
526 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
527 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
528 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
529 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
530
531 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
532 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
533 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
534
535 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
536 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
537 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
538
539 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
540 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
541 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
542 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
543 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
544 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
545 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
546 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
547 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
548 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
549
550 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
551 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
552 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
553
554 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
555 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
556
557 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
558 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
559 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
560
561 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
562 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
563 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
564 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
565 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
566 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
567
568 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
569 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
570 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
571 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
572 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
573 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
574
575 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)                                      
576 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
577 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
578 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
579 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
580 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
581
582 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
583 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
584 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
585 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
586
587 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
588 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
589
590 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
591 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
592
593 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
594 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
595 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
596 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
597 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
598
599 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
600 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
601
602 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
603 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
604 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
605
606 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
607 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
608
609 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
610
611 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
612 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
613 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
614 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
615 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
616 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
617 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
618 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
619 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
620 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
621 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
622 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
623
624 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
625 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
626 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
627 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
628
629 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
630 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
631
632 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
633 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
634 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
635 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
636
637 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
638 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
639 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
640 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
641 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
642
643 /*
644  * second 'segment' (?) reserved for mixer
645  * buffers..
646  */
647
648 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
649 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
650 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
651 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
652 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
653 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
654 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
655 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
656 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
657 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
658 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
659 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
660 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
661 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
662 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
663 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
664
665 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
666 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
667 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
668 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
669 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
670 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
671 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
672 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
673 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
674 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
675 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
676
677 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
678 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
679 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
680 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
681 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
682 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
683
684 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
685 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
686 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
687 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
688
689 /*
690  * client data area offsets
691  */
692 #define CDATA_INSTANCE_READY            0x00
693
694 #define CDATA_HOST_SRC_ADDRL            0x01
695 #define CDATA_HOST_SRC_ADDRH            0x02
696 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
697 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
698 #define CDATA_HOST_SRC_CURRENTL         0x05
699 #define CDATA_HOST_SRC_CURRENTH         0x06
700
701 #define CDATA_IN_BUF_CONNECT            0x07
702 #define CDATA_OUT_BUF_CONNECT           0x08
703
704 #define CDATA_IN_BUF_BEGIN              0x09
705 #define CDATA_IN_BUF_END_PLUS_1         0x0A
706 #define CDATA_IN_BUF_HEAD               0x0B
707 #define CDATA_IN_BUF_TAIL               0x0C
708 #define CDATA_OUT_BUF_BEGIN             0x0D
709 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
710 #define CDATA_OUT_BUF_HEAD              0x0F
711 #define CDATA_OUT_BUF_TAIL              0x10
712
713 #define CDATA_DMA_CONTROL               0x11
714 #define CDATA_RESERVED                  0x12
715
716 #define CDATA_FREQUENCY                 0x13
717 #define CDATA_LEFT_VOLUME               0x14
718 #define CDATA_RIGHT_VOLUME              0x15
719 #define CDATA_LEFT_SUR_VOL              0x16
720 #define CDATA_RIGHT_SUR_VOL             0x17
721
722 #define CDATA_HEADER_LEN                0x18
723
724 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
725 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
726 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
727 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
728 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
729 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
730 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
731 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
732
733 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
734 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
735 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
736 #define MINISRC_BIQUAD_STAGE    2
737 #define MINISRC_COEF_LOC          0x175
738
739 #define DMACONTROL_BLOCK_MASK           0x000F
740 #define  DMAC_BLOCK0_SELECTOR           0x0000
741 #define  DMAC_BLOCK1_SELECTOR           0x0001
742 #define  DMAC_BLOCK2_SELECTOR           0x0002
743 #define  DMAC_BLOCK3_SELECTOR           0x0003
744 #define  DMAC_BLOCK4_SELECTOR           0x0004
745 #define  DMAC_BLOCK5_SELECTOR           0x0005
746 #define  DMAC_BLOCK6_SELECTOR           0x0006
747 #define  DMAC_BLOCK7_SELECTOR           0x0007
748 #define  DMAC_BLOCK8_SELECTOR           0x0008
749 #define  DMAC_BLOCK9_SELECTOR           0x0009
750 #define  DMAC_BLOCKA_SELECTOR           0x000A
751 #define  DMAC_BLOCKB_SELECTOR           0x000B
752 #define  DMAC_BLOCKC_SELECTOR           0x000C
753 #define  DMAC_BLOCKD_SELECTOR           0x000D
754 #define  DMAC_BLOCKE_SELECTOR           0x000E
755 #define  DMAC_BLOCKF_SELECTOR           0x000F
756 #define DMACONTROL_PAGE_MASK            0x00F0
757 #define  DMAC_PAGE0_SELECTOR            0x0030
758 #define  DMAC_PAGE1_SELECTOR            0x0020
759 #define  DMAC_PAGE2_SELECTOR            0x0010
760 #define  DMAC_PAGE3_SELECTOR            0x0000
761 #define DMACONTROL_AUTOREPEAT           0x1000
762 #define DMACONTROL_STOPPED              0x2000
763 #define DMACONTROL_DIRECTION            0x0100
764
765 /*
766  * an arbitrary volume we set the internal
767  * volume settings to so that the ac97 volume
768  * range is a little less insane.  0x7fff is 
769  * max.
770  */
771 #define ARB_VOLUME ( 0x6800 )
772
773 /*
774  */
775
776 struct m3_list {
777         int curlen;
778         int mem_addr;
779         int max;
780 };
781
782 struct m3_dma {
783
784         int number;
785         struct snd_pcm_substream *substream;
786
787         struct assp_instance {
788                 unsigned short code, data;
789         } inst;
790
791         int running;
792         int opened;
793
794         unsigned long buffer_addr;
795         int dma_size;
796         int period_size;
797         unsigned int hwptr;
798         int count;
799
800         int index[3];
801         struct m3_list *index_list[3];
802
803         int in_lists;
804         
805         struct list_head list;
806
807 };
808     
809 struct snd_m3 {
810         
811         struct snd_card *card;
812
813         unsigned long iobase;
814
815         int irq;
816         unsigned int allegro_flag : 1;
817
818         struct snd_ac97 *ac97;
819
820         struct snd_pcm *pcm;
821
822         struct pci_dev *pci;
823
824         int dacs_active;
825         int timer_users;
826
827         struct m3_list  msrc_list;
828         struct m3_list  mixer_list;
829         struct m3_list  adc1_list;
830         struct m3_list  dma_list;
831
832         /* for storing reset state..*/
833         u8 reset_state;
834
835         int external_amp;
836         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
837         unsigned int hv_config;         /* hardware-volume config bits */
838         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
839                                            (e.g. for IrDA on Dell Inspirons) */
840         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
841
842         /* midi */
843         struct snd_rawmidi *rmidi;
844
845         /* pcm streams */
846         int num_substreams;
847         struct m3_dma *substreams;
848
849         spinlock_t reg_lock;
850         spinlock_t ac97_lock;
851
852         struct snd_kcontrol *master_switch;
853         struct snd_kcontrol *master_volume;
854         struct tasklet_struct hwvol_tq;
855
856 #ifdef CONFIG_PM
857         u16 *suspend_mem;
858 #endif
859
860         const struct firmware *assp_kernel_image;
861         const struct firmware *assp_minisrc_image;
862 };
863
864 /*
865  * pci ids
866  */
867 static struct pci_device_id snd_m3_ids[] = {
868         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
869          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
870         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
871          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
872         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
873          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
874         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
875          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
876         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
877          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
878         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
879          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
880         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
881          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
882         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
883          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
884         {0,},
885 };
886
887 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
888
889 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
890         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
891         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
892         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
893         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
894         { } /* END */
895 };
896
897 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
898         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
899         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
900         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
901         { } /* END */
902 };
903
904 /* hardware volume quirks */
905 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
906         /* Allegro chips */
907         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
932         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
933                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
934         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
935                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
936         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
937                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
938         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
939                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
940         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
941                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
942         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
943                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
944         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
945                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
946         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
947                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
948         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
949                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
950         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
951                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
952         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
953                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
954         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
955                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
956         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
957         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
958         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
959         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
960         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
961         /* Maestro3 chips */
962         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
963         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
964         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
965         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
966         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
967         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
968         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
969         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
970         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
971         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
972         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
973         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
974         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
975         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
977         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
978         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
979         { } /* END */
980 };
981
982 /* HP Omnibook quirks */
983 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
984         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
985         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
986         { } /* END */
987 };
988
989 /*
990  * lowlevel functions
991  */
992
993 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
994 {
995         outw(value, chip->iobase + reg);
996 }
997
998 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
999 {
1000         return inw(chip->iobase + reg);
1001 }
1002
1003 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1004 {
1005         outb(value, chip->iobase + reg);
1006 }
1007
1008 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1009 {
1010         return inb(chip->iobase + reg);
1011 }
1012
1013 /*
1014  * access 16bit words to the code or data regions of the dsp's memory.
1015  * index addresses 16bit words.
1016  */
1017 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1018 {
1019         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1020         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1021         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1022 }
1023
1024 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1025 {
1026         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1027         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1028         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1029 }
1030
1031 static void snd_m3_assp_halt(struct snd_m3 *chip)
1032 {
1033         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1034         msleep(10);
1035         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1036 }
1037
1038 static void snd_m3_assp_continue(struct snd_m3 *chip)
1039 {
1040         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1041 }
1042
1043
1044 /*
1045  * This makes me sad. the maestro3 has lists
1046  * internally that must be packed.. 0 terminates,
1047  * apparently, or maybe all unused entries have
1048  * to be 0, the lists have static lengths set
1049  * by the binary code images.
1050  */
1051
1052 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1053 {
1054         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1055                           list->mem_addr + list->curlen,
1056                           val);
1057         return list->curlen++;
1058 }
1059
1060 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1061 {
1062         u16  val;
1063         int lastindex = list->curlen - 1;
1064
1065         if (index != lastindex) {
1066                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1067                                        list->mem_addr + lastindex);
1068                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1069                                   list->mem_addr + index,
1070                                   val);
1071         }
1072
1073         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1074                           list->mem_addr + lastindex,
1075                           0);
1076
1077         list->curlen--;
1078 }
1079
1080 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1081 {
1082         chip->timer_users++;
1083         if (chip->timer_users != 1) 
1084                 return;
1085
1086         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1087                           KDATA_TIMER_COUNT_RELOAD,
1088                           240);
1089
1090         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1091                           KDATA_TIMER_COUNT_CURRENT,
1092                           240);
1093
1094         snd_m3_outw(chip,
1095                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1096                     HOST_INT_CTRL);
1097 }
1098
1099 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1100 {
1101         chip->timer_users--;
1102         if (chip->timer_users > 0)  
1103                 return;
1104
1105         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1106                           KDATA_TIMER_COUNT_RELOAD,
1107                           0);
1108
1109         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1110                           KDATA_TIMER_COUNT_CURRENT,
1111                           0);
1112
1113         snd_m3_outw(chip,
1114                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1115                     HOST_INT_CTRL);
1116 }
1117
1118 /*
1119  * start/stop
1120  */
1121
1122 /* spinlock held! */
1123 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1124                             struct snd_pcm_substream *subs)
1125 {
1126         if (! s || ! subs)
1127                 return -EINVAL;
1128
1129         snd_m3_inc_timer_users(chip);
1130         switch (subs->stream) {
1131         case SNDRV_PCM_STREAM_PLAYBACK:
1132                 chip->dacs_active++;
1133                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1134                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1135                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1136                                   KDATA_MIXER_TASK_NUMBER,
1137                                   chip->dacs_active);
1138                 break;
1139         case SNDRV_PCM_STREAM_CAPTURE:
1140                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1141                                   KDATA_ADC1_REQUEST, 1);
1142                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1143                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1144                 break;
1145         }
1146         return 0;
1147 }
1148
1149 /* spinlock held! */
1150 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1151                            struct snd_pcm_substream *subs)
1152 {
1153         if (! s || ! subs)
1154                 return -EINVAL;
1155
1156         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1157                           s->inst.data + CDATA_INSTANCE_READY, 0);
1158         snd_m3_dec_timer_users(chip);
1159         switch (subs->stream) {
1160         case SNDRV_PCM_STREAM_PLAYBACK:
1161                 chip->dacs_active--;
1162                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1163                                   KDATA_MIXER_TASK_NUMBER, 
1164                                   chip->dacs_active);
1165                 break;
1166         case SNDRV_PCM_STREAM_CAPTURE:
1167                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1168                                   KDATA_ADC1_REQUEST, 0);
1169                 break;
1170         }
1171         return 0;
1172 }
1173
1174 static int
1175 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1176 {
1177         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1178         struct m3_dma *s = subs->runtime->private_data;
1179         int err = -EINVAL;
1180
1181         snd_assert(s != NULL, return -ENXIO);
1182
1183         spin_lock(&chip->reg_lock);
1184         switch (cmd) {
1185         case SNDRV_PCM_TRIGGER_START:
1186         case SNDRV_PCM_TRIGGER_RESUME:
1187                 if (s->running)
1188                         err = -EBUSY;
1189                 else {
1190                         s->running = 1;
1191                         err = snd_m3_pcm_start(chip, s, subs);
1192                 }
1193                 break;
1194         case SNDRV_PCM_TRIGGER_STOP:
1195         case SNDRV_PCM_TRIGGER_SUSPEND:
1196                 if (! s->running)
1197                         err = 0; /* should return error? */
1198                 else {
1199                         s->running = 0;
1200                         err = snd_m3_pcm_stop(chip, s, subs);
1201                 }
1202                 break;
1203         }
1204         spin_unlock(&chip->reg_lock);
1205         return err;
1206 }
1207
1208 /*
1209  * setup
1210  */
1211 static void 
1212 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1213 {
1214         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1215         struct snd_pcm_runtime *runtime = subs->runtime;
1216
1217         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1218                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1219                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1220         } else {
1221                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1222                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1223         }
1224         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1225         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1226
1227         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1228         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1229         s->hwptr = 0;
1230         s->count = 0;
1231
1232 #define LO(x) ((x) & 0xffff)
1233 #define HI(x) LO((x) >> 16)
1234
1235         /* host dma buffer pointers */
1236         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1237                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1238                           LO(s->buffer_addr));
1239
1240         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1241                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1242                           HI(s->buffer_addr));
1243
1244         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1246                           LO(s->buffer_addr + s->dma_size));
1247
1248         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1249                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1250                           HI(s->buffer_addr + s->dma_size));
1251
1252         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1254                           LO(s->buffer_addr));
1255
1256         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1257                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1258                           HI(s->buffer_addr));
1259 #undef LO
1260 #undef HI
1261
1262         /* dsp buffers */
1263
1264         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265                           s->inst.data + CDATA_IN_BUF_BEGIN,
1266                           dsp_in_buffer);
1267
1268         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1270                           dsp_in_buffer + (dsp_in_size / 2));
1271
1272         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273                           s->inst.data + CDATA_IN_BUF_HEAD,
1274                           dsp_in_buffer);
1275     
1276         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1277                           s->inst.data + CDATA_IN_BUF_TAIL,
1278                           dsp_in_buffer);
1279
1280         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1281                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1282                           dsp_out_buffer);
1283
1284         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1285                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1286                           dsp_out_buffer + (dsp_out_size / 2));
1287
1288         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1289                           s->inst.data + CDATA_OUT_BUF_HEAD,
1290                           dsp_out_buffer);
1291
1292         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1293                           s->inst.data + CDATA_OUT_BUF_TAIL,
1294                           dsp_out_buffer);
1295 }
1296
1297 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1298                               struct snd_pcm_runtime *runtime)
1299 {
1300         u32 freq;
1301
1302         /* 
1303          * put us in the lists if we're not already there
1304          */
1305         if (! s->in_lists) {
1306                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1307                                               s->inst.data >> DP_SHIFT_COUNT);
1308                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1309                                               s->inst.data >> DP_SHIFT_COUNT);
1310                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1311                                               s->inst.data >> DP_SHIFT_COUNT);
1312                 s->in_lists = 1;
1313         }
1314
1315         /* write to 'mono' word */
1316         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1317                           s->inst.data + SRC3_DIRECTION_OFFSET + 1, 
1318                           runtime->channels == 2 ? 0 : 1);
1319         /* write to '8bit' word */
1320         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1321                           s->inst.data + SRC3_DIRECTION_OFFSET + 2, 
1322                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1323
1324         /* set up dac/adc rate */
1325         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1326         if (freq) 
1327                 freq--;
1328
1329         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1330                           s->inst.data + CDATA_FREQUENCY,
1331                           freq);
1332 }
1333
1334
1335 static const struct play_vals {
1336         u16 addr, val;
1337 } pv[] = {
1338         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1339         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1340         {SRC3_DIRECTION_OFFSET, 0} ,
1341         /* +1, +2 are stereo/16 bit */
1342         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1343         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1344         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1345         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1346         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1347         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1348         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1349         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1350         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1351         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1352         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1353         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1354         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1355         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1356         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1357         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1358         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1359 };
1360
1361
1362 /* the mode passed should be already shifted and masked */
1363 static void
1364 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1365                       struct snd_pcm_substream *subs)
1366 {
1367         unsigned int i;
1368
1369         /*
1370          * some per client initializers
1371          */
1372
1373         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1375                           s->inst.data + 40 + 8);
1376
1377         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1378                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1379                           s->inst.code + MINISRC_COEF_LOC);
1380
1381         /* enable or disable low pass filter? */
1382         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1384                           subs->runtime->rate > 45000 ? 0xff : 0);
1385     
1386         /* tell it which way dma is going? */
1387         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1388                           s->inst.data + CDATA_DMA_CONTROL,
1389                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1390
1391         /*
1392          * set an armload of static initializers
1393          */
1394         for (i = 0; i < ARRAY_SIZE(pv); i++) 
1395                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1396                                   s->inst.data + pv[i].addr, pv[i].val);
1397 }
1398
1399 /*
1400  *    Native record driver 
1401  */
1402 static const struct rec_vals {
1403         u16 addr, val;
1404 } rv[] = {
1405         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1406         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1407         {SRC3_DIRECTION_OFFSET, 1} ,
1408         /* +1, +2 are stereo/16 bit */
1409         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1410         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1411         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1412         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1413         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1414         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1415         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1416         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1417         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1418         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1419         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1420         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1421         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1422         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1423         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1424         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1425         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1426         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1427         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1428 };
1429
1430 static void
1431 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1432 {
1433         unsigned int i;
1434
1435         /*
1436          * some per client initializers
1437          */
1438
1439         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1440                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1441                           s->inst.data + 40 + 8);
1442
1443         /* tell it which way dma is going? */
1444         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1445                           s->inst.data + CDATA_DMA_CONTROL,
1446                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 
1447                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1448
1449         /*
1450          * set an armload of static initializers
1451          */
1452         for (i = 0; i < ARRAY_SIZE(rv); i++) 
1453                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1454                                   s->inst.data + rv[i].addr, rv[i].val);
1455 }
1456
1457 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1458                                 struct snd_pcm_hw_params *hw_params)
1459 {
1460         struct m3_dma *s = substream->runtime->private_data;
1461         int err;
1462
1463         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1464                 return err;
1465         /* set buffer address */
1466         s->buffer_addr = substream->runtime->dma_addr;
1467         if (s->buffer_addr & 0x3) {
1468                 snd_printk(KERN_ERR "oh my, not aligned\n");
1469                 s->buffer_addr = s->buffer_addr & ~0x3;
1470         }
1471         return 0;
1472 }
1473
1474 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1475 {
1476         struct m3_dma *s;
1477         
1478         if (substream->runtime->private_data == NULL)
1479                 return 0;
1480         s = substream->runtime->private_data;
1481         snd_pcm_lib_free_pages(substream);
1482         s->buffer_addr = 0;
1483         return 0;
1484 }
1485
1486 static int
1487 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1488 {
1489         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1490         struct snd_pcm_runtime *runtime = subs->runtime;
1491         struct m3_dma *s = runtime->private_data;
1492
1493         snd_assert(s != NULL, return -ENXIO);
1494
1495         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1496             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1497                 return -EINVAL;
1498         if (runtime->rate > 48000 ||
1499             runtime->rate < 8000)
1500                 return -EINVAL;
1501
1502         spin_lock_irq(&chip->reg_lock);
1503
1504         snd_m3_pcm_setup1(chip, s, subs);
1505
1506         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1507                 snd_m3_playback_setup(chip, s, subs);
1508         else
1509                 snd_m3_capture_setup(chip, s, subs);
1510
1511         snd_m3_pcm_setup2(chip, s, runtime);
1512
1513         spin_unlock_irq(&chip->reg_lock);
1514
1515         return 0;
1516 }
1517
1518 /*
1519  * get current pointer
1520  */
1521 static unsigned int
1522 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1523 {
1524         u16 hi = 0, lo = 0;
1525         int retry = 10;
1526         u32 addr;
1527
1528         /*
1529          * try and get a valid answer
1530          */
1531         while (retry--) {
1532                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1533                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1534
1535                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1536                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1537
1538                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1539                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1540                         break;
1541         }
1542         addr = lo | ((u32)hi<<16);
1543         return (unsigned int)(addr - s->buffer_addr);
1544 }
1545
1546 static snd_pcm_uframes_t
1547 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1548 {
1549         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1550         unsigned int ptr;
1551         struct m3_dma *s = subs->runtime->private_data;
1552         snd_assert(s != NULL, return 0);
1553
1554         spin_lock(&chip->reg_lock);
1555         ptr = snd_m3_get_pointer(chip, s, subs);
1556         spin_unlock(&chip->reg_lock);
1557         return bytes_to_frames(subs->runtime, ptr);
1558 }
1559
1560
1561 /* update pointer */
1562 /* spinlock held! */
1563 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1564 {
1565         struct snd_pcm_substream *subs = s->substream;
1566         unsigned int hwptr;
1567         int diff;
1568
1569         if (! s->running)
1570                 return;
1571
1572         hwptr = snd_m3_get_pointer(chip, s, subs);
1573
1574         /* try to avoid expensive modulo divisions */
1575         if (hwptr >= s->dma_size)
1576                 hwptr %= s->dma_size;
1577
1578         diff = s->dma_size + hwptr - s->hwptr;
1579         if (diff >= s->dma_size)
1580                 diff %= s->dma_size;
1581
1582         s->hwptr = hwptr;
1583         s->count += diff;
1584
1585         if (s->count >= (signed)s->period_size) {
1586
1587                 if (s->count < 2 * (signed)s->period_size)
1588                         s->count -= (signed)s->period_size;
1589                 else
1590                         s->count %= s->period_size;
1591
1592                 spin_unlock(&chip->reg_lock);
1593                 snd_pcm_period_elapsed(subs);
1594                 spin_lock(&chip->reg_lock);
1595         }
1596 }
1597
1598 static void snd_m3_update_hw_volume(unsigned long private_data)
1599 {
1600         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1601         int x, val;
1602         unsigned long flags;
1603
1604         /* Figure out which volume control button was pushed,
1605            based on differences from the default register
1606            values. */
1607         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1608
1609         /* Reset the volume control registers. */
1610         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1611         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1612         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1613         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1614
1615         if (!chip->master_switch || !chip->master_volume)
1616                 return;
1617
1618         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1619         spin_lock_irqsave(&chip->ac97_lock, flags);
1620
1621         val = chip->ac97->regs[AC97_MASTER_VOL];
1622         switch (x) {
1623         case 0x88:
1624                 /* mute */
1625                 val ^= 0x8000;
1626                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1627                 outw(val, chip->iobase + CODEC_DATA);
1628                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1629                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1630                                &chip->master_switch->id);
1631                 break;
1632         case 0xaa:
1633                 /* volume up */
1634                 if ((val & 0x7f) > 0)
1635                         val--;
1636                 if ((val & 0x7f00) > 0)
1637                         val -= 0x0100;
1638                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1639                 outw(val, chip->iobase + CODEC_DATA);
1640                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1641                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1642                                &chip->master_volume->id);
1643                 break;
1644         case 0x66:
1645                 /* volume down */
1646                 if ((val & 0x7f) < 0x1f)
1647                         val++;
1648                 if ((val & 0x7f00) < 0x1f00)
1649                         val += 0x0100;
1650                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1651                 outw(val, chip->iobase + CODEC_DATA);
1652                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1653                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1654                                &chip->master_volume->id);
1655                 break;
1656         }
1657         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1658 }
1659
1660 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1661 {
1662         struct snd_m3 *chip = dev_id;
1663         u8 status;
1664         int i;
1665
1666         status = inb(chip->iobase + HOST_INT_STATUS);
1667
1668         if (status == 0xff)
1669                 return IRQ_NONE;
1670
1671         if (status & HV_INT_PENDING)
1672                 tasklet_hi_schedule(&chip->hwvol_tq);
1673
1674         /*
1675          * ack an assp int if its running
1676          * and has an int pending
1677          */
1678         if (status & ASSP_INT_PENDING) {
1679                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1680                 if (!(ctl & STOP_ASSP_CLOCK)) {
1681                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1682                         if (ctl & DSP2HOST_REQ_TIMER) {
1683                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1684                                 /* update adc/dac info if it was a timer int */
1685                                 spin_lock(&chip->reg_lock);
1686                                 for (i = 0; i < chip->num_substreams; i++) {
1687                                         struct m3_dma *s = &chip->substreams[i];
1688                                         if (s->running)
1689                                                 snd_m3_update_ptr(chip, s);
1690                                 }
1691                                 spin_unlock(&chip->reg_lock);
1692                         }
1693                 }
1694         }
1695
1696 #if 0 /* TODO: not supported yet */
1697         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1698                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1699 #endif
1700
1701         /* ack ints */
1702         outb(status, chip->iobase + HOST_INT_STATUS);
1703
1704         return IRQ_HANDLED;
1705 }
1706
1707
1708 /*
1709  */
1710
1711 static struct snd_pcm_hardware snd_m3_playback =
1712 {
1713         .info =                 (SNDRV_PCM_INFO_MMAP |
1714                                  SNDRV_PCM_INFO_INTERLEAVED |
1715                                  SNDRV_PCM_INFO_MMAP_VALID |
1716                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1717                                  /*SNDRV_PCM_INFO_PAUSE |*/
1718                                  SNDRV_PCM_INFO_RESUME),
1719         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1720         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1721         .rate_min =             8000,
1722         .rate_max =             48000,
1723         .channels_min =         1,
1724         .channels_max =         2,
1725         .buffer_bytes_max =     (512*1024),
1726         .period_bytes_min =     64,
1727         .period_bytes_max =     (512*1024),
1728         .periods_min =          1,
1729         .periods_max =          1024,
1730 };
1731
1732 static struct snd_pcm_hardware snd_m3_capture =
1733 {
1734         .info =                 (SNDRV_PCM_INFO_MMAP |
1735                                  SNDRV_PCM_INFO_INTERLEAVED |
1736                                  SNDRV_PCM_INFO_MMAP_VALID |
1737                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1738                                  /*SNDRV_PCM_INFO_PAUSE |*/
1739                                  SNDRV_PCM_INFO_RESUME),
1740         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1741         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1742         .rate_min =             8000,
1743         .rate_max =             48000,
1744         .channels_min =         1,
1745         .channels_max =         2,
1746         .buffer_bytes_max =     (512*1024),
1747         .period_bytes_min =     64,
1748         .period_bytes_max =     (512*1024),
1749         .periods_min =          1,
1750         .periods_max =          1024,
1751 };
1752
1753
1754 /*
1755  */
1756
1757 static int
1758 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1759 {
1760         int i;
1761         struct m3_dma *s;
1762
1763         spin_lock_irq(&chip->reg_lock);
1764         for (i = 0; i < chip->num_substreams; i++) {
1765                 s = &chip->substreams[i];
1766                 if (! s->opened)
1767                         goto __found;
1768         }
1769         spin_unlock_irq(&chip->reg_lock);
1770         return -ENOMEM;
1771 __found:
1772         s->opened = 1;
1773         s->running = 0;
1774         spin_unlock_irq(&chip->reg_lock);
1775
1776         subs->runtime->private_data = s;
1777         s->substream = subs;
1778
1779         /* set list owners */
1780         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1781                 s->index_list[0] = &chip->mixer_list;
1782         } else
1783                 s->index_list[0] = &chip->adc1_list;
1784         s->index_list[1] = &chip->msrc_list;
1785         s->index_list[2] = &chip->dma_list;
1786
1787         return 0;
1788 }
1789
1790 static void
1791 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1792 {
1793         struct m3_dma *s = subs->runtime->private_data;
1794
1795         if (s == NULL)
1796                 return; /* not opened properly */
1797
1798         spin_lock_irq(&chip->reg_lock);
1799         if (s->substream && s->running)
1800                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1801         if (s->in_lists) {
1802                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1803                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1804                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1805                 s->in_lists = 0;
1806         }
1807         s->running = 0;
1808         s->opened = 0;
1809         spin_unlock_irq(&chip->reg_lock);
1810 }
1811
1812 static int
1813 snd_m3_playback_open(struct snd_pcm_substream *subs)
1814 {
1815         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1816         struct snd_pcm_runtime *runtime = subs->runtime;
1817         int err;
1818
1819         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1820                 return err;
1821
1822         runtime->hw = snd_m3_playback;
1823
1824         return 0;
1825 }
1826
1827 static int
1828 snd_m3_playback_close(struct snd_pcm_substream *subs)
1829 {
1830         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1831
1832         snd_m3_substream_close(chip, subs);
1833         return 0;
1834 }
1835
1836 static int
1837 snd_m3_capture_open(struct snd_pcm_substream *subs)
1838 {
1839         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1840         struct snd_pcm_runtime *runtime = subs->runtime;
1841         int err;
1842
1843         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1844                 return err;
1845
1846         runtime->hw = snd_m3_capture;
1847
1848         return 0;
1849 }
1850
1851 static int
1852 snd_m3_capture_close(struct snd_pcm_substream *subs)
1853 {
1854         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1855
1856         snd_m3_substream_close(chip, subs);
1857         return 0;
1858 }
1859
1860 /*
1861  * create pcm instance
1862  */
1863
1864 static struct snd_pcm_ops snd_m3_playback_ops = {
1865         .open =         snd_m3_playback_open,
1866         .close =        snd_m3_playback_close,
1867         .ioctl =        snd_pcm_lib_ioctl,
1868         .hw_params =    snd_m3_pcm_hw_params,
1869         .hw_free =      snd_m3_pcm_hw_free,
1870         .prepare =      snd_m3_pcm_prepare,
1871         .trigger =      snd_m3_pcm_trigger,
1872         .pointer =      snd_m3_pcm_pointer,
1873 };
1874
1875 static struct snd_pcm_ops snd_m3_capture_ops = {
1876         .open =         snd_m3_capture_open,
1877         .close =        snd_m3_capture_close,
1878         .ioctl =        snd_pcm_lib_ioctl,
1879         .hw_params =    snd_m3_pcm_hw_params,
1880         .hw_free =      snd_m3_pcm_hw_free,
1881         .prepare =      snd_m3_pcm_prepare,
1882         .trigger =      snd_m3_pcm_trigger,
1883         .pointer =      snd_m3_pcm_pointer,
1884 };
1885
1886 static int __devinit
1887 snd_m3_pcm(struct snd_m3 * chip, int device)
1888 {
1889         struct snd_pcm *pcm;
1890         int err;
1891
1892         err = snd_pcm_new(chip->card, chip->card->driver, device,
1893                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1894         if (err < 0)
1895                 return err;
1896
1897         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1898         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1899
1900         pcm->private_data = chip;
1901         pcm->info_flags = 0;
1902         strcpy(pcm->name, chip->card->driver);
1903         chip->pcm = pcm;
1904         
1905         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1906                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1907
1908         return 0;
1909 }
1910
1911
1912 /*
1913  * ac97 interface
1914  */
1915
1916 /*
1917  * Wait for the ac97 serial bus to be free.
1918  * return nonzero if the bus is still busy.
1919  */
1920 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1921 {
1922         int i = 10000;
1923
1924         do {
1925                 if (! (snd_m3_inb(chip, 0x30) & 1))
1926                         return 0;
1927                 cpu_relax();
1928         } while (i-- > 0);
1929
1930         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1931         return 1;
1932 }
1933
1934 static unsigned short
1935 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1936 {
1937         struct snd_m3 *chip = ac97->private_data;
1938         unsigned long flags;
1939         unsigned short data = 0xffff;
1940
1941         if (snd_m3_ac97_wait(chip))
1942                 goto fail;
1943         spin_lock_irqsave(&chip->ac97_lock, flags);
1944         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1945         if (snd_m3_ac97_wait(chip))
1946                 goto fail_unlock;
1947         data = snd_m3_inw(chip, CODEC_DATA);
1948 fail_unlock:
1949         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1950 fail:
1951         return data;
1952 }
1953
1954 static void
1955 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1956 {
1957         struct snd_m3 *chip = ac97->private_data;
1958         unsigned long flags;
1959
1960         if (snd_m3_ac97_wait(chip))
1961                 return;
1962         spin_lock_irqsave(&chip->ac97_lock, flags);
1963         snd_m3_outw(chip, val, CODEC_DATA);
1964         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1965         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1966 }
1967
1968
1969 static void snd_m3_remote_codec_config(int io, int isremote)
1970 {
1971         isremote = isremote ? 1 : 0;
1972
1973         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1974              io + RING_BUS_CTRL_B);
1975         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1976              io + SDO_OUT_DEST_CTRL);
1977         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1978              io + SDO_IN_DEST_CTRL);
1979 }
1980
1981 /* 
1982  * hack, returns non zero on err 
1983  */
1984 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1985 {
1986         u16 ret;
1987
1988         if (snd_m3_ac97_wait(chip))
1989                 return 1;
1990
1991         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1992
1993         if (snd_m3_ac97_wait(chip))
1994                 return 1;
1995
1996         ret = snd_m3_inw(chip, 0x32);
1997
1998         return (ret == 0) || (ret == 0xffff);
1999 }
2000
2001 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2002 {
2003         u16 dir;
2004         int delay1 = 0, delay2 = 0, i;
2005         int io = chip->iobase;
2006
2007         if (chip->allegro_flag) {
2008                 /*
2009                  * the onboard codec on the allegro seems 
2010                  * to want to wait a very long time before
2011                  * coming back to life 
2012                  */
2013                 delay1 = 50;
2014                 delay2 = 800;
2015         } else {
2016                 /* maestro3 */
2017                 delay1 = 20;
2018                 delay2 = 500;
2019         }
2020
2021         for (i = 0; i < 5; i++) {
2022                 dir = inw(io + GPIO_DIRECTION);
2023                 if (!chip->irda_workaround)
2024                         dir |= 0x10; /* assuming pci bus master? */
2025
2026                 snd_m3_remote_codec_config(io, 0);
2027
2028                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2029                 udelay(20);
2030
2031                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2032                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2033                 outw(0, io + GPIO_DATA);
2034                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2035
2036                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2037
2038                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2039                 udelay(5);
2040                 /* ok, bring back the ac-link */
2041                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2042                 outw(~0, io + GPIO_MASK);
2043
2044                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2045
2046                 if (! snd_m3_try_read_vendor(chip))
2047                         break;
2048
2049                 delay1 += 10;
2050                 delay2 += 100;
2051
2052                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2053                            delay1, delay2);
2054         }
2055
2056 #if 0
2057         /* more gung-ho reset that doesn't
2058          * seem to work anywhere :)
2059          */
2060         tmp = inw(io + RING_BUS_CTRL_A);
2061         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2062         msleep(20);
2063         outw(tmp, io + RING_BUS_CTRL_A);
2064         msleep(50);
2065 #endif
2066 }
2067
2068 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2069 {
2070         struct snd_ac97_bus *pbus;
2071         struct snd_ac97_template ac97;
2072         struct snd_ctl_elem_id id;
2073         int err;
2074         static struct snd_ac97_bus_ops ops = {
2075                 .write = snd_m3_ac97_write,
2076                 .read = snd_m3_ac97_read,
2077         };
2078
2079         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2080                 return err;
2081         
2082         memset(&ac97, 0, sizeof(ac97));
2083         ac97.private_data = chip;
2084         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2085                 return err;
2086
2087         /* seems ac97 PCM needs initialization.. hack hack.. */
2088         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2089         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2090         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2091
2092         memset(&id, 0, sizeof(id));
2093         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2094         strcpy(id.name, "Master Playback Switch");
2095         chip->master_switch = snd_ctl_find_id(chip->card, &id);
2096         memset(&id, 0, sizeof(id));
2097         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2098         strcpy(id.name, "Master Playback Volume");
2099         chip->master_volume = snd_ctl_find_id(chip->card, &id);
2100
2101         return 0;
2102 }
2103
2104
2105 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2106
2107 /*
2108  * DSP Code images
2109  */
2110
2111 static const u16 assp_kernel_image[] = {
2112     0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, 
2113     0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 
2114     0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 
2115     0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, 
2116     0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, 
2117     0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, 
2118     0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, 
2119     0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, 
2120     0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, 
2121     0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, 
2122     0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, 
2123     0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, 
2124     0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, 
2125     0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, 
2126     0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, 
2127     0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, 
2128     0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, 
2129     0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, 
2130     0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, 
2131     0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, 
2132     0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, 
2133     0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, 
2134     0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, 
2135     0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, 
2136     0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, 
2137     0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, 
2138     0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, 
2139     0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, 
2140     0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, 
2141     0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, 
2142     0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, 
2143     0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, 
2144     0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, 
2145     0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, 
2146     0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 
2147     0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, 
2148     0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, 
2149     0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, 
2150     0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, 
2151     0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 
2152     0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, 
2153     0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, 
2154     0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, 
2155     0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, 
2156     0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, 
2157     0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 
2158     0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, 
2159     0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, 
2160     0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, 
2161     0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 
2162     0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, 
2163     0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, 
2164     0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, 
2165     0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, 
2166     0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, 
2167     0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, 
2168     0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, 
2169     0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, 
2170     0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 
2171     0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, 
2172     0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 
2173     0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, 
2174     0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, 
2175     0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, 
2176     0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, 
2177     0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, 
2178     0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, 
2179     0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, 
2180     0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, 
2181     0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, 
2182     0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, 
2183     0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, 
2184     0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, 
2185     0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, 
2186     0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, 
2187     0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, 
2188     0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, 
2189     0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, 
2190     0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, 
2191     0xBE3A, 
2192 };
2193
2194 /*
2195  * Mini sample rate converter code image
2196  * that is to be loaded at 0x400 on the DSP.
2197  */
2198 static const u16 assp_minisrc_image[] = {
2199
2200     0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, 
2201     0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, 
2202     0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, 
2203     0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, 
2204     0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, 
2205     0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, 
2206     0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, 
2207     0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, 
2208     0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, 
2209     0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, 
2210     0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, 
2211     0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, 
2212     0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, 
2213     0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, 
2214     0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, 
2215     0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, 
2216     0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, 
2217     0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, 
2218     0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, 
2219     0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, 
2220     0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, 
2221     0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, 
2222     0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, 
2223     0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, 
2224     0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, 
2225     0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, 
2226     0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, 
2227     0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, 
2228     0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, 
2229     0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, 
2230     0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, 
2231     0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
2232     0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
2233 };
2234
2235 static const struct firmware assp_kernel = {
2236         .data = (u8 *)assp_kernel_image,
2237         .size = sizeof assp_kernel_image
2238 };
2239 static const struct firmware assp_minisrc = {
2240         .data = (u8 *)assp_minisrc_image,
2241         .size = sizeof assp_minisrc_image
2242 };
2243
2244 #else /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2245
2246 #ifdef __LITTLE_ENDIAN
2247 static inline void snd_m3_convert_from_le(const struct firmware *fw) { }
2248 #else
2249 static void snd_m3_convert_from_le(const struct firmware *fw)
2250 {
2251         int i;
2252         u16 *data = (u16 *)fw->data;
2253
2254         for (i = 0; i < fw->size / 2; ++i)
2255                 le16_to_cpus(&data[i]);
2256 }
2257 #endif
2258
2259 #endif /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2260
2261
2262 /*
2263  * initialize ASSP
2264  */
2265
2266 #define MINISRC_LPF_LEN 10
2267 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2268         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2269         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2270 };
2271
2272 static void snd_m3_assp_init(struct snd_m3 *chip)
2273 {
2274         unsigned int i;
2275         u16 *data;
2276
2277         /* zero kernel data */
2278         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2279                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2280                                   KDATA_BASE_ADDR + i, 0);
2281
2282         /* zero mixer data? */
2283         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2284                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2285                                   KDATA_BASE_ADDR2 + i, 0);
2286
2287         /* init dma pointer */
2288         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2289                           KDATA_CURRENT_DMA,
2290                           KDATA_DMA_XFER0);
2291
2292         /* write kernel into code memory.. */
2293         data = (u16 *)chip->assp_kernel_image->data;
2294         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2295                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 
2296                                   REV_B_CODE_MEMORY_BEGIN + i, data[i]);
2297         }
2298
2299         /*
2300          * We only have this one client and we know that 0x400
2301          * is free in our kernel's mem map, so lets just
2302          * drop it there.  It seems that the minisrc doesn't
2303          * need vectors, so we won't bother with them..
2304          */
2305         data = (u16 *)chip->assp_minisrc_image->data;
2306         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2307                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 
2308                                   0x400 + i, data[i]);
2309         }
2310
2311         /*
2312          * write the coefficients for the low pass filter?
2313          */
2314         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2315                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2316                                   0x400 + MINISRC_COEF_LOC + i,
2317                                   minisrc_lpf[i]);
2318         }
2319
2320         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2321                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2322                           0x8000);
2323
2324         /*
2325          * the minisrc is the only thing on
2326          * our task list..
2327          */
2328         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2329                           KDATA_TASK0,
2330                           0x400);
2331
2332         /*
2333          * init the mixer number..
2334          */
2335
2336         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2337                           KDATA_MIXER_TASK_NUMBER,0);
2338
2339         /*
2340          * EXTREME KERNEL MASTER VOLUME
2341          */
2342         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2343                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2344         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2345                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2346
2347         chip->mixer_list.curlen = 0;
2348         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2349         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2350         chip->adc1_list.curlen = 0;
2351         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2352         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2353         chip->dma_list.curlen = 0;
2354         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2355         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2356         chip->msrc_list.curlen = 0;
2357         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2358         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2359 }
2360
2361
2362 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2363 {
2364         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + 
2365                                MINISRC_IN_BUFFER_SIZE / 2 +
2366                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2367         int address, i;
2368
2369         /*
2370          * the revb memory map has 0x1100 through 0x1c00
2371          * free.  
2372          */
2373
2374         /*
2375          * align instance address to 256 bytes so that its
2376          * shifted list address is aligned.
2377          * list address = (mem address >> 1) >> 7;
2378          */
2379         data_bytes = ALIGN(data_bytes, 256);
2380         address = 0x1100 + ((data_bytes/2) * index);
2381
2382         if ((address + (data_bytes/2)) >= 0x1c00) {
2383                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2384                            data_bytes, index, address);
2385                 return -ENOMEM;
2386         }
2387
2388         s->number = index;
2389         s->inst.code = 0x400;
2390         s->inst.data = address;
2391
2392         for (i = data_bytes / 2; i > 0; address++, i--) {
2393                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2394                                   address, 0);
2395         }
2396
2397         return 0;
2398 }
2399
2400
2401 /* 
2402  * this works for the reference board, have to find
2403  * out about others
2404  *
2405  * this needs more magic for 4 speaker, but..
2406  */
2407 static void
2408 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2409 {
2410         int io = chip->iobase;
2411         u16 gpo, polarity;
2412
2413         if (! chip->external_amp)
2414                 return;
2415
2416         polarity = enable ? 0 : 1;
2417         polarity = polarity << chip->amp_gpio;
2418         gpo = 1 << chip->amp_gpio;
2419
2420         outw(~gpo, io + GPIO_MASK);
2421
2422         outw(inw(io + GPIO_DIRECTION) | gpo,
2423              io + GPIO_DIRECTION);
2424
2425         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2426              io + GPIO_DATA);
2427
2428         outw(0xffff, io + GPIO_MASK);
2429 }
2430
2431 static int
2432 snd_m3_chip_init(struct snd_m3 *chip)
2433 {
2434         struct pci_dev *pcidev = chip->pci;
2435         unsigned long io = chip->iobase;
2436         u32 n;
2437         u16 w;
2438         u8 t; /* makes as much sense as 'n', no? */
2439
2440         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2441         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2442                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2443                DISABLE_LEGACY);
2444         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2445
2446         if (chip->is_omnibook) {
2447                 /*
2448                  * Volume buttons on some HP OmniBook laptops don't work
2449                  * correctly. This makes them work for the most part.
2450                  *
2451                  * Volume up and down buttons on the laptop side work.
2452                  * Fn+cursor_up (volme up) works.
2453                  * Fn+cursor_down (volume down) doesn't work.
2454                  * Fn+F7 (mute) works acts as volume up.
2455                  */
2456                 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2457                 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2458                 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2459                 outw(0xffff, io + GPIO_MASK);
2460         }
2461         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2462         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2463         n |= chip->hv_config;
2464         /* For some reason we must always use reduced debounce. */
2465         n |= REDUCED_DEBOUNCE;
2466         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2467         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2468
2469         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2470         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2471         n &= ~INT_CLK_SELECT;
2472         if (!chip->allegro_flag) {
2473                 n &= ~INT_CLK_MULT_ENABLE; 
2474                 n |= INT_CLK_SRC_NOT_PCI;
2475         }
2476         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2477         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2478
2479         if (chip->allegro_flag) {
2480                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2481                 n |= IN_CLK_12MHZ_SELECT;
2482                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2483         }
2484
2485         t = inb(chip->iobase + ASSP_CONTROL_A);
2486         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2487         t |= ASSP_CLK_49MHZ_SELECT;
2488         t |= ASSP_0_WS_ENABLE; 
2489         outb(t, chip->iobase + ASSP_CONTROL_A);
2490
2491         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2492         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); 
2493
2494         outb(0x00, io + HARDWARE_VOL_CTRL);
2495         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2496         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2497         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2498         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2499
2500         return 0;
2501
2502
2503 static void
2504 snd_m3_enable_ints(struct snd_m3 *chip)
2505 {
2506         unsigned long io = chip->iobase;
2507         unsigned short val;
2508
2509         /* TODO: MPU401 not supported yet */
2510         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2511         if (chip->hv_config & HV_CTRL_ENABLE)
2512                 val |= HV_INT_ENABLE;
2513         outw(val, io + HOST_INT_CTRL);
2514         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2515              io + ASSP_CONTROL_C);
2516 }
2517
2518
2519 /*
2520  */
2521
2522 static int snd_m3_free(struct snd_m3 *chip)
2523 {
2524         struct m3_dma *s;
2525         int i;
2526
2527         if (chip->substreams) {
2528                 spin_lock_irq(&chip->reg_lock);
2529                 for (i = 0; i < chip->num_substreams; i++) {
2530                         s = &chip->substreams[i];
2531                         /* check surviving pcms; this should not happen though.. */
2532                         if (s->substream && s->running)
2533                                 snd_m3_pcm_stop(chip, s, s->substream);
2534                 }
2535                 spin_unlock_irq(&chip->reg_lock);
2536                 kfree(chip->substreams);
2537         }
2538         if (chip->iobase) {
2539                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2540         }
2541
2542 #ifdef CONFIG_PM
2543         vfree(chip->suspend_mem);
2544 #endif
2545
2546         if (chip->irq >= 0) {
2547                 synchronize_irq(chip->irq);
2548                 free_irq(chip->irq, chip);
2549         }
2550
2551         if (chip->iobase)
2552                 pci_release_regions(chip->pci);
2553
2554 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2555         release_firmware(chip->assp_kernel_image);
2556         release_firmware(chip->assp_minisrc_image);
2557 #endif
2558
2559         pci_disable_device(chip->pci);
2560         kfree(chip);
2561         return 0;
2562 }
2563
2564
2565 /*
2566  * APM support
2567  */
2568 #ifdef CONFIG_PM
2569 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2570 {
2571         struct snd_card *card = pci_get_drvdata(pci);
2572         struct snd_m3 *chip = card->private_data;
2573         int i, index;
2574
2575         if (chip->suspend_mem == NULL)
2576                 return 0;
2577
2578         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2579         snd_pcm_suspend_all(chip->pcm);
2580         snd_ac97_suspend(chip->ac97);
2581
2582         msleep(10); /* give the assp a chance to idle.. */
2583
2584         snd_m3_assp_halt(chip);
2585
2586         /* save dsp image */
2587         index = 0;
2588         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2589                 chip->suspend_mem[index++] = 
2590                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2591         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2592                 chip->suspend_mem[index++] = 
2593                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2594
2595         pci_disable_device(pci);
2596         pci_save_state(pci);
2597         pci_set_power_state(pci, pci_choose_state(pci, state));
2598         return 0;
2599 }
2600
2601 static int m3_resume(struct pci_dev *pci)
2602 {
2603         struct snd_card *card = pci_get_drvdata(pci);
2604         struct snd_m3 *chip = card->private_data;
2605         int i, index;
2606
2607         if (chip->suspend_mem == NULL)
2608                 return 0;
2609
2610         pci_set_power_state(pci, PCI_D0);
2611         pci_restore_state(pci);
2612         if (pci_enable_device(pci) < 0) {
2613                 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2614                        "disabling device\n");
2615                 snd_card_disconnect(card);
2616                 return -EIO;
2617         }
2618         pci_set_master(pci);
2619
2620         /* first lets just bring everything back. .*/
2621         snd_m3_outw(chip, 0, 0x54);
2622         snd_m3_outw(chip, 0, 0x56);
2623
2624         snd_m3_chip_init(chip);
2625         snd_m3_assp_halt(chip);
2626         snd_m3_ac97_reset(chip);
2627
2628         /* restore dsp image */
2629         index = 0;
2630         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2631                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, 
2632                                   chip->suspend_mem[index++]);
2633         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2634                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, 
2635                                   chip->suspend_mem[index++]);
2636
2637         /* tell the dma engine to restart itself */
2638         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2639                           KDATA_DMA_ACTIVE, 0);
2640
2641         /* restore ac97 registers */
2642         snd_ac97_resume(chip->ac97);
2643
2644         snd_m3_assp_continue(chip);
2645         snd_m3_enable_ints(chip);
2646         snd_m3_amp_enable(chip, 1);
2647
2648         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2649         return 0;
2650 }
2651 #endif /* CONFIG_PM */
2652
2653
2654 /*
2655  */
2656
2657 static int snd_m3_dev_free(struct snd_device *device)
2658 {
2659         struct snd_m3 *chip = device->device_data;
2660         return snd_m3_free(chip);
2661 }
2662
2663 static int __devinit
2664 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2665               int enable_amp,
2666               int amp_gpio,
2667               struct snd_m3 **chip_ret)
2668 {
2669         struct snd_m3 *chip;
2670         int i, err;
2671         const struct snd_pci_quirk *quirk;
2672         static struct snd_device_ops ops = {
2673                 .dev_free =     snd_m3_dev_free,
2674         };
2675
2676         *chip_ret = NULL;
2677
2678         if (pci_enable_device(pci))
2679                 return -EIO;
2680
2681         /* check, if we can restrict PCI DMA transfers to 28 bits */
2682         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2683             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2684                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2685                 pci_disable_device(pci);
2686                 return -ENXIO;
2687         }
2688
2689         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2690         if (chip == NULL) {
2691                 pci_disable_device(pci);
2692                 return -ENOMEM;
2693         }
2694
2695         spin_lock_init(&chip->reg_lock);
2696         spin_lock_init(&chip->ac97_lock);
2697
2698         switch (pci->device) {
2699         case PCI_DEVICE_ID_ESS_ALLEGRO:
2700         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2701         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2702         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2703                 chip->allegro_flag = 1;
2704                 break;
2705         }
2706
2707         chip->card = card;
2708         chip->pci = pci;
2709         chip->irq = -1;
2710
2711         chip->external_amp = enable_amp;
2712         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2713                 chip->amp_gpio = amp_gpio;
2714         else {
2715                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2716                 if (quirk) {
2717                         snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2718                                     "for '%s'\n", quirk->name);
2719                         chip->amp_gpio = quirk->value;
2720                 } else if (chip->allegro_flag)
2721                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2722                 else /* presumably this is for all 'maestro3's.. */
2723                         chip->amp_gpio = GPO_EXT_AMP_M3;
2724         }
2725
2726         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2727         if (quirk) {
2728                 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2729                             "for '%s'\n", quirk->name);
2730                 chip->irda_workaround = 1;
2731         }
2732         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2733         if (quirk)
2734                 chip->hv_config = quirk->value;
2735         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2736                 chip->is_omnibook = 1;
2737
2738         chip->num_substreams = NR_DSPS;
2739         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2740                                    GFP_KERNEL);
2741         if (chip->substreams == NULL) {
2742                 kfree(chip);
2743                 pci_disable_device(pci);
2744                 return -ENOMEM;
2745         }
2746
2747 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2748         chip->assp_kernel_image = &assp_kernel;
2749 #else
2750         err = request_firmware(&chip->assp_kernel_image,
2751                                "ess/maestro3_assp_kernel.fw", &pci->dev);
2752         if (err < 0) {
2753                 snd_m3_free(chip);
2754                 return err;
2755         } else
2756                 snd_m3_convert_from_le(chip->assp_kernel_image);
2757 #endif
2758
2759 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2760         chip->assp_minisrc_image = &assp_minisrc;
2761 #else
2762         err = request_firmware(&chip->assp_minisrc_image,
2763                                "ess/maestro3_assp_minisrc.fw", &pci->dev);
2764         if (err < 0) {
2765                 snd_m3_free(chip);
2766                 return err;
2767         } else
2768                 snd_m3_convert_from_le(chip->assp_minisrc_image);
2769 #endif
2770
2771         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2772                 snd_m3_free(chip);
2773                 return err;
2774         }
2775         chip->iobase = pci_resource_start(pci, 0);
2776         
2777         /* just to be sure */
2778         pci_set_master(pci);
2779
2780         snd_m3_chip_init(chip);
2781         snd_m3_assp_halt(chip);
2782
2783         snd_m3_ac97_reset(chip);
2784
2785         snd_m3_amp_enable(chip, 1);
2786
2787         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2788
2789         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2790                         card->driver, chip)) {
2791                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2792                 snd_m3_free(chip);
2793                 return -ENOMEM;
2794         }
2795         chip->irq = pci->irq;
2796
2797 #ifdef CONFIG_PM
2798         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2799         if (chip->suspend_mem == NULL)
2800                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2801 #endif
2802
2803         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2804                 snd_m3_free(chip);
2805                 return err;
2806         }
2807
2808         if ((err = snd_m3_mixer(chip)) < 0)
2809                 return err;
2810
2811         for (i = 0; i < chip->num_substreams; i++) {
2812                 struct m3_dma *s = &chip->substreams[i];
2813                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2814                         return err;
2815         }
2816
2817         if ((err = snd_m3_pcm(chip, 0)) < 0)
2818                 return err;
2819     
2820         snd_m3_enable_ints(chip);
2821         snd_m3_assp_continue(chip);
2822
2823         snd_card_set_dev(card, &pci->dev);
2824
2825         *chip_ret = chip;
2826
2827         return 0; 
2828 }
2829
2830 /*
2831  */
2832 static int __devinit
2833 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2834 {
2835         static int dev;
2836         struct snd_card *card;
2837         struct snd_m3 *chip;
2838         int err;
2839
2840         /* don't pick up modems */
2841         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2842                 return -ENODEV;
2843
2844         if (dev >= SNDRV_CARDS)
2845                 return -ENODEV;
2846         if (!enable[dev]) {
2847                 dev++;
2848                 return -ENOENT;
2849         }
2850
2851         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2852         if (card == NULL)
2853                 return -ENOMEM;
2854
2855         switch (pci->device) {
2856         case PCI_DEVICE_ID_ESS_ALLEGRO:
2857         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2858                 strcpy(card->driver, "Allegro");
2859                 break;
2860         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2861         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2862                 strcpy(card->driver, "Canyon3D-2");
2863                 break;
2864         default:
2865                 strcpy(card->driver, "Maestro3");
2866                 break;
2867         }
2868
2869         if ((err = snd_m3_create(card, pci,
2870                                  external_amp[dev],
2871                                  amp_gpio[dev],
2872                                  &chip)) < 0) {
2873                 snd_card_free(card);
2874                 return err;
2875         }
2876         card->private_data = chip;
2877
2878         sprintf(card->shortname, "ESS %s PCI", card->driver);
2879         sprintf(card->longname, "%s at 0x%lx, irq %d",
2880                 card->shortname, chip->iobase, chip->irq);
2881
2882         if ((err = snd_card_register(card)) < 0) {
2883                 snd_card_free(card);
2884                 return err;
2885         }
2886
2887 #if 0 /* TODO: not supported yet */
2888         /* TODO enable MIDI IRQ and I/O */
2889         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2890                                   chip->iobase + MPU401_DATA_PORT,
2891                                   MPU401_INFO_INTEGRATED,
2892                                   chip->irq, 0, &chip->rmidi);
2893         if (err < 0)
2894                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2895 #endif
2896
2897         pci_set_drvdata(pci, card);
2898         dev++;
2899         return 0;
2900 }
2901
2902 static void __devexit snd_m3_remove(struct pci_dev *pci)
2903 {
2904         snd_card_free(pci_get_drvdata(pci));
2905         pci_set_drvdata(pci, NULL);
2906 }
2907
2908 static struct pci_driver driver = {
2909         .name = "Maestro3",
2910         .id_table = snd_m3_ids,
2911         .probe = snd_m3_probe,
2912         .remove = __devexit_p(snd_m3_remove),
2913 #ifdef CONFIG_PM
2914         .suspend = m3_suspend,
2915         .resume = m3_resume,
2916 #endif
2917 };
2918         
2919 static int __init alsa_card_m3_init(void)
2920 {
2921         return pci_register_driver(&driver);
2922 }
2923
2924 static void __exit alsa_card_m3_exit(void)
2925 {
2926         pci_unregister_driver(&driver);
2927 }
2928
2929 module_init(alsa_card_m3_init)
2930 module_exit(alsa_card_m3_exit)