Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[linux-2.6.git] / sound / pci / maestro3.c
1 /*
2  * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3  * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4  *                       Takashi Iwai <tiwai@suse.de>
5  *
6  * Most of the hardware init stuffs are based on maestro3 driver for
7  * OSS/Free by Zach Brown.  Many thanks to Zach!
8  *
9  *   This program is free software; you can redistribute it and/or modify
10  *   it under the terms of the GNU General Public License as published by
11  *   the Free Software Foundation; either version 2 of the License, or
12  *   (at your option) any later version.
13  *
14  *   This program is distributed in the hope that it will be useful,
15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *   GNU General Public License for more details.
18  *
19  *   You should have received a copy of the GNU General Public License
20  *   along with this program; if not, write to the Free Software
21  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  *
23  *
24  * ChangeLog:
25  * Aug. 27, 2001
26  *     - Fixed deadlock on capture
27  *     - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28  *
29  */
30  
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <sound/core.h>
45 #include <sound/info.h>
46 #include <sound/control.h>
47 #include <sound/pcm.h>
48 #include <sound/mpu401.h>
49 #include <sound/ac97_codec.h>
50 #include <sound/initval.h>
51 #include <asm/byteorder.h>
52
53 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54 MODULE_DESCRIPTION("ESS Maestro3 PCI");
55 MODULE_LICENSE("GPL");
56 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57                 "{ESS,ES1988},"
58                 "{ESS,Allegro PCI},"
59                 "{ESS,Allegro-1 PCI},"
60                 "{ESS,Canyon3D-2/LE PCI}}");
61 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
62 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
63
64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
66 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
67 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
68 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
69
70 module_param_array(index, int, NULL, 0444);
71 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
72 module_param_array(id, charp, NULL, 0444);
73 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
74 module_param_array(enable, bool, NULL, 0444);
75 MODULE_PARM_DESC(enable, "Enable this soundcard.");
76 module_param_array(external_amp, bool, NULL, 0444);
77 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
78 module_param_array(amp_gpio, int, NULL, 0444);
79 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
80
81 #define MAX_PLAYBACKS   2
82 #define MAX_CAPTURES    1
83 #define NR_DSPS         (MAX_PLAYBACKS + MAX_CAPTURES)
84
85
86 /*
87  * maestro3 registers
88  */
89
90 /* Allegro PCI configuration registers */
91 #define PCI_LEGACY_AUDIO_CTRL   0x40
92 #define SOUND_BLASTER_ENABLE    0x00000001
93 #define FM_SYNTHESIS_ENABLE     0x00000002
94 #define GAME_PORT_ENABLE        0x00000004
95 #define MPU401_IO_ENABLE        0x00000008
96 #define MPU401_IRQ_ENABLE       0x00000010
97 #define ALIAS_10BIT_IO          0x00000020
98 #define SB_DMA_MASK             0x000000C0
99 #define SB_DMA_0                0x00000040
100 #define SB_DMA_1                0x00000040
101 #define SB_DMA_R                0x00000080
102 #define SB_DMA_3                0x000000C0
103 #define SB_IRQ_MASK             0x00000700
104 #define SB_IRQ_5                0x00000000
105 #define SB_IRQ_7                0x00000100
106 #define SB_IRQ_9                0x00000200
107 #define SB_IRQ_10               0x00000300
108 #define MIDI_IRQ_MASK           0x00003800
109 #define SERIAL_IRQ_ENABLE       0x00004000
110 #define DISABLE_LEGACY          0x00008000
111
112 #define PCI_ALLEGRO_CONFIG      0x50
113 #define SB_ADDR_240             0x00000004
114 #define MPU_ADDR_MASK           0x00000018
115 #define MPU_ADDR_330            0x00000000
116 #define MPU_ADDR_300            0x00000008
117 #define MPU_ADDR_320            0x00000010
118 #define MPU_ADDR_340            0x00000018
119 #define USE_PCI_TIMING          0x00000040
120 #define POSTED_WRITE_ENABLE     0x00000080
121 #define DMA_POLICY_MASK         0x00000700
122 #define DMA_DDMA                0x00000000
123 #define DMA_TDMA                0x00000100
124 #define DMA_PCPCI               0x00000200
125 #define DMA_WBDMA16             0x00000400
126 #define DMA_WBDMA4              0x00000500
127 #define DMA_WBDMA2              0x00000600
128 #define DMA_WBDMA1              0x00000700
129 #define DMA_SAFE_GUARD          0x00000800
130 #define HI_PERF_GP_ENABLE       0x00001000
131 #define PIC_SNOOP_MODE_0        0x00002000
132 #define PIC_SNOOP_MODE_1        0x00004000
133 #define SOUNDBLASTER_IRQ_MASK   0x00008000
134 #define RING_IN_ENABLE          0x00010000
135 #define SPDIF_TEST_MODE         0x00020000
136 #define CLK_MULT_MODE_SELECT_2  0x00040000
137 #define EEPROM_WRITE_ENABLE     0x00080000
138 #define CODEC_DIR_IN            0x00100000
139 #define HV_BUTTON_FROM_GD       0x00200000
140 #define REDUCED_DEBOUNCE        0x00400000
141 #define HV_CTRL_ENABLE          0x00800000
142 #define SPDIF_ENABLE            0x01000000
143 #define CLK_DIV_SELECT          0x06000000
144 #define CLK_DIV_BY_48           0x00000000
145 #define CLK_DIV_BY_49           0x02000000
146 #define CLK_DIV_BY_50           0x04000000
147 #define CLK_DIV_RESERVED        0x06000000
148 #define PM_CTRL_ENABLE          0x08000000
149 #define CLK_MULT_MODE_SELECT    0x30000000
150 #define CLK_MULT_MODE_SHIFT     28
151 #define CLK_MULT_MODE_0         0x00000000
152 #define CLK_MULT_MODE_1         0x10000000
153 #define CLK_MULT_MODE_2         0x20000000
154 #define CLK_MULT_MODE_3         0x30000000
155 #define INT_CLK_SELECT          0x40000000
156 #define INT_CLK_MULT_RESET      0x80000000
157
158 /* M3 */
159 #define INT_CLK_SRC_NOT_PCI     0x00100000
160 #define INT_CLK_MULT_ENABLE     0x80000000
161
162 #define PCI_ACPI_CONTROL        0x54
163 #define PCI_ACPI_D0             0x00000000
164 #define PCI_ACPI_D1             0xB4F70000
165 #define PCI_ACPI_D2             0xB4F7B4F7
166
167 #define PCI_USER_CONFIG         0x58
168 #define EXT_PCI_MASTER_ENABLE   0x00000001
169 #define SPDIF_OUT_SELECT        0x00000002
170 #define TEST_PIN_DIR_CTRL       0x00000004
171 #define AC97_CODEC_TEST         0x00000020
172 #define TRI_STATE_BUFFER        0x00000080
173 #define IN_CLK_12MHZ_SELECT     0x00000100
174 #define MULTI_FUNC_DISABLE      0x00000200
175 #define EXT_MASTER_PAIR_SEL     0x00000400
176 #define PCI_MASTER_SUPPORT      0x00000800
177 #define STOP_CLOCK_ENABLE       0x00001000
178 #define EAPD_DRIVE_ENABLE       0x00002000
179 #define REQ_TRI_STATE_ENABLE    0x00004000
180 #define REQ_LOW_ENABLE          0x00008000
181 #define MIDI_1_ENABLE           0x00010000
182 #define MIDI_2_ENABLE           0x00020000
183 #define SB_AUDIO_SYNC           0x00040000
184 #define HV_CTRL_TEST            0x00100000
185 #define SOUNDBLASTER_TEST       0x00400000
186
187 #define PCI_USER_CONFIG_C       0x5C
188
189 #define PCI_DDMA_CTRL           0x60
190 #define DDMA_ENABLE             0x00000001
191
192
193 /* Allegro registers */
194 #define HOST_INT_CTRL           0x18
195 #define SB_INT_ENABLE           0x0001
196 #define MPU401_INT_ENABLE       0x0002
197 #define ASSP_INT_ENABLE         0x0010
198 #define RING_INT_ENABLE         0x0020
199 #define HV_INT_ENABLE           0x0040
200 #define CLKRUN_GEN_ENABLE       0x0100
201 #define HV_CTRL_TO_PME          0x0400
202 #define SOFTWARE_RESET_ENABLE   0x8000
203
204 /*
205  * should be using the above defines, probably.
206  */
207 #define REGB_ENABLE_RESET               0x01
208 #define REGB_STOP_CLOCK                 0x10
209
210 #define HOST_INT_STATUS         0x1A
211 #define SB_INT_PENDING          0x01
212 #define MPU401_INT_PENDING      0x02
213 #define ASSP_INT_PENDING        0x10
214 #define RING_INT_PENDING        0x20
215 #define HV_INT_PENDING          0x40
216
217 #define HARDWARE_VOL_CTRL       0x1B
218 #define SHADOW_MIX_REG_VOICE    0x1C
219 #define HW_VOL_COUNTER_VOICE    0x1D
220 #define SHADOW_MIX_REG_MASTER   0x1E
221 #define HW_VOL_COUNTER_MASTER   0x1F
222
223 #define CODEC_COMMAND           0x30
224 #define CODEC_READ_B            0x80
225
226 #define CODEC_STATUS            0x30
227 #define CODEC_BUSY_B            0x01
228
229 #define CODEC_DATA              0x32
230
231 #define RING_BUS_CTRL_A         0x36
232 #define RAC_PME_ENABLE          0x0100
233 #define RAC_SDFS_ENABLE         0x0200
234 #define LAC_PME_ENABLE          0x0400
235 #define LAC_SDFS_ENABLE         0x0800
236 #define SERIAL_AC_LINK_ENABLE   0x1000
237 #define IO_SRAM_ENABLE          0x2000
238 #define IIS_INPUT_ENABLE        0x8000
239
240 #define RING_BUS_CTRL_B         0x38
241 #define SECOND_CODEC_ID_MASK    0x0003
242 #define SPDIF_FUNC_ENABLE       0x0010
243 #define SECOND_AC_ENABLE        0x0020
244 #define SB_MODULE_INTF_ENABLE   0x0040
245 #define SSPE_ENABLE             0x0040
246 #define M3I_DOCK_ENABLE         0x0080
247
248 #define SDO_OUT_DEST_CTRL       0x3A
249 #define COMMAND_ADDR_OUT        0x0003
250 #define PCM_LR_OUT_LOCAL        0x0000
251 #define PCM_LR_OUT_REMOTE       0x0004
252 #define PCM_LR_OUT_MUTE         0x0008
253 #define PCM_LR_OUT_BOTH         0x000C
254 #define LINE1_DAC_OUT_LOCAL     0x0000
255 #define LINE1_DAC_OUT_REMOTE    0x0010
256 #define LINE1_DAC_OUT_MUTE      0x0020
257 #define LINE1_DAC_OUT_BOTH      0x0030
258 #define PCM_CLS_OUT_LOCAL       0x0000
259 #define PCM_CLS_OUT_REMOTE      0x0040
260 #define PCM_CLS_OUT_MUTE        0x0080
261 #define PCM_CLS_OUT_BOTH        0x00C0
262 #define PCM_RLF_OUT_LOCAL       0x0000
263 #define PCM_RLF_OUT_REMOTE      0x0100
264 #define PCM_RLF_OUT_MUTE        0x0200
265 #define PCM_RLF_OUT_BOTH        0x0300
266 #define LINE2_DAC_OUT_LOCAL     0x0000
267 #define LINE2_DAC_OUT_REMOTE    0x0400
268 #define LINE2_DAC_OUT_MUTE      0x0800
269 #define LINE2_DAC_OUT_BOTH      0x0C00
270 #define HANDSET_OUT_LOCAL       0x0000
271 #define HANDSET_OUT_REMOTE      0x1000
272 #define HANDSET_OUT_MUTE        0x2000
273 #define HANDSET_OUT_BOTH        0x3000
274 #define IO_CTRL_OUT_LOCAL       0x0000
275 #define IO_CTRL_OUT_REMOTE      0x4000
276 #define IO_CTRL_OUT_MUTE        0x8000
277 #define IO_CTRL_OUT_BOTH        0xC000
278
279 #define SDO_IN_DEST_CTRL        0x3C
280 #define STATUS_ADDR_IN          0x0003
281 #define PCM_LR_IN_LOCAL         0x0000
282 #define PCM_LR_IN_REMOTE        0x0004
283 #define PCM_LR_RESERVED         0x0008
284 #define PCM_LR_IN_BOTH          0x000C
285 #define LINE1_ADC_IN_LOCAL      0x0000
286 #define LINE1_ADC_IN_REMOTE     0x0010
287 #define LINE1_ADC_IN_MUTE       0x0020
288 #define MIC_ADC_IN_LOCAL        0x0000
289 #define MIC_ADC_IN_REMOTE       0x0040
290 #define MIC_ADC_IN_MUTE         0x0080
291 #define LINE2_DAC_IN_LOCAL      0x0000
292 #define LINE2_DAC_IN_REMOTE     0x0400
293 #define LINE2_DAC_IN_MUTE       0x0800
294 #define HANDSET_IN_LOCAL        0x0000
295 #define HANDSET_IN_REMOTE       0x1000
296 #define HANDSET_IN_MUTE         0x2000
297 #define IO_STATUS_IN_LOCAL      0x0000
298 #define IO_STATUS_IN_REMOTE     0x4000
299
300 #define SPDIF_IN_CTRL           0x3E
301 #define SPDIF_IN_ENABLE         0x0001
302
303 #define GPIO_DATA               0x60
304 #define GPIO_DATA_MASK          0x0FFF
305 #define GPIO_HV_STATUS          0x3000
306 #define GPIO_PME_STATUS         0x4000
307
308 #define GPIO_MASK               0x64
309 #define GPIO_DIRECTION          0x68
310 #define GPO_PRIMARY_AC97        0x0001
311 #define GPI_LINEOUT_SENSE       0x0004
312 #define GPO_SECONDARY_AC97      0x0008
313 #define GPI_VOL_DOWN            0x0010
314 #define GPI_VOL_UP              0x0020
315 #define GPI_IIS_CLK             0x0040
316 #define GPI_IIS_LRCLK           0x0080
317 #define GPI_IIS_DATA            0x0100
318 #define GPI_DOCKING_STATUS      0x0100
319 #define GPI_HEADPHONE_SENSE     0x0200
320 #define GPO_EXT_AMP_SHUTDOWN    0x1000
321
322 #define GPO_EXT_AMP_M3          1       /* default m3 amp */
323 #define GPO_EXT_AMP_ALLEGRO     8       /* default allegro amp */
324
325 /* M3 */
326 #define GPO_M3_EXT_AMP_SHUTDN   0x0002
327
328 #define ASSP_INDEX_PORT         0x80
329 #define ASSP_MEMORY_PORT        0x82
330 #define ASSP_DATA_PORT          0x84
331
332 #define MPU401_DATA_PORT        0x98
333 #define MPU401_STATUS_PORT      0x99
334
335 #define CLK_MULT_DATA_PORT      0x9C
336
337 #define ASSP_CONTROL_A          0xA2
338 #define ASSP_0_WS_ENABLE        0x01
339 #define ASSP_CTRL_A_RESERVED1   0x02
340 #define ASSP_CTRL_A_RESERVED2   0x04
341 #define ASSP_CLK_49MHZ_SELECT   0x08
342 #define FAST_PLU_ENABLE         0x10
343 #define ASSP_CTRL_A_RESERVED3   0x20
344 #define DSP_CLK_36MHZ_SELECT    0x40
345
346 #define ASSP_CONTROL_B          0xA4
347 #define RESET_ASSP              0x00
348 #define RUN_ASSP                0x01
349 #define ENABLE_ASSP_CLOCK       0x00
350 #define STOP_ASSP_CLOCK         0x10
351 #define RESET_TOGGLE            0x40
352
353 #define ASSP_CONTROL_C          0xA6
354 #define ASSP_HOST_INT_ENABLE    0x01
355 #define FM_ADDR_REMAP_DISABLE   0x02
356 #define HOST_WRITE_PORT_ENABLE  0x08
357
358 #define ASSP_HOST_INT_STATUS    0xAC
359 #define DSP2HOST_REQ_PIORECORD  0x01
360 #define DSP2HOST_REQ_I2SRATE    0x02
361 #define DSP2HOST_REQ_TIMER      0x04
362
363 /* AC97 registers */
364 /* XXX fix this crap up */
365 /*#define AC97_RESET              0x00*/
366
367 #define AC97_VOL_MUTE_B         0x8000
368 #define AC97_VOL_M              0x1F
369 #define AC97_LEFT_VOL_S         8
370
371 #define AC97_MASTER_VOL         0x02
372 #define AC97_LINE_LEVEL_VOL     0x04
373 #define AC97_MASTER_MONO_VOL    0x06
374 #define AC97_PC_BEEP_VOL        0x0A
375 #define AC97_PC_BEEP_VOL_M      0x0F
376 #define AC97_SROUND_MASTER_VOL  0x38
377 #define AC97_PC_BEEP_VOL_S      1
378
379 /*#define AC97_PHONE_VOL          0x0C
380 #define AC97_MIC_VOL            0x0E*/
381 #define AC97_MIC_20DB_ENABLE    0x40
382
383 /*#define AC97_LINEIN_VOL         0x10
384 #define AC97_CD_VOL             0x12
385 #define AC97_VIDEO_VOL          0x14
386 #define AC97_AUX_VOL            0x16*/
387 #define AC97_PCM_OUT_VOL        0x18
388 /*#define AC97_RECORD_SELECT      0x1A*/
389 #define AC97_RECORD_MIC         0x00
390 #define AC97_RECORD_CD          0x01
391 #define AC97_RECORD_VIDEO       0x02
392 #define AC97_RECORD_AUX         0x03
393 #define AC97_RECORD_MONO_MUX    0x02
394 #define AC97_RECORD_DIGITAL     0x03
395 #define AC97_RECORD_LINE        0x04
396 #define AC97_RECORD_STEREO      0x05
397 #define AC97_RECORD_MONO        0x06
398 #define AC97_RECORD_PHONE       0x07
399
400 /*#define AC97_RECORD_GAIN        0x1C*/
401 #define AC97_RECORD_VOL_M       0x0F
402
403 /*#define AC97_GENERAL_PURPOSE    0x20*/
404 #define AC97_POWER_DOWN_CTRL    0x26
405 #define AC97_ADC_READY          0x0001
406 #define AC97_DAC_READY          0x0002
407 #define AC97_ANALOG_READY       0x0004
408 #define AC97_VREF_ON            0x0008
409 #define AC97_PR0                0x0100
410 #define AC97_PR1                0x0200
411 #define AC97_PR2                0x0400
412 #define AC97_PR3                0x0800
413 #define AC97_PR4                0x1000
414
415 #define AC97_RESERVED1          0x28
416
417 #define AC97_VENDOR_TEST        0x5A
418
419 #define AC97_CLOCK_DELAY        0x5C
420 #define AC97_LINEOUT_MUX_SEL    0x0001
421 #define AC97_MONO_MUX_SEL       0x0002
422 #define AC97_CLOCK_DELAY_SEL    0x1F
423 #define AC97_DAC_CDS_SHIFT      6
424 #define AC97_ADC_CDS_SHIFT      11
425
426 #define AC97_MULTI_CHANNEL_SEL  0x74
427
428 /*#define AC97_VENDOR_ID1         0x7C
429 #define AC97_VENDOR_ID2         0x7E*/
430
431 /*
432  * ASSP control regs
433  */
434 #define DSP_PORT_TIMER_COUNT    0x06
435
436 #define DSP_PORT_MEMORY_INDEX   0x80
437
438 #define DSP_PORT_MEMORY_TYPE    0x82
439 #define MEMTYPE_INTERNAL_CODE   0x0002
440 #define MEMTYPE_INTERNAL_DATA   0x0003
441 #define MEMTYPE_MASK            0x0003
442
443 #define DSP_PORT_MEMORY_DATA    0x84
444
445 #define DSP_PORT_CONTROL_REG_A  0xA2
446 #define DSP_PORT_CONTROL_REG_B  0xA4
447 #define DSP_PORT_CONTROL_REG_C  0xA6
448
449 #define REV_A_CODE_MEMORY_BEGIN         0x0000
450 #define REV_A_CODE_MEMORY_END           0x0FFF
451 #define REV_A_CODE_MEMORY_UNIT_LENGTH   0x0040
452 #define REV_A_CODE_MEMORY_LENGTH        (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
453
454 #define REV_B_CODE_MEMORY_BEGIN         0x0000
455 #define REV_B_CODE_MEMORY_END           0x0BFF
456 #define REV_B_CODE_MEMORY_UNIT_LENGTH   0x0040
457 #define REV_B_CODE_MEMORY_LENGTH        (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
458
459 #define REV_A_DATA_MEMORY_BEGIN         0x1000
460 #define REV_A_DATA_MEMORY_END           0x2FFF
461 #define REV_A_DATA_MEMORY_UNIT_LENGTH   0x0080
462 #define REV_A_DATA_MEMORY_LENGTH        (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
463
464 #define REV_B_DATA_MEMORY_BEGIN         0x1000
465 #define REV_B_DATA_MEMORY_END           0x2BFF
466 #define REV_B_DATA_MEMORY_UNIT_LENGTH   0x0080
467 #define REV_B_DATA_MEMORY_LENGTH        (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
468
469
470 #define NUM_UNITS_KERNEL_CODE          16
471 #define NUM_UNITS_KERNEL_DATA           2
472
473 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
474 #define NUM_UNITS_KERNEL_DATA_WITH_HSP  5
475
476 /*
477  * Kernel data layout
478  */
479
480 #define DP_SHIFT_COUNT                  7
481
482 #define KDATA_BASE_ADDR                 0x1000
483 #define KDATA_BASE_ADDR2                0x1080
484
485 #define KDATA_TASK0                     (KDATA_BASE_ADDR + 0x0000)
486 #define KDATA_TASK1                     (KDATA_BASE_ADDR + 0x0001)
487 #define KDATA_TASK2                     (KDATA_BASE_ADDR + 0x0002)
488 #define KDATA_TASK3                     (KDATA_BASE_ADDR + 0x0003)
489 #define KDATA_TASK4                     (KDATA_BASE_ADDR + 0x0004)
490 #define KDATA_TASK5                     (KDATA_BASE_ADDR + 0x0005)
491 #define KDATA_TASK6                     (KDATA_BASE_ADDR + 0x0006)
492 #define KDATA_TASK7                     (KDATA_BASE_ADDR + 0x0007)
493 #define KDATA_TASK_ENDMARK              (KDATA_BASE_ADDR + 0x0008)
494
495 #define KDATA_CURRENT_TASK              (KDATA_BASE_ADDR + 0x0009)
496 #define KDATA_TASK_SWITCH               (KDATA_BASE_ADDR + 0x000A)
497
498 #define KDATA_INSTANCE0_POS3D           (KDATA_BASE_ADDR + 0x000B)
499 #define KDATA_INSTANCE1_POS3D           (KDATA_BASE_ADDR + 0x000C)
500 #define KDATA_INSTANCE2_POS3D           (KDATA_BASE_ADDR + 0x000D)
501 #define KDATA_INSTANCE3_POS3D           (KDATA_BASE_ADDR + 0x000E)
502 #define KDATA_INSTANCE4_POS3D           (KDATA_BASE_ADDR + 0x000F)
503 #define KDATA_INSTANCE5_POS3D           (KDATA_BASE_ADDR + 0x0010)
504 #define KDATA_INSTANCE6_POS3D           (KDATA_BASE_ADDR + 0x0011)
505 #define KDATA_INSTANCE7_POS3D           (KDATA_BASE_ADDR + 0x0012)
506 #define KDATA_INSTANCE8_POS3D           (KDATA_BASE_ADDR + 0x0013)
507 #define KDATA_INSTANCE_POS3D_ENDMARK    (KDATA_BASE_ADDR + 0x0014)
508
509 #define KDATA_INSTANCE0_SPKVIRT         (KDATA_BASE_ADDR + 0x0015)
510 #define KDATA_INSTANCE_SPKVIRT_ENDMARK  (KDATA_BASE_ADDR + 0x0016)
511
512 #define KDATA_INSTANCE0_SPDIF           (KDATA_BASE_ADDR + 0x0017)
513 #define KDATA_INSTANCE_SPDIF_ENDMARK    (KDATA_BASE_ADDR + 0x0018)
514
515 #define KDATA_INSTANCE0_MODEM           (KDATA_BASE_ADDR + 0x0019)
516 #define KDATA_INSTANCE_MODEM_ENDMARK    (KDATA_BASE_ADDR + 0x001A)
517
518 #define KDATA_INSTANCE0_SRC             (KDATA_BASE_ADDR + 0x001B)
519 #define KDATA_INSTANCE1_SRC             (KDATA_BASE_ADDR + 0x001C)
520 #define KDATA_INSTANCE_SRC_ENDMARK      (KDATA_BASE_ADDR + 0x001D)
521
522 #define KDATA_INSTANCE0_MINISRC         (KDATA_BASE_ADDR + 0x001E)
523 #define KDATA_INSTANCE1_MINISRC         (KDATA_BASE_ADDR + 0x001F)
524 #define KDATA_INSTANCE2_MINISRC         (KDATA_BASE_ADDR + 0x0020)
525 #define KDATA_INSTANCE3_MINISRC         (KDATA_BASE_ADDR + 0x0021)
526 #define KDATA_INSTANCE_MINISRC_ENDMARK  (KDATA_BASE_ADDR + 0x0022)
527
528 #define KDATA_INSTANCE0_CPYTHRU         (KDATA_BASE_ADDR + 0x0023)
529 #define KDATA_INSTANCE1_CPYTHRU         (KDATA_BASE_ADDR + 0x0024)
530 #define KDATA_INSTANCE_CPYTHRU_ENDMARK  (KDATA_BASE_ADDR + 0x0025)
531
532 #define KDATA_CURRENT_DMA               (KDATA_BASE_ADDR + 0x0026)
533 #define KDATA_DMA_SWITCH                (KDATA_BASE_ADDR + 0x0027)
534 #define KDATA_DMA_ACTIVE                (KDATA_BASE_ADDR + 0x0028)
535
536 #define KDATA_DMA_XFER0                 (KDATA_BASE_ADDR + 0x0029)
537 #define KDATA_DMA_XFER1                 (KDATA_BASE_ADDR + 0x002A)
538 #define KDATA_DMA_XFER2                 (KDATA_BASE_ADDR + 0x002B)
539 #define KDATA_DMA_XFER3                 (KDATA_BASE_ADDR + 0x002C)
540 #define KDATA_DMA_XFER4                 (KDATA_BASE_ADDR + 0x002D)
541 #define KDATA_DMA_XFER5                 (KDATA_BASE_ADDR + 0x002E)
542 #define KDATA_DMA_XFER6                 (KDATA_BASE_ADDR + 0x002F)
543 #define KDATA_DMA_XFER7                 (KDATA_BASE_ADDR + 0x0030)
544 #define KDATA_DMA_XFER8                 (KDATA_BASE_ADDR + 0x0031)
545 #define KDATA_DMA_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0032)
546
547 #define KDATA_I2S_SAMPLE_COUNT          (KDATA_BASE_ADDR + 0x0033)
548 #define KDATA_I2S_INT_METER             (KDATA_BASE_ADDR + 0x0034)
549 #define KDATA_I2S_ACTIVE                (KDATA_BASE_ADDR + 0x0035)
550
551 #define KDATA_TIMER_COUNT_RELOAD        (KDATA_BASE_ADDR + 0x0036)
552 #define KDATA_TIMER_COUNT_CURRENT       (KDATA_BASE_ADDR + 0x0037)
553
554 #define KDATA_HALT_SYNCH_CLIENT         (KDATA_BASE_ADDR + 0x0038)
555 #define KDATA_HALT_SYNCH_DMA            (KDATA_BASE_ADDR + 0x0039)
556 #define KDATA_HALT_ACKNOWLEDGE          (KDATA_BASE_ADDR + 0x003A)
557
558 #define KDATA_ADC1_XFER0                (KDATA_BASE_ADDR + 0x003B)
559 #define KDATA_ADC1_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x003C)
560 #define KDATA_ADC1_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x003D)
561 #define KDATA_ADC1_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x003E)
562 #define KDATA_ADC1_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x003F)
563 #define KDATA_ADC1_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0040)
564
565 #define KDATA_ADC2_XFER0                (KDATA_BASE_ADDR + 0x0041)
566 #define KDATA_ADC2_XFER_ENDMARK         (KDATA_BASE_ADDR + 0x0042)
567 #define KDATA_ADC2_LEFT_VOLUME                  (KDATA_BASE_ADDR + 0x0043)
568 #define KDATA_ADC2_RIGHT_VOLUME                 (KDATA_BASE_ADDR + 0x0044)
569 #define KDATA_ADC2_LEFT_SUR_VOL                 (KDATA_BASE_ADDR + 0x0045)
570 #define KDATA_ADC2_RIGHT_SUR_VOL                (KDATA_BASE_ADDR + 0x0046)
571
572 #define KDATA_CD_XFER0                                  (KDATA_BASE_ADDR + 0x0047)                                      
573 #define KDATA_CD_XFER_ENDMARK                   (KDATA_BASE_ADDR + 0x0048)
574 #define KDATA_CD_LEFT_VOLUME                    (KDATA_BASE_ADDR + 0x0049)
575 #define KDATA_CD_RIGHT_VOLUME                   (KDATA_BASE_ADDR + 0x004A)
576 #define KDATA_CD_LEFT_SUR_VOL                   (KDATA_BASE_ADDR + 0x004B)
577 #define KDATA_CD_RIGHT_SUR_VOL                  (KDATA_BASE_ADDR + 0x004C)
578
579 #define KDATA_MIC_XFER0                                 (KDATA_BASE_ADDR + 0x004D)
580 #define KDATA_MIC_XFER_ENDMARK                  (KDATA_BASE_ADDR + 0x004E)
581 #define KDATA_MIC_VOLUME                                (KDATA_BASE_ADDR + 0x004F)
582 #define KDATA_MIC_SUR_VOL                               (KDATA_BASE_ADDR + 0x0050)
583
584 #define KDATA_I2S_XFER0                 (KDATA_BASE_ADDR + 0x0051)
585 #define KDATA_I2S_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0052)
586
587 #define KDATA_CHI_XFER0                 (KDATA_BASE_ADDR + 0x0053)
588 #define KDATA_CHI_XFER_ENDMARK          (KDATA_BASE_ADDR + 0x0054)
589
590 #define KDATA_SPDIF_XFER                (KDATA_BASE_ADDR + 0x0055)
591 #define KDATA_SPDIF_CURRENT_FRAME       (KDATA_BASE_ADDR + 0x0056)
592 #define KDATA_SPDIF_FRAME0              (KDATA_BASE_ADDR + 0x0057)
593 #define KDATA_SPDIF_FRAME1              (KDATA_BASE_ADDR + 0x0058)
594 #define KDATA_SPDIF_FRAME2              (KDATA_BASE_ADDR + 0x0059)
595
596 #define KDATA_SPDIF_REQUEST             (KDATA_BASE_ADDR + 0x005A)
597 #define KDATA_SPDIF_TEMP                (KDATA_BASE_ADDR + 0x005B)
598
599 #define KDATA_SPDIFIN_XFER0             (KDATA_BASE_ADDR + 0x005C)
600 #define KDATA_SPDIFIN_XFER_ENDMARK      (KDATA_BASE_ADDR + 0x005D)
601 #define KDATA_SPDIFIN_INT_METER         (KDATA_BASE_ADDR + 0x005E)
602
603 #define KDATA_DSP_RESET_COUNT           (KDATA_BASE_ADDR + 0x005F)
604 #define KDATA_DEBUG_OUTPUT              (KDATA_BASE_ADDR + 0x0060)
605
606 #define KDATA_KERNEL_ISR_LIST           (KDATA_BASE_ADDR + 0x0061)
607
608 #define KDATA_KERNEL_ISR_CBSR1          (KDATA_BASE_ADDR + 0x0062)
609 #define KDATA_KERNEL_ISR_CBER1          (KDATA_BASE_ADDR + 0x0063)
610 #define KDATA_KERNEL_ISR_CBCR           (KDATA_BASE_ADDR + 0x0064)
611 #define KDATA_KERNEL_ISR_AR0            (KDATA_BASE_ADDR + 0x0065)
612 #define KDATA_KERNEL_ISR_AR1            (KDATA_BASE_ADDR + 0x0066)
613 #define KDATA_KERNEL_ISR_AR2            (KDATA_BASE_ADDR + 0x0067)
614 #define KDATA_KERNEL_ISR_AR3            (KDATA_BASE_ADDR + 0x0068)
615 #define KDATA_KERNEL_ISR_AR4            (KDATA_BASE_ADDR + 0x0069)
616 #define KDATA_KERNEL_ISR_AR5            (KDATA_BASE_ADDR + 0x006A)
617 #define KDATA_KERNEL_ISR_BRCR           (KDATA_BASE_ADDR + 0x006B)
618 #define KDATA_KERNEL_ISR_PASR           (KDATA_BASE_ADDR + 0x006C)
619 #define KDATA_KERNEL_ISR_PAER           (KDATA_BASE_ADDR + 0x006D)
620
621 #define KDATA_CLIENT_SCRATCH0           (KDATA_BASE_ADDR + 0x006E)
622 #define KDATA_CLIENT_SCRATCH1           (KDATA_BASE_ADDR + 0x006F)
623 #define KDATA_KERNEL_SCRATCH            (KDATA_BASE_ADDR + 0x0070)
624 #define KDATA_KERNEL_ISR_SCRATCH        (KDATA_BASE_ADDR + 0x0071)
625
626 #define KDATA_OUEUE_LEFT                (KDATA_BASE_ADDR + 0x0072)
627 #define KDATA_QUEUE_RIGHT               (KDATA_BASE_ADDR + 0x0073)
628
629 #define KDATA_ADC1_REQUEST              (KDATA_BASE_ADDR + 0x0074)
630 #define KDATA_ADC2_REQUEST              (KDATA_BASE_ADDR + 0x0075)
631 #define KDATA_CD_REQUEST                                (KDATA_BASE_ADDR + 0x0076)
632 #define KDATA_MIC_REQUEST                               (KDATA_BASE_ADDR + 0x0077)
633
634 #define KDATA_ADC1_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0078)
635 #define KDATA_ADC2_MIXER_REQUEST        (KDATA_BASE_ADDR + 0x0079)
636 #define KDATA_CD_MIXER_REQUEST                  (KDATA_BASE_ADDR + 0x007A)
637 #define KDATA_MIC_MIXER_REQUEST                 (KDATA_BASE_ADDR + 0x007B)
638 #define KDATA_MIC_SYNC_COUNTER                  (KDATA_BASE_ADDR + 0x007C)
639
640 /*
641  * second 'segment' (?) reserved for mixer
642  * buffers..
643  */
644
645 #define KDATA_MIXER_WORD0               (KDATA_BASE_ADDR2 + 0x0000)
646 #define KDATA_MIXER_WORD1               (KDATA_BASE_ADDR2 + 0x0001)
647 #define KDATA_MIXER_WORD2               (KDATA_BASE_ADDR2 + 0x0002)
648 #define KDATA_MIXER_WORD3               (KDATA_BASE_ADDR2 + 0x0003)
649 #define KDATA_MIXER_WORD4               (KDATA_BASE_ADDR2 + 0x0004)
650 #define KDATA_MIXER_WORD5               (KDATA_BASE_ADDR2 + 0x0005)
651 #define KDATA_MIXER_WORD6               (KDATA_BASE_ADDR2 + 0x0006)
652 #define KDATA_MIXER_WORD7               (KDATA_BASE_ADDR2 + 0x0007)
653 #define KDATA_MIXER_WORD8               (KDATA_BASE_ADDR2 + 0x0008)
654 #define KDATA_MIXER_WORD9               (KDATA_BASE_ADDR2 + 0x0009)
655 #define KDATA_MIXER_WORDA               (KDATA_BASE_ADDR2 + 0x000A)
656 #define KDATA_MIXER_WORDB               (KDATA_BASE_ADDR2 + 0x000B)
657 #define KDATA_MIXER_WORDC               (KDATA_BASE_ADDR2 + 0x000C)
658 #define KDATA_MIXER_WORDD               (KDATA_BASE_ADDR2 + 0x000D)
659 #define KDATA_MIXER_WORDE               (KDATA_BASE_ADDR2 + 0x000E)
660 #define KDATA_MIXER_WORDF               (KDATA_BASE_ADDR2 + 0x000F)
661
662 #define KDATA_MIXER_XFER0               (KDATA_BASE_ADDR2 + 0x0010)
663 #define KDATA_MIXER_XFER1               (KDATA_BASE_ADDR2 + 0x0011)
664 #define KDATA_MIXER_XFER2               (KDATA_BASE_ADDR2 + 0x0012)
665 #define KDATA_MIXER_XFER3               (KDATA_BASE_ADDR2 + 0x0013)
666 #define KDATA_MIXER_XFER4               (KDATA_BASE_ADDR2 + 0x0014)
667 #define KDATA_MIXER_XFER5               (KDATA_BASE_ADDR2 + 0x0015)
668 #define KDATA_MIXER_XFER6               (KDATA_BASE_ADDR2 + 0x0016)
669 #define KDATA_MIXER_XFER7               (KDATA_BASE_ADDR2 + 0x0017)
670 #define KDATA_MIXER_XFER8               (KDATA_BASE_ADDR2 + 0x0018)
671 #define KDATA_MIXER_XFER9               (KDATA_BASE_ADDR2 + 0x0019)
672 #define KDATA_MIXER_XFER_ENDMARK        (KDATA_BASE_ADDR2 + 0x001A)
673
674 #define KDATA_MIXER_TASK_NUMBER         (KDATA_BASE_ADDR2 + 0x001B)
675 #define KDATA_CURRENT_MIXER             (KDATA_BASE_ADDR2 + 0x001C)
676 #define KDATA_MIXER_ACTIVE              (KDATA_BASE_ADDR2 + 0x001D)
677 #define KDATA_MIXER_BANK_STATUS         (KDATA_BASE_ADDR2 + 0x001E)
678 #define KDATA_DAC_LEFT_VOLUME           (KDATA_BASE_ADDR2 + 0x001F)
679 #define KDATA_DAC_RIGHT_VOLUME          (KDATA_BASE_ADDR2 + 0x0020)
680
681 #define MAX_INSTANCE_MINISRC            (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
682 #define MAX_VIRTUAL_DMA_CHANNELS        (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
683 #define MAX_VIRTUAL_MIXER_CHANNELS      (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
684 #define MAX_VIRTUAL_ADC1_CHANNELS       (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
685
686 /*
687  * client data area offsets
688  */
689 #define CDATA_INSTANCE_READY            0x00
690
691 #define CDATA_HOST_SRC_ADDRL            0x01
692 #define CDATA_HOST_SRC_ADDRH            0x02
693 #define CDATA_HOST_SRC_END_PLUS_1L      0x03
694 #define CDATA_HOST_SRC_END_PLUS_1H      0x04
695 #define CDATA_HOST_SRC_CURRENTL         0x05
696 #define CDATA_HOST_SRC_CURRENTH         0x06
697
698 #define CDATA_IN_BUF_CONNECT            0x07
699 #define CDATA_OUT_BUF_CONNECT           0x08
700
701 #define CDATA_IN_BUF_BEGIN              0x09
702 #define CDATA_IN_BUF_END_PLUS_1         0x0A
703 #define CDATA_IN_BUF_HEAD               0x0B
704 #define CDATA_IN_BUF_TAIL               0x0C
705 #define CDATA_OUT_BUF_BEGIN             0x0D
706 #define CDATA_OUT_BUF_END_PLUS_1        0x0E
707 #define CDATA_OUT_BUF_HEAD              0x0F
708 #define CDATA_OUT_BUF_TAIL              0x10
709
710 #define CDATA_DMA_CONTROL               0x11
711 #define CDATA_RESERVED                  0x12
712
713 #define CDATA_FREQUENCY                 0x13
714 #define CDATA_LEFT_VOLUME               0x14
715 #define CDATA_RIGHT_VOLUME              0x15
716 #define CDATA_LEFT_SUR_VOL              0x16
717 #define CDATA_RIGHT_SUR_VOL             0x17
718
719 #define CDATA_HEADER_LEN                0x18
720
721 #define SRC3_DIRECTION_OFFSET           CDATA_HEADER_LEN
722 #define SRC3_MODE_OFFSET                (CDATA_HEADER_LEN + 1)
723 #define SRC3_WORD_LENGTH_OFFSET         (CDATA_HEADER_LEN + 2)
724 #define SRC3_PARAMETER_OFFSET           (CDATA_HEADER_LEN + 3)
725 #define SRC3_COEFF_ADDR_OFFSET          (CDATA_HEADER_LEN + 8)
726 #define SRC3_FILTAP_ADDR_OFFSET         (CDATA_HEADER_LEN + 10)
727 #define SRC3_TEMP_INBUF_ADDR_OFFSET     (CDATA_HEADER_LEN + 16)
728 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET    (CDATA_HEADER_LEN + 17)
729
730 #define MINISRC_IN_BUFFER_SIZE   ( 0x50 * 2 )
731 #define MINISRC_OUT_BUFFER_SIZE  ( 0x50 * 2 * 2)
732 #define MINISRC_TMP_BUFFER_SIZE  ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733 #define MINISRC_BIQUAD_STAGE    2
734 #define MINISRC_COEF_LOC          0x175
735
736 #define DMACONTROL_BLOCK_MASK           0x000F
737 #define  DMAC_BLOCK0_SELECTOR           0x0000
738 #define  DMAC_BLOCK1_SELECTOR           0x0001
739 #define  DMAC_BLOCK2_SELECTOR           0x0002
740 #define  DMAC_BLOCK3_SELECTOR           0x0003
741 #define  DMAC_BLOCK4_SELECTOR           0x0004
742 #define  DMAC_BLOCK5_SELECTOR           0x0005
743 #define  DMAC_BLOCK6_SELECTOR           0x0006
744 #define  DMAC_BLOCK7_SELECTOR           0x0007
745 #define  DMAC_BLOCK8_SELECTOR           0x0008
746 #define  DMAC_BLOCK9_SELECTOR           0x0009
747 #define  DMAC_BLOCKA_SELECTOR           0x000A
748 #define  DMAC_BLOCKB_SELECTOR           0x000B
749 #define  DMAC_BLOCKC_SELECTOR           0x000C
750 #define  DMAC_BLOCKD_SELECTOR           0x000D
751 #define  DMAC_BLOCKE_SELECTOR           0x000E
752 #define  DMAC_BLOCKF_SELECTOR           0x000F
753 #define DMACONTROL_PAGE_MASK            0x00F0
754 #define  DMAC_PAGE0_SELECTOR            0x0030
755 #define  DMAC_PAGE1_SELECTOR            0x0020
756 #define  DMAC_PAGE2_SELECTOR            0x0010
757 #define  DMAC_PAGE3_SELECTOR            0x0000
758 #define DMACONTROL_AUTOREPEAT           0x1000
759 #define DMACONTROL_STOPPED              0x2000
760 #define DMACONTROL_DIRECTION            0x0100
761
762 /*
763  * an arbitrary volume we set the internal
764  * volume settings to so that the ac97 volume
765  * range is a little less insane.  0x7fff is 
766  * max.
767  */
768 #define ARB_VOLUME ( 0x6800 )
769
770 /*
771  */
772
773 struct m3_list {
774         int curlen;
775         int mem_addr;
776         int max;
777 };
778
779 struct m3_dma {
780
781         int number;
782         struct snd_pcm_substream *substream;
783
784         struct assp_instance {
785                 unsigned short code, data;
786         } inst;
787
788         int running;
789         int opened;
790
791         unsigned long buffer_addr;
792         int dma_size;
793         int period_size;
794         unsigned int hwptr;
795         int count;
796
797         int index[3];
798         struct m3_list *index_list[3];
799
800         int in_lists;
801         
802         struct list_head list;
803
804 };
805     
806 struct snd_m3 {
807         
808         struct snd_card *card;
809
810         unsigned long iobase;
811
812         int irq;
813         unsigned int allegro_flag : 1;
814
815         struct snd_ac97 *ac97;
816
817         struct snd_pcm *pcm;
818
819         struct pci_dev *pci;
820
821         int dacs_active;
822         int timer_users;
823
824         struct m3_list  msrc_list;
825         struct m3_list  mixer_list;
826         struct m3_list  adc1_list;
827         struct m3_list  dma_list;
828
829         /* for storing reset state..*/
830         u8 reset_state;
831
832         int external_amp;
833         int amp_gpio;   /* gpio pin #  for external amp, -1 = default */
834         unsigned int hv_config;         /* hardware-volume config bits */
835         unsigned irda_workaround :1;    /* avoid to touch 0x10 on GPIO_DIRECTION
836                                            (e.g. for IrDA on Dell Inspirons) */
837         unsigned is_omnibook :1;        /* Do HP OmniBook GPIO magic? */
838
839         /* midi */
840         struct snd_rawmidi *rmidi;
841
842         /* pcm streams */
843         int num_substreams;
844         struct m3_dma *substreams;
845
846         spinlock_t reg_lock;
847         spinlock_t ac97_lock;
848
849         struct snd_kcontrol *master_switch;
850         struct snd_kcontrol *master_volume;
851         struct tasklet_struct hwvol_tq;
852
853 #ifdef CONFIG_PM
854         u16 *suspend_mem;
855 #endif
856
857         const struct firmware *assp_kernel_image;
858         const struct firmware *assp_minisrc_image;
859 };
860
861 /*
862  * pci ids
863  */
864 static struct pci_device_id snd_m3_ids[] = {
865         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
866          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
867         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
868          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
869         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
870          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
871         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
872          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
873         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
874          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
876          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
878          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879         {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
880          PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881         {0,},
882 };
883
884 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
885
886 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
887         SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
888         SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
889         SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
890         SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
891         { } /* END */
892 };
893
894 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
895         SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
896         SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
897         SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
898         { } /* END */
899 };
900
901 /* hardware volume quirks */
902 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
903         /* Allegro chips */
904         SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
905         SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
906         SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907         SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908         SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909         SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910         SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911         SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912         SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913         SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914         SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915         SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916         SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917         SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918         SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919         SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920         SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921         SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922         SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923         SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924         SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925         SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926         SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927         SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928         SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929         SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
930                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
931         SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
932                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933         SND_PCI_QUIRK(0x107B, 0x340A, NULL,
934                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935         SND_PCI_QUIRK(0x107B, 0x3450, NULL,
936                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937         SND_PCI_QUIRK(0x109F, 0x3134, NULL,
938                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939         SND_PCI_QUIRK(0x109F, 0x3161, NULL,
940                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941         SND_PCI_QUIRK(0x144D, 0x3280, NULL,
942                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943         SND_PCI_QUIRK(0x144D, 0x3281, NULL,
944                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945         SND_PCI_QUIRK(0x144D, 0xC002, NULL,
946                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947         SND_PCI_QUIRK(0x144D, 0xC003, NULL,
948                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949         SND_PCI_QUIRK(0x1509, 0x1740, NULL,
950                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951         SND_PCI_QUIRK(0x1610, 0x0010, NULL,
952                       HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953         SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
954         SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
955         SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
956         SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
957         SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
958         /* Maestro3 chips */
959         SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
960         SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
961         SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
962         SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
963         SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
964         SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
965         SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
966         SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
967         SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
968         SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
969         SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
970         SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
971         SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
972         SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
973         SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
974         SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975         SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976         { } /* END */
977 };
978
979 /* HP Omnibook quirks */
980 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
981         SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
982         SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
983         { } /* END */
984 };
985
986 /*
987  * lowlevel functions
988  */
989
990 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
991 {
992         outw(value, chip->iobase + reg);
993 }
994
995 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
996 {
997         return inw(chip->iobase + reg);
998 }
999
1000 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1001 {
1002         outb(value, chip->iobase + reg);
1003 }
1004
1005 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1006 {
1007         return inb(chip->iobase + reg);
1008 }
1009
1010 /*
1011  * access 16bit words to the code or data regions of the dsp's memory.
1012  * index addresses 16bit words.
1013  */
1014 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1015 {
1016         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1017         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1018         return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1019 }
1020
1021 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1022 {
1023         snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1024         snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1025         snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1026 }
1027
1028 static void snd_m3_assp_halt(struct snd_m3 *chip)
1029 {
1030         chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1031         msleep(10);
1032         snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1033 }
1034
1035 static void snd_m3_assp_continue(struct snd_m3 *chip)
1036 {
1037         snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1038 }
1039
1040
1041 /*
1042  * This makes me sad. the maestro3 has lists
1043  * internally that must be packed.. 0 terminates,
1044  * apparently, or maybe all unused entries have
1045  * to be 0, the lists have static lengths set
1046  * by the binary code images.
1047  */
1048
1049 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1050 {
1051         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1052                           list->mem_addr + list->curlen,
1053                           val);
1054         return list->curlen++;
1055 }
1056
1057 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1058 {
1059         u16  val;
1060         int lastindex = list->curlen - 1;
1061
1062         if (index != lastindex) {
1063                 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1064                                        list->mem_addr + lastindex);
1065                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1066                                   list->mem_addr + index,
1067                                   val);
1068         }
1069
1070         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1071                           list->mem_addr + lastindex,
1072                           0);
1073
1074         list->curlen--;
1075 }
1076
1077 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1078 {
1079         chip->timer_users++;
1080         if (chip->timer_users != 1) 
1081                 return;
1082
1083         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084                           KDATA_TIMER_COUNT_RELOAD,
1085                           240);
1086
1087         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088                           KDATA_TIMER_COUNT_CURRENT,
1089                           240);
1090
1091         snd_m3_outw(chip,
1092                     snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1093                     HOST_INT_CTRL);
1094 }
1095
1096 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1097 {
1098         chip->timer_users--;
1099         if (chip->timer_users > 0)  
1100                 return;
1101
1102         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1103                           KDATA_TIMER_COUNT_RELOAD,
1104                           0);
1105
1106         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107                           KDATA_TIMER_COUNT_CURRENT,
1108                           0);
1109
1110         snd_m3_outw(chip,
1111                     snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1112                     HOST_INT_CTRL);
1113 }
1114
1115 /*
1116  * start/stop
1117  */
1118
1119 /* spinlock held! */
1120 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1121                             struct snd_pcm_substream *subs)
1122 {
1123         if (! s || ! subs)
1124                 return -EINVAL;
1125
1126         snd_m3_inc_timer_users(chip);
1127         switch (subs->stream) {
1128         case SNDRV_PCM_STREAM_PLAYBACK:
1129                 chip->dacs_active++;
1130                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1131                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1132                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133                                   KDATA_MIXER_TASK_NUMBER,
1134                                   chip->dacs_active);
1135                 break;
1136         case SNDRV_PCM_STREAM_CAPTURE:
1137                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1138                                   KDATA_ADC1_REQUEST, 1);
1139                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140                                   s->inst.data + CDATA_INSTANCE_READY, 1);
1141                 break;
1142         }
1143         return 0;
1144 }
1145
1146 /* spinlock held! */
1147 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1148                            struct snd_pcm_substream *subs)
1149 {
1150         if (! s || ! subs)
1151                 return -EINVAL;
1152
1153         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1154                           s->inst.data + CDATA_INSTANCE_READY, 0);
1155         snd_m3_dec_timer_users(chip);
1156         switch (subs->stream) {
1157         case SNDRV_PCM_STREAM_PLAYBACK:
1158                 chip->dacs_active--;
1159                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1160                                   KDATA_MIXER_TASK_NUMBER, 
1161                                   chip->dacs_active);
1162                 break;
1163         case SNDRV_PCM_STREAM_CAPTURE:
1164                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1165                                   KDATA_ADC1_REQUEST, 0);
1166                 break;
1167         }
1168         return 0;
1169 }
1170
1171 static int
1172 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1173 {
1174         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1175         struct m3_dma *s = subs->runtime->private_data;
1176         int err = -EINVAL;
1177
1178         snd_assert(s != NULL, return -ENXIO);
1179
1180         spin_lock(&chip->reg_lock);
1181         switch (cmd) {
1182         case SNDRV_PCM_TRIGGER_START:
1183         case SNDRV_PCM_TRIGGER_RESUME:
1184                 if (s->running)
1185                         err = -EBUSY;
1186                 else {
1187                         s->running = 1;
1188                         err = snd_m3_pcm_start(chip, s, subs);
1189                 }
1190                 break;
1191         case SNDRV_PCM_TRIGGER_STOP:
1192         case SNDRV_PCM_TRIGGER_SUSPEND:
1193                 if (! s->running)
1194                         err = 0; /* should return error? */
1195                 else {
1196                         s->running = 0;
1197                         err = snd_m3_pcm_stop(chip, s, subs);
1198                 }
1199                 break;
1200         }
1201         spin_unlock(&chip->reg_lock);
1202         return err;
1203 }
1204
1205 /*
1206  * setup
1207  */
1208 static void 
1209 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1210 {
1211         int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1212         struct snd_pcm_runtime *runtime = subs->runtime;
1213
1214         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1215                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1216                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1217         } else {
1218                 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1219                 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1220         }
1221         dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1222         dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1223
1224         s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1225         s->period_size = frames_to_bytes(runtime, runtime->period_size);
1226         s->hwptr = 0;
1227         s->count = 0;
1228
1229 #define LO(x) ((x) & 0xffff)
1230 #define HI(x) LO((x) >> 16)
1231
1232         /* host dma buffer pointers */
1233         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1234                           s->inst.data + CDATA_HOST_SRC_ADDRL,
1235                           LO(s->buffer_addr));
1236
1237         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1238                           s->inst.data + CDATA_HOST_SRC_ADDRH,
1239                           HI(s->buffer_addr));
1240
1241         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1242                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1243                           LO(s->buffer_addr + s->dma_size));
1244
1245         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1246                           s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1247                           HI(s->buffer_addr + s->dma_size));
1248
1249         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1250                           s->inst.data + CDATA_HOST_SRC_CURRENTL,
1251                           LO(s->buffer_addr));
1252
1253         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1254                           s->inst.data + CDATA_HOST_SRC_CURRENTH,
1255                           HI(s->buffer_addr));
1256 #undef LO
1257 #undef HI
1258
1259         /* dsp buffers */
1260
1261         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1262                           s->inst.data + CDATA_IN_BUF_BEGIN,
1263                           dsp_in_buffer);
1264
1265         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1266                           s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1267                           dsp_in_buffer + (dsp_in_size / 2));
1268
1269         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1270                           s->inst.data + CDATA_IN_BUF_HEAD,
1271                           dsp_in_buffer);
1272     
1273         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1274                           s->inst.data + CDATA_IN_BUF_TAIL,
1275                           dsp_in_buffer);
1276
1277         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1278                           s->inst.data + CDATA_OUT_BUF_BEGIN,
1279                           dsp_out_buffer);
1280
1281         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1282                           s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1283                           dsp_out_buffer + (dsp_out_size / 2));
1284
1285         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1286                           s->inst.data + CDATA_OUT_BUF_HEAD,
1287                           dsp_out_buffer);
1288
1289         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1290                           s->inst.data + CDATA_OUT_BUF_TAIL,
1291                           dsp_out_buffer);
1292 }
1293
1294 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1295                               struct snd_pcm_runtime *runtime)
1296 {
1297         u32 freq;
1298
1299         /* 
1300          * put us in the lists if we're not already there
1301          */
1302         if (! s->in_lists) {
1303                 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1304                                               s->inst.data >> DP_SHIFT_COUNT);
1305                 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1306                                               s->inst.data >> DP_SHIFT_COUNT);
1307                 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1308                                               s->inst.data >> DP_SHIFT_COUNT);
1309                 s->in_lists = 1;
1310         }
1311
1312         /* write to 'mono' word */
1313         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1314                           s->inst.data + SRC3_DIRECTION_OFFSET + 1, 
1315                           runtime->channels == 2 ? 0 : 1);
1316         /* write to '8bit' word */
1317         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1318                           s->inst.data + SRC3_DIRECTION_OFFSET + 2, 
1319                           snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1320
1321         /* set up dac/adc rate */
1322         freq = ((runtime->rate << 15) + 24000 ) / 48000;
1323         if (freq) 
1324                 freq--;
1325
1326         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1327                           s->inst.data + CDATA_FREQUENCY,
1328                           freq);
1329 }
1330
1331
1332 static const struct play_vals {
1333         u16 addr, val;
1334 } pv[] = {
1335         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1336         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1337         {SRC3_DIRECTION_OFFSET, 0} ,
1338         /* +1, +2 are stereo/16 bit */
1339         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1340         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1341         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1342         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1343         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1344         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1345         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1346         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1347         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1348         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1349         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1350         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1351         {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1352         {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1353         {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1354         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1355         {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1356 };
1357
1358
1359 /* the mode passed should be already shifted and masked */
1360 static void
1361 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1362                       struct snd_pcm_substream *subs)
1363 {
1364         unsigned int i;
1365
1366         /*
1367          * some per client initializers
1368          */
1369
1370         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1371                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1372                           s->inst.data + 40 + 8);
1373
1374         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1375                           s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1376                           s->inst.code + MINISRC_COEF_LOC);
1377
1378         /* enable or disable low pass filter? */
1379         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1380                           s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1381                           subs->runtime->rate > 45000 ? 0xff : 0);
1382     
1383         /* tell it which way dma is going? */
1384         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1385                           s->inst.data + CDATA_DMA_CONTROL,
1386                           DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1387
1388         /*
1389          * set an armload of static initializers
1390          */
1391         for (i = 0; i < ARRAY_SIZE(pv); i++) 
1392                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1393                                   s->inst.data + pv[i].addr, pv[i].val);
1394 }
1395
1396 /*
1397  *    Native record driver 
1398  */
1399 static const struct rec_vals {
1400         u16 addr, val;
1401 } rv[] = {
1402         {CDATA_LEFT_VOLUME, ARB_VOLUME},
1403         {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1404         {SRC3_DIRECTION_OFFSET, 1} ,
1405         /* +1, +2 are stereo/16 bit */
1406         {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1407         {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1408         {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1409         {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1410         {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1411         {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1412         {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1413         {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1414         {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1415         {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1416         {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1417         {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1418         {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1419         {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1420         {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1421         {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1422         {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1423         {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1424         {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1425 };
1426
1427 static void
1428 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1429 {
1430         unsigned int i;
1431
1432         /*
1433          * some per client initializers
1434          */
1435
1436         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1437                           s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1438                           s->inst.data + 40 + 8);
1439
1440         /* tell it which way dma is going? */
1441         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1442                           s->inst.data + CDATA_DMA_CONTROL,
1443                           DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 
1444                           DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1445
1446         /*
1447          * set an armload of static initializers
1448          */
1449         for (i = 0; i < ARRAY_SIZE(rv); i++) 
1450                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1451                                   s->inst.data + rv[i].addr, rv[i].val);
1452 }
1453
1454 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1455                                 struct snd_pcm_hw_params *hw_params)
1456 {
1457         struct m3_dma *s = substream->runtime->private_data;
1458         int err;
1459
1460         if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1461                 return err;
1462         /* set buffer address */
1463         s->buffer_addr = substream->runtime->dma_addr;
1464         if (s->buffer_addr & 0x3) {
1465                 snd_printk(KERN_ERR "oh my, not aligned\n");
1466                 s->buffer_addr = s->buffer_addr & ~0x3;
1467         }
1468         return 0;
1469 }
1470
1471 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1472 {
1473         struct m3_dma *s;
1474         
1475         if (substream->runtime->private_data == NULL)
1476                 return 0;
1477         s = substream->runtime->private_data;
1478         snd_pcm_lib_free_pages(substream);
1479         s->buffer_addr = 0;
1480         return 0;
1481 }
1482
1483 static int
1484 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1485 {
1486         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1487         struct snd_pcm_runtime *runtime = subs->runtime;
1488         struct m3_dma *s = runtime->private_data;
1489
1490         snd_assert(s != NULL, return -ENXIO);
1491
1492         if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1493             runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1494                 return -EINVAL;
1495         if (runtime->rate > 48000 ||
1496             runtime->rate < 8000)
1497                 return -EINVAL;
1498
1499         spin_lock_irq(&chip->reg_lock);
1500
1501         snd_m3_pcm_setup1(chip, s, subs);
1502
1503         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1504                 snd_m3_playback_setup(chip, s, subs);
1505         else
1506                 snd_m3_capture_setup(chip, s, subs);
1507
1508         snd_m3_pcm_setup2(chip, s, runtime);
1509
1510         spin_unlock_irq(&chip->reg_lock);
1511
1512         return 0;
1513 }
1514
1515 /*
1516  * get current pointer
1517  */
1518 static unsigned int
1519 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1520 {
1521         u16 hi = 0, lo = 0;
1522         int retry = 10;
1523         u32 addr;
1524
1525         /*
1526          * try and get a valid answer
1527          */
1528         while (retry--) {
1529                 hi =  snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1530                                        s->inst.data + CDATA_HOST_SRC_CURRENTH);
1531
1532                 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1533                                       s->inst.data + CDATA_HOST_SRC_CURRENTL);
1534
1535                 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1536                                            s->inst.data + CDATA_HOST_SRC_CURRENTH))
1537                         break;
1538         }
1539         addr = lo | ((u32)hi<<16);
1540         return (unsigned int)(addr - s->buffer_addr);
1541 }
1542
1543 static snd_pcm_uframes_t
1544 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1545 {
1546         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1547         unsigned int ptr;
1548         struct m3_dma *s = subs->runtime->private_data;
1549         snd_assert(s != NULL, return 0);
1550
1551         spin_lock(&chip->reg_lock);
1552         ptr = snd_m3_get_pointer(chip, s, subs);
1553         spin_unlock(&chip->reg_lock);
1554         return bytes_to_frames(subs->runtime, ptr);
1555 }
1556
1557
1558 /* update pointer */
1559 /* spinlock held! */
1560 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1561 {
1562         struct snd_pcm_substream *subs = s->substream;
1563         unsigned int hwptr;
1564         int diff;
1565
1566         if (! s->running)
1567                 return;
1568
1569         hwptr = snd_m3_get_pointer(chip, s, subs);
1570
1571         /* try to avoid expensive modulo divisions */
1572         if (hwptr >= s->dma_size)
1573                 hwptr %= s->dma_size;
1574
1575         diff = s->dma_size + hwptr - s->hwptr;
1576         if (diff >= s->dma_size)
1577                 diff %= s->dma_size;
1578
1579         s->hwptr = hwptr;
1580         s->count += diff;
1581
1582         if (s->count >= (signed)s->period_size) {
1583
1584                 if (s->count < 2 * (signed)s->period_size)
1585                         s->count -= (signed)s->period_size;
1586                 else
1587                         s->count %= s->period_size;
1588
1589                 spin_unlock(&chip->reg_lock);
1590                 snd_pcm_period_elapsed(subs);
1591                 spin_lock(&chip->reg_lock);
1592         }
1593 }
1594
1595 static void snd_m3_update_hw_volume(unsigned long private_data)
1596 {
1597         struct snd_m3 *chip = (struct snd_m3 *) private_data;
1598         int x, val;
1599         unsigned long flags;
1600
1601         /* Figure out which volume control button was pushed,
1602            based on differences from the default register
1603            values. */
1604         x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1605
1606         /* Reset the volume control registers. */
1607         outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1608         outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1609         outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1610         outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1611
1612         if (!chip->master_switch || !chip->master_volume)
1613                 return;
1614
1615         /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1616         spin_lock_irqsave(&chip->ac97_lock, flags);
1617
1618         val = chip->ac97->regs[AC97_MASTER_VOL];
1619         switch (x) {
1620         case 0x88:
1621                 /* mute */
1622                 val ^= 0x8000;
1623                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1624                 outw(val, chip->iobase + CODEC_DATA);
1625                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1626                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1627                                &chip->master_switch->id);
1628                 break;
1629         case 0xaa:
1630                 /* volume up */
1631                 if ((val & 0x7f) > 0)
1632                         val--;
1633                 if ((val & 0x7f00) > 0)
1634                         val -= 0x0100;
1635                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1636                 outw(val, chip->iobase + CODEC_DATA);
1637                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1638                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1639                                &chip->master_volume->id);
1640                 break;
1641         case 0x66:
1642                 /* volume down */
1643                 if ((val & 0x7f) < 0x1f)
1644                         val++;
1645                 if ((val & 0x7f00) < 0x1f00)
1646                         val += 0x0100;
1647                 chip->ac97->regs[AC97_MASTER_VOL] = val;
1648                 outw(val, chip->iobase + CODEC_DATA);
1649                 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1650                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1651                                &chip->master_volume->id);
1652                 break;
1653         }
1654         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1655 }
1656
1657 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1658 {
1659         struct snd_m3 *chip = dev_id;
1660         u8 status;
1661         int i;
1662
1663         status = inb(chip->iobase + HOST_INT_STATUS);
1664
1665         if (status == 0xff)
1666                 return IRQ_NONE;
1667
1668         if (status & HV_INT_PENDING)
1669                 tasklet_hi_schedule(&chip->hwvol_tq);
1670
1671         /*
1672          * ack an assp int if its running
1673          * and has an int pending
1674          */
1675         if (status & ASSP_INT_PENDING) {
1676                 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1677                 if (!(ctl & STOP_ASSP_CLOCK)) {
1678                         ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1679                         if (ctl & DSP2HOST_REQ_TIMER) {
1680                                 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1681                                 /* update adc/dac info if it was a timer int */
1682                                 spin_lock(&chip->reg_lock);
1683                                 for (i = 0; i < chip->num_substreams; i++) {
1684                                         struct m3_dma *s = &chip->substreams[i];
1685                                         if (s->running)
1686                                                 snd_m3_update_ptr(chip, s);
1687                                 }
1688                                 spin_unlock(&chip->reg_lock);
1689                         }
1690                 }
1691         }
1692
1693 #if 0 /* TODO: not supported yet */
1694         if ((status & MPU401_INT_PENDING) && chip->rmidi)
1695                 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1696 #endif
1697
1698         /* ack ints */
1699         outb(status, chip->iobase + HOST_INT_STATUS);
1700
1701         return IRQ_HANDLED;
1702 }
1703
1704
1705 /*
1706  */
1707
1708 static struct snd_pcm_hardware snd_m3_playback =
1709 {
1710         .info =                 (SNDRV_PCM_INFO_MMAP |
1711                                  SNDRV_PCM_INFO_INTERLEAVED |
1712                                  SNDRV_PCM_INFO_MMAP_VALID |
1713                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1714                                  /*SNDRV_PCM_INFO_PAUSE |*/
1715                                  SNDRV_PCM_INFO_RESUME),
1716         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1717         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1718         .rate_min =             8000,
1719         .rate_max =             48000,
1720         .channels_min =         1,
1721         .channels_max =         2,
1722         .buffer_bytes_max =     (512*1024),
1723         .period_bytes_min =     64,
1724         .period_bytes_max =     (512*1024),
1725         .periods_min =          1,
1726         .periods_max =          1024,
1727 };
1728
1729 static struct snd_pcm_hardware snd_m3_capture =
1730 {
1731         .info =                 (SNDRV_PCM_INFO_MMAP |
1732                                  SNDRV_PCM_INFO_INTERLEAVED |
1733                                  SNDRV_PCM_INFO_MMAP_VALID |
1734                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1735                                  /*SNDRV_PCM_INFO_PAUSE |*/
1736                                  SNDRV_PCM_INFO_RESUME),
1737         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1738         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1739         .rate_min =             8000,
1740         .rate_max =             48000,
1741         .channels_min =         1,
1742         .channels_max =         2,
1743         .buffer_bytes_max =     (512*1024),
1744         .period_bytes_min =     64,
1745         .period_bytes_max =     (512*1024),
1746         .periods_min =          1,
1747         .periods_max =          1024,
1748 };
1749
1750
1751 /*
1752  */
1753
1754 static int
1755 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1756 {
1757         int i;
1758         struct m3_dma *s;
1759
1760         spin_lock_irq(&chip->reg_lock);
1761         for (i = 0; i < chip->num_substreams; i++) {
1762                 s = &chip->substreams[i];
1763                 if (! s->opened)
1764                         goto __found;
1765         }
1766         spin_unlock_irq(&chip->reg_lock);
1767         return -ENOMEM;
1768 __found:
1769         s->opened = 1;
1770         s->running = 0;
1771         spin_unlock_irq(&chip->reg_lock);
1772
1773         subs->runtime->private_data = s;
1774         s->substream = subs;
1775
1776         /* set list owners */
1777         if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1778                 s->index_list[0] = &chip->mixer_list;
1779         } else
1780                 s->index_list[0] = &chip->adc1_list;
1781         s->index_list[1] = &chip->msrc_list;
1782         s->index_list[2] = &chip->dma_list;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1789 {
1790         struct m3_dma *s = subs->runtime->private_data;
1791
1792         if (s == NULL)
1793                 return; /* not opened properly */
1794
1795         spin_lock_irq(&chip->reg_lock);
1796         if (s->substream && s->running)
1797                 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1798         if (s->in_lists) {
1799                 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1800                 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1801                 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1802                 s->in_lists = 0;
1803         }
1804         s->running = 0;
1805         s->opened = 0;
1806         spin_unlock_irq(&chip->reg_lock);
1807 }
1808
1809 static int
1810 snd_m3_playback_open(struct snd_pcm_substream *subs)
1811 {
1812         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1813         struct snd_pcm_runtime *runtime = subs->runtime;
1814         int err;
1815
1816         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1817                 return err;
1818
1819         runtime->hw = snd_m3_playback;
1820
1821         return 0;
1822 }
1823
1824 static int
1825 snd_m3_playback_close(struct snd_pcm_substream *subs)
1826 {
1827         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1828
1829         snd_m3_substream_close(chip, subs);
1830         return 0;
1831 }
1832
1833 static int
1834 snd_m3_capture_open(struct snd_pcm_substream *subs)
1835 {
1836         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1837         struct snd_pcm_runtime *runtime = subs->runtime;
1838         int err;
1839
1840         if ((err = snd_m3_substream_open(chip, subs)) < 0)
1841                 return err;
1842
1843         runtime->hw = snd_m3_capture;
1844
1845         return 0;
1846 }
1847
1848 static int
1849 snd_m3_capture_close(struct snd_pcm_substream *subs)
1850 {
1851         struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1852
1853         snd_m3_substream_close(chip, subs);
1854         return 0;
1855 }
1856
1857 /*
1858  * create pcm instance
1859  */
1860
1861 static struct snd_pcm_ops snd_m3_playback_ops = {
1862         .open =         snd_m3_playback_open,
1863         .close =        snd_m3_playback_close,
1864         .ioctl =        snd_pcm_lib_ioctl,
1865         .hw_params =    snd_m3_pcm_hw_params,
1866         .hw_free =      snd_m3_pcm_hw_free,
1867         .prepare =      snd_m3_pcm_prepare,
1868         .trigger =      snd_m3_pcm_trigger,
1869         .pointer =      snd_m3_pcm_pointer,
1870 };
1871
1872 static struct snd_pcm_ops snd_m3_capture_ops = {
1873         .open =         snd_m3_capture_open,
1874         .close =        snd_m3_capture_close,
1875         .ioctl =        snd_pcm_lib_ioctl,
1876         .hw_params =    snd_m3_pcm_hw_params,
1877         .hw_free =      snd_m3_pcm_hw_free,
1878         .prepare =      snd_m3_pcm_prepare,
1879         .trigger =      snd_m3_pcm_trigger,
1880         .pointer =      snd_m3_pcm_pointer,
1881 };
1882
1883 static int __devinit
1884 snd_m3_pcm(struct snd_m3 * chip, int device)
1885 {
1886         struct snd_pcm *pcm;
1887         int err;
1888
1889         err = snd_pcm_new(chip->card, chip->card->driver, device,
1890                           MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1891         if (err < 0)
1892                 return err;
1893
1894         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1895         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1896
1897         pcm->private_data = chip;
1898         pcm->info_flags = 0;
1899         strcpy(pcm->name, chip->card->driver);
1900         chip->pcm = pcm;
1901         
1902         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1903                                               snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1904
1905         return 0;
1906 }
1907
1908
1909 /*
1910  * ac97 interface
1911  */
1912
1913 /*
1914  * Wait for the ac97 serial bus to be free.
1915  * return nonzero if the bus is still busy.
1916  */
1917 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1918 {
1919         int i = 10000;
1920
1921         do {
1922                 if (! (snd_m3_inb(chip, 0x30) & 1))
1923                         return 0;
1924                 cpu_relax();
1925         } while (i-- > 0);
1926
1927         snd_printk(KERN_ERR "ac97 serial bus busy\n");
1928         return 1;
1929 }
1930
1931 static unsigned short
1932 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1933 {
1934         struct snd_m3 *chip = ac97->private_data;
1935         unsigned long flags;
1936         unsigned short data = 0xffff;
1937
1938         if (snd_m3_ac97_wait(chip))
1939                 goto fail;
1940         spin_lock_irqsave(&chip->ac97_lock, flags);
1941         snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1942         if (snd_m3_ac97_wait(chip))
1943                 goto fail_unlock;
1944         data = snd_m3_inw(chip, CODEC_DATA);
1945 fail_unlock:
1946         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1947 fail:
1948         return data;
1949 }
1950
1951 static void
1952 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1953 {
1954         struct snd_m3 *chip = ac97->private_data;
1955         unsigned long flags;
1956
1957         if (snd_m3_ac97_wait(chip))
1958                 return;
1959         spin_lock_irqsave(&chip->ac97_lock, flags);
1960         snd_m3_outw(chip, val, CODEC_DATA);
1961         snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1962         spin_unlock_irqrestore(&chip->ac97_lock, flags);
1963 }
1964
1965
1966 static void snd_m3_remote_codec_config(int io, int isremote)
1967 {
1968         isremote = isremote ? 1 : 0;
1969
1970         outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1971              io + RING_BUS_CTRL_B);
1972         outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1973              io + SDO_OUT_DEST_CTRL);
1974         outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1975              io + SDO_IN_DEST_CTRL);
1976 }
1977
1978 /* 
1979  * hack, returns non zero on err 
1980  */
1981 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1982 {
1983         u16 ret;
1984
1985         if (snd_m3_ac97_wait(chip))
1986                 return 1;
1987
1988         snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1989
1990         if (snd_m3_ac97_wait(chip))
1991                 return 1;
1992
1993         ret = snd_m3_inw(chip, 0x32);
1994
1995         return (ret == 0) || (ret == 0xffff);
1996 }
1997
1998 static void snd_m3_ac97_reset(struct snd_m3 *chip)
1999 {
2000         u16 dir;
2001         int delay1 = 0, delay2 = 0, i;
2002         int io = chip->iobase;
2003
2004         if (chip->allegro_flag) {
2005                 /*
2006                  * the onboard codec on the allegro seems 
2007                  * to want to wait a very long time before
2008                  * coming back to life 
2009                  */
2010                 delay1 = 50;
2011                 delay2 = 800;
2012         } else {
2013                 /* maestro3 */
2014                 delay1 = 20;
2015                 delay2 = 500;
2016         }
2017
2018         for (i = 0; i < 5; i++) {
2019                 dir = inw(io + GPIO_DIRECTION);
2020                 if (!chip->irda_workaround)
2021                         dir |= 0x10; /* assuming pci bus master? */
2022
2023                 snd_m3_remote_codec_config(io, 0);
2024
2025                 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2026                 udelay(20);
2027
2028                 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2029                 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2030                 outw(0, io + GPIO_DATA);
2031                 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2032
2033                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2034
2035                 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2036                 udelay(5);
2037                 /* ok, bring back the ac-link */
2038                 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2039                 outw(~0, io + GPIO_MASK);
2040
2041                 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2042
2043                 if (! snd_m3_try_read_vendor(chip))
2044                         break;
2045
2046                 delay1 += 10;
2047                 delay2 += 100;
2048
2049                 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2050                            delay1, delay2);
2051         }
2052
2053 #if 0
2054         /* more gung-ho reset that doesn't
2055          * seem to work anywhere :)
2056          */
2057         tmp = inw(io + RING_BUS_CTRL_A);
2058         outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2059         msleep(20);
2060         outw(tmp, io + RING_BUS_CTRL_A);
2061         msleep(50);
2062 #endif
2063 }
2064
2065 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2066 {
2067         struct snd_ac97_bus *pbus;
2068         struct snd_ac97_template ac97;
2069         struct snd_ctl_elem_id elem_id;
2070         int err;
2071         static struct snd_ac97_bus_ops ops = {
2072                 .write = snd_m3_ac97_write,
2073                 .read = snd_m3_ac97_read,
2074         };
2075
2076         if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2077                 return err;
2078         
2079         memset(&ac97, 0, sizeof(ac97));
2080         ac97.private_data = chip;
2081         if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2082                 return err;
2083
2084         /* seems ac97 PCM needs initialization.. hack hack.. */
2085         snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2086         schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2087         snd_ac97_write(chip->ac97, AC97_PCM, 0);
2088
2089         memset(&elem_id, 0, sizeof(elem_id));
2090         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2091         strcpy(elem_id.name, "Master Playback Switch");
2092         chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2093         memset(&elem_id, 0, sizeof(elem_id));
2094         elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2095         strcpy(elem_id.name, "Master Playback Volume");
2096         chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2097
2098         return 0;
2099 }
2100
2101
2102 /*
2103  * initialize ASSP
2104  */
2105
2106 #define MINISRC_LPF_LEN 10
2107 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2108         0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2109         0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2110 };
2111
2112 static void snd_m3_assp_init(struct snd_m3 *chip)
2113 {
2114         unsigned int i;
2115         const u16 *data;
2116
2117         /* zero kernel data */
2118         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2119                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2120                                   KDATA_BASE_ADDR + i, 0);
2121
2122         /* zero mixer data? */
2123         for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2124                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2125                                   KDATA_BASE_ADDR2 + i, 0);
2126
2127         /* init dma pointer */
2128         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2129                           KDATA_CURRENT_DMA,
2130                           KDATA_DMA_XFER0);
2131
2132         /* write kernel into code memory.. */
2133         data = (const u16 *)chip->assp_kernel_image->data;
2134         for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2135                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 
2136                                   REV_B_CODE_MEMORY_BEGIN + i,
2137                                   le16_to_cpu(data[i]));
2138         }
2139
2140         /*
2141          * We only have this one client and we know that 0x400
2142          * is free in our kernel's mem map, so lets just
2143          * drop it there.  It seems that the minisrc doesn't
2144          * need vectors, so we won't bother with them..
2145          */
2146         data = (const u16 *)chip->assp_minisrc_image->data;
2147         for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2148                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 
2149                                   0x400 + i, le16_to_cpu(data[i]));
2150         }
2151
2152         /*
2153          * write the coefficients for the low pass filter?
2154          */
2155         for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2156                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2157                                   0x400 + MINISRC_COEF_LOC + i,
2158                                   minisrc_lpf[i]);
2159         }
2160
2161         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2162                           0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2163                           0x8000);
2164
2165         /*
2166          * the minisrc is the only thing on
2167          * our task list..
2168          */
2169         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2170                           KDATA_TASK0,
2171                           0x400);
2172
2173         /*
2174          * init the mixer number..
2175          */
2176
2177         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2178                           KDATA_MIXER_TASK_NUMBER,0);
2179
2180         /*
2181          * EXTREME KERNEL MASTER VOLUME
2182          */
2183         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2184                           KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2185         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2186                           KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2187
2188         chip->mixer_list.curlen = 0;
2189         chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2190         chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2191         chip->adc1_list.curlen = 0;
2192         chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2193         chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2194         chip->dma_list.curlen = 0;
2195         chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2196         chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2197         chip->msrc_list.curlen = 0;
2198         chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2199         chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2200 }
2201
2202
2203 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2204 {
2205         int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + 
2206                                MINISRC_IN_BUFFER_SIZE / 2 +
2207                                1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2208         int address, i;
2209
2210         /*
2211          * the revb memory map has 0x1100 through 0x1c00
2212          * free.  
2213          */
2214
2215         /*
2216          * align instance address to 256 bytes so that its
2217          * shifted list address is aligned.
2218          * list address = (mem address >> 1) >> 7;
2219          */
2220         data_bytes = ALIGN(data_bytes, 256);
2221         address = 0x1100 + ((data_bytes/2) * index);
2222
2223         if ((address + (data_bytes/2)) >= 0x1c00) {
2224                 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2225                            data_bytes, index, address);
2226                 return -ENOMEM;
2227         }
2228
2229         s->number = index;
2230         s->inst.code = 0x400;
2231         s->inst.data = address;
2232
2233         for (i = data_bytes / 2; i > 0; address++, i--) {
2234                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2235                                   address, 0);
2236         }
2237
2238         return 0;
2239 }
2240
2241
2242 /* 
2243  * this works for the reference board, have to find
2244  * out about others
2245  *
2246  * this needs more magic for 4 speaker, but..
2247  */
2248 static void
2249 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2250 {
2251         int io = chip->iobase;
2252         u16 gpo, polarity;
2253
2254         if (! chip->external_amp)
2255                 return;
2256
2257         polarity = enable ? 0 : 1;
2258         polarity = polarity << chip->amp_gpio;
2259         gpo = 1 << chip->amp_gpio;
2260
2261         outw(~gpo, io + GPIO_MASK);
2262
2263         outw(inw(io + GPIO_DIRECTION) | gpo,
2264              io + GPIO_DIRECTION);
2265
2266         outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2267              io + GPIO_DATA);
2268
2269         outw(0xffff, io + GPIO_MASK);
2270 }
2271
2272 static void
2273 snd_m3_hv_init(struct snd_m3 *chip)
2274 {
2275         unsigned long io = chip->iobase;
2276         u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2277
2278         if (!chip->is_omnibook)
2279                 return;
2280
2281         /*
2282          * Volume buttons on some HP OmniBook laptops
2283          * require some GPIO magic to work correctly.
2284          */
2285         outw(0xffff, io + GPIO_MASK);
2286         outw(0x0000, io + GPIO_DATA);
2287
2288         outw(~val, io + GPIO_MASK);
2289         outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2290         outw(val, io + GPIO_MASK);
2291
2292         outw(0xffff, io + GPIO_MASK);
2293 }
2294
2295 static int
2296 snd_m3_chip_init(struct snd_m3 *chip)
2297 {
2298         struct pci_dev *pcidev = chip->pci;
2299         unsigned long io = chip->iobase;
2300         u32 n;
2301         u16 w;
2302         u8 t; /* makes as much sense as 'n', no? */
2303
2304         pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2305         w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2306                MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2307                DISABLE_LEGACY);
2308         pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2309
2310         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2311         n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2312         n |= chip->hv_config;
2313         /* For some reason we must always use reduced debounce. */
2314         n |= REDUCED_DEBOUNCE;
2315         n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2316         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2317
2318         outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2319         pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2320         n &= ~INT_CLK_SELECT;
2321         if (!chip->allegro_flag) {
2322                 n &= ~INT_CLK_MULT_ENABLE; 
2323                 n |= INT_CLK_SRC_NOT_PCI;
2324         }
2325         n &=  ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2326         pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2327
2328         if (chip->allegro_flag) {
2329                 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2330                 n |= IN_CLK_12MHZ_SELECT;
2331                 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2332         }
2333
2334         t = inb(chip->iobase + ASSP_CONTROL_A);
2335         t &= ~( DSP_CLK_36MHZ_SELECT  | ASSP_CLK_49MHZ_SELECT);
2336         t |= ASSP_CLK_49MHZ_SELECT;
2337         t |= ASSP_0_WS_ENABLE; 
2338         outb(t, chip->iobase + ASSP_CONTROL_A);
2339
2340         snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2341         outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); 
2342
2343         outb(0x00, io + HARDWARE_VOL_CTRL);
2344         outb(0x88, io + SHADOW_MIX_REG_VOICE);
2345         outb(0x88, io + HW_VOL_COUNTER_VOICE);
2346         outb(0x88, io + SHADOW_MIX_REG_MASTER);
2347         outb(0x88, io + HW_VOL_COUNTER_MASTER);
2348
2349         return 0;
2350
2351
2352 static void
2353 snd_m3_enable_ints(struct snd_m3 *chip)
2354 {
2355         unsigned long io = chip->iobase;
2356         unsigned short val;
2357
2358         /* TODO: MPU401 not supported yet */
2359         val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2360         if (chip->hv_config & HV_CTRL_ENABLE)
2361                 val |= HV_INT_ENABLE;
2362         outw(val, io + HOST_INT_CTRL);
2363         outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2364              io + ASSP_CONTROL_C);
2365 }
2366
2367
2368 /*
2369  */
2370
2371 static int snd_m3_free(struct snd_m3 *chip)
2372 {
2373         struct m3_dma *s;
2374         int i;
2375
2376         if (chip->substreams) {
2377                 spin_lock_irq(&chip->reg_lock);
2378                 for (i = 0; i < chip->num_substreams; i++) {
2379                         s = &chip->substreams[i];
2380                         /* check surviving pcms; this should not happen though.. */
2381                         if (s->substream && s->running)
2382                                 snd_m3_pcm_stop(chip, s, s->substream);
2383                 }
2384                 spin_unlock_irq(&chip->reg_lock);
2385                 kfree(chip->substreams);
2386         }
2387         if (chip->iobase) {
2388                 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2389         }
2390
2391 #ifdef CONFIG_PM
2392         vfree(chip->suspend_mem);
2393 #endif
2394
2395         if (chip->irq >= 0)
2396                 free_irq(chip->irq, chip);
2397
2398         if (chip->iobase)
2399                 pci_release_regions(chip->pci);
2400
2401         release_firmware(chip->assp_kernel_image);
2402         release_firmware(chip->assp_minisrc_image);
2403
2404         pci_disable_device(chip->pci);
2405         kfree(chip);
2406         return 0;
2407 }
2408
2409
2410 /*
2411  * APM support
2412  */
2413 #ifdef CONFIG_PM
2414 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2415 {
2416         struct snd_card *card = pci_get_drvdata(pci);
2417         struct snd_m3 *chip = card->private_data;
2418         int i, dsp_index;
2419
2420         if (chip->suspend_mem == NULL)
2421                 return 0;
2422
2423         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2424         snd_pcm_suspend_all(chip->pcm);
2425         snd_ac97_suspend(chip->ac97);
2426
2427         msleep(10); /* give the assp a chance to idle.. */
2428
2429         snd_m3_assp_halt(chip);
2430
2431         /* save dsp image */
2432         dsp_index = 0;
2433         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2434                 chip->suspend_mem[dsp_index++] =
2435                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2436         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2437                 chip->suspend_mem[dsp_index++] =
2438                         snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2439
2440         pci_disable_device(pci);
2441         pci_save_state(pci);
2442         pci_set_power_state(pci, pci_choose_state(pci, state));
2443         return 0;
2444 }
2445
2446 static int m3_resume(struct pci_dev *pci)
2447 {
2448         struct snd_card *card = pci_get_drvdata(pci);
2449         struct snd_m3 *chip = card->private_data;
2450         int i, dsp_index;
2451
2452         if (chip->suspend_mem == NULL)
2453                 return 0;
2454
2455         pci_set_power_state(pci, PCI_D0);
2456         pci_restore_state(pci);
2457         if (pci_enable_device(pci) < 0) {
2458                 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2459                        "disabling device\n");
2460                 snd_card_disconnect(card);
2461                 return -EIO;
2462         }
2463         pci_set_master(pci);
2464
2465         /* first lets just bring everything back. .*/
2466         snd_m3_outw(chip, 0, 0x54);
2467         snd_m3_outw(chip, 0, 0x56);
2468
2469         snd_m3_chip_init(chip);
2470         snd_m3_assp_halt(chip);
2471         snd_m3_ac97_reset(chip);
2472
2473         /* restore dsp image */
2474         dsp_index = 0;
2475         for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2476                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, 
2477                                   chip->suspend_mem[dsp_index++]);
2478         for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2479                 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, 
2480                                   chip->suspend_mem[dsp_index++]);
2481
2482         /* tell the dma engine to restart itself */
2483         snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 
2484                           KDATA_DMA_ACTIVE, 0);
2485
2486         /* restore ac97 registers */
2487         snd_ac97_resume(chip->ac97);
2488
2489         snd_m3_assp_continue(chip);
2490         snd_m3_enable_ints(chip);
2491         snd_m3_amp_enable(chip, 1);
2492
2493         snd_m3_hv_init(chip);
2494
2495         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2496         return 0;
2497 }
2498 #endif /* CONFIG_PM */
2499
2500
2501 /*
2502  */
2503
2504 static int snd_m3_dev_free(struct snd_device *device)
2505 {
2506         struct snd_m3 *chip = device->device_data;
2507         return snd_m3_free(chip);
2508 }
2509
2510 static int __devinit
2511 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2512               int enable_amp,
2513               int amp_gpio,
2514               struct snd_m3 **chip_ret)
2515 {
2516         struct snd_m3 *chip;
2517         int i, err;
2518         const struct snd_pci_quirk *quirk;
2519         static struct snd_device_ops ops = {
2520                 .dev_free =     snd_m3_dev_free,
2521         };
2522
2523         *chip_ret = NULL;
2524
2525         if (pci_enable_device(pci))
2526                 return -EIO;
2527
2528         /* check, if we can restrict PCI DMA transfers to 28 bits */
2529         if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2530             pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2531                 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2532                 pci_disable_device(pci);
2533                 return -ENXIO;
2534         }
2535
2536         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2537         if (chip == NULL) {
2538                 pci_disable_device(pci);
2539                 return -ENOMEM;
2540         }
2541
2542         spin_lock_init(&chip->reg_lock);
2543         spin_lock_init(&chip->ac97_lock);
2544
2545         switch (pci->device) {
2546         case PCI_DEVICE_ID_ESS_ALLEGRO:
2547         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2548         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2549         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2550                 chip->allegro_flag = 1;
2551                 break;
2552         }
2553
2554         chip->card = card;
2555         chip->pci = pci;
2556         chip->irq = -1;
2557
2558         chip->external_amp = enable_amp;
2559         if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2560                 chip->amp_gpio = amp_gpio;
2561         else {
2562                 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2563                 if (quirk) {
2564                         snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2565                                     "for '%s'\n", quirk->name);
2566                         chip->amp_gpio = quirk->value;
2567                 } else if (chip->allegro_flag)
2568                         chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2569                 else /* presumably this is for all 'maestro3's.. */
2570                         chip->amp_gpio = GPO_EXT_AMP_M3;
2571         }
2572
2573         quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2574         if (quirk) {
2575                 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2576                             "for '%s'\n", quirk->name);
2577                 chip->irda_workaround = 1;
2578         }
2579         quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2580         if (quirk)
2581                 chip->hv_config = quirk->value;
2582         if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2583                 chip->is_omnibook = 1;
2584
2585         chip->num_substreams = NR_DSPS;
2586         chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2587                                    GFP_KERNEL);
2588         if (chip->substreams == NULL) {
2589                 kfree(chip);
2590                 pci_disable_device(pci);
2591                 return -ENOMEM;
2592         }
2593
2594         err = request_firmware(&chip->assp_kernel_image,
2595                                "ess/maestro3_assp_kernel.fw", &pci->dev);
2596         if (err < 0) {
2597                 snd_m3_free(chip);
2598                 return err;
2599         }
2600
2601         err = request_firmware(&chip->assp_minisrc_image,
2602                                "ess/maestro3_assp_minisrc.fw", &pci->dev);
2603         if (err < 0) {
2604                 snd_m3_free(chip);
2605                 return err;
2606         }
2607
2608         if ((err = pci_request_regions(pci, card->driver)) < 0) {
2609                 snd_m3_free(chip);
2610                 return err;
2611         }
2612         chip->iobase = pci_resource_start(pci, 0);
2613         
2614         /* just to be sure */
2615         pci_set_master(pci);
2616
2617         snd_m3_chip_init(chip);
2618         snd_m3_assp_halt(chip);
2619
2620         snd_m3_ac97_reset(chip);
2621
2622         snd_m3_amp_enable(chip, 1);
2623
2624         snd_m3_hv_init(chip);
2625
2626         tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2627
2628         if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2629                         card->driver, chip)) {
2630                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2631                 snd_m3_free(chip);
2632                 return -ENOMEM;
2633         }
2634         chip->irq = pci->irq;
2635
2636 #ifdef CONFIG_PM
2637         chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2638         if (chip->suspend_mem == NULL)
2639                 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2640 #endif
2641
2642         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2643                 snd_m3_free(chip);
2644                 return err;
2645         }
2646
2647         if ((err = snd_m3_mixer(chip)) < 0)
2648                 return err;
2649
2650         for (i = 0; i < chip->num_substreams; i++) {
2651                 struct m3_dma *s = &chip->substreams[i];
2652                 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2653                         return err;
2654         }
2655
2656         if ((err = snd_m3_pcm(chip, 0)) < 0)
2657                 return err;
2658     
2659         snd_m3_enable_ints(chip);
2660         snd_m3_assp_continue(chip);
2661
2662         snd_card_set_dev(card, &pci->dev);
2663
2664         *chip_ret = chip;
2665
2666         return 0; 
2667 }
2668
2669 /*
2670  */
2671 static int __devinit
2672 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2673 {
2674         static int dev;
2675         struct snd_card *card;
2676         struct snd_m3 *chip;
2677         int err;
2678
2679         /* don't pick up modems */
2680         if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2681                 return -ENODEV;
2682
2683         if (dev >= SNDRV_CARDS)
2684                 return -ENODEV;
2685         if (!enable[dev]) {
2686                 dev++;
2687                 return -ENOENT;
2688         }
2689
2690         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2691         if (card == NULL)
2692                 return -ENOMEM;
2693
2694         switch (pci->device) {
2695         case PCI_DEVICE_ID_ESS_ALLEGRO:
2696         case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2697                 strcpy(card->driver, "Allegro");
2698                 break;
2699         case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2700         case PCI_DEVICE_ID_ESS_CANYON3D_2:
2701                 strcpy(card->driver, "Canyon3D-2");
2702                 break;
2703         default:
2704                 strcpy(card->driver, "Maestro3");
2705                 break;
2706         }
2707
2708         if ((err = snd_m3_create(card, pci,
2709                                  external_amp[dev],
2710                                  amp_gpio[dev],
2711                                  &chip)) < 0) {
2712                 snd_card_free(card);
2713                 return err;
2714         }
2715         card->private_data = chip;
2716
2717         sprintf(card->shortname, "ESS %s PCI", card->driver);
2718         sprintf(card->longname, "%s at 0x%lx, irq %d",
2719                 card->shortname, chip->iobase, chip->irq);
2720
2721         if ((err = snd_card_register(card)) < 0) {
2722                 snd_card_free(card);
2723                 return err;
2724         }
2725
2726 #if 0 /* TODO: not supported yet */
2727         /* TODO enable MIDI IRQ and I/O */
2728         err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2729                                   chip->iobase + MPU401_DATA_PORT,
2730                                   MPU401_INFO_INTEGRATED,
2731                                   chip->irq, 0, &chip->rmidi);
2732         if (err < 0)
2733                 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2734 #endif
2735
2736         pci_set_drvdata(pci, card);
2737         dev++;
2738         return 0;
2739 }
2740
2741 static void __devexit snd_m3_remove(struct pci_dev *pci)
2742 {
2743         snd_card_free(pci_get_drvdata(pci));
2744         pci_set_drvdata(pci, NULL);
2745 }
2746
2747 static struct pci_driver driver = {
2748         .name = "Maestro3",
2749         .id_table = snd_m3_ids,
2750         .probe = snd_m3_probe,
2751         .remove = __devexit_p(snd_m3_remove),
2752 #ifdef CONFIG_PM
2753         .suspend = m3_suspend,
2754         .resume = m3_resume,
2755 #endif
2756 };
2757         
2758 static int __init alsa_card_m3_init(void)
2759 {
2760         return pci_register_driver(&driver);
2761 }
2762
2763 static void __exit alsa_card_m3_exit(void)
2764 {
2765         pci_unregister_driver(&driver);
2766 }
2767
2768 module_init(alsa_card_m3_init)
2769 module_exit(alsa_card_m3_exit)