Smack: update for file capabilities
[linux-2.6.git] / sound / pci / intel8x0.c
1 /*
2  *   ALSA driver for Intel ICH (i8x0) chipsets
3  *
4  *      Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5  *
6  *
7  *   This code also contains alpha support for SiS 735 chipsets provided
8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9  *   for SiS735, so the code is not fully functional.
10  *
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
25
26  *
27  */      
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/moduleparam.h>
36 #include <sound/core.h>
37 #include <sound/pcm.h>
38 #include <sound/ac97_codec.h>
39 #include <sound/info.h>
40 #include <sound/initval.h>
41 /* for 440MX workaround */
42 #include <asm/pgtable.h>
43 #include <asm/cacheflush.h>
44
45 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
46 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
49                 "{Intel,82901AB-ICH0},"
50                 "{Intel,82801BA-ICH2},"
51                 "{Intel,82801CA-ICH3},"
52                 "{Intel,82801DB-ICH4},"
53                 "{Intel,ICH5},"
54                 "{Intel,ICH6},"
55                 "{Intel,ICH7},"
56                 "{Intel,6300ESB},"
57                 "{Intel,ESB2},"
58                 "{Intel,MX440},"
59                 "{SiS,SI7012},"
60                 "{NVidia,nForce Audio},"
61                 "{NVidia,nForce2 Audio},"
62                 "{AMD,AMD768},"
63                 "{AMD,AMD8111},"
64                 "{ALI,M5455}}");
65
66 static int index = SNDRV_DEFAULT_IDX1;  /* Index 0-MAX */
67 static char *id = SNDRV_DEFAULT_STR1;   /* ID for this card */
68 static int ac97_clock;
69 static char *ac97_quirk;
70 static int buggy_semaphore;
71 static int buggy_irq = -1; /* auto-check */
72 static int xbox;
73 static int spdif_aclink = -1;
74
75 module_param(index, int, 0444);
76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
77 module_param(id, charp, 0444);
78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
79 module_param(ac97_clock, int, 0444);
80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
81 module_param(ac97_quirk, charp, 0444);
82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
83 module_param(buggy_semaphore, bool, 0444);
84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
85 module_param(buggy_irq, bool, 0444);
86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
87 module_param(xbox, bool, 0444);
88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
89 module_param(spdif_aclink, int, 0444);
90 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
91
92 /* just for backward compatibility */
93 static int enable;
94 module_param(enable, bool, 0444);
95 static int joystick;
96 module_param(joystick, int, 0444);
97
98 /*
99  *  Direct registers
100  */
101 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
102
103 #define ICHREG(x) ICH_REG_##x
104
105 #define DEFINE_REGSET(name,base) \
106 enum { \
107         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
108         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
109         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
110         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
111         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
112         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
113         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
114 };
115
116 /* busmaster blocks */
117 DEFINE_REGSET(OFF, 0);          /* offset */
118 DEFINE_REGSET(PI, 0x00);        /* PCM in */
119 DEFINE_REGSET(PO, 0x10);        /* PCM out */
120 DEFINE_REGSET(MC, 0x20);        /* Mic in */
121
122 /* ICH4 busmaster blocks */
123 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
124 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
125 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
126
127 /* values for each busmaster block */
128
129 /* LVI */
130 #define ICH_REG_LVI_MASK                0x1f
131
132 /* SR */
133 #define ICH_FIFOE                       0x10    /* FIFO error */
134 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
135 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
136 #define ICH_CELV                        0x02    /* current equals last valid */
137 #define ICH_DCH                         0x01    /* DMA controller halted */
138
139 /* PIV */
140 #define ICH_REG_PIV_MASK                0x1f    /* mask */
141
142 /* CR */
143 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
144 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
145 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
146 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
147 #define ICH_STARTBM                     0x01    /* start busmaster operation */
148
149
150 /* global block */
151 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
152 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
153 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
154 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
155 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
156 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
157 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
158 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
159 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
160 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
161 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
162 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
163 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
164 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
165 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
166 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
167 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
168 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
169 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
170 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
171 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
172 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
173 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
174 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
175 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
176 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
177 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
178 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
179 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
180 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
181 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
182 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
183 #define   ICH_SIS_TRI           0x00080000      /* SIS: tertiary resume irq */
184 #define   ICH_SIS_TCR           0x00040000      /* SIS: tertiary codec ready */
185 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
186 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
187 #define   ICH_RCS               0x00008000      /* read completion status */
188 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
189 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
190 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
191 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
192 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
193 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
194 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
195 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
196 #define   ICH_POINT             0x00000040      /* playback interrupt */
197 #define   ICH_PIINT             0x00000020      /* capture interrupt */
198 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
199 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
200 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
201 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
202 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
203 #define   ICH_CAS               0x01            /* codec access semaphore */
204 #define ICH_REG_SDM             0x80
205 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
206 #define   ICH_DI2L_SHIFT        6
207 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
208 #define   ICH_DI1L_SHIFT        4
209 #define   ICH_SE                0x00000008      /* steer enable */
210 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
211
212 #define ICH_MAX_FRAGS           32              /* max hw frags */
213
214
215 /*
216  * registers for Ali5455
217  */
218
219 /* ALi 5455 busmaster blocks */
220 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
221 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
222 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
223 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
224 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
225 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
226 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
227 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
228 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
229 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
230 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
231
232 enum {
233         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
234         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
235         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
236         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
237         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
238         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
239         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
240         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
241         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
242         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
243         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
244         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
245         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
246         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
247         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
248         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
249         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
250         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
251         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
252         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
253         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
254 };
255
256 #define ALI_CAS_SEM_BUSY        0x80000000
257 #define ALI_CPR_ADDR_SECONDARY  0x100
258 #define ALI_CPR_ADDR_READ       0x80
259 #define ALI_CSPSR_CODEC_READY   0x08
260 #define ALI_CSPSR_READ_OK       0x02
261 #define ALI_CSPSR_WRITE_OK      0x01
262
263 /* interrupts for the whole chip by interrupt status register finish */
264  
265 #define ALI_INT_MICIN2          (1<<26)
266 #define ALI_INT_PCMIN2          (1<<25)
267 #define ALI_INT_I2SIN           (1<<24)
268 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
269 #define ALI_INT_SPDIFIN         (1<<22)
270 #define ALI_INT_LFEOUT          (1<<21)
271 #define ALI_INT_CENTEROUT       (1<<20)
272 #define ALI_INT_CODECSPDIFOUT   (1<<19)
273 #define ALI_INT_MICIN           (1<<18)
274 #define ALI_INT_PCMOUT          (1<<17)
275 #define ALI_INT_PCMIN           (1<<16)
276 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
277 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
278 #define ALI_INT_GPIO            (1<<1)
279 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
280                                  ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
281
282 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
283 #define ICH_ALI_SC_AC97_DBL     (1<<30)
284 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
285 #define ICH_ALI_SC_IN_BITS      (3<<18)
286 #define ICH_ALI_SC_OUT_BITS     (3<<16)
287 #define ICH_ALI_SC_6CH_CFG      (3<<14)
288 #define ICH_ALI_SC_PCM_4        (1<<8)
289 #define ICH_ALI_SC_PCM_6        (2<<8)
290 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
291
292 #define ICH_ALI_SS_SEC_ID       (3<<5)
293 #define ICH_ALI_SS_PRI_ID       (3<<3)
294
295 #define ICH_ALI_IF_AC97SP       (1<<21)
296 #define ICH_ALI_IF_MC           (1<<20)
297 #define ICH_ALI_IF_PI           (1<<19)
298 #define ICH_ALI_IF_MC2          (1<<18)
299 #define ICH_ALI_IF_PI2          (1<<17)
300 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
301 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
302 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
303 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
304 #define ICH_ALI_IF_PO_SPDF      (1<<3)
305 #define ICH_ALI_IF_PO           (1<<1)
306
307 /*
308  *  
309  */
310
311 enum {
312         ICHD_PCMIN,
313         ICHD_PCMOUT,
314         ICHD_MIC,
315         ICHD_MIC2,
316         ICHD_PCM2IN,
317         ICHD_SPBAR,
318         ICHD_LAST = ICHD_SPBAR
319 };
320 enum {
321         NVD_PCMIN,
322         NVD_PCMOUT,
323         NVD_MIC,
324         NVD_SPBAR,
325         NVD_LAST = NVD_SPBAR
326 };
327 enum {
328         ALID_PCMIN,
329         ALID_PCMOUT,
330         ALID_MIC,
331         ALID_AC97SPDIFOUT,
332         ALID_SPDIFIN,
333         ALID_SPDIFOUT,
334         ALID_LAST = ALID_SPDIFOUT
335 };
336
337 #define get_ichdev(substream) (substream->runtime->private_data)
338
339 struct ichdev {
340         unsigned int ichd;                      /* ich device number */
341         unsigned long reg_offset;               /* offset to bmaddr */
342         u32 *bdbar;                             /* CPU address (32bit) */
343         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
344         struct snd_pcm_substream *substream;
345         unsigned int physbuf;                   /* physical address (32bit) */
346         unsigned int size;
347         unsigned int fragsize;
348         unsigned int fragsize1;
349         unsigned int position;
350         unsigned int pos_shift;
351         int frags;
352         int lvi;
353         int lvi_frag;
354         int civ;
355         int ack;
356         int ack_reload;
357         unsigned int ack_bit;
358         unsigned int roff_sr;
359         unsigned int roff_picb;
360         unsigned int int_sta_mask;              /* interrupt status mask */
361         unsigned int ali_slot;                  /* ALI DMA slot */
362         struct ac97_pcm *pcm;
363         int pcm_open_flag;
364         unsigned int page_attr_changed: 1;
365         unsigned int suspended: 1;
366 };
367
368 struct intel8x0 {
369         unsigned int device_type;
370
371         int irq;
372
373         void __iomem *addr;
374         void __iomem *bmaddr;
375
376         struct pci_dev *pci;
377         struct snd_card *card;
378
379         int pcm_devs;
380         struct snd_pcm *pcm[6];
381         struct ichdev ichd[6];
382
383         unsigned multi4: 1,
384                  multi6: 1,
385                  dra: 1,
386                  smp20bit: 1;
387         unsigned in_ac97_init: 1,
388                  in_sdin_init: 1;
389         unsigned in_measurement: 1;     /* during ac97 clock measurement */
390         unsigned fix_nocache: 1;        /* workaround for 440MX */
391         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
392         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
393         unsigned buggy_semaphore: 1;    /* workaround for buggy codec semaphore */
394
395         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
396         unsigned int sdm_saved; /* SDM reg value */
397
398         struct snd_ac97_bus *ac97_bus;
399         struct snd_ac97 *ac97[3];
400         unsigned int ac97_sdin[3];
401         unsigned int max_codecs, ncodecs;
402         unsigned int *codec_bit;
403         unsigned int codec_isr_bits;
404         unsigned int codec_ready_bits;
405
406         spinlock_t reg_lock;
407         
408         u32 bdbars_count;
409         struct snd_dma_buffer bdbars;
410         u32 int_sta_reg;                /* interrupt status register */
411         u32 int_sta_mask;               /* interrupt status mask */
412 };
413
414 static struct pci_device_id snd_intel8x0_ids[] = {
415         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
416         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
417         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
418         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
419         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
420         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
421         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
422         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
423         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
424         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
425         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
426         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
427         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
428         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
429         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
430         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
431         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
432         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
433         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
434         { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP51 */
435         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
436         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
437         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
438         { 0, }
439 };
440
441 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
442
443 /*
444  *  Lowlevel I/O - busmaster
445  */
446
447 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
448 {
449         return ioread8(chip->bmaddr + offset);
450 }
451
452 static inline u16 igetword(struct intel8x0 *chip, u32 offset)
453 {
454         return ioread16(chip->bmaddr + offset);
455 }
456
457 static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
458 {
459         return ioread32(chip->bmaddr + offset);
460 }
461
462 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
463 {
464         iowrite8(val, chip->bmaddr + offset);
465 }
466
467 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
468 {
469         iowrite16(val, chip->bmaddr + offset);
470 }
471
472 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
473 {
474         iowrite32(val, chip->bmaddr + offset);
475 }
476
477 /*
478  *  Lowlevel I/O - AC'97 registers
479  */
480
481 static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
482 {
483         return ioread16(chip->addr + offset);
484 }
485
486 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
487 {
488         iowrite16(val, chip->addr + offset);
489 }
490
491 /*
492  *  Basic I/O
493  */
494
495 /*
496  * access to AC97 codec via normal i/o (for ICH and SIS7012)
497  */
498
499 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
500 {
501         int time;
502         
503         if (codec > 2)
504                 return -EIO;
505         if (chip->in_sdin_init) {
506                 /* we don't know the ready bit assignment at the moment */
507                 /* so we check any */
508                 codec = chip->codec_isr_bits;
509         } else {
510                 codec = chip->codec_bit[chip->ac97_sdin[codec]];
511         }
512
513         /* codec ready ? */
514         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
515                 return -EIO;
516
517         if (chip->buggy_semaphore)
518                 return 0; /* just ignore ... */
519
520         /* Anyone holding a semaphore for 1 msec should be shot... */
521         time = 100;
522         do {
523                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
524                         return 0;
525                 udelay(10);
526         } while (time--);
527
528         /* access to some forbidden (non existant) ac97 registers will not
529          * reset the semaphore. So even if you don't get the semaphore, still
530          * continue the access. We don't need the semaphore anyway. */
531         snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
532                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
533         iagetword(chip, 0);     /* clear semaphore flag */
534         /* I don't care about the semaphore */
535         return -EBUSY;
536 }
537  
538 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
539                                      unsigned short reg,
540                                      unsigned short val)
541 {
542         struct intel8x0 *chip = ac97->private_data;
543         
544         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
545                 if (! chip->in_ac97_init)
546                         snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
547         }
548         iaputword(chip, reg + ac97->num * 0x80, val);
549 }
550
551 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
552                                               unsigned short reg)
553 {
554         struct intel8x0 *chip = ac97->private_data;
555         unsigned short res;
556         unsigned int tmp;
557
558         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
559                 if (! chip->in_ac97_init)
560                         snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
561                 res = 0xffff;
562         } else {
563                 res = iagetword(chip, reg + ac97->num * 0x80);
564                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
565                         /* reset RCS and preserve other R/WC bits */
566                         iputdword(chip, ICHREG(GLOB_STA), tmp &
567                                   ~(chip->codec_ready_bits | ICH_GSCI));
568                         if (! chip->in_ac97_init)
569                                 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
570                         res = 0xffff;
571                 }
572         }
573         return res;
574 }
575
576 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
577                                                    unsigned int codec)
578 {
579         unsigned int tmp;
580
581         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
582                 iagetword(chip, codec * 0x80);
583                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
584                         /* reset RCS and preserve other R/WC bits */
585                         iputdword(chip, ICHREG(GLOB_STA), tmp &
586                                   ~(chip->codec_ready_bits | ICH_GSCI));
587                 }
588         }
589 }
590
591 /*
592  * access to AC97 for Ali5455
593  */
594 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
595 {
596         int count = 0;
597         for (count = 0; count < 0x7f; count++) {
598                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
599                 if (val & mask)
600                         return 0;
601         }
602         if (! chip->in_ac97_init)
603                 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
604         return -EBUSY;
605 }
606
607 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
608 {
609         int time = 100;
610         if (chip->buggy_semaphore)
611                 return 0; /* just ignore ... */
612         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
613                 udelay(1);
614         if (! time && ! chip->in_ac97_init)
615                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
616         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
617 }
618
619 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
620 {
621         struct intel8x0 *chip = ac97->private_data;
622         unsigned short data = 0xffff;
623
624         if (snd_intel8x0_ali_codec_semaphore(chip))
625                 goto __err;
626         reg |= ALI_CPR_ADDR_READ;
627         if (ac97->num)
628                 reg |= ALI_CPR_ADDR_SECONDARY;
629         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
630         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
631                 goto __err;
632         data = igetword(chip, ICHREG(ALI_SPR));
633  __err:
634         return data;
635 }
636
637 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
638                                          unsigned short val)
639 {
640         struct intel8x0 *chip = ac97->private_data;
641
642         if (snd_intel8x0_ali_codec_semaphore(chip))
643                 return;
644         iputword(chip, ICHREG(ALI_CPR), val);
645         if (ac97->num)
646                 reg |= ALI_CPR_ADDR_SECONDARY;
647         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
648         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
649 }
650
651
652 /*
653  * DMA I/O
654  */
655 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
656 {
657         int idx;
658         u32 *bdbar = ichdev->bdbar;
659         unsigned long port = ichdev->reg_offset;
660
661         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
662         if (ichdev->size == ichdev->fragsize) {
663                 ichdev->ack_reload = ichdev->ack = 2;
664                 ichdev->fragsize1 = ichdev->fragsize >> 1;
665                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
666                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
667                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
668                                                      ichdev->fragsize1 >> ichdev->pos_shift);
669                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
670                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
671                                                      ichdev->fragsize1 >> ichdev->pos_shift);
672                 }
673                 ichdev->frags = 2;
674         } else {
675                 ichdev->ack_reload = ichdev->ack = 1;
676                 ichdev->fragsize1 = ichdev->fragsize;
677                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
678                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
679                                                      (((idx >> 1) * ichdev->fragsize) %
680                                                       ichdev->size));
681                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
682                                                      ichdev->fragsize >> ichdev->pos_shift);
683 #if 0
684                         printk("bdbar[%i] = 0x%x [0x%x]\n",
685                                idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
686 #endif
687                 }
688                 ichdev->frags = ichdev->size / ichdev->fragsize;
689         }
690         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
691         ichdev->civ = 0;
692         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
693         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
694         ichdev->position = 0;
695 #if 0
696         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
697                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
698 #endif
699         /* clear interrupts */
700         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
701 }
702
703 #ifdef __i386__
704 /*
705  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
706  * which aborts PCI busmaster for audio transfer.  A workaround is to set
707  * the pages as non-cached.  For details, see the errata in
708  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
709  */
710 static void fill_nocache(void *buf, int size, int nocache)
711 {
712         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
713         if (nocache)
714                 set_pages_uc(virt_to_page(buf), size);
715         else
716                 set_pages_wb(virt_to_page(buf), size);
717 }
718 #else
719 #define fill_nocache(buf, size, nocache) do { ; } while (0)
720 #endif
721
722 /*
723  *  Interrupt handler
724  */
725
726 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
727 {
728         unsigned long port = ichdev->reg_offset;
729         unsigned long flags;
730         int status, civ, i, step;
731         int ack = 0;
732
733         spin_lock_irqsave(&chip->reg_lock, flags);
734         status = igetbyte(chip, port + ichdev->roff_sr);
735         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
736         if (!(status & ICH_BCIS)) {
737                 step = 0;
738         } else if (civ == ichdev->civ) {
739                 // snd_printd("civ same %d\n", civ);
740                 step = 1;
741                 ichdev->civ++;
742                 ichdev->civ &= ICH_REG_LVI_MASK;
743         } else {
744                 step = civ - ichdev->civ;
745                 if (step < 0)
746                         step += ICH_REG_LVI_MASK + 1;
747                 // if (step != 1)
748                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
749                 ichdev->civ = civ;
750         }
751
752         ichdev->position += step * ichdev->fragsize1;
753         if (! chip->in_measurement)
754                 ichdev->position %= ichdev->size;
755         ichdev->lvi += step;
756         ichdev->lvi &= ICH_REG_LVI_MASK;
757         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
758         for (i = 0; i < step; i++) {
759                 ichdev->lvi_frag++;
760                 ichdev->lvi_frag %= ichdev->frags;
761                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
762 #if 0
763         printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
764                ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
765                ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
766                inl(port + 4), inb(port + ICH_REG_OFF_CR));
767 #endif
768                 if (--ichdev->ack == 0) {
769                         ichdev->ack = ichdev->ack_reload;
770                         ack = 1;
771                 }
772         }
773         spin_unlock_irqrestore(&chip->reg_lock, flags);
774         if (ack && ichdev->substream) {
775                 snd_pcm_period_elapsed(ichdev->substream);
776         }
777         iputbyte(chip, port + ichdev->roff_sr,
778                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
779 }
780
781 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
782 {
783         struct intel8x0 *chip = dev_id;
784         struct ichdev *ichdev;
785         unsigned int status;
786         unsigned int i;
787
788         status = igetdword(chip, chip->int_sta_reg);
789         if (status == 0xffffffff)       /* we are not yet resumed */
790                 return IRQ_NONE;
791
792         if ((status & chip->int_sta_mask) == 0) {
793                 if (status) {
794                         /* ack */
795                         iputdword(chip, chip->int_sta_reg, status);
796                         if (! chip->buggy_irq)
797                                 status = 0;
798                 }
799                 return IRQ_RETVAL(status);
800         }
801
802         for (i = 0; i < chip->bdbars_count; i++) {
803                 ichdev = &chip->ichd[i];
804                 if (status & ichdev->int_sta_mask)
805                         snd_intel8x0_update(chip, ichdev);
806         }
807
808         /* ack them */
809         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
810         
811         return IRQ_HANDLED;
812 }
813
814 /*
815  *  PCM part
816  */
817
818 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
819 {
820         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
821         struct ichdev *ichdev = get_ichdev(substream);
822         unsigned char val = 0;
823         unsigned long port = ichdev->reg_offset;
824
825         switch (cmd) {
826         case SNDRV_PCM_TRIGGER_RESUME:
827                 ichdev->suspended = 0;
828                 /* fallthru */
829         case SNDRV_PCM_TRIGGER_START:
830                 val = ICH_IOCE | ICH_STARTBM;
831                 break;
832         case SNDRV_PCM_TRIGGER_SUSPEND:
833                 ichdev->suspended = 1;
834                 /* fallthru */
835         case SNDRV_PCM_TRIGGER_STOP:
836                 val = 0;
837                 break;
838         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
839                 val = ICH_IOCE;
840                 break;
841         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
842                 val = ICH_IOCE | ICH_STARTBM;
843                 break;
844         default:
845                 return -EINVAL;
846         }
847         iputbyte(chip, port + ICH_REG_OFF_CR, val);
848         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
849                 /* wait until DMA stopped */
850                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
851                 /* reset whole DMA things */
852                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
853         }
854         return 0;
855 }
856
857 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
858 {
859         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
860         struct ichdev *ichdev = get_ichdev(substream);
861         unsigned long port = ichdev->reg_offset;
862         static int fiforeg[] = {
863                 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
864         };
865         unsigned int val, fifo;
866
867         val = igetdword(chip, ICHREG(ALI_DMACR));
868         switch (cmd) {
869         case SNDRV_PCM_TRIGGER_RESUME:
870                 ichdev->suspended = 0;
871                 /* fallthru */
872         case SNDRV_PCM_TRIGGER_START:
873         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
874                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
875                         /* clear FIFO for synchronization of channels */
876                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
877                         fifo &= ~(0xff << (ichdev->ali_slot % 4));  
878                         fifo |= 0x83 << (ichdev->ali_slot % 4); 
879                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
880                 }
881                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
882                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
883                 /* start DMA */
884                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
885                 break;
886         case SNDRV_PCM_TRIGGER_SUSPEND:
887                 ichdev->suspended = 1;
888                 /* fallthru */
889         case SNDRV_PCM_TRIGGER_STOP:
890         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
891                 /* pause */
892                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
893                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
894                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
895                         ;
896                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
897                         break;
898                 /* reset whole DMA things */
899                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
900                 /* clear interrupts */
901                 iputbyte(chip, port + ICH_REG_OFF_SR,
902                          igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
903                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
904                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
905                 break;
906         default:
907                 return -EINVAL;
908         }
909         return 0;
910 }
911
912 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
913                                   struct snd_pcm_hw_params *hw_params)
914 {
915         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
916         struct ichdev *ichdev = get_ichdev(substream);
917         struct snd_pcm_runtime *runtime = substream->runtime;
918         int dbl = params_rate(hw_params) > 48000;
919         int err;
920
921         if (chip->fix_nocache && ichdev->page_attr_changed) {
922                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
923                 ichdev->page_attr_changed = 0;
924         }
925         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
926         if (err < 0)
927                 return err;
928         if (chip->fix_nocache) {
929                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
930                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
931                         ichdev->page_attr_changed = 1;
932                 }
933         }
934         if (ichdev->pcm_open_flag) {
935                 snd_ac97_pcm_close(ichdev->pcm);
936                 ichdev->pcm_open_flag = 0;
937         }
938         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
939                                 params_channels(hw_params),
940                                 ichdev->pcm->r[dbl].slots);
941         if (err >= 0) {
942                 ichdev->pcm_open_flag = 1;
943                 /* Force SPDIF setting */
944                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
945                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
946                                           params_rate(hw_params));
947         }
948         return err;
949 }
950
951 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
952 {
953         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
954         struct ichdev *ichdev = get_ichdev(substream);
955
956         if (ichdev->pcm_open_flag) {
957                 snd_ac97_pcm_close(ichdev->pcm);
958                 ichdev->pcm_open_flag = 0;
959         }
960         if (chip->fix_nocache && ichdev->page_attr_changed) {
961                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
962                 ichdev->page_attr_changed = 0;
963         }
964         return snd_pcm_lib_free_pages(substream);
965 }
966
967 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
968                                        struct snd_pcm_runtime *runtime)
969 {
970         unsigned int cnt;
971         int dbl = runtime->rate > 48000;
972
973         spin_lock_irq(&chip->reg_lock);
974         switch (chip->device_type) {
975         case DEVICE_ALI:
976                 cnt = igetdword(chip, ICHREG(ALI_SCR));
977                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
978                 if (runtime->channels == 4 || dbl)
979                         cnt |= ICH_ALI_SC_PCM_4;
980                 else if (runtime->channels == 6)
981                         cnt |= ICH_ALI_SC_PCM_6;
982                 iputdword(chip, ICHREG(ALI_SCR), cnt);
983                 break;
984         case DEVICE_SIS:
985                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
986                 cnt &= ~ICH_SIS_PCM_246_MASK;
987                 if (runtime->channels == 4 || dbl)
988                         cnt |= ICH_SIS_PCM_4;
989                 else if (runtime->channels == 6)
990                         cnt |= ICH_SIS_PCM_6;
991                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
992                 break;
993         default:
994                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
995                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
996                 if (runtime->channels == 4 || dbl)
997                         cnt |= ICH_PCM_4;
998                 else if (runtime->channels == 6)
999                         cnt |= ICH_PCM_6;
1000                 if (chip->device_type == DEVICE_NFORCE) {
1001                         /* reset to 2ch once to keep the 6 channel data in alignment,
1002                          * to start from Front Left always
1003                          */
1004                         if (cnt & ICH_PCM_246_MASK) {
1005                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1006                                 spin_unlock_irq(&chip->reg_lock);
1007                                 msleep(50); /* grrr... */
1008                                 spin_lock_irq(&chip->reg_lock);
1009                         }
1010                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1011                         if (runtime->sample_bits > 16)
1012                                 cnt |= ICH_PCM_20BIT;
1013                 }
1014                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1015                 break;
1016         }
1017         spin_unlock_irq(&chip->reg_lock);
1018 }
1019
1020 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1021 {
1022         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1023         struct snd_pcm_runtime *runtime = substream->runtime;
1024         struct ichdev *ichdev = get_ichdev(substream);
1025
1026         ichdev->physbuf = runtime->dma_addr;
1027         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1028         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1029         if (ichdev->ichd == ICHD_PCMOUT) {
1030                 snd_intel8x0_setup_pcm_out(chip, runtime);
1031                 if (chip->device_type == DEVICE_INTEL_ICH4)
1032                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1033         }
1034         snd_intel8x0_setup_periods(chip, ichdev);
1035         return 0;
1036 }
1037
1038 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1039 {
1040         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1041         struct ichdev *ichdev = get_ichdev(substream);
1042         size_t ptr1, ptr;
1043         int civ, timeout = 100;
1044         unsigned int position;
1045
1046         spin_lock(&chip->reg_lock);
1047         do {
1048                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1049                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1050                 position = ichdev->position;
1051                 if (ptr1 == 0) {
1052                         udelay(10);
1053                         continue;
1054                 }
1055                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1056                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1057                         break;
1058         } while (timeout--);
1059         ptr1 <<= ichdev->pos_shift;
1060         ptr = ichdev->fragsize1 - ptr1;
1061         ptr += position;
1062         spin_unlock(&chip->reg_lock);
1063         if (ptr >= ichdev->size)
1064                 return 0;
1065         return bytes_to_frames(substream->runtime, ptr);
1066 }
1067
1068 static struct snd_pcm_hardware snd_intel8x0_stream =
1069 {
1070         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1071                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1072                                  SNDRV_PCM_INFO_MMAP_VALID |
1073                                  SNDRV_PCM_INFO_PAUSE |
1074                                  SNDRV_PCM_INFO_RESUME),
1075         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1076         .rates =                SNDRV_PCM_RATE_48000,
1077         .rate_min =             48000,
1078         .rate_max =             48000,
1079         .channels_min =         2,
1080         .channels_max =         2,
1081         .buffer_bytes_max =     128 * 1024,
1082         .period_bytes_min =     32,
1083         .period_bytes_max =     128 * 1024,
1084         .periods_min =          1,
1085         .periods_max =          1024,
1086         .fifo_size =            0,
1087 };
1088
1089 static unsigned int channels4[] = {
1090         2, 4,
1091 };
1092
1093 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1094         .count = ARRAY_SIZE(channels4),
1095         .list = channels4,
1096         .mask = 0,
1097 };
1098
1099 static unsigned int channels6[] = {
1100         2, 4, 6,
1101 };
1102
1103 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1104         .count = ARRAY_SIZE(channels6),
1105         .list = channels6,
1106         .mask = 0,
1107 };
1108
1109 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1110 {
1111         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1112         struct snd_pcm_runtime *runtime = substream->runtime;
1113         int err;
1114
1115         ichdev->substream = substream;
1116         runtime->hw = snd_intel8x0_stream;
1117         runtime->hw.rates = ichdev->pcm->rates;
1118         snd_pcm_limit_hw_rates(runtime);
1119         if (chip->device_type == DEVICE_SIS) {
1120                 runtime->hw.buffer_bytes_max = 64*1024;
1121                 runtime->hw.period_bytes_max = 64*1024;
1122         }
1123         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1124                 return err;
1125         runtime->private_data = ichdev;
1126         return 0;
1127 }
1128
1129 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1130 {
1131         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1132         struct snd_pcm_runtime *runtime = substream->runtime;
1133         int err;
1134
1135         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1136         if (err < 0)
1137                 return err;
1138
1139         if (chip->multi6) {
1140                 runtime->hw.channels_max = 6;
1141                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1142                                            &hw_constraints_channels6);
1143         } else if (chip->multi4) {
1144                 runtime->hw.channels_max = 4;
1145                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1146                                            &hw_constraints_channels4);
1147         }
1148         if (chip->dra) {
1149                 snd_ac97_pcm_double_rate_rules(runtime);
1150         }
1151         if (chip->smp20bit) {
1152                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1153                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1154         }
1155         return 0;
1156 }
1157
1158 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1159 {
1160         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1161
1162         chip->ichd[ICHD_PCMOUT].substream = NULL;
1163         return 0;
1164 }
1165
1166 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1167 {
1168         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1169
1170         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1171 }
1172
1173 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1174 {
1175         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1176
1177         chip->ichd[ICHD_PCMIN].substream = NULL;
1178         return 0;
1179 }
1180
1181 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1182 {
1183         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1184
1185         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1186 }
1187
1188 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1189 {
1190         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1191
1192         chip->ichd[ICHD_MIC].substream = NULL;
1193         return 0;
1194 }
1195
1196 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1197 {
1198         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1199
1200         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1201 }
1202
1203 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1204 {
1205         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1206
1207         chip->ichd[ICHD_MIC2].substream = NULL;
1208         return 0;
1209 }
1210
1211 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1212 {
1213         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1214
1215         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1216 }
1217
1218 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1219 {
1220         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1221
1222         chip->ichd[ICHD_PCM2IN].substream = NULL;
1223         return 0;
1224 }
1225
1226 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1227 {
1228         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1229         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1230
1231         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1232 }
1233
1234 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1235 {
1236         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1237         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1238
1239         chip->ichd[idx].substream = NULL;
1240         return 0;
1241 }
1242
1243 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1244 {
1245         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1246         unsigned int val;
1247
1248         spin_lock_irq(&chip->reg_lock);
1249         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1250         val |= ICH_ALI_IF_AC97SP;
1251         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1252         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1253         spin_unlock_irq(&chip->reg_lock);
1254
1255         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1256 }
1257
1258 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1259 {
1260         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1261         unsigned int val;
1262
1263         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1264         spin_lock_irq(&chip->reg_lock);
1265         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1266         val &= ~ICH_ALI_IF_AC97SP;
1267         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1268         spin_unlock_irq(&chip->reg_lock);
1269
1270         return 0;
1271 }
1272
1273 #if 0 // NYI
1274 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1275 {
1276         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1277
1278         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1279 }
1280
1281 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1282 {
1283         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1284
1285         chip->ichd[ALID_SPDIFIN].substream = NULL;
1286         return 0;
1287 }
1288
1289 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1290 {
1291         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1292
1293         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1294 }
1295
1296 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1297 {
1298         struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1299
1300         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1301         return 0;
1302 }
1303 #endif
1304
1305 static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1306         .open =         snd_intel8x0_playback_open,
1307         .close =        snd_intel8x0_playback_close,
1308         .ioctl =        snd_pcm_lib_ioctl,
1309         .hw_params =    snd_intel8x0_hw_params,
1310         .hw_free =      snd_intel8x0_hw_free,
1311         .prepare =      snd_intel8x0_pcm_prepare,
1312         .trigger =      snd_intel8x0_pcm_trigger,
1313         .pointer =      snd_intel8x0_pcm_pointer,
1314 };
1315
1316 static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1317         .open =         snd_intel8x0_capture_open,
1318         .close =        snd_intel8x0_capture_close,
1319         .ioctl =        snd_pcm_lib_ioctl,
1320         .hw_params =    snd_intel8x0_hw_params,
1321         .hw_free =      snd_intel8x0_hw_free,
1322         .prepare =      snd_intel8x0_pcm_prepare,
1323         .trigger =      snd_intel8x0_pcm_trigger,
1324         .pointer =      snd_intel8x0_pcm_pointer,
1325 };
1326
1327 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1328         .open =         snd_intel8x0_mic_open,
1329         .close =        snd_intel8x0_mic_close,
1330         .ioctl =        snd_pcm_lib_ioctl,
1331         .hw_params =    snd_intel8x0_hw_params,
1332         .hw_free =      snd_intel8x0_hw_free,
1333         .prepare =      snd_intel8x0_pcm_prepare,
1334         .trigger =      snd_intel8x0_pcm_trigger,
1335         .pointer =      snd_intel8x0_pcm_pointer,
1336 };
1337
1338 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1339         .open =         snd_intel8x0_mic2_open,
1340         .close =        snd_intel8x0_mic2_close,
1341         .ioctl =        snd_pcm_lib_ioctl,
1342         .hw_params =    snd_intel8x0_hw_params,
1343         .hw_free =      snd_intel8x0_hw_free,
1344         .prepare =      snd_intel8x0_pcm_prepare,
1345         .trigger =      snd_intel8x0_pcm_trigger,
1346         .pointer =      snd_intel8x0_pcm_pointer,
1347 };
1348
1349 static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1350         .open =         snd_intel8x0_capture2_open,
1351         .close =        snd_intel8x0_capture2_close,
1352         .ioctl =        snd_pcm_lib_ioctl,
1353         .hw_params =    snd_intel8x0_hw_params,
1354         .hw_free =      snd_intel8x0_hw_free,
1355         .prepare =      snd_intel8x0_pcm_prepare,
1356         .trigger =      snd_intel8x0_pcm_trigger,
1357         .pointer =      snd_intel8x0_pcm_pointer,
1358 };
1359
1360 static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1361         .open =         snd_intel8x0_spdif_open,
1362         .close =        snd_intel8x0_spdif_close,
1363         .ioctl =        snd_pcm_lib_ioctl,
1364         .hw_params =    snd_intel8x0_hw_params,
1365         .hw_free =      snd_intel8x0_hw_free,
1366         .prepare =      snd_intel8x0_pcm_prepare,
1367         .trigger =      snd_intel8x0_pcm_trigger,
1368         .pointer =      snd_intel8x0_pcm_pointer,
1369 };
1370
1371 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1372         .open =         snd_intel8x0_playback_open,
1373         .close =        snd_intel8x0_playback_close,
1374         .ioctl =        snd_pcm_lib_ioctl,
1375         .hw_params =    snd_intel8x0_hw_params,
1376         .hw_free =      snd_intel8x0_hw_free,
1377         .prepare =      snd_intel8x0_pcm_prepare,
1378         .trigger =      snd_intel8x0_ali_trigger,
1379         .pointer =      snd_intel8x0_pcm_pointer,
1380 };
1381
1382 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1383         .open =         snd_intel8x0_capture_open,
1384         .close =        snd_intel8x0_capture_close,
1385         .ioctl =        snd_pcm_lib_ioctl,
1386         .hw_params =    snd_intel8x0_hw_params,
1387         .hw_free =      snd_intel8x0_hw_free,
1388         .prepare =      snd_intel8x0_pcm_prepare,
1389         .trigger =      snd_intel8x0_ali_trigger,
1390         .pointer =      snd_intel8x0_pcm_pointer,
1391 };
1392
1393 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1394         .open =         snd_intel8x0_mic_open,
1395         .close =        snd_intel8x0_mic_close,
1396         .ioctl =        snd_pcm_lib_ioctl,
1397         .hw_params =    snd_intel8x0_hw_params,
1398         .hw_free =      snd_intel8x0_hw_free,
1399         .prepare =      snd_intel8x0_pcm_prepare,
1400         .trigger =      snd_intel8x0_ali_trigger,
1401         .pointer =      snd_intel8x0_pcm_pointer,
1402 };
1403
1404 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1405         .open =         snd_intel8x0_ali_ac97spdifout_open,
1406         .close =        snd_intel8x0_ali_ac97spdifout_close,
1407         .ioctl =        snd_pcm_lib_ioctl,
1408         .hw_params =    snd_intel8x0_hw_params,
1409         .hw_free =      snd_intel8x0_hw_free,
1410         .prepare =      snd_intel8x0_pcm_prepare,
1411         .trigger =      snd_intel8x0_ali_trigger,
1412         .pointer =      snd_intel8x0_pcm_pointer,
1413 };
1414
1415 #if 0 // NYI
1416 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1417         .open =         snd_intel8x0_ali_spdifin_open,
1418         .close =        snd_intel8x0_ali_spdifin_close,
1419         .ioctl =        snd_pcm_lib_ioctl,
1420         .hw_params =    snd_intel8x0_hw_params,
1421         .hw_free =      snd_intel8x0_hw_free,
1422         .prepare =      snd_intel8x0_pcm_prepare,
1423         .trigger =      snd_intel8x0_pcm_trigger,
1424         .pointer =      snd_intel8x0_pcm_pointer,
1425 };
1426
1427 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1428         .open =         snd_intel8x0_ali_spdifout_open,
1429         .close =        snd_intel8x0_ali_spdifout_close,
1430         .ioctl =        snd_pcm_lib_ioctl,
1431         .hw_params =    snd_intel8x0_hw_params,
1432         .hw_free =      snd_intel8x0_hw_free,
1433         .prepare =      snd_intel8x0_pcm_prepare,
1434         .trigger =      snd_intel8x0_pcm_trigger,
1435         .pointer =      snd_intel8x0_pcm_pointer,
1436 };
1437 #endif // NYI
1438
1439 struct ich_pcm_table {
1440         char *suffix;
1441         struct snd_pcm_ops *playback_ops;
1442         struct snd_pcm_ops *capture_ops;
1443         size_t prealloc_size;
1444         size_t prealloc_max_size;
1445         int ac97_idx;
1446 };
1447
1448 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1449                                        struct ich_pcm_table *rec)
1450 {
1451         struct snd_pcm *pcm;
1452         int err;
1453         char name[32];
1454
1455         if (rec->suffix)
1456                 sprintf(name, "Intel ICH - %s", rec->suffix);
1457         else
1458                 strcpy(name, "Intel ICH");
1459         err = snd_pcm_new(chip->card, name, device,
1460                           rec->playback_ops ? 1 : 0,
1461                           rec->capture_ops ? 1 : 0, &pcm);
1462         if (err < 0)
1463                 return err;
1464
1465         if (rec->playback_ops)
1466                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1467         if (rec->capture_ops)
1468                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1469
1470         pcm->private_data = chip;
1471         pcm->info_flags = 0;
1472         if (rec->suffix)
1473                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1474         else
1475                 strcpy(pcm->name, chip->card->shortname);
1476         chip->pcm[device] = pcm;
1477
1478         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1479                                               snd_dma_pci_data(chip->pci),
1480                                               rec->prealloc_size, rec->prealloc_max_size);
1481
1482         return 0;
1483 }
1484
1485 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1486         {
1487                 .playback_ops = &snd_intel8x0_playback_ops,
1488                 .capture_ops = &snd_intel8x0_capture_ops,
1489                 .prealloc_size = 64 * 1024,
1490                 .prealloc_max_size = 128 * 1024,
1491         },
1492         {
1493                 .suffix = "MIC ADC",
1494                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1495                 .prealloc_size = 0,
1496                 .prealloc_max_size = 128 * 1024,
1497                 .ac97_idx = ICHD_MIC,
1498         },
1499         {
1500                 .suffix = "MIC2 ADC",
1501                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1502                 .prealloc_size = 0,
1503                 .prealloc_max_size = 128 * 1024,
1504                 .ac97_idx = ICHD_MIC2,
1505         },
1506         {
1507                 .suffix = "ADC2",
1508                 .capture_ops = &snd_intel8x0_capture2_ops,
1509                 .prealloc_size = 0,
1510                 .prealloc_max_size = 128 * 1024,
1511                 .ac97_idx = ICHD_PCM2IN,
1512         },
1513         {
1514                 .suffix = "IEC958",
1515                 .playback_ops = &snd_intel8x0_spdif_ops,
1516                 .prealloc_size = 64 * 1024,
1517                 .prealloc_max_size = 128 * 1024,
1518                 .ac97_idx = ICHD_SPBAR,
1519         },
1520 };
1521
1522 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1523         {
1524                 .playback_ops = &snd_intel8x0_playback_ops,
1525                 .capture_ops = &snd_intel8x0_capture_ops,
1526                 .prealloc_size = 64 * 1024,
1527                 .prealloc_max_size = 128 * 1024,
1528         },
1529         {
1530                 .suffix = "MIC ADC",
1531                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1532                 .prealloc_size = 0,
1533                 .prealloc_max_size = 128 * 1024,
1534                 .ac97_idx = NVD_MIC,
1535         },
1536         {
1537                 .suffix = "IEC958",
1538                 .playback_ops = &snd_intel8x0_spdif_ops,
1539                 .prealloc_size = 64 * 1024,
1540                 .prealloc_max_size = 128 * 1024,
1541                 .ac97_idx = NVD_SPBAR,
1542         },
1543 };
1544
1545 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1546         {
1547                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1548                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1549                 .prealloc_size = 64 * 1024,
1550                 .prealloc_max_size = 128 * 1024,
1551         },
1552         {
1553                 .suffix = "MIC ADC",
1554                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1555                 .prealloc_size = 0,
1556                 .prealloc_max_size = 128 * 1024,
1557                 .ac97_idx = ALID_MIC,
1558         },
1559         {
1560                 .suffix = "IEC958",
1561                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1562                 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1563                 .prealloc_size = 64 * 1024,
1564                 .prealloc_max_size = 128 * 1024,
1565                 .ac97_idx = ALID_AC97SPDIFOUT,
1566         },
1567 #if 0 // NYI
1568         {
1569                 .suffix = "HW IEC958",
1570                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1571                 .prealloc_size = 64 * 1024,
1572                 .prealloc_max_size = 128 * 1024,
1573         },
1574 #endif
1575 };
1576
1577 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1578 {
1579         int i, tblsize, device, err;
1580         struct ich_pcm_table *tbl, *rec;
1581
1582         switch (chip->device_type) {
1583         case DEVICE_INTEL_ICH4:
1584                 tbl = intel_pcms;
1585                 tblsize = ARRAY_SIZE(intel_pcms);
1586                 if (spdif_aclink)
1587                         tblsize--;
1588                 break;
1589         case DEVICE_NFORCE:
1590                 tbl = nforce_pcms;
1591                 tblsize = ARRAY_SIZE(nforce_pcms);
1592                 if (spdif_aclink)
1593                         tblsize--;
1594                 break;
1595         case DEVICE_ALI:
1596                 tbl = ali_pcms;
1597                 tblsize = ARRAY_SIZE(ali_pcms);
1598                 break;
1599         default:
1600                 tbl = intel_pcms;
1601                 tblsize = 2;
1602                 break;
1603         }
1604
1605         device = 0;
1606         for (i = 0; i < tblsize; i++) {
1607                 rec = tbl + i;
1608                 if (i > 0 && rec->ac97_idx) {
1609                         /* activate PCM only when associated AC'97 codec */
1610                         if (! chip->ichd[rec->ac97_idx].pcm)
1611                                 continue;
1612                 }
1613                 err = snd_intel8x0_pcm1(chip, device, rec);
1614                 if (err < 0)
1615                         return err;
1616                 device++;
1617         }
1618
1619         chip->pcm_devs = device;
1620         return 0;
1621 }
1622         
1623
1624 /*
1625  *  Mixer part
1626  */
1627
1628 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1629 {
1630         struct intel8x0 *chip = bus->private_data;
1631         chip->ac97_bus = NULL;
1632 }
1633
1634 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1635 {
1636         struct intel8x0 *chip = ac97->private_data;
1637         chip->ac97[ac97->num] = NULL;
1638 }
1639
1640 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1641         /* front PCM */
1642         {
1643                 .exclusive = 1,
1644                 .r = {  {
1645                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1646                                          (1 << AC97_SLOT_PCM_RIGHT) |
1647                                          (1 << AC97_SLOT_PCM_CENTER) |
1648                                          (1 << AC97_SLOT_PCM_SLEFT) |
1649                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1650                                          (1 << AC97_SLOT_LFE)
1651                         },
1652                         {
1653                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1654                                          (1 << AC97_SLOT_PCM_RIGHT) |
1655                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1656                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1657                         }
1658                 }
1659         },
1660         /* PCM IN #1 */
1661         {
1662                 .stream = 1,
1663                 .exclusive = 1,
1664                 .r = {  {
1665                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1666                                          (1 << AC97_SLOT_PCM_RIGHT)
1667                         }
1668                 }
1669         },
1670         /* MIC IN #1 */
1671         {
1672                 .stream = 1,
1673                 .exclusive = 1,
1674                 .r = {  {
1675                                 .slots = (1 << AC97_SLOT_MIC)
1676                         }
1677                 }
1678         },
1679         /* S/PDIF PCM */
1680         {
1681                 .exclusive = 1,
1682                 .spdif = 1,
1683                 .r = {  {
1684                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1685                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1686                         }
1687                 }
1688         },
1689         /* PCM IN #2 */
1690         {
1691                 .stream = 1,
1692                 .exclusive = 1,
1693                 .r = {  {
1694                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1695                                          (1 << AC97_SLOT_PCM_RIGHT)
1696                         }
1697                 }
1698         },
1699         /* MIC IN #2 */
1700         {
1701                 .stream = 1,
1702                 .exclusive = 1,
1703                 .r = {  {
1704                                 .slots = (1 << AC97_SLOT_MIC)
1705                         }
1706                 }
1707         },
1708 };
1709
1710 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1711         {
1712                 .subvendor = 0x0e11,
1713                 .subdevice = 0x008a,
1714                 .name = "Compaq Evo W4000",     /* AD1885 */
1715                 .type = AC97_TUNE_HP_ONLY
1716         },
1717         {
1718                 .subvendor = 0x0e11,
1719                 .subdevice = 0x00b8,
1720                 .name = "Compaq Evo D510C",
1721                 .type = AC97_TUNE_HP_ONLY
1722         },
1723         {
1724                 .subvendor = 0x0e11,
1725                 .subdevice = 0x0860,
1726                 .name = "HP/Compaq nx7010",
1727                 .type = AC97_TUNE_MUTE_LED
1728         },
1729         {
1730                 .subvendor = 0x1014,
1731                 .subdevice = 0x1f00,
1732                 .name = "MS-9128",
1733                 .type = AC97_TUNE_ALC_JACK
1734         },
1735         {
1736                 .subvendor = 0x1014,
1737                 .subdevice = 0x0267,
1738                 .name = "IBM NetVista A30p",    /* AD1981B */
1739                 .type = AC97_TUNE_HP_ONLY
1740         },
1741         {
1742                 .subvendor = 0x1025,
1743                 .subdevice = 0x0083,
1744                 .name = "Acer Aspire 3003LCi",
1745                 .type = AC97_TUNE_HP_ONLY
1746         },
1747         {
1748                 .subvendor = 0x1028,
1749                 .subdevice = 0x00d8,
1750                 .name = "Dell Precision 530",   /* AD1885 */
1751                 .type = AC97_TUNE_HP_ONLY
1752         },
1753         {
1754                 .subvendor = 0x1028,
1755                 .subdevice = 0x010d,
1756                 .name = "Dell", /* which model?  AD1885 */
1757                 .type = AC97_TUNE_HP_ONLY
1758         },
1759         {
1760                 .subvendor = 0x1028,
1761                 .subdevice = 0x0126,
1762                 .name = "Dell Optiplex GX260",  /* AD1981A */
1763                 .type = AC97_TUNE_HP_ONLY
1764         },
1765         {
1766                 .subvendor = 0x1028,
1767                 .subdevice = 0x012c,
1768                 .name = "Dell Precision 650",   /* AD1981A */
1769                 .type = AC97_TUNE_HP_ONLY
1770         },
1771         {
1772                 .subvendor = 0x1028,
1773                 .subdevice = 0x012d,
1774                 .name = "Dell Precision 450",   /* AD1981B*/
1775                 .type = AC97_TUNE_HP_ONLY
1776         },
1777         {
1778                 .subvendor = 0x1028,
1779                 .subdevice = 0x0147,
1780                 .name = "Dell", /* which model?  AD1981B*/
1781                 .type = AC97_TUNE_HP_ONLY
1782         },
1783         {
1784                 .subvendor = 0x1028,
1785                 .subdevice = 0x0151,
1786                 .name = "Dell Optiplex GX270",  /* AD1981B */
1787                 .type = AC97_TUNE_HP_ONLY
1788         },
1789         {
1790                 .subvendor = 0x1028,
1791                 .subdevice = 0x014e,
1792                 .name = "Dell D800", /* STAC9750/51 */
1793                 .type = AC97_TUNE_HP_ONLY
1794         },
1795         {
1796                 .subvendor = 0x1028,
1797                 .subdevice = 0x0163,
1798                 .name = "Dell Unknown", /* STAC9750/51 */
1799                 .type = AC97_TUNE_HP_ONLY
1800         },
1801         {
1802                 .subvendor = 0x1028,
1803                 .subdevice = 0x0186,
1804                 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1805                 .type = AC97_TUNE_HP_MUTE_LED
1806         },
1807         {
1808                 .subvendor = 0x1028,
1809                 .subdevice = 0x0188,
1810                 .name = "Dell Inspiron 6000",
1811                 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
1812         },
1813         {
1814                 .subvendor = 0x1028,
1815                 .subdevice = 0x0191,
1816                 .name = "Dell Inspiron 8600",
1817                 .type = AC97_TUNE_HP_ONLY
1818         },
1819         {
1820                 .subvendor = 0x103c,
1821                 .subdevice = 0x006d,
1822                 .name = "HP zv5000",
1823                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1824         },
1825         {       /* FIXME: which codec? */
1826                 .subvendor = 0x103c,
1827                 .subdevice = 0x00c3,
1828                 .name = "HP xw6000",
1829                 .type = AC97_TUNE_HP_ONLY
1830         },
1831         {
1832                 .subvendor = 0x103c,
1833                 .subdevice = 0x088c,
1834                 .name = "HP nc8000",
1835                 .type = AC97_TUNE_HP_MUTE_LED
1836         },
1837         {
1838                 .subvendor = 0x103c,
1839                 .subdevice = 0x0890,
1840                 .name = "HP nc6000",
1841                 .type = AC97_TUNE_MUTE_LED
1842         },
1843         {
1844                 .subvendor = 0x103c,
1845                 .subdevice = 0x0934,
1846                 .name = "HP nx8220",
1847                 .type = AC97_TUNE_MUTE_LED
1848         },
1849         {
1850                 .subvendor = 0x103c,
1851                 .subdevice = 0x129d,
1852                 .name = "HP xw8000",
1853                 .type = AC97_TUNE_HP_ONLY
1854         },
1855         {
1856                 .subvendor = 0x103c,
1857                 .subdevice = 0x0938,
1858                 .name = "HP nc4200",
1859                 .type = AC97_TUNE_HP_MUTE_LED
1860         },
1861         {
1862                 .subvendor = 0x103c,
1863                 .subdevice = 0x099c,
1864                 .name = "HP nx6110/nc6120",
1865                 .type = AC97_TUNE_HP_MUTE_LED
1866         },
1867         {
1868                 .subvendor = 0x103c,
1869                 .subdevice = 0x0944,
1870                 .name = "HP nc6220",
1871                 .type = AC97_TUNE_HP_MUTE_LED
1872         },
1873         {
1874                 .subvendor = 0x103c,
1875                 .subdevice = 0x0934,
1876                 .name = "HP nc8220",
1877                 .type = AC97_TUNE_HP_MUTE_LED
1878         },
1879         {
1880                 .subvendor = 0x103c,
1881                 .subdevice = 0x12f1,
1882                 .name = "HP xw8200",    /* AD1981B*/
1883                 .type = AC97_TUNE_HP_ONLY
1884         },
1885         {
1886                 .subvendor = 0x103c,
1887                 .subdevice = 0x12f2,
1888                 .name = "HP xw6200",
1889                 .type = AC97_TUNE_HP_ONLY
1890         },
1891         {
1892                 .subvendor = 0x103c,
1893                 .subdevice = 0x3008,
1894                 .name = "HP xw4200",    /* AD1981B*/
1895                 .type = AC97_TUNE_HP_ONLY
1896         },
1897         {
1898                 .subvendor = 0x104d,
1899                 .subdevice = 0x8197,
1900                 .name = "Sony S1XP",
1901                 .type = AC97_TUNE_INV_EAPD
1902         },
1903         {
1904                 .subvendor = 0x1043,
1905                 .subdevice = 0x80f3,
1906                 .name = "ASUS ICH5/AD1985",
1907                 .type = AC97_TUNE_AD_SHARING
1908         },
1909         {
1910                 .subvendor = 0x10cf,
1911                 .subdevice = 0x11c3,
1912                 .name = "Fujitsu-Siemens E4010",
1913                 .type = AC97_TUNE_HP_ONLY
1914         },
1915         {
1916                 .subvendor = 0x10cf,
1917                 .subdevice = 0x1225,
1918                 .name = "Fujitsu-Siemens T3010",
1919                 .type = AC97_TUNE_HP_ONLY
1920         },
1921         {
1922                 .subvendor = 0x10cf,
1923                 .subdevice = 0x1253,
1924                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1925                 .type = AC97_TUNE_HP_ONLY
1926         },
1927         {
1928                 .subvendor = 0x10cf,
1929                 .subdevice = 0x127e,
1930                 .name = "Fujitsu Lifebook C1211D",
1931                 .type = AC97_TUNE_HP_ONLY
1932         },
1933         {
1934                 .subvendor = 0x10cf,
1935                 .subdevice = 0x12ec,
1936                 .name = "Fujitsu-Siemens 4010",
1937                 .type = AC97_TUNE_HP_ONLY
1938         },
1939         {
1940                 .subvendor = 0x10cf,
1941                 .subdevice = 0x12f2,
1942                 .name = "Fujitsu-Siemens Celsius H320",
1943                 .type = AC97_TUNE_SWAP_HP
1944         },
1945         {
1946                 .subvendor = 0x10f1,
1947                 .subdevice = 0x2665,
1948                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1949                 .type = AC97_TUNE_HP_ONLY
1950         },
1951         {
1952                 .subvendor = 0x10f1,
1953                 .subdevice = 0x2885,
1954                 .name = "AMD64 Mobo",   /* ALC650 */
1955                 .type = AC97_TUNE_HP_ONLY
1956         },
1957         {
1958                 .subvendor = 0x10f1,
1959                 .subdevice = 0x2895,
1960                 .name = "Tyan Thunder K8WE",
1961                 .type = AC97_TUNE_HP_ONLY
1962         },
1963         {
1964                 .subvendor = 0x10f7,
1965                 .subdevice = 0x834c,
1966                 .name = "Panasonic CF-R4",
1967                 .type = AC97_TUNE_HP_ONLY,
1968         },
1969         {
1970                 .subvendor = 0x110a,
1971                 .subdevice = 0x0056,
1972                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1973                 .type = AC97_TUNE_HP_ONLY
1974         },
1975         {
1976                 .subvendor = 0x11d4,
1977                 .subdevice = 0x5375,
1978                 .name = "ADI AD1985 (discrete)",
1979                 .type = AC97_TUNE_HP_ONLY
1980         },
1981         {
1982                 .subvendor = 0x1462,
1983                 .subdevice = 0x5470,
1984                 .name = "MSI P4 ATX 645 Ultra",
1985                 .type = AC97_TUNE_HP_ONLY
1986         },
1987         {
1988                 .subvendor = 0x1734,
1989                 .subdevice = 0x0088,
1990                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1991                 .type = AC97_TUNE_HP_ONLY
1992         },
1993         {
1994                 .subvendor = 0x8086,
1995                 .subdevice = 0x2000,
1996                 .mask = 0xfff0,
1997                 .name = "Intel ICH5/AD1985",
1998                 .type = AC97_TUNE_AD_SHARING
1999         },
2000         {
2001                 .subvendor = 0x8086,
2002                 .subdevice = 0x4000,
2003                 .mask = 0xfff0,
2004                 .name = "Intel ICH5/AD1985",
2005                 .type = AC97_TUNE_AD_SHARING
2006         },
2007         {
2008                 .subvendor = 0x8086,
2009                 .subdevice = 0x4856,
2010                 .name = "Intel D845WN (82801BA)",
2011                 .type = AC97_TUNE_SWAP_HP
2012         },
2013         {
2014                 .subvendor = 0x8086,
2015                 .subdevice = 0x4d44,
2016                 .name = "Intel D850EMV2",       /* AD1885 */
2017                 .type = AC97_TUNE_HP_ONLY
2018         },
2019         {
2020                 .subvendor = 0x8086,
2021                 .subdevice = 0x4d56,
2022                 .name = "Intel ICH/AD1885",
2023                 .type = AC97_TUNE_HP_ONLY
2024         },
2025         {
2026                 .subvendor = 0x8086,
2027                 .subdevice = 0x6000,
2028                 .mask = 0xfff0,
2029                 .name = "Intel ICH5/AD1985",
2030                 .type = AC97_TUNE_AD_SHARING
2031         },
2032         {
2033                 .subvendor = 0x8086,
2034                 .subdevice = 0xe000,
2035                 .mask = 0xfff0,
2036                 .name = "Intel ICH5/AD1985",
2037                 .type = AC97_TUNE_AD_SHARING
2038         },
2039 #if 0 /* FIXME: this seems wrong on most boards */
2040         {
2041                 .subvendor = 0x8086,
2042                 .subdevice = 0xa000,
2043                 .mask = 0xfff0,
2044                 .name = "Intel ICH5/AD1985",
2045                 .type = AC97_TUNE_HP_ONLY
2046         },
2047 #endif
2048         { } /* terminator */
2049 };
2050
2051 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2052                                         const char *quirk_override)
2053 {
2054         struct snd_ac97_bus *pbus;
2055         struct snd_ac97_template ac97;
2056         int err;
2057         unsigned int i, codecs;
2058         unsigned int glob_sta = 0;
2059         struct snd_ac97_bus_ops *ops;
2060         static struct snd_ac97_bus_ops standard_bus_ops = {
2061                 .write = snd_intel8x0_codec_write,
2062                 .read = snd_intel8x0_codec_read,
2063         };
2064         static struct snd_ac97_bus_ops ali_bus_ops = {
2065                 .write = snd_intel8x0_ali_codec_write,
2066                 .read = snd_intel8x0_ali_codec_read,
2067         };
2068
2069         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2070         if (!spdif_aclink) {
2071                 switch (chip->device_type) {
2072                 case DEVICE_NFORCE:
2073                         chip->spdif_idx = NVD_SPBAR;
2074                         break;
2075                 case DEVICE_ALI:
2076                         chip->spdif_idx = ALID_AC97SPDIFOUT;
2077                         break;
2078                 case DEVICE_INTEL_ICH4:
2079                         chip->spdif_idx = ICHD_SPBAR;
2080                         break;
2081                 };
2082         }
2083
2084         chip->in_ac97_init = 1;
2085         
2086         memset(&ac97, 0, sizeof(ac97));
2087         ac97.private_data = chip;
2088         ac97.private_free = snd_intel8x0_mixer_free_ac97;
2089         ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
2090         if (chip->xbox)
2091                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2092         if (chip->device_type != DEVICE_ALI) {
2093                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2094                 ops = &standard_bus_ops;
2095                 chip->in_sdin_init = 1;
2096                 codecs = 0;
2097                 for (i = 0; i < chip->max_codecs; i++) {
2098                         if (! (glob_sta & chip->codec_bit[i]))
2099                                 continue;
2100                         if (chip->device_type == DEVICE_INTEL_ICH4) {
2101                                 snd_intel8x0_codec_read_test(chip, codecs);
2102                                 chip->ac97_sdin[codecs] =
2103                                         igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2104                                 snd_assert(chip->ac97_sdin[codecs] < 3,
2105                                            chip->ac97_sdin[codecs] = 0);
2106                         } else
2107                                 chip->ac97_sdin[codecs] = i;
2108                         codecs++;
2109                 }
2110                 chip->in_sdin_init = 0;
2111                 if (! codecs)
2112                         codecs = 1;
2113         } else {
2114                 ops = &ali_bus_ops;
2115                 codecs = 1;
2116                 /* detect the secondary codec */
2117                 for (i = 0; i < 100; i++) {
2118                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2119                         if (reg & 0x40) {
2120                                 codecs = 2;
2121                                 break;
2122                         }
2123                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2124                         udelay(1);
2125                 }
2126         }
2127         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2128                 goto __err;
2129         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2130         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2131                 pbus->clock = ac97_clock;
2132         /* FIXME: my test board doesn't work well with VRA... */
2133         if (chip->device_type == DEVICE_ALI)
2134                 pbus->no_vra = 1;
2135         else
2136                 pbus->dra = 1;
2137         chip->ac97_bus = pbus;
2138         chip->ncodecs = codecs;
2139
2140         ac97.pci = chip->pci;
2141         for (i = 0; i < codecs; i++) {
2142                 ac97.num = i;
2143                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2144                         if (err != -EACCES)
2145                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2146                         if (i == 0)
2147                                 goto __err;
2148                 }
2149         }
2150         /* tune up the primary codec */
2151         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2152         /* enable separate SDINs for ICH4 */
2153         if (chip->device_type == DEVICE_INTEL_ICH4)
2154                 pbus->isdin = 1;
2155         /* find the available PCM streams */
2156         i = ARRAY_SIZE(ac97_pcm_defs);
2157         if (chip->device_type != DEVICE_INTEL_ICH4)
2158                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2159         if (chip->spdif_idx < 0)
2160                 i--;            /* do not allocate S/PDIF */
2161         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2162         if (err < 0)
2163                 goto __err;
2164         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2165         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2166         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2167         if (chip->spdif_idx >= 0)
2168                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2169         if (chip->device_type == DEVICE_INTEL_ICH4) {
2170                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2171                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2172         }
2173         /* enable separate SDINs for ICH4 */
2174         if (chip->device_type == DEVICE_INTEL_ICH4) {
2175                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2176                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2177                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2178                 if (pcm) {
2179                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2180                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2181                         for (i = 1; i < 4; i++) {
2182                                 if (pcm->r[0].codec[i]) {
2183                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2184                                         break;
2185                                 }
2186                         }
2187                 } else {
2188                         tmp &= ~ICH_SE; /* steer disable */
2189                 }
2190                 iputbyte(chip, ICHREG(SDM), tmp);
2191         }
2192         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2193                 chip->multi4 = 1;
2194                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2195                         chip->multi6 = 1;
2196         }
2197         if (pbus->pcms[0].r[1].rslots[0]) {
2198                 chip->dra = 1;
2199         }
2200         if (chip->device_type == DEVICE_INTEL_ICH4) {
2201                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2202                         chip->smp20bit = 1;
2203         }
2204         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2205                 /* 48kHz only */
2206                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2207         }
2208         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2209                 /* use slot 10/11 for SPDIF */
2210                 u32 val;
2211                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2212                 val |= ICH_PCM_SPDIF_1011;
2213                 iputdword(chip, ICHREG(GLOB_CNT), val);
2214                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2215         }
2216         chip->in_ac97_init = 0;
2217         return 0;
2218
2219  __err:
2220         /* clear the cold-reset bit for the next chance */
2221         if (chip->device_type != DEVICE_ALI)
2222                 iputdword(chip, ICHREG(GLOB_CNT),
2223                           igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2224         return err;
2225 }
2226
2227
2228 /*
2229  *
2230  */
2231
2232 static void do_ali_reset(struct intel8x0 *chip)
2233 {
2234         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2235         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2236         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2237         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2238         iputdword(chip, ICHREG(ALI_INTERFACECR),
2239                   ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2240         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2241         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2242 }
2243
2244 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
2245 {
2246         unsigned long end_time;
2247         unsigned int cnt, status, nstatus;
2248         
2249         /* put logic to right state */
2250         /* first clear status bits */
2251         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2252         if (chip->device_type == DEVICE_NFORCE)
2253                 status |= ICH_NVSPINT;
2254         cnt = igetdword(chip, ICHREG(GLOB_STA));
2255         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2256
2257         /* ACLink on, 2 channels */
2258         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2259         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2260 #ifdef CONFIG_SND_AC97_POWER_SAVE
2261         /* do cold reset - the full ac97 powerdown may leave the controller
2262          * in a warm state but actually it cannot communicate with the codec.
2263          */
2264         iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2265         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2266         udelay(10);
2267         iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2268         msleep(1);
2269 #else
2270         /* finish cold or do warm reset */
2271         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2272         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2273         end_time = (jiffies + (HZ / 4)) + 1;
2274         do {
2275                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2276                         goto __ok;
2277                 schedule_timeout_uninterruptible(1);
2278         } while (time_after_eq(end_time, jiffies));
2279         snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2280                    igetdword(chip, ICHREG(GLOB_CNT)));
2281         return -EIO;
2282
2283       __ok:
2284 #endif
2285         if (probing) {
2286                 /* wait for any codec ready status.
2287                  * Once it becomes ready it should remain ready
2288                  * as long as we do not disable the ac97 link.
2289                  */
2290                 end_time = jiffies + HZ;
2291                 do {
2292                         status = igetdword(chip, ICHREG(GLOB_STA)) &
2293                                 chip->codec_isr_bits;
2294                         if (status)
2295                                 break;
2296                         schedule_timeout_uninterruptible(1);
2297                 } while (time_after_eq(end_time, jiffies));
2298                 if (! status) {
2299                         /* no codec is found */
2300                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2301                                    igetdword(chip, ICHREG(GLOB_STA)));
2302                         return -EIO;
2303                 }
2304
2305                 /* wait for other codecs ready status. */
2306                 end_time = jiffies + HZ / 4;
2307                 while (status != chip->codec_isr_bits &&
2308                        time_after_eq(end_time, jiffies)) {
2309                         schedule_timeout_uninterruptible(1);
2310                         status |= igetdword(chip, ICHREG(GLOB_STA)) &
2311                                 chip->codec_isr_bits;
2312                 }
2313
2314         } else {
2315                 /* resume phase */
2316                 int i;
2317                 status = 0;
2318                 for (i = 0; i < chip->ncodecs; i++)
2319                         if (chip->ac97[i])
2320                                 status |= chip->codec_bit[chip->ac97_sdin[i]];
2321                 /* wait until all the probed codecs are ready */
2322                 end_time = jiffies + HZ;
2323                 do {
2324                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2325                                 chip->codec_isr_bits;
2326                         if (status == nstatus)
2327                                 break;
2328                         schedule_timeout_uninterruptible(1);
2329                 } while (time_after_eq(end_time, jiffies));
2330         }
2331
2332         if (chip->device_type == DEVICE_SIS) {
2333                 /* unmute the output on SIS7012 */
2334                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2335         }
2336         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2337                 /* enable SPDIF interrupt */
2338                 unsigned int val;
2339                 pci_read_config_dword(chip->pci, 0x4c, &val);
2340                 val |= 0x1000000;
2341                 pci_write_config_dword(chip->pci, 0x4c, val);
2342         }
2343         return 0;
2344 }
2345
2346 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
2347 {
2348         u32 reg;
2349         int i = 0;
2350
2351         reg = igetdword(chip, ICHREG(ALI_SCR));
2352         if ((reg & 2) == 0)     /* Cold required */
2353                 reg |= 2;
2354         else
2355                 reg |= 1;       /* Warm */
2356         reg &= ~0x80000000;     /* ACLink on */
2357         iputdword(chip, ICHREG(ALI_SCR), reg);
2358
2359         for (i = 0; i < HZ / 2; i++) {
2360                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2361                         goto __ok;
2362                 schedule_timeout_uninterruptible(1);
2363         }
2364         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2365         if (probing)
2366                 return -EIO;
2367
2368  __ok:
2369         for (i = 0; i < HZ / 2; i++) {
2370                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2371                 if (reg & 0x80) /* primary codec */
2372                         break;
2373                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2374                 schedule_timeout_uninterruptible(1);
2375         }
2376
2377         do_ali_reset(chip);
2378         return 0;
2379 }
2380
2381 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
2382 {
2383         unsigned int i, timeout;
2384         int err;
2385         
2386         if (chip->device_type != DEVICE_ALI) {
2387                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2388                         return err;
2389                 iagetword(chip, 0);     /* clear semaphore flag */
2390         } else {
2391                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2392                         return err;
2393         }
2394
2395         /* disable interrupts */
2396         for (i = 0; i < chip->bdbars_count; i++)
2397                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2398         /* reset channels */
2399         for (i = 0; i < chip->bdbars_count; i++)
2400                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2401         for (i = 0; i < chip->bdbars_count; i++) {
2402                 timeout = 100000;
2403                 while (--timeout != 0) {
2404                         if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2405                                 break;
2406                 }
2407                 if (timeout == 0)
2408                         printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2409         }
2410         /* initialize Buffer Descriptor Lists */
2411         for (i = 0; i < chip->bdbars_count; i++)
2412                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2413                           chip->ichd[i].bdbar_addr);
2414         return 0;
2415 }
2416
2417 static int snd_intel8x0_free(struct intel8x0 *chip)
2418 {
2419         unsigned int i;
2420
2421         if (chip->irq < 0)
2422                 goto __hw_end;
2423         /* disable interrupts */
2424         for (i = 0; i < chip->bdbars_count; i++)
2425                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2426         /* reset channels */
2427         for (i = 0; i < chip->bdbars_count; i++)
2428                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2429         if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
2430                 /* stop the spdif interrupt */
2431                 unsigned int val;
2432                 pci_read_config_dword(chip->pci, 0x4c, &val);
2433                 val &= ~0x1000000;
2434                 pci_write_config_dword(chip->pci, 0x4c, val);
2435         }
2436         /* --- */
2437         synchronize_irq(chip->irq);
2438       __hw_end:
2439         if (chip->irq >= 0)
2440                 free_irq(chip->irq, chip);
2441         if (chip->bdbars.area) {
2442                 if (chip->fix_nocache)
2443                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2444                 snd_dma_free_pages(&chip->bdbars);
2445         }
2446         if (chip->addr)
2447                 pci_iounmap(chip->pci, chip->addr);
2448         if (chip->bmaddr)
2449                 pci_iounmap(chip->pci, chip->bmaddr);
2450         pci_release_regions(chip->pci);
2451         pci_disable_device(chip->pci);
2452         kfree(chip);
2453         return 0;
2454 }
2455
2456 #ifdef CONFIG_PM
2457 /*
2458  * power management
2459  */
2460 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
2461 {
2462         struct snd_card *card = pci_get_drvdata(pci);
2463         struct intel8x0 *chip = card->private_data;
2464         int i;
2465
2466         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2467         for (i = 0; i < chip->pcm_devs; i++)
2468                 snd_pcm_suspend_all(chip->pcm[i]);
2469         /* clear nocache */
2470         if (chip->fix_nocache) {
2471                 for (i = 0; i < chip->bdbars_count; i++) {
2472                         struct ichdev *ichdev = &chip->ichd[i];
2473                         if (ichdev->substream && ichdev->page_attr_changed) {
2474                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2475                                 if (runtime->dma_area)
2476                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2477                         }
2478                 }
2479         }
2480         for (i = 0; i < chip->ncodecs; i++)
2481                 snd_ac97_suspend(chip->ac97[i]);
2482         if (chip->device_type == DEVICE_INTEL_ICH4)
2483                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2484
2485         if (chip->irq >= 0) {
2486                 synchronize_irq(chip->irq);
2487                 free_irq(chip->irq, chip);
2488                 chip->irq = -1;
2489         }
2490         pci_disable_device(pci);
2491         pci_save_state(pci);
2492         /* The call below may disable built-in speaker on some laptops
2493          * after S2RAM.  So, don't touch it.
2494          */
2495         /* pci_set_power_state(pci, pci_choose_state(pci, state)); */
2496         return 0;
2497 }
2498
2499 static int intel8x0_resume(struct pci_dev *pci)
2500 {
2501         struct snd_card *card = pci_get_drvdata(pci);
2502         struct intel8x0 *chip = card->private_data;
2503         int i;
2504
2505         pci_set_power_state(pci, PCI_D0);
2506         pci_restore_state(pci);
2507         if (pci_enable_device(pci) < 0) {
2508                 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2509                        "disabling device\n");
2510                 snd_card_disconnect(card);
2511                 return -EIO;
2512         }
2513         pci_set_master(pci);
2514         snd_intel8x0_chip_init(chip, 0);
2515         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2516                         IRQF_SHARED, card->shortname, chip)) {
2517                 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2518                        "disabling device\n", pci->irq);
2519                 snd_card_disconnect(card);
2520                 return -EIO;
2521         }
2522         chip->irq = pci->irq;
2523         synchronize_irq(chip->irq);
2524
2525         /* re-initialize mixer stuff */
2526         if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
2527                 /* enable separate SDINs for ICH4 */
2528                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2529                 /* use slot 10/11 for SPDIF */
2530                 iputdword(chip, ICHREG(GLOB_CNT),
2531                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2532                           ICH_PCM_SPDIF_1011);
2533         }
2534
2535         /* refill nocache */
2536         if (chip->fix_nocache)
2537                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2538
2539         for (i = 0; i < chip->ncodecs; i++)
2540                 snd_ac97_resume(chip->ac97[i]);
2541
2542         /* refill nocache */
2543         if (chip->fix_nocache) {
2544                 for (i = 0; i < chip->bdbars_count; i++) {
2545                         struct ichdev *ichdev = &chip->ichd[i];
2546                         if (ichdev->substream && ichdev->page_attr_changed) {
2547                                 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
2548                                 if (runtime->dma_area)
2549                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2550                         }
2551                 }
2552         }
2553
2554         /* resume status */
2555         for (i = 0; i < chip->bdbars_count; i++) {
2556                 struct ichdev *ichdev = &chip->ichd[i];
2557                 unsigned long port = ichdev->reg_offset;
2558                 if (! ichdev->substream || ! ichdev->suspended)
2559                         continue;
2560                 if (ichdev->ichd == ICHD_PCMOUT)
2561                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2562                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2563                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2564                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2565                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2566         }
2567
2568         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2569         return 0;
2570 }
2571 #endif /* CONFIG_PM */
2572
2573 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2574
2575 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2576 {
2577         struct snd_pcm_substream *subs;
2578         struct ichdev *ichdev;
2579         unsigned long port;
2580         unsigned long pos, t;
2581         struct timeval start_time, stop_time;
2582
2583         if (chip->ac97_bus->clock != 48000)
2584                 return; /* specified in module option */
2585
2586         subs = chip->pcm[0]->streams[0].substream;
2587         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2588                 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
2589                 return;
2590         }
2591         ichdev = &chip->ichd[ICHD_PCMOUT];
2592         ichdev->physbuf = subs->dma_buffer.addr;
2593         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2594         ichdev->substream = NULL; /* don't process interrupts */
2595
2596         /* set rate */
2597         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2598                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2599                 return;
2600         }
2601         snd_intel8x0_setup_periods(chip, ichdev);
2602         port = ichdev->reg_offset;
2603         spin_lock_irq(&chip->reg_lock);
2604         chip->in_measurement = 1;
2605         /* trigger */
2606         if (chip->device_type != DEVICE_ALI)
2607                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2608         else {
2609                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2610                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2611         }
2612         do_gettimeofday(&start_time);
2613         spin_unlock_irq(&chip->reg_lock);
2614         msleep(50);
2615         spin_lock_irq(&chip->reg_lock);
2616         /* check the position */
2617         pos = ichdev->fragsize1;
2618         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2619         pos += ichdev->position;
2620         chip->in_measurement = 0;
2621         do_gettimeofday(&stop_time);
2622         /* stop */
2623         if (chip->device_type == DEVICE_ALI) {
2624                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2625                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2626                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2627                         ;
2628         } else {
2629                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2630                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2631                         ;
2632         }
2633         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2634         spin_unlock_irq(&chip->reg_lock);
2635
2636         t = stop_time.tv_sec - start_time.tv_sec;
2637         t *= 1000000;
2638         t += stop_time.tv_usec - start_time.tv_usec;
2639         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2640         if (t == 0) {
2641                 snd_printk(KERN_ERR "?? calculation error..\n");
2642                 return;
2643         }
2644         pos = (pos / 4) * 1000;
2645         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2646         if (pos < 40000 || pos >= 60000) 
2647                 /* abnormal value. hw problem? */
2648                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2649         else if (pos < 47500 || pos > 48500)
2650                 /* not 48000Hz, tuning the clock.. */
2651                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2652         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2653         snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2654 }
2655
2656 #ifdef CONFIG_PROC_FS
2657 static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2658                                    struct snd_info_buffer *buffer)
2659 {
2660         struct intel8x0 *chip = entry->private_data;
2661         unsigned int tmp;
2662
2663         snd_iprintf(buffer, "Intel8x0\n\n");
2664         if (chip->device_type == DEVICE_ALI)
2665                 return;
2666         tmp = igetdword(chip, ICHREG(GLOB_STA));
2667         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2668         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2669         if (chip->device_type == DEVICE_INTEL_ICH4)
2670                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2671         snd_iprintf(buffer, "AC'97 codecs ready    :");
2672         if (tmp & chip->codec_isr_bits) {
2673                 int i;
2674                 static const char *codecs[3] = {
2675                         "primary", "secondary", "tertiary"
2676                 };
2677                 for (i = 0; i < chip->max_codecs; i++)
2678                         if (tmp & chip->codec_bit[i])
2679                                 snd_iprintf(buffer, " %s", codecs[i]);
2680         } else
2681                 snd_iprintf(buffer, " none");
2682         snd_iprintf(buffer, "\n");
2683         if (chip->device_type == DEVICE_INTEL_ICH4 ||
2684             chip->device_type == DEVICE_SIS)
2685                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2686                         chip->ac97_sdin[0],
2687                         chip->ac97_sdin[1],
2688                         chip->ac97_sdin[2]);
2689 }
2690
2691 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
2692 {
2693         struct snd_info_entry *entry;
2694
2695         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2696                 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
2697 }
2698 #else
2699 #define snd_intel8x0_proc_init(x)
2700 #endif
2701
2702 static int snd_intel8x0_dev_free(struct snd_device *device)
2703 {
2704         struct intel8x0 *chip = device->device_data;
2705         return snd_intel8x0_free(chip);
2706 }
2707
2708 struct ich_reg_info {
2709         unsigned int int_sta_mask;
2710         unsigned int offset;
2711 };
2712
2713 static unsigned int ich_codec_bits[3] = {
2714         ICH_PCR, ICH_SCR, ICH_TCR
2715 };
2716 static unsigned int sis_codec_bits[3] = {
2717         ICH_PCR, ICH_SCR, ICH_SIS_TCR
2718 };
2719
2720 static int __devinit snd_intel8x0_create(struct snd_card *card,
2721                                          struct pci_dev *pci,
2722                                          unsigned long device_type,
2723                                          struct intel8x0 ** r_intel8x0)
2724 {
2725         struct intel8x0 *chip;
2726         int err;
2727         unsigned int i;
2728         unsigned int int_sta_masks;
2729         struct ichdev *ichdev;
2730         static struct snd_device_ops ops = {
2731                 .dev_free =     snd_intel8x0_dev_free,
2732         };
2733
2734         static unsigned int bdbars[] = {
2735                 3, /* DEVICE_INTEL */
2736                 6, /* DEVICE_INTEL_ICH4 */
2737                 3, /* DEVICE_SIS */
2738                 6, /* DEVICE_ALI */
2739                 4, /* DEVICE_NFORCE */
2740         };
2741         static struct ich_reg_info intel_regs[6] = {
2742                 { ICH_PIINT, 0 },
2743                 { ICH_POINT, 0x10 },
2744                 { ICH_MCINT, 0x20 },
2745                 { ICH_M2INT, 0x40 },
2746                 { ICH_P2INT, 0x50 },
2747                 { ICH_SPINT, 0x60 },
2748         };
2749         static struct ich_reg_info nforce_regs[4] = {
2750                 { ICH_PIINT, 0 },
2751                 { ICH_POINT, 0x10 },
2752                 { ICH_MCINT, 0x20 },
2753                 { ICH_NVSPINT, 0x70 },
2754         };
2755         static struct ich_reg_info ali_regs[6] = {
2756                 { ALI_INT_PCMIN, 0x40 },
2757                 { ALI_INT_PCMOUT, 0x50 },
2758                 { ALI_INT_MICIN, 0x60 },
2759                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2760                 { ALI_INT_SPDIFIN, 0xa0 },
2761                 { ALI_INT_SPDIFOUT, 0xb0 },
2762         };
2763         struct ich_reg_info *tbl;
2764
2765         *r_intel8x0 = NULL;
2766
2767         if ((err = pci_enable_device(pci)) < 0)
2768                 return err;
2769
2770         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2771         if (chip == NULL) {
2772                 pci_disable_device(pci);
2773                 return -ENOMEM;
2774         }
2775         spin_lock_init(&chip->reg_lock);
2776         chip->device_type = device_type;
2777         chip->card = card;
2778         chip->pci = pci;
2779         chip->irq = -1;
2780
2781         /* module parameters */
2782         chip->buggy_irq = buggy_irq;
2783         chip->buggy_semaphore = buggy_semaphore;
2784         if (xbox)
2785                 chip->xbox = 1;
2786
2787         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2788             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2789                 chip->fix_nocache = 1; /* enable workaround */
2790
2791         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2792                 kfree(chip);
2793                 pci_disable_device(pci);
2794                 return err;
2795         }
2796
2797         if (device_type == DEVICE_ALI) {
2798                 /* ALI5455 has no ac97 region */
2799                 chip->bmaddr = pci_iomap(pci, 0, 0);
2800                 goto port_inited;
2801         }
2802
2803         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2804                 chip->addr = pci_iomap(pci, 2, 0);
2805         else
2806                 chip->addr = pci_iomap(pci, 0, 0);
2807         if (!chip->addr) {
2808                 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2809                 snd_intel8x0_free(chip);
2810                 return -EIO;
2811         }
2812         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2813                 chip->bmaddr = pci_iomap(pci, 3, 0);
2814         else
2815                 chip->bmaddr = pci_iomap(pci, 1, 0);
2816         if (!chip->bmaddr) {
2817                 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2818                 snd_intel8x0_free(chip);
2819                 return -EIO;
2820         }
2821
2822  port_inited:
2823         chip->bdbars_count = bdbars[device_type];
2824
2825         /* initialize offsets */
2826         switch (device_type) {
2827         case DEVICE_NFORCE:
2828                 tbl = nforce_regs;
2829                 break;
2830         case DEVICE_ALI:
2831                 tbl = ali_regs;
2832                 break;
2833         default:
2834                 tbl = intel_regs;
2835                 break;
2836         }
2837         for (i = 0; i < chip->bdbars_count; i++) {
2838                 ichdev = &chip->ichd[i];
2839                 ichdev->ichd = i;
2840                 ichdev->reg_offset = tbl[i].offset;
2841                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2842                 if (device_type == DEVICE_SIS) {
2843                         /* SiS 7012 swaps the registers */
2844                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2845                         ichdev->roff_picb = ICH_REG_OFF_SR;
2846                 } else {
2847                         ichdev->roff_sr = ICH_REG_OFF_SR;
2848                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2849                 }
2850                 if (device_type == DEVICE_ALI)
2851                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2852                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2853                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2854         }
2855
2856         /* allocate buffer descriptor lists */
2857         /* the start of each lists must be aligned to 8 bytes */
2858         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2859                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2860                                 &chip->bdbars) < 0) {
2861                 snd_intel8x0_free(chip);
2862                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2863                 return -ENOMEM;
2864         }
2865         /* tables must be aligned to 8 bytes here, but the kernel pages
2866            are much bigger, so we don't care (on i386) */
2867         /* workaround for 440MX */
2868         if (chip->fix_nocache)
2869                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2870         int_sta_masks = 0;
2871         for (i = 0; i < chip->bdbars_count; i++) {
2872                 ichdev = &chip->ichd[i];
2873                 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2874                         (i * ICH_MAX_FRAGS * 2);
2875                 ichdev->bdbar_addr = chip->bdbars.addr +
2876                         (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2877                 int_sta_masks |= ichdev->int_sta_mask;
2878         }
2879         chip->int_sta_reg = device_type == DEVICE_ALI ?
2880                 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2881         chip->int_sta_mask = int_sta_masks;
2882
2883         pci_set_master(pci);
2884
2885         switch(chip->device_type) {
2886         case DEVICE_INTEL_ICH4:
2887                 /* ICH4 can have three codecs */
2888                 chip->max_codecs = 3;
2889                 chip->codec_bit = ich_codec_bits;
2890                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2891                 break;
2892         case DEVICE_SIS:
2893                 /* recent SIS7012 can have three codecs */
2894                 chip->max_codecs = 3;
2895                 chip->codec_bit = sis_codec_bits;
2896                 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2897                 break;
2898         default:
2899                 /* others up to two codecs */
2900                 chip->max_codecs = 2;
2901                 chip->codec_bit = ich_codec_bits;
2902                 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2903                 break;
2904         }
2905         for (i = 0; i < chip->max_codecs; i++)
2906                 chip->codec_isr_bits |= chip->codec_bit[i];
2907
2908         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2909                 snd_intel8x0_free(chip);
2910                 return err;
2911         }
2912
2913         /* request irq after initializaing int_sta_mask, etc */
2914         if (request_irq(pci->irq, snd_intel8x0_interrupt,
2915                         IRQF_SHARED, card->shortname, chip)) {
2916                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2917                 snd_intel8x0_free(chip);
2918                 return -EBUSY;
2919         }
2920         chip->irq = pci->irq;
2921
2922         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2923                 snd_intel8x0_free(chip);
2924                 return err;
2925         }
2926
2927         snd_card_set_dev(card, &pci->dev);
2928
2929         *r_intel8x0 = chip;
2930         return 0;
2931 }
2932
2933 static struct shortname_table {
2934         unsigned int id;
2935         const char *s;
2936 } shortnames[] __devinitdata = {
2937         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2938         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2939         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2940         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2941         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2942         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2943         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2944         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2945         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2946         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2947         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2948         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2949         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2950         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2951         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2952         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2953         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2954         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2955         { 0x003a, "NVidia MCP04" },
2956         { 0x746d, "AMD AMD8111" },
2957         { 0x7445, "AMD AMD768" },
2958         { 0x5455, "ALi M5455" },
2959         { 0, NULL },
2960 };
2961
2962 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
2963         SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
2964         { } /* end */
2965 };
2966
2967 /* look up white/black list for SPDIF over ac-link */
2968 static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
2969 {
2970         const struct snd_pci_quirk *w;
2971
2972         w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
2973         if (w) {
2974                 if (w->value)
2975                         snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
2976                                     "AC-Link for %s\n", w->name);
2977                 else
2978                         snd_printdd(KERN_INFO "intel8x0: Using integrated "
2979                                     "SPDIF DMA for %s\n", w->name);
2980                 return w->value;
2981         }
2982         return 0;
2983 }
2984
2985 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2986                                         const struct pci_device_id *pci_id)
2987 {
2988         struct snd_card *card;
2989         struct intel8x0 *chip;
2990         int err;
2991         struct shortname_table *name;
2992
2993         card = snd_card_new(index, id, THIS_MODULE, 0);
2994         if (card == NULL)
2995                 return -ENOMEM;
2996
2997         if (spdif_aclink < 0)
2998                 spdif_aclink = check_default_spdif_aclink(pci);
2999
3000         strcpy(card->driver, "ICH");
3001         if (!spdif_aclink) {
3002                 switch (pci_id->driver_data) {
3003                 case DEVICE_NFORCE:
3004                         strcpy(card->driver, "NFORCE");
3005                         break;
3006                 case DEVICE_INTEL_ICH4:
3007                         strcpy(card->driver, "ICH4");
3008                 }
3009         }
3010
3011         strcpy(card->shortname, "Intel ICH");
3012         for (name = shortnames; name->id; name++) {
3013                 if (pci->device == name->id) {
3014                         strcpy(card->shortname, name->s);
3015                         break;
3016                 }
3017         }
3018
3019         if (buggy_irq < 0) {
3020                 /* some Nforce[2] and ICH boards have problems with IRQ handling.
3021                  * Needs to return IRQ_HANDLED for unknown irqs.
3022                  */
3023                 if (pci_id->driver_data == DEVICE_NFORCE)
3024                         buggy_irq = 1;
3025                 else
3026                         buggy_irq = 0;
3027         }
3028
3029         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3030                                        &chip)) < 0) {
3031                 snd_card_free(card);
3032                 return err;
3033         }
3034         card->private_data = chip;
3035
3036         if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
3037                 snd_card_free(card);
3038                 return err;
3039         }
3040         if ((err = snd_intel8x0_pcm(chip)) < 0) {
3041                 snd_card_free(card);
3042                 return err;
3043         }
3044         
3045         snd_intel8x0_proc_init(chip);
3046
3047         snprintf(card->longname, sizeof(card->longname),
3048                  "%s with %s at irq %i", card->shortname,
3049                  snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
3050
3051         if (! ac97_clock)
3052                 intel8x0_measure_ac97_clock(chip);
3053
3054         if ((err = snd_card_register(card)) < 0) {
3055                 snd_card_free(card);
3056                 return err;
3057         }
3058         pci_set_drvdata(pci, card);
3059         return 0;
3060 }
3061
3062 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3063 {
3064         snd_card_free(pci_get_drvdata(pci));
3065         pci_set_drvdata(pci, NULL);
3066 }
3067
3068 static struct pci_driver driver = {
3069         .name = "Intel ICH",
3070         .id_table = snd_intel8x0_ids,
3071         .probe = snd_intel8x0_probe,
3072         .remove = __devexit_p(snd_intel8x0_remove),
3073 #ifdef CONFIG_PM
3074         .suspend = intel8x0_suspend,
3075         .resume = intel8x0_resume,
3076 #endif
3077 };
3078
3079
3080 static int __init alsa_card_intel8x0_init(void)
3081 {
3082         return pci_register_driver(&driver);
3083 }
3084
3085 static void __exit alsa_card_intel8x0_exit(void)
3086 {
3087         pci_unregister_driver(&driver);
3088 }
3089
3090 module_init(alsa_card_intel8x0_init)
3091 module_exit(alsa_card_intel8x0_exit)