ALSA: hda: take reg_lock in azx_init_cmd_io/azx_free_cmd_io
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75                  "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84                  "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
87
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92                  "(in second, 0 = disable).");
93
94 /* reset the HD-audio controller in power save mode.
95  * this may give more power-saving, but will take longer time to
96  * wake up.
97  */
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101 #endif
102
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105                          "{Intel, ICH6M},"
106                          "{Intel, ICH7},"
107                          "{Intel, ESB2},"
108                          "{Intel, ICH8},"
109                          "{Intel, ICH9},"
110                          "{Intel, ICH10},"
111                          "{Intel, PCH},"
112                          "{Intel, SCH},"
113                          "{ATI, SB450},"
114                          "{ATI, SB600},"
115                          "{ATI, RS600},"
116                          "{ATI, RS690},"
117                          "{ATI, RS780},"
118                          "{ATI, R600},"
119                          "{ATI, RV630},"
120                          "{ATI, RV610},"
121                          "{ATI, RV670},"
122                          "{ATI, RV635},"
123                          "{ATI, RV620},"
124                          "{ATI, RV770},"
125                          "{VIA, VT8251},"
126                          "{VIA, VT8237A},"
127                          "{SiS, SIS966},"
128                          "{ULI, M5461}}");
129 MODULE_DESCRIPTION("Intel HDA driver");
130
131 #ifdef CONFIG_SND_VERBOSE_PRINTK
132 #define SFX     /* nop */
133 #else
134 #define SFX     "hda-intel: "
135 #endif
136
137 /*
138  * registers
139  */
140 #define ICH6_REG_GCAP                   0x00
141 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
142 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
143 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
144 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
145 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
146 #define ICH6_REG_VMIN                   0x02
147 #define ICH6_REG_VMAJ                   0x03
148 #define ICH6_REG_OUTPAY                 0x04
149 #define ICH6_REG_INPAY                  0x06
150 #define ICH6_REG_GCTL                   0x08
151 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
152 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
153 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
154 #define ICH6_REG_WAKEEN                 0x0c
155 #define ICH6_REG_STATESTS               0x0e
156 #define ICH6_REG_GSTS                   0x10
157 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
158 #define ICH6_REG_INTCTL                 0x20
159 #define ICH6_REG_INTSTS                 0x24
160 #define ICH6_REG_WALCLK                 0x30
161 #define ICH6_REG_SYNC                   0x34    
162 #define ICH6_REG_CORBLBASE              0x40
163 #define ICH6_REG_CORBUBASE              0x44
164 #define ICH6_REG_CORBWP                 0x48
165 #define ICH6_REG_CORBRP                 0x4a
166 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
167 #define ICH6_REG_CORBCTL                0x4c
168 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
169 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
170 #define ICH6_REG_CORBSTS                0x4d
171 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
172 #define ICH6_REG_CORBSIZE               0x4e
173
174 #define ICH6_REG_RIRBLBASE              0x50
175 #define ICH6_REG_RIRBUBASE              0x54
176 #define ICH6_REG_RIRBWP                 0x58
177 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
178 #define ICH6_REG_RINTCNT                0x5a
179 #define ICH6_REG_RIRBCTL                0x5c
180 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
181 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
182 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
183 #define ICH6_REG_RIRBSTS                0x5d
184 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
185 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
186 #define ICH6_REG_RIRBSIZE               0x5e
187
188 #define ICH6_REG_IC                     0x60
189 #define ICH6_REG_IR                     0x64
190 #define ICH6_REG_IRS                    0x68
191 #define   ICH6_IRS_VALID        (1<<1)
192 #define   ICH6_IRS_BUSY         (1<<0)
193
194 #define ICH6_REG_DPLBASE                0x70
195 #define ICH6_REG_DPUBASE                0x74
196 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
197
198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
200
201 /* stream register offsets from stream base */
202 #define ICH6_REG_SD_CTL                 0x00
203 #define ICH6_REG_SD_STS                 0x03
204 #define ICH6_REG_SD_LPIB                0x04
205 #define ICH6_REG_SD_CBL                 0x08
206 #define ICH6_REG_SD_LVI                 0x0c
207 #define ICH6_REG_SD_FIFOW               0x0e
208 #define ICH6_REG_SD_FIFOSIZE            0x10
209 #define ICH6_REG_SD_FORMAT              0x12
210 #define ICH6_REG_SD_BDLPL               0x18
211 #define ICH6_REG_SD_BDLPU               0x1c
212
213 /* PCI space */
214 #define ICH6_PCIREG_TCSEL       0x44
215
216 /*
217  * other constants
218  */
219
220 /* max number of SDs */
221 /* ICH, ATI and VIA have 4 playback and 4 capture */
222 #define ICH6_NUM_CAPTURE        4
223 #define ICH6_NUM_PLAYBACK       4
224
225 /* ULI has 6 playback and 5 capture */
226 #define ULI_NUM_CAPTURE         5
227 #define ULI_NUM_PLAYBACK        6
228
229 /* ATI HDMI has 1 playback and 0 capture */
230 #define ATIHDMI_NUM_CAPTURE     0
231 #define ATIHDMI_NUM_PLAYBACK    1
232
233 /* TERA has 4 playback and 3 capture */
234 #define TERA_NUM_CAPTURE        3
235 #define TERA_NUM_PLAYBACK       4
236
237 /* this number is statically defined for simplicity */
238 #define MAX_AZX_DEV             16
239
240 /* max number of fragments - we may use more if allocating more pages for BDL */
241 #define BDL_SIZE                4096
242 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
243 #define AZX_MAX_FRAG            32
244 /* max buffer size - no h/w limit, you can increase as you like */
245 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
246 /* max number of PCM devics per card */
247 #define AZX_MAX_PCMS            8
248
249 /* RIRB int mask: overrun[2], response[0] */
250 #define RIRB_INT_RESPONSE       0x01
251 #define RIRB_INT_OVERRUN        0x04
252 #define RIRB_INT_MASK           0x05
253
254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
255 #define AZX_MAX_CODECS          4
256 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
257
258 /* SD_CTL bits */
259 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
260 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
261 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
262 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
263 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
264 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
265 #define SD_CTL_STREAM_TAG_SHIFT 20
266
267 /* SD_CTL and SD_STS */
268 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
269 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
270 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
271 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
272                                  SD_INT_COMPLETE)
273
274 /* SD_STS */
275 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
276
277 /* INTCTL and INTSTS */
278 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
279 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
280 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
281
282 /* below are so far hardcoded - should read registers in future */
283 #define ICH6_MAX_CORB_ENTRIES   256
284 #define ICH6_MAX_RIRB_ENTRIES   256
285
286 /* position fix mode */
287 enum {
288         POS_FIX_AUTO,
289         POS_FIX_LPIB,
290         POS_FIX_POSBUF,
291 };
292
293 /* Defines for ATI HD Audio support in SB450 south bridge */
294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
296
297 /* Defines for Nvidia HDA support */
298 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
299 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
300 #define NVIDIA_HDA_ISTRM_COH          0x4d
301 #define NVIDIA_HDA_OSTRM_COH          0x4c
302 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
303
304 /* Defines for Intel SCH HDA snoop control */
305 #define INTEL_SCH_HDA_DEVC      0x78
306 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
307
308 /* Define IN stream 0 FIFO size offset in VIA controller */
309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
310 /* Define VIA HD Audio Device ID*/
311 #define VIA_HDAC_DEVICE_ID              0x3288
312
313 /* HD Audio class code */
314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
315
316 /*
317  */
318
319 struct azx_dev {
320         struct snd_dma_buffer bdl; /* BDL buffer */
321         u32 *posbuf;            /* position buffer pointer */
322
323         unsigned int bufsize;   /* size of the play buffer in bytes */
324         unsigned int period_bytes; /* size of the period in bytes */
325         unsigned int frags;     /* number for period in the play buffer */
326         unsigned int fifo_size; /* FIFO size */
327         unsigned long start_jiffies;    /* start + minimum jiffies */
328         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
329
330         void __iomem *sd_addr;  /* stream descriptor pointer */
331
332         u32 sd_int_sta_mask;    /* stream int status mask */
333
334         /* pcm support */
335         struct snd_pcm_substream *substream;    /* assigned substream,
336                                                  * set in PCM open
337                                                  */
338         unsigned int format_val;        /* format value to be set in the
339                                          * controller and the codec
340                                          */
341         unsigned char stream_tag;       /* assigned stream */
342         unsigned char index;            /* stream index */
343
344         unsigned int opened :1;
345         unsigned int running :1;
346         unsigned int irq_pending :1;
347         unsigned int start_flag: 1;     /* stream full start flag */
348         /*
349          * For VIA:
350          *  A flag to ensure DMA position is 0
351          *  when link position is not greater than FIFO size
352          */
353         unsigned int insufficient :1;
354 };
355
356 /* CORB/RIRB */
357 struct azx_rb {
358         u32 *buf;               /* CORB/RIRB buffer
359                                  * Each CORB entry is 4byte, RIRB is 8byte
360                                  */
361         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
362         /* for RIRB */
363         unsigned short rp, wp;  /* read/write pointers */
364         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
365         u32 res[AZX_MAX_CODECS];        /* last read value */
366 };
367
368 struct azx {
369         struct snd_card *card;
370         struct pci_dev *pci;
371         int dev_index;
372
373         /* chip type specific */
374         int driver_type;
375         int playback_streams;
376         int playback_index_offset;
377         int capture_streams;
378         int capture_index_offset;
379         int num_streams;
380
381         /* pci resources */
382         unsigned long addr;
383         void __iomem *remap_addr;
384         int irq;
385
386         /* locks */
387         spinlock_t reg_lock;
388         struct mutex open_mutex;
389
390         /* streams (x num_streams) */
391         struct azx_dev *azx_dev;
392
393         /* PCM */
394         struct snd_pcm *pcm[AZX_MAX_PCMS];
395
396         /* HD codec */
397         unsigned short codec_mask;
398         int  codec_probe_mask; /* copied from probe_mask option */
399         struct hda_bus *bus;
400
401         /* CORB/RIRB */
402         struct azx_rb corb;
403         struct azx_rb rirb;
404
405         /* CORB/RIRB and position buffers */
406         struct snd_dma_buffer rb;
407         struct snd_dma_buffer posbuf;
408
409         /* flags */
410         int position_fix;
411         unsigned int running :1;
412         unsigned int initialized :1;
413         unsigned int single_cmd :1;
414         unsigned int polling_mode :1;
415         unsigned int msi :1;
416         unsigned int irq_pending_warned :1;
417         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
418         unsigned int probing :1; /* codec probing phase */
419
420         /* for debugging */
421         unsigned int last_cmd;  /* last issued command (to sync) */
422
423         /* for pending irqs */
424         struct work_struct irq_pending_work;
425
426         /* reboot notifier (for mysterious hangup problem at power-down) */
427         struct notifier_block reboot_notifier;
428 };
429
430 /* driver types */
431 enum {
432         AZX_DRIVER_ICH,
433         AZX_DRIVER_SCH,
434         AZX_DRIVER_ATI,
435         AZX_DRIVER_ATIHDMI,
436         AZX_DRIVER_VIA,
437         AZX_DRIVER_SIS,
438         AZX_DRIVER_ULI,
439         AZX_DRIVER_NVIDIA,
440         AZX_DRIVER_TERA,
441         AZX_DRIVER_GENERIC,
442         AZX_NUM_DRIVERS, /* keep this as last entry */
443 };
444
445 static char *driver_short_names[] __devinitdata = {
446         [AZX_DRIVER_ICH] = "HDA Intel",
447         [AZX_DRIVER_SCH] = "HDA Intel MID",
448         [AZX_DRIVER_ATI] = "HDA ATI SB",
449         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
450         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
451         [AZX_DRIVER_SIS] = "HDA SIS966",
452         [AZX_DRIVER_ULI] = "HDA ULI M5461",
453         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
454         [AZX_DRIVER_TERA] = "HDA Teradici", 
455         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
456 };
457
458 /*
459  * macros for easy use
460  */
461 #define azx_writel(chip,reg,value) \
462         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
463 #define azx_readl(chip,reg) \
464         readl((chip)->remap_addr + ICH6_REG_##reg)
465 #define azx_writew(chip,reg,value) \
466         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
467 #define azx_readw(chip,reg) \
468         readw((chip)->remap_addr + ICH6_REG_##reg)
469 #define azx_writeb(chip,reg,value) \
470         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
471 #define azx_readb(chip,reg) \
472         readb((chip)->remap_addr + ICH6_REG_##reg)
473
474 #define azx_sd_writel(dev,reg,value) \
475         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
476 #define azx_sd_readl(dev,reg) \
477         readl((dev)->sd_addr + ICH6_REG_##reg)
478 #define azx_sd_writew(dev,reg,value) \
479         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
480 #define azx_sd_readw(dev,reg) \
481         readw((dev)->sd_addr + ICH6_REG_##reg)
482 #define azx_sd_writeb(dev,reg,value) \
483         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
484 #define azx_sd_readb(dev,reg) \
485         readb((dev)->sd_addr + ICH6_REG_##reg)
486
487 /* for pcm support */
488 #define get_azx_dev(substream) (substream->runtime->private_data)
489
490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
491
492 /*
493  * Interface for HD codec
494  */
495
496 /*
497  * CORB / RIRB interface
498  */
499 static int azx_alloc_cmd_io(struct azx *chip)
500 {
501         int err;
502
503         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
504         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
505                                   snd_dma_pci_data(chip->pci),
506                                   PAGE_SIZE, &chip->rb);
507         if (err < 0) {
508                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
509                 return err;
510         }
511         return 0;
512 }
513
514 static void azx_init_cmd_io(struct azx *chip)
515 {
516         spin_lock_irq(&chip->reg_lock);
517         /* CORB set up */
518         chip->corb.addr = chip->rb.addr;
519         chip->corb.buf = (u32 *)chip->rb.area;
520         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
521         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
522
523         /* set the corb size to 256 entries (ULI requires explicitly) */
524         azx_writeb(chip, CORBSIZE, 0x02);
525         /* set the corb write pointer to 0 */
526         azx_writew(chip, CORBWP, 0);
527         /* reset the corb hw read pointer */
528         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
529         /* enable corb dma */
530         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
531
532         /* RIRB set up */
533         chip->rirb.addr = chip->rb.addr + 2048;
534         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
535         chip->rirb.wp = chip->rirb.rp = 0;
536         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
537         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
538         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
539
540         /* set the rirb size to 256 entries (ULI requires explicitly) */
541         azx_writeb(chip, RIRBSIZE, 0x02);
542         /* reset the rirb hw write pointer */
543         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
544         /* set N=1, get RIRB response interrupt for new entry */
545         azx_writew(chip, RINTCNT, 1);
546         /* enable rirb dma and response irq */
547         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
548         spin_unlock_irq(&chip->reg_lock);
549 }
550
551 static void azx_free_cmd_io(struct azx *chip)
552 {
553         spin_lock_irq(&chip->reg_lock);
554         /* disable ringbuffer DMAs */
555         azx_writeb(chip, RIRBCTL, 0);
556         azx_writeb(chip, CORBCTL, 0);
557         spin_unlock_irq(&chip->reg_lock);
558 }
559
560 static unsigned int azx_command_addr(u32 cmd)
561 {
562         unsigned int addr = cmd >> 28;
563
564         if (addr >= AZX_MAX_CODECS) {
565                 snd_BUG();
566                 addr = 0;
567         }
568
569         return addr;
570 }
571
572 static unsigned int azx_response_addr(u32 res)
573 {
574         unsigned int addr = res & 0xf;
575
576         if (addr >= AZX_MAX_CODECS) {
577                 snd_BUG();
578                 addr = 0;
579         }
580
581         return addr;
582 }
583
584 /* send a command */
585 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
586 {
587         struct azx *chip = bus->private_data;
588         unsigned int addr = azx_command_addr(val);
589         unsigned int wp;
590
591         /* add command to corb */
592         wp = azx_readb(chip, CORBWP);
593         wp++;
594         wp %= ICH6_MAX_CORB_ENTRIES;
595
596         spin_lock_irq(&chip->reg_lock);
597         chip->rirb.cmds[addr]++;
598         chip->corb.buf[wp] = cpu_to_le32(val);
599         azx_writel(chip, CORBWP, wp);
600         spin_unlock_irq(&chip->reg_lock);
601
602         return 0;
603 }
604
605 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
606
607 /* retrieve RIRB entry - called from interrupt handler */
608 static void azx_update_rirb(struct azx *chip)
609 {
610         unsigned int rp, wp;
611         unsigned int addr;
612         u32 res, res_ex;
613
614         wp = azx_readb(chip, RIRBWP);
615         if (wp == chip->rirb.wp)
616                 return;
617         chip->rirb.wp = wp;
618
619         while (chip->rirb.rp != wp) {
620                 chip->rirb.rp++;
621                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
622
623                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
624                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
625                 res = le32_to_cpu(chip->rirb.buf[rp]);
626                 addr = azx_response_addr(res_ex);
627                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
628                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
629                 else if (chip->rirb.cmds[addr]) {
630                         chip->rirb.res[addr] = res;
631                         smp_wmb();
632                         chip->rirb.cmds[addr]--;
633                 }
634         }
635 }
636
637 /* receive a response */
638 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
639                                           unsigned int addr)
640 {
641         struct azx *chip = bus->private_data;
642         unsigned long timeout;
643
644  again:
645         timeout = jiffies + msecs_to_jiffies(1000);
646         for (;;) {
647                 if (chip->polling_mode) {
648                         spin_lock_irq(&chip->reg_lock);
649                         azx_update_rirb(chip);
650                         spin_unlock_irq(&chip->reg_lock);
651                 }
652                 if (!chip->rirb.cmds[addr]) {
653                         smp_rmb();
654                         bus->rirb_error = 0;
655                         return chip->rirb.res[addr]; /* the last value */
656                 }
657                 if (time_after(jiffies, timeout))
658                         break;
659                 if (bus->needs_damn_long_delay)
660                         msleep(2); /* temporary workaround */
661                 else {
662                         udelay(10);
663                         cond_resched();
664                 }
665         }
666
667         if (chip->msi) {
668                 snd_printk(KERN_WARNING SFX "No response from codec, "
669                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
670                 free_irq(chip->irq, chip);
671                 chip->irq = -1;
672                 pci_disable_msi(chip->pci);
673                 chip->msi = 0;
674                 if (azx_acquire_irq(chip, 1) < 0) {
675                         bus->rirb_error = 1;
676                         return -1;
677                 }
678                 goto again;
679         }
680
681         if (!chip->polling_mode) {
682                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
683                            "switching to polling mode: last cmd=0x%08x\n",
684                            chip->last_cmd);
685                 chip->polling_mode = 1;
686                 goto again;
687         }
688
689         if (chip->probing) {
690                 /* If this critical timeout happens during the codec probing
691                  * phase, this is likely an access to a non-existing codec
692                  * slot.  Better to return an error and reset the system.
693                  */
694                 return -1;
695         }
696
697         /* a fatal communication error; need either to reset or to fallback
698          * to the single_cmd mode
699          */
700         bus->rirb_error = 1;
701         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
702                 bus->response_reset = 1;
703                 return -1; /* give a chance to retry */
704         }
705
706         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
707                    "switching to single_cmd mode: last cmd=0x%08x\n",
708                    chip->last_cmd);
709         chip->single_cmd = 1;
710         bus->response_reset = 0;
711         /* re-initialize CORB/RIRB */
712         azx_free_cmd_io(chip);
713         azx_init_cmd_io(chip);
714         return -1;
715 }
716
717 /*
718  * Use the single immediate command instead of CORB/RIRB for simplicity
719  *
720  * Note: according to Intel, this is not preferred use.  The command was
721  *       intended for the BIOS only, and may get confused with unsolicited
722  *       responses.  So, we shouldn't use it for normal operation from the
723  *       driver.
724  *       I left the codes, however, for debugging/testing purposes.
725  */
726
727 /* receive a response */
728 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
729 {
730         int timeout = 50;
731
732         while (timeout--) {
733                 /* check IRV busy bit */
734                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
735                         /* reuse rirb.res as the response return value */
736                         chip->rirb.res[addr] = azx_readl(chip, IR);
737                         return 0;
738                 }
739                 udelay(1);
740         }
741         if (printk_ratelimit())
742                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
743                            azx_readw(chip, IRS));
744         chip->rirb.res[addr] = -1;
745         return -EIO;
746 }
747
748 /* send a command */
749 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
750 {
751         struct azx *chip = bus->private_data;
752         unsigned int addr = azx_command_addr(val);
753         int timeout = 50;
754
755         bus->rirb_error = 0;
756         while (timeout--) {
757                 /* check ICB busy bit */
758                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
759                         /* Clear IRV valid bit */
760                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
761                                    ICH6_IRS_VALID);
762                         azx_writel(chip, IC, val);
763                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
764                                    ICH6_IRS_BUSY);
765                         return azx_single_wait_for_response(chip, addr);
766                 }
767                 udelay(1);
768         }
769         if (printk_ratelimit())
770                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
771                            azx_readw(chip, IRS), val);
772         return -EIO;
773 }
774
775 /* receive a response */
776 static unsigned int azx_single_get_response(struct hda_bus *bus,
777                                             unsigned int addr)
778 {
779         struct azx *chip = bus->private_data;
780         return chip->rirb.res[addr];
781 }
782
783 /*
784  * The below are the main callbacks from hda_codec.
785  *
786  * They are just the skeleton to call sub-callbacks according to the
787  * current setting of chip->single_cmd.
788  */
789
790 /* send a command */
791 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
792 {
793         struct azx *chip = bus->private_data;
794
795         chip->last_cmd = val;
796         if (chip->single_cmd)
797                 return azx_single_send_cmd(bus, val);
798         else
799                 return azx_corb_send_cmd(bus, val);
800 }
801
802 /* get a response */
803 static unsigned int azx_get_response(struct hda_bus *bus,
804                                      unsigned int addr)
805 {
806         struct azx *chip = bus->private_data;
807         if (chip->single_cmd)
808                 return azx_single_get_response(bus, addr);
809         else
810                 return azx_rirb_get_response(bus, addr);
811 }
812
813 #ifdef CONFIG_SND_HDA_POWER_SAVE
814 static void azx_power_notify(struct hda_bus *bus);
815 #endif
816
817 /* reset codec link */
818 static int azx_reset(struct azx *chip)
819 {
820         int count;
821
822         /* clear STATESTS */
823         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
824
825         /* reset controller */
826         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
827
828         count = 50;
829         while (azx_readb(chip, GCTL) && --count)
830                 msleep(1);
831
832         /* delay for >= 100us for codec PLL to settle per spec
833          * Rev 0.9 section 5.5.1
834          */
835         msleep(1);
836
837         /* Bring controller out of reset */
838         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
839
840         count = 50;
841         while (!azx_readb(chip, GCTL) && --count)
842                 msleep(1);
843
844         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
845         msleep(1);
846
847         /* check to see if controller is ready */
848         if (!azx_readb(chip, GCTL)) {
849                 snd_printd(SFX "azx_reset: controller not ready!\n");
850                 return -EBUSY;
851         }
852
853         /* Accept unsolicited responses */
854         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
855
856         /* detect codecs */
857         if (!chip->codec_mask) {
858                 chip->codec_mask = azx_readw(chip, STATESTS);
859                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
860         }
861
862         return 0;
863 }
864
865
866 /*
867  * Lowlevel interface
868  */  
869
870 /* enable interrupts */
871 static void azx_int_enable(struct azx *chip)
872 {
873         /* enable controller CIE and GIE */
874         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
875                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
876 }
877
878 /* disable interrupts */
879 static void azx_int_disable(struct azx *chip)
880 {
881         int i;
882
883         /* disable interrupts in stream descriptor */
884         for (i = 0; i < chip->num_streams; i++) {
885                 struct azx_dev *azx_dev = &chip->azx_dev[i];
886                 azx_sd_writeb(azx_dev, SD_CTL,
887                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
888         }
889
890         /* disable SIE for all streams */
891         azx_writeb(chip, INTCTL, 0);
892
893         /* disable controller CIE and GIE */
894         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
895                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
896 }
897
898 /* clear interrupts */
899 static void azx_int_clear(struct azx *chip)
900 {
901         int i;
902
903         /* clear stream status */
904         for (i = 0; i < chip->num_streams; i++) {
905                 struct azx_dev *azx_dev = &chip->azx_dev[i];
906                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
907         }
908
909         /* clear STATESTS */
910         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
911
912         /* clear rirb status */
913         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
914
915         /* clear int status */
916         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
917 }
918
919 /* start a stream */
920 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
921 {
922         /*
923          * Before stream start, initialize parameter
924          */
925         azx_dev->insufficient = 1;
926
927         /* enable SIE */
928         azx_writeb(chip, INTCTL,
929                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
930         /* set DMA start and interrupt mask */
931         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
932                       SD_CTL_DMA_START | SD_INT_MASK);
933 }
934
935 /* stop DMA */
936 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
937 {
938         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
939                       ~(SD_CTL_DMA_START | SD_INT_MASK));
940         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
941 }
942
943 /* stop a stream */
944 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
945 {
946         azx_stream_clear(chip, azx_dev);
947         /* disable SIE */
948         azx_writeb(chip, INTCTL,
949                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
950 }
951
952
953 /*
954  * reset and start the controller registers
955  */
956 static void azx_init_chip(struct azx *chip)
957 {
958         if (chip->initialized)
959                 return;
960
961         /* reset controller */
962         azx_reset(chip);
963
964         /* initialize interrupts */
965         azx_int_clear(chip);
966         azx_int_enable(chip);
967
968         /* initialize the codec command I/O */
969         azx_init_cmd_io(chip);
970
971         /* program the position buffer */
972         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
973         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
974
975         chip->initialized = 1;
976 }
977
978 /*
979  * initialize the PCI registers
980  */
981 /* update bits in a PCI register byte */
982 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
983                             unsigned char mask, unsigned char val)
984 {
985         unsigned char data;
986
987         pci_read_config_byte(pci, reg, &data);
988         data &= ~mask;
989         data |= (val & mask);
990         pci_write_config_byte(pci, reg, data);
991 }
992
993 static void azx_init_pci(struct azx *chip)
994 {
995         unsigned short snoop;
996
997         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
998          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
999          * Ensuring these bits are 0 clears playback static on some HD Audio
1000          * codecs
1001          */
1002         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1003
1004         switch (chip->driver_type) {
1005         case AZX_DRIVER_ATI:
1006                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1007                 update_pci_byte(chip->pci,
1008                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1009                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1010                 break;
1011         case AZX_DRIVER_NVIDIA:
1012                 /* For NVIDIA HDA, enable snoop */
1013                 update_pci_byte(chip->pci,
1014                                 NVIDIA_HDA_TRANSREG_ADDR,
1015                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1016                 update_pci_byte(chip->pci,
1017                                 NVIDIA_HDA_ISTRM_COH,
1018                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1019                 update_pci_byte(chip->pci,
1020                                 NVIDIA_HDA_OSTRM_COH,
1021                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1022                 break;
1023         case AZX_DRIVER_SCH:
1024                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1025                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1026                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1027                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1028                         pci_read_config_word(chip->pci,
1029                                 INTEL_SCH_HDA_DEVC, &snoop);
1030                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1031                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1032                                 ? "Failed" : "OK");
1033                 }
1034                 break;
1035
1036         }
1037 }
1038
1039
1040 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1041
1042 /*
1043  * interrupt handler
1044  */
1045 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1046 {
1047         struct azx *chip = dev_id;
1048         struct azx_dev *azx_dev;
1049         u32 status;
1050         int i, ok;
1051
1052         spin_lock(&chip->reg_lock);
1053
1054         status = azx_readl(chip, INTSTS);
1055         if (status == 0) {
1056                 spin_unlock(&chip->reg_lock);
1057                 return IRQ_NONE;
1058         }
1059         
1060         for (i = 0; i < chip->num_streams; i++) {
1061                 azx_dev = &chip->azx_dev[i];
1062                 if (status & azx_dev->sd_int_sta_mask) {
1063                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1064                         if (!azx_dev->substream || !azx_dev->running)
1065                                 continue;
1066                         /* check whether this IRQ is really acceptable */
1067                         ok = azx_position_ok(chip, azx_dev);
1068                         if (ok == 1) {
1069                                 azx_dev->irq_pending = 0;
1070                                 spin_unlock(&chip->reg_lock);
1071                                 snd_pcm_period_elapsed(azx_dev->substream);
1072                                 spin_lock(&chip->reg_lock);
1073                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1074                                 /* bogus IRQ, process it later */
1075                                 azx_dev->irq_pending = 1;
1076                                 queue_work(chip->bus->workq,
1077                                            &chip->irq_pending_work);
1078                         }
1079                 }
1080         }
1081
1082         /* clear rirb int */
1083         status = azx_readb(chip, RIRBSTS);
1084         if (status & RIRB_INT_MASK) {
1085                 if (status & RIRB_INT_RESPONSE)
1086                         azx_update_rirb(chip);
1087                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1088         }
1089
1090 #if 0
1091         /* clear state status int */
1092         if (azx_readb(chip, STATESTS) & 0x04)
1093                 azx_writeb(chip, STATESTS, 0x04);
1094 #endif
1095         spin_unlock(&chip->reg_lock);
1096         
1097         return IRQ_HANDLED;
1098 }
1099
1100
1101 /*
1102  * set up a BDL entry
1103  */
1104 static int setup_bdle(struct snd_pcm_substream *substream,
1105                       struct azx_dev *azx_dev, u32 **bdlp,
1106                       int ofs, int size, int with_ioc)
1107 {
1108         u32 *bdl = *bdlp;
1109
1110         while (size > 0) {
1111                 dma_addr_t addr;
1112                 int chunk;
1113
1114                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1115                         return -EINVAL;
1116
1117                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1118                 /* program the address field of the BDL entry */
1119                 bdl[0] = cpu_to_le32((u32)addr);
1120                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1121                 /* program the size field of the BDL entry */
1122                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1123                 bdl[2] = cpu_to_le32(chunk);
1124                 /* program the IOC to enable interrupt
1125                  * only when the whole fragment is processed
1126                  */
1127                 size -= chunk;
1128                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1129                 bdl += 4;
1130                 azx_dev->frags++;
1131                 ofs += chunk;
1132         }
1133         *bdlp = bdl;
1134         return ofs;
1135 }
1136
1137 /*
1138  * set up BDL entries
1139  */
1140 static int azx_setup_periods(struct azx *chip,
1141                              struct snd_pcm_substream *substream,
1142                              struct azx_dev *azx_dev)
1143 {
1144         u32 *bdl;
1145         int i, ofs, periods, period_bytes;
1146         int pos_adj;
1147
1148         /* reset BDL address */
1149         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1150         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1151
1152         period_bytes = azx_dev->period_bytes;
1153         periods = azx_dev->bufsize / period_bytes;
1154
1155         /* program the initial BDL entries */
1156         bdl = (u32 *)azx_dev->bdl.area;
1157         ofs = 0;
1158         azx_dev->frags = 0;
1159         pos_adj = bdl_pos_adj[chip->dev_index];
1160         if (pos_adj > 0) {
1161                 struct snd_pcm_runtime *runtime = substream->runtime;
1162                 int pos_align = pos_adj;
1163                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1164                 if (!pos_adj)
1165                         pos_adj = pos_align;
1166                 else
1167                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1168                                 pos_align;
1169                 pos_adj = frames_to_bytes(runtime, pos_adj);
1170                 if (pos_adj >= period_bytes) {
1171                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1172                                    bdl_pos_adj[chip->dev_index]);
1173                         pos_adj = 0;
1174                 } else {
1175                         ofs = setup_bdle(substream, azx_dev,
1176                                          &bdl, ofs, pos_adj, 1);
1177                         if (ofs < 0)
1178                                 goto error;
1179                 }
1180         } else
1181                 pos_adj = 0;
1182         for (i = 0; i < periods; i++) {
1183                 if (i == periods - 1 && pos_adj)
1184                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1185                                          period_bytes - pos_adj, 0);
1186                 else
1187                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1188                                          period_bytes, 1);
1189                 if (ofs < 0)
1190                         goto error;
1191         }
1192         return 0;
1193
1194  error:
1195         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1196                    azx_dev->bufsize, period_bytes);
1197         return -EINVAL;
1198 }
1199
1200 /* reset stream */
1201 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1202 {
1203         unsigned char val;
1204         int timeout;
1205
1206         azx_stream_clear(chip, azx_dev);
1207
1208         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1209                       SD_CTL_STREAM_RESET);
1210         udelay(3);
1211         timeout = 300;
1212         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1213                --timeout)
1214                 ;
1215         val &= ~SD_CTL_STREAM_RESET;
1216         azx_sd_writeb(azx_dev, SD_CTL, val);
1217         udelay(3);
1218
1219         timeout = 300;
1220         /* waiting for hardware to report that the stream is out of reset */
1221         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1222                --timeout)
1223                 ;
1224
1225         /* reset first position - may not be synced with hw at this time */
1226         *azx_dev->posbuf = 0;
1227 }
1228
1229 /*
1230  * set up the SD for streaming
1231  */
1232 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1233 {
1234         /* make sure the run bit is zero for SD */
1235         azx_stream_clear(chip, azx_dev);
1236         /* program the stream_tag */
1237         azx_sd_writel(azx_dev, SD_CTL,
1238                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1239                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1240
1241         /* program the length of samples in cyclic buffer */
1242         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1243
1244         /* program the stream format */
1245         /* this value needs to be the same as the one programmed */
1246         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1247
1248         /* program the stream LVI (last valid index) of the BDL */
1249         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1250
1251         /* program the BDL address */
1252         /* lower BDL address */
1253         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1254         /* upper BDL address */
1255         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1256
1257         /* enable the position buffer */
1258         if (chip->position_fix == POS_FIX_POSBUF ||
1259             chip->position_fix == POS_FIX_AUTO ||
1260             chip->via_dmapos_patch) {
1261                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1262                         azx_writel(chip, DPLBASE,
1263                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1264         }
1265
1266         /* set the interrupt enable bits in the descriptor control register */
1267         azx_sd_writel(azx_dev, SD_CTL,
1268                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1269
1270         return 0;
1271 }
1272
1273 /*
1274  * Probe the given codec address
1275  */
1276 static int probe_codec(struct azx *chip, int addr)
1277 {
1278         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1279                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1280         unsigned int res;
1281
1282         mutex_lock(&chip->bus->cmd_mutex);
1283         chip->probing = 1;
1284         azx_send_cmd(chip->bus, cmd);
1285         res = azx_get_response(chip->bus, addr);
1286         chip->probing = 0;
1287         mutex_unlock(&chip->bus->cmd_mutex);
1288         if (res == -1)
1289                 return -EIO;
1290         snd_printdd(SFX "codec #%d probed OK\n", addr);
1291         return 0;
1292 }
1293
1294 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1295                                  struct hda_pcm *cpcm);
1296 static void azx_stop_chip(struct azx *chip);
1297
1298 static void azx_bus_reset(struct hda_bus *bus)
1299 {
1300         struct azx *chip = bus->private_data;
1301
1302         bus->in_reset = 1;
1303         azx_stop_chip(chip);
1304         azx_init_chip(chip);
1305 #ifdef CONFIG_PM
1306         if (chip->initialized) {
1307                 int i;
1308
1309                 for (i = 0; i < AZX_MAX_PCMS; i++)
1310                         snd_pcm_suspend_all(chip->pcm[i]);
1311                 snd_hda_suspend(chip->bus);
1312                 snd_hda_resume(chip->bus);
1313         }
1314 #endif
1315         bus->in_reset = 0;
1316 }
1317
1318 /*
1319  * Codec initialization
1320  */
1321
1322 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1323 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1324         [AZX_DRIVER_TERA] = 1,
1325 };
1326
1327 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1328                                       int no_init)
1329 {
1330         struct hda_bus_template bus_temp;
1331         int c, codecs, err;
1332         int max_slots;
1333
1334         memset(&bus_temp, 0, sizeof(bus_temp));
1335         bus_temp.private_data = chip;
1336         bus_temp.modelname = model;
1337         bus_temp.pci = chip->pci;
1338         bus_temp.ops.command = azx_send_cmd;
1339         bus_temp.ops.get_response = azx_get_response;
1340         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1341         bus_temp.ops.bus_reset = azx_bus_reset;
1342 #ifdef CONFIG_SND_HDA_POWER_SAVE
1343         bus_temp.power_save = &power_save;
1344         bus_temp.ops.pm_notify = azx_power_notify;
1345 #endif
1346
1347         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1348         if (err < 0)
1349                 return err;
1350
1351         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1352                 chip->bus->needs_damn_long_delay = 1;
1353
1354         codecs = 0;
1355         max_slots = azx_max_codecs[chip->driver_type];
1356         if (!max_slots)
1357                 max_slots = AZX_MAX_CODECS;
1358
1359         /* First try to probe all given codec slots */
1360         for (c = 0; c < max_slots; c++) {
1361                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1362                         if (probe_codec(chip, c) < 0) {
1363                                 /* Some BIOSen give you wrong codec addresses
1364                                  * that don't exist
1365                                  */
1366                                 snd_printk(KERN_WARNING SFX
1367                                            "Codec #%d probe error; "
1368                                            "disabling it...\n", c);
1369                                 chip->codec_mask &= ~(1 << c);
1370                                 /* More badly, accessing to a non-existing
1371                                  * codec often screws up the controller chip,
1372                                  * and distrubs the further communications.
1373                                  * Thus if an error occurs during probing,
1374                                  * better to reset the controller chip to
1375                                  * get back to the sanity state.
1376                                  */
1377                                 azx_stop_chip(chip);
1378                                 azx_init_chip(chip);
1379                         }
1380                 }
1381         }
1382
1383         /* Then create codec instances */
1384         for (c = 0; c < max_slots; c++) {
1385                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1386                         struct hda_codec *codec;
1387                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1388                         if (err < 0)
1389                                 continue;
1390                         codecs++;
1391                 }
1392         }
1393         if (!codecs) {
1394                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1395                 return -ENXIO;
1396         }
1397
1398         return 0;
1399 }
1400
1401
1402 /*
1403  * PCM support
1404  */
1405
1406 /* assign a stream for the PCM */
1407 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1408 {
1409         int dev, i, nums;
1410         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1411                 dev = chip->playback_index_offset;
1412                 nums = chip->playback_streams;
1413         } else {
1414                 dev = chip->capture_index_offset;
1415                 nums = chip->capture_streams;
1416         }
1417         for (i = 0; i < nums; i++, dev++)
1418                 if (!chip->azx_dev[dev].opened) {
1419                         chip->azx_dev[dev].opened = 1;
1420                         return &chip->azx_dev[dev];
1421                 }
1422         return NULL;
1423 }
1424
1425 /* release the assigned stream */
1426 static inline void azx_release_device(struct azx_dev *azx_dev)
1427 {
1428         azx_dev->opened = 0;
1429 }
1430
1431 static struct snd_pcm_hardware azx_pcm_hw = {
1432         .info =                 (SNDRV_PCM_INFO_MMAP |
1433                                  SNDRV_PCM_INFO_INTERLEAVED |
1434                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1435                                  SNDRV_PCM_INFO_MMAP_VALID |
1436                                  /* No full-resume yet implemented */
1437                                  /* SNDRV_PCM_INFO_RESUME |*/
1438                                  SNDRV_PCM_INFO_PAUSE |
1439                                  SNDRV_PCM_INFO_SYNC_START),
1440         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1441         .rates =                SNDRV_PCM_RATE_48000,
1442         .rate_min =             48000,
1443         .rate_max =             48000,
1444         .channels_min =         2,
1445         .channels_max =         2,
1446         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1447         .period_bytes_min =     128,
1448         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1449         .periods_min =          2,
1450         .periods_max =          AZX_MAX_FRAG,
1451         .fifo_size =            0,
1452 };
1453
1454 struct azx_pcm {
1455         struct azx *chip;
1456         struct hda_codec *codec;
1457         struct hda_pcm_stream *hinfo[2];
1458 };
1459
1460 static int azx_pcm_open(struct snd_pcm_substream *substream)
1461 {
1462         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1463         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1464         struct azx *chip = apcm->chip;
1465         struct azx_dev *azx_dev;
1466         struct snd_pcm_runtime *runtime = substream->runtime;
1467         unsigned long flags;
1468         int err;
1469
1470         mutex_lock(&chip->open_mutex);
1471         azx_dev = azx_assign_device(chip, substream->stream);
1472         if (azx_dev == NULL) {
1473                 mutex_unlock(&chip->open_mutex);
1474                 return -EBUSY;
1475         }
1476         runtime->hw = azx_pcm_hw;
1477         runtime->hw.channels_min = hinfo->channels_min;
1478         runtime->hw.channels_max = hinfo->channels_max;
1479         runtime->hw.formats = hinfo->formats;
1480         runtime->hw.rates = hinfo->rates;
1481         snd_pcm_limit_hw_rates(runtime);
1482         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1483         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1484                                    128);
1485         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1486                                    128);
1487         snd_hda_power_up(apcm->codec);
1488         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1489         if (err < 0) {
1490                 azx_release_device(azx_dev);
1491                 snd_hda_power_down(apcm->codec);
1492                 mutex_unlock(&chip->open_mutex);
1493                 return err;
1494         }
1495         snd_pcm_limit_hw_rates(runtime);
1496         /* sanity check */
1497         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1498             snd_BUG_ON(!runtime->hw.channels_max) ||
1499             snd_BUG_ON(!runtime->hw.formats) ||
1500             snd_BUG_ON(!runtime->hw.rates)) {
1501                 azx_release_device(azx_dev);
1502                 hinfo->ops.close(hinfo, apcm->codec, substream);
1503                 snd_hda_power_down(apcm->codec);
1504                 mutex_unlock(&chip->open_mutex);
1505                 return -EINVAL;
1506         }
1507         spin_lock_irqsave(&chip->reg_lock, flags);
1508         azx_dev->substream = substream;
1509         azx_dev->running = 0;
1510         spin_unlock_irqrestore(&chip->reg_lock, flags);
1511
1512         runtime->private_data = azx_dev;
1513         snd_pcm_set_sync(substream);
1514         mutex_unlock(&chip->open_mutex);
1515         return 0;
1516 }
1517
1518 static int azx_pcm_close(struct snd_pcm_substream *substream)
1519 {
1520         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1521         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1522         struct azx *chip = apcm->chip;
1523         struct azx_dev *azx_dev = get_azx_dev(substream);
1524         unsigned long flags;
1525
1526         mutex_lock(&chip->open_mutex);
1527         spin_lock_irqsave(&chip->reg_lock, flags);
1528         azx_dev->substream = NULL;
1529         azx_dev->running = 0;
1530         spin_unlock_irqrestore(&chip->reg_lock, flags);
1531         azx_release_device(azx_dev);
1532         hinfo->ops.close(hinfo, apcm->codec, substream);
1533         snd_hda_power_down(apcm->codec);
1534         mutex_unlock(&chip->open_mutex);
1535         return 0;
1536 }
1537
1538 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1539                              struct snd_pcm_hw_params *hw_params)
1540 {
1541         struct azx_dev *azx_dev = get_azx_dev(substream);
1542
1543         azx_dev->bufsize = 0;
1544         azx_dev->period_bytes = 0;
1545         azx_dev->format_val = 0;
1546         return snd_pcm_lib_malloc_pages(substream,
1547                                         params_buffer_bytes(hw_params));
1548 }
1549
1550 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1551 {
1552         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1553         struct azx_dev *azx_dev = get_azx_dev(substream);
1554         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1555
1556         /* reset BDL address */
1557         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1558         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1559         azx_sd_writel(azx_dev, SD_CTL, 0);
1560         azx_dev->bufsize = 0;
1561         azx_dev->period_bytes = 0;
1562         azx_dev->format_val = 0;
1563
1564         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1565
1566         return snd_pcm_lib_free_pages(substream);
1567 }
1568
1569 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1570 {
1571         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1572         struct azx *chip = apcm->chip;
1573         struct azx_dev *azx_dev = get_azx_dev(substream);
1574         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1575         struct snd_pcm_runtime *runtime = substream->runtime;
1576         unsigned int bufsize, period_bytes, format_val;
1577         int err;
1578
1579         azx_stream_reset(chip, azx_dev);
1580         format_val = snd_hda_calc_stream_format(runtime->rate,
1581                                                 runtime->channels,
1582                                                 runtime->format,
1583                                                 hinfo->maxbps);
1584         if (!format_val) {
1585                 snd_printk(KERN_ERR SFX
1586                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1587                            runtime->rate, runtime->channels, runtime->format);
1588                 return -EINVAL;
1589         }
1590
1591         bufsize = snd_pcm_lib_buffer_bytes(substream);
1592         period_bytes = snd_pcm_lib_period_bytes(substream);
1593
1594         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1595                     bufsize, format_val);
1596
1597         if (bufsize != azx_dev->bufsize ||
1598             period_bytes != azx_dev->period_bytes ||
1599             format_val != azx_dev->format_val) {
1600                 azx_dev->bufsize = bufsize;
1601                 azx_dev->period_bytes = period_bytes;
1602                 azx_dev->format_val = format_val;
1603                 err = azx_setup_periods(chip, substream, azx_dev);
1604                 if (err < 0)
1605                         return err;
1606         }
1607
1608         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1609                                                 (runtime->rate * 2);
1610         azx_setup_controller(chip, azx_dev);
1611         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1612                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1613         else
1614                 azx_dev->fifo_size = 0;
1615
1616         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1617                                   azx_dev->format_val, substream);
1618 }
1619
1620 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1621 {
1622         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1623         struct azx *chip = apcm->chip;
1624         struct azx_dev *azx_dev;
1625         struct snd_pcm_substream *s;
1626         int rstart = 0, start, nsync = 0, sbits = 0;
1627         int nwait, timeout;
1628
1629         switch (cmd) {
1630         case SNDRV_PCM_TRIGGER_START:
1631                 rstart = 1;
1632         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1633         case SNDRV_PCM_TRIGGER_RESUME:
1634                 start = 1;
1635                 break;
1636         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1637         case SNDRV_PCM_TRIGGER_SUSPEND:
1638         case SNDRV_PCM_TRIGGER_STOP:
1639                 start = 0;
1640                 break;
1641         default:
1642                 return -EINVAL;
1643         }
1644
1645         snd_pcm_group_for_each_entry(s, substream) {
1646                 if (s->pcm->card != substream->pcm->card)
1647                         continue;
1648                 azx_dev = get_azx_dev(s);
1649                 sbits |= 1 << azx_dev->index;
1650                 nsync++;
1651                 snd_pcm_trigger_done(s, substream);
1652         }
1653
1654         spin_lock(&chip->reg_lock);
1655         if (nsync > 1) {
1656                 /* first, set SYNC bits of corresponding streams */
1657                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1658         }
1659         snd_pcm_group_for_each_entry(s, substream) {
1660                 if (s->pcm->card != substream->pcm->card)
1661                         continue;
1662                 azx_dev = get_azx_dev(s);
1663                 if (rstart) {
1664                         azx_dev->start_flag = 1;
1665                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1666                 }
1667                 if (start)
1668                         azx_stream_start(chip, azx_dev);
1669                 else
1670                         azx_stream_stop(chip, azx_dev);
1671                 azx_dev->running = start;
1672         }
1673         spin_unlock(&chip->reg_lock);
1674         if (start) {
1675                 if (nsync == 1)
1676                         return 0;
1677                 /* wait until all FIFOs get ready */
1678                 for (timeout = 5000; timeout; timeout--) {
1679                         nwait = 0;
1680                         snd_pcm_group_for_each_entry(s, substream) {
1681                                 if (s->pcm->card != substream->pcm->card)
1682                                         continue;
1683                                 azx_dev = get_azx_dev(s);
1684                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1685                                       SD_STS_FIFO_READY))
1686                                         nwait++;
1687                         }
1688                         if (!nwait)
1689                                 break;
1690                         cpu_relax();
1691                 }
1692         } else {
1693                 /* wait until all RUN bits are cleared */
1694                 for (timeout = 5000; timeout; timeout--) {
1695                         nwait = 0;
1696                         snd_pcm_group_for_each_entry(s, substream) {
1697                                 if (s->pcm->card != substream->pcm->card)
1698                                         continue;
1699                                 azx_dev = get_azx_dev(s);
1700                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1701                                     SD_CTL_DMA_START)
1702                                         nwait++;
1703                         }
1704                         if (!nwait)
1705                                 break;
1706                         cpu_relax();
1707                 }
1708         }
1709         if (nsync > 1) {
1710                 spin_lock(&chip->reg_lock);
1711                 /* reset SYNC bits */
1712                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1713                 spin_unlock(&chip->reg_lock);
1714         }
1715         return 0;
1716 }
1717
1718 /* get the current DMA position with correction on VIA chips */
1719 static unsigned int azx_via_get_position(struct azx *chip,
1720                                          struct azx_dev *azx_dev)
1721 {
1722         unsigned int link_pos, mini_pos, bound_pos;
1723         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1724         unsigned int fifo_size;
1725
1726         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1727         if (azx_dev->index >= 4) {
1728                 /* Playback, no problem using link position */
1729                 return link_pos;
1730         }
1731
1732         /* Capture */
1733         /* For new chipset,
1734          * use mod to get the DMA position just like old chipset
1735          */
1736         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1737         mod_dma_pos %= azx_dev->period_bytes;
1738
1739         /* azx_dev->fifo_size can't get FIFO size of in stream.
1740          * Get from base address + offset.
1741          */
1742         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1743
1744         if (azx_dev->insufficient) {
1745                 /* Link position never gather than FIFO size */
1746                 if (link_pos <= fifo_size)
1747                         return 0;
1748
1749                 azx_dev->insufficient = 0;
1750         }
1751
1752         if (link_pos <= fifo_size)
1753                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1754         else
1755                 mini_pos = link_pos - fifo_size;
1756
1757         /* Find nearest previous boudary */
1758         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1759         mod_link_pos = link_pos % azx_dev->period_bytes;
1760         if (mod_link_pos >= fifo_size)
1761                 bound_pos = link_pos - mod_link_pos;
1762         else if (mod_dma_pos >= mod_mini_pos)
1763                 bound_pos = mini_pos - mod_mini_pos;
1764         else {
1765                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1766                 if (bound_pos >= azx_dev->bufsize)
1767                         bound_pos = 0;
1768         }
1769
1770         /* Calculate real DMA position we want */
1771         return bound_pos + mod_dma_pos;
1772 }
1773
1774 static unsigned int azx_get_position(struct azx *chip,
1775                                      struct azx_dev *azx_dev)
1776 {
1777         unsigned int pos;
1778
1779         if (chip->via_dmapos_patch)
1780                 pos = azx_via_get_position(chip, azx_dev);
1781         else if (chip->position_fix == POS_FIX_POSBUF ||
1782                  chip->position_fix == POS_FIX_AUTO) {
1783                 /* use the position buffer */
1784                 pos = le32_to_cpu(*azx_dev->posbuf);
1785         } else {
1786                 /* read LPIB */
1787                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1788         }
1789         if (pos >= azx_dev->bufsize)
1790                 pos = 0;
1791         return pos;
1792 }
1793
1794 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1795 {
1796         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1797         struct azx *chip = apcm->chip;
1798         struct azx_dev *azx_dev = get_azx_dev(substream);
1799         return bytes_to_frames(substream->runtime,
1800                                azx_get_position(chip, azx_dev));
1801 }
1802
1803 /*
1804  * Check whether the current DMA position is acceptable for updating
1805  * periods.  Returns non-zero if it's OK.
1806  *
1807  * Many HD-audio controllers appear pretty inaccurate about
1808  * the update-IRQ timing.  The IRQ is issued before actually the
1809  * data is processed.  So, we need to process it afterwords in a
1810  * workqueue.
1811  */
1812 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1813 {
1814         unsigned int pos;
1815
1816         if (azx_dev->start_flag &&
1817             time_before_eq(jiffies, azx_dev->start_jiffies))
1818                 return -1;      /* bogus (too early) interrupt */
1819         azx_dev->start_flag = 0;
1820
1821         pos = azx_get_position(chip, azx_dev);
1822         if (chip->position_fix == POS_FIX_AUTO) {
1823                 if (!pos) {
1824                         printk(KERN_WARNING
1825                                "hda-intel: Invalid position buffer, "
1826                                "using LPIB read method instead.\n");
1827                         chip->position_fix = POS_FIX_LPIB;
1828                         pos = azx_get_position(chip, azx_dev);
1829                 } else
1830                         chip->position_fix = POS_FIX_POSBUF;
1831         }
1832
1833         if (!bdl_pos_adj[chip->dev_index])
1834                 return 1; /* no delayed ack */
1835         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1836                 return 0; /* NG - it's below the period boundary */
1837         return 1; /* OK, it's fine */
1838 }
1839
1840 /*
1841  * The work for pending PCM period updates.
1842  */
1843 static void azx_irq_pending_work(struct work_struct *work)
1844 {
1845         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1846         int i, pending;
1847
1848         if (!chip->irq_pending_warned) {
1849                 printk(KERN_WARNING
1850                        "hda-intel: IRQ timing workaround is activated "
1851                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1852                        chip->card->number);
1853                 chip->irq_pending_warned = 1;
1854         }
1855
1856         for (;;) {
1857                 pending = 0;
1858                 spin_lock_irq(&chip->reg_lock);
1859                 for (i = 0; i < chip->num_streams; i++) {
1860                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1861                         if (!azx_dev->irq_pending ||
1862                             !azx_dev->substream ||
1863                             !azx_dev->running)
1864                                 continue;
1865                         if (azx_position_ok(chip, azx_dev)) {
1866                                 azx_dev->irq_pending = 0;
1867                                 spin_unlock(&chip->reg_lock);
1868                                 snd_pcm_period_elapsed(azx_dev->substream);
1869                                 spin_lock(&chip->reg_lock);
1870                         } else
1871                                 pending++;
1872                 }
1873                 spin_unlock_irq(&chip->reg_lock);
1874                 if (!pending)
1875                         return;
1876                 cond_resched();
1877         }
1878 }
1879
1880 /* clear irq_pending flags and assure no on-going workq */
1881 static void azx_clear_irq_pending(struct azx *chip)
1882 {
1883         int i;
1884
1885         spin_lock_irq(&chip->reg_lock);
1886         for (i = 0; i < chip->num_streams; i++)
1887                 chip->azx_dev[i].irq_pending = 0;
1888         spin_unlock_irq(&chip->reg_lock);
1889 }
1890
1891 static struct snd_pcm_ops azx_pcm_ops = {
1892         .open = azx_pcm_open,
1893         .close = azx_pcm_close,
1894         .ioctl = snd_pcm_lib_ioctl,
1895         .hw_params = azx_pcm_hw_params,
1896         .hw_free = azx_pcm_hw_free,
1897         .prepare = azx_pcm_prepare,
1898         .trigger = azx_pcm_trigger,
1899         .pointer = azx_pcm_pointer,
1900         .page = snd_pcm_sgbuf_ops_page,
1901 };
1902
1903 static void azx_pcm_free(struct snd_pcm *pcm)
1904 {
1905         struct azx_pcm *apcm = pcm->private_data;
1906         if (apcm) {
1907                 apcm->chip->pcm[pcm->device] = NULL;
1908                 kfree(apcm);
1909         }
1910 }
1911
1912 static int
1913 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1914                       struct hda_pcm *cpcm)
1915 {
1916         struct azx *chip = bus->private_data;
1917         struct snd_pcm *pcm;
1918         struct azx_pcm *apcm;
1919         int pcm_dev = cpcm->device;
1920         int s, err;
1921
1922         if (pcm_dev >= AZX_MAX_PCMS) {
1923                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1924                            pcm_dev);
1925                 return -EINVAL;
1926         }
1927         if (chip->pcm[pcm_dev]) {
1928                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1929                 return -EBUSY;
1930         }
1931         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1932                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1933                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1934                           &pcm);
1935         if (err < 0)
1936                 return err;
1937         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1938         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1939         if (apcm == NULL)
1940                 return -ENOMEM;
1941         apcm->chip = chip;
1942         apcm->codec = codec;
1943         pcm->private_data = apcm;
1944         pcm->private_free = azx_pcm_free;
1945         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1946                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1947         chip->pcm[pcm_dev] = pcm;
1948         cpcm->pcm = pcm;
1949         for (s = 0; s < 2; s++) {
1950                 apcm->hinfo[s] = &cpcm->stream[s];
1951                 if (cpcm->stream[s].substreams)
1952                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1953         }
1954         /* buffer pre-allocation */
1955         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1956                                               snd_dma_pci_data(chip->pci),
1957                                               1024 * 64, 32 * 1024 * 1024);
1958         return 0;
1959 }
1960
1961 /*
1962  * mixer creation - all stuff is implemented in hda module
1963  */
1964 static int __devinit azx_mixer_create(struct azx *chip)
1965 {
1966         return snd_hda_build_controls(chip->bus);
1967 }
1968
1969
1970 /*
1971  * initialize SD streams
1972  */
1973 static int __devinit azx_init_stream(struct azx *chip)
1974 {
1975         int i;
1976
1977         /* initialize each stream (aka device)
1978          * assign the starting bdl address to each stream (device)
1979          * and initialize
1980          */
1981         for (i = 0; i < chip->num_streams; i++) {
1982                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1983                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1984                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1985                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1986                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1987                 azx_dev->sd_int_sta_mask = 1 << i;
1988                 /* stream tag: must be non-zero and unique */
1989                 azx_dev->index = i;
1990                 azx_dev->stream_tag = i + 1;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1997 {
1998         if (request_irq(chip->pci->irq, azx_interrupt,
1999                         chip->msi ? 0 : IRQF_SHARED,
2000                         "HDA Intel", chip)) {
2001                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2002                        "disabling device\n", chip->pci->irq);
2003                 if (do_disconnect)
2004                         snd_card_disconnect(chip->card);
2005                 return -1;
2006         }
2007         chip->irq = chip->pci->irq;
2008         pci_intx(chip->pci, !chip->msi);
2009         return 0;
2010 }
2011
2012
2013 static void azx_stop_chip(struct azx *chip)
2014 {
2015         if (!chip->initialized)
2016                 return;
2017
2018         /* disable interrupts */
2019         azx_int_disable(chip);
2020         azx_int_clear(chip);
2021
2022         /* disable CORB/RIRB */
2023         azx_free_cmd_io(chip);
2024
2025         /* disable position buffer */
2026         azx_writel(chip, DPLBASE, 0);
2027         azx_writel(chip, DPUBASE, 0);
2028
2029         chip->initialized = 0;
2030 }
2031
2032 #ifdef CONFIG_SND_HDA_POWER_SAVE
2033 /* power-up/down the controller */
2034 static void azx_power_notify(struct hda_bus *bus)
2035 {
2036         struct azx *chip = bus->private_data;
2037         struct hda_codec *c;
2038         int power_on = 0;
2039
2040         list_for_each_entry(c, &bus->codec_list, list) {
2041                 if (c->power_on) {
2042                         power_on = 1;
2043                         break;
2044                 }
2045         }
2046         if (power_on)
2047                 azx_init_chip(chip);
2048         else if (chip->running && power_save_controller)
2049                 azx_stop_chip(chip);
2050 }
2051 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2052
2053 #ifdef CONFIG_PM
2054 /*
2055  * power management
2056  */
2057
2058 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2059 {
2060         struct hda_codec *codec;
2061
2062         list_for_each_entry(codec, &bus->codec_list, list) {
2063                 if (snd_hda_codec_needs_resume(codec))
2064                         return 1;
2065         }
2066         return 0;
2067 }
2068
2069 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2070 {
2071         struct snd_card *card = pci_get_drvdata(pci);
2072         struct azx *chip = card->private_data;
2073         int i;
2074
2075         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2076         azx_clear_irq_pending(chip);
2077         for (i = 0; i < AZX_MAX_PCMS; i++)
2078                 snd_pcm_suspend_all(chip->pcm[i]);
2079         if (chip->initialized)
2080                 snd_hda_suspend(chip->bus);
2081         azx_stop_chip(chip);
2082         if (chip->irq >= 0) {
2083                 free_irq(chip->irq, chip);
2084                 chip->irq = -1;
2085         }
2086         if (chip->msi)
2087                 pci_disable_msi(chip->pci);
2088         pci_disable_device(pci);
2089         pci_save_state(pci);
2090         pci_set_power_state(pci, pci_choose_state(pci, state));
2091         return 0;
2092 }
2093
2094 static int azx_resume(struct pci_dev *pci)
2095 {
2096         struct snd_card *card = pci_get_drvdata(pci);
2097         struct azx *chip = card->private_data;
2098
2099         pci_set_power_state(pci, PCI_D0);
2100         pci_restore_state(pci);
2101         if (pci_enable_device(pci) < 0) {
2102                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2103                        "disabling device\n");
2104                 snd_card_disconnect(card);
2105                 return -EIO;
2106         }
2107         pci_set_master(pci);
2108         if (chip->msi)
2109                 if (pci_enable_msi(pci) < 0)
2110                         chip->msi = 0;
2111         if (azx_acquire_irq(chip, 1) < 0)
2112                 return -EIO;
2113         azx_init_pci(chip);
2114
2115         if (snd_hda_codecs_inuse(chip->bus))
2116                 azx_init_chip(chip);
2117
2118         snd_hda_resume(chip->bus);
2119         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2120         return 0;
2121 }
2122 #endif /* CONFIG_PM */
2123
2124
2125 /*
2126  * reboot notifier for hang-up problem at power-down
2127  */
2128 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2129 {
2130         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2131         azx_stop_chip(chip);
2132         return NOTIFY_OK;
2133 }
2134
2135 static void azx_notifier_register(struct azx *chip)
2136 {
2137         chip->reboot_notifier.notifier_call = azx_halt;
2138         register_reboot_notifier(&chip->reboot_notifier);
2139 }
2140
2141 static void azx_notifier_unregister(struct azx *chip)
2142 {
2143         if (chip->reboot_notifier.notifier_call)
2144                 unregister_reboot_notifier(&chip->reboot_notifier);
2145 }
2146
2147 /*
2148  * destructor
2149  */
2150 static int azx_free(struct azx *chip)
2151 {
2152         int i;
2153
2154         azx_notifier_unregister(chip);
2155
2156         if (chip->initialized) {
2157                 azx_clear_irq_pending(chip);
2158                 for (i = 0; i < chip->num_streams; i++)
2159                         azx_stream_stop(chip, &chip->azx_dev[i]);
2160                 azx_stop_chip(chip);
2161         }
2162
2163         if (chip->irq >= 0)
2164                 free_irq(chip->irq, (void*)chip);
2165         if (chip->msi)
2166                 pci_disable_msi(chip->pci);
2167         if (chip->remap_addr)
2168                 iounmap(chip->remap_addr);
2169
2170         if (chip->azx_dev) {
2171                 for (i = 0; i < chip->num_streams; i++)
2172                         if (chip->azx_dev[i].bdl.area)
2173                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2174         }
2175         if (chip->rb.area)
2176                 snd_dma_free_pages(&chip->rb);
2177         if (chip->posbuf.area)
2178                 snd_dma_free_pages(&chip->posbuf);
2179         pci_release_regions(chip->pci);
2180         pci_disable_device(chip->pci);
2181         kfree(chip->azx_dev);
2182         kfree(chip);
2183
2184         return 0;
2185 }
2186
2187 static int azx_dev_free(struct snd_device *device)
2188 {
2189         return azx_free(device->device_data);
2190 }
2191
2192 /*
2193  * white/black-listing for position_fix
2194  */
2195 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2196         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2197         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2198         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2199         {}
2200 };
2201
2202 static int __devinit check_position_fix(struct azx *chip, int fix)
2203 {
2204         const struct snd_pci_quirk *q;
2205
2206         switch (fix) {
2207         case POS_FIX_LPIB:
2208         case POS_FIX_POSBUF:
2209                 return fix;
2210         }
2211
2212         /* Check VIA/ATI HD Audio Controller exist */
2213         switch (chip->driver_type) {
2214         case AZX_DRIVER_VIA:
2215         case AZX_DRIVER_ATI:
2216                 chip->via_dmapos_patch = 1;
2217                 /* Use link position directly, avoid any transfer problem. */
2218                 return POS_FIX_LPIB;
2219         }
2220         chip->via_dmapos_patch = 0;
2221
2222         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2223         if (q) {
2224                 printk(KERN_INFO
2225                        "hda_intel: position_fix set to %d "
2226                        "for device %04x:%04x\n",
2227                        q->value, q->subvendor, q->subdevice);
2228                 return q->value;
2229         }
2230         return POS_FIX_AUTO;
2231 }
2232
2233 /*
2234  * black-lists for probe_mask
2235  */
2236 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2237         /* Thinkpad often breaks the controller communication when accessing
2238          * to the non-working (or non-existing) modem codec slot.
2239          */
2240         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2241         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2242         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2243         /* broken BIOS */
2244         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2245         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2246         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2247         /* forced codec slots */
2248         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2249         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2250         {}
2251 };
2252
2253 #define AZX_FORCE_CODEC_MASK    0x100
2254
2255 static void __devinit check_probe_mask(struct azx *chip, int dev)
2256 {
2257         const struct snd_pci_quirk *q;
2258
2259         chip->codec_probe_mask = probe_mask[dev];
2260         if (chip->codec_probe_mask == -1) {
2261                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2262                 if (q) {
2263                         printk(KERN_INFO
2264                                "hda_intel: probe_mask set to 0x%x "
2265                                "for device %04x:%04x\n",
2266                                q->value, q->subvendor, q->subdevice);
2267                         chip->codec_probe_mask = q->value;
2268                 }
2269         }
2270
2271         /* check forced option */
2272         if (chip->codec_probe_mask != -1 &&
2273             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2274                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2275                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2276                        chip->codec_mask);
2277         }
2278 }
2279
2280
2281 /*
2282  * constructor
2283  */
2284 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2285                                 int dev, int driver_type,
2286                                 struct azx **rchip)
2287 {
2288         struct azx *chip;
2289         int i, err;
2290         unsigned short gcap;
2291         static struct snd_device_ops ops = {
2292                 .dev_free = azx_dev_free,
2293         };
2294
2295         *rchip = NULL;
2296
2297         err = pci_enable_device(pci);
2298         if (err < 0)
2299                 return err;
2300
2301         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2302         if (!chip) {
2303                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2304                 pci_disable_device(pci);
2305                 return -ENOMEM;
2306         }
2307
2308         spin_lock_init(&chip->reg_lock);
2309         mutex_init(&chip->open_mutex);
2310         chip->card = card;
2311         chip->pci = pci;
2312         chip->irq = -1;
2313         chip->driver_type = driver_type;
2314         chip->msi = enable_msi;
2315         chip->dev_index = dev;
2316         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2317
2318         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2319         check_probe_mask(chip, dev);
2320
2321         chip->single_cmd = single_cmd;
2322
2323         if (bdl_pos_adj[dev] < 0) {
2324                 switch (chip->driver_type) {
2325                 case AZX_DRIVER_ICH:
2326                         bdl_pos_adj[dev] = 1;
2327                         break;
2328                 default:
2329                         bdl_pos_adj[dev] = 32;
2330                         break;
2331                 }
2332         }
2333
2334 #if BITS_PER_LONG != 64
2335         /* Fix up base address on ULI M5461 */
2336         if (chip->driver_type == AZX_DRIVER_ULI) {
2337                 u16 tmp3;
2338                 pci_read_config_word(pci, 0x40, &tmp3);
2339                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2340                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2341         }
2342 #endif
2343
2344         err = pci_request_regions(pci, "ICH HD audio");
2345         if (err < 0) {
2346                 kfree(chip);
2347                 pci_disable_device(pci);
2348                 return err;
2349         }
2350
2351         chip->addr = pci_resource_start(pci, 0);
2352         chip->remap_addr = pci_ioremap_bar(pci, 0);
2353         if (chip->remap_addr == NULL) {
2354                 snd_printk(KERN_ERR SFX "ioremap error\n");
2355                 err = -ENXIO;
2356                 goto errout;
2357         }
2358
2359         if (chip->msi)
2360                 if (pci_enable_msi(pci) < 0)
2361                         chip->msi = 0;
2362
2363         if (azx_acquire_irq(chip, 0) < 0) {
2364                 err = -EBUSY;
2365                 goto errout;
2366         }
2367
2368         pci_set_master(pci);
2369         synchronize_irq(chip->irq);
2370
2371         gcap = azx_readw(chip, GCAP);
2372         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2373
2374         /* disable SB600 64bit support for safety */
2375         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2376             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2377                 struct pci_dev *p_smbus;
2378                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2379                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2380                                          NULL);
2381                 if (p_smbus) {
2382                         if (p_smbus->revision < 0x30)
2383                                 gcap &= ~ICH6_GCAP_64OK;
2384                         pci_dev_put(p_smbus);
2385                 }
2386         }
2387
2388         /* allow 64bit DMA address if supported by H/W */
2389         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2390                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2391         else {
2392                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2393                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2394         }
2395
2396         /* read number of streams from GCAP register instead of using
2397          * hardcoded value
2398          */
2399         chip->capture_streams = (gcap >> 8) & 0x0f;
2400         chip->playback_streams = (gcap >> 12) & 0x0f;
2401         if (!chip->playback_streams && !chip->capture_streams) {
2402                 /* gcap didn't give any info, switching to old method */
2403
2404                 switch (chip->driver_type) {
2405                 case AZX_DRIVER_ULI:
2406                         chip->playback_streams = ULI_NUM_PLAYBACK;
2407                         chip->capture_streams = ULI_NUM_CAPTURE;
2408                         break;
2409                 case AZX_DRIVER_ATIHDMI:
2410                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2411                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2412                         break;
2413                 case AZX_DRIVER_GENERIC:
2414                 default:
2415                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2416                         chip->capture_streams = ICH6_NUM_CAPTURE;
2417                         break;
2418                 }
2419         }
2420         chip->capture_index_offset = 0;
2421         chip->playback_index_offset = chip->capture_streams;
2422         chip->num_streams = chip->playback_streams + chip->capture_streams;
2423         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2424                                 GFP_KERNEL);
2425         if (!chip->azx_dev) {
2426                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2427                 goto errout;
2428         }
2429
2430         for (i = 0; i < chip->num_streams; i++) {
2431                 /* allocate memory for the BDL for each stream */
2432                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2433                                           snd_dma_pci_data(chip->pci),
2434                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2435                 if (err < 0) {
2436                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2437                         goto errout;
2438                 }
2439         }
2440         /* allocate memory for the position buffer */
2441         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2442                                   snd_dma_pci_data(chip->pci),
2443                                   chip->num_streams * 8, &chip->posbuf);
2444         if (err < 0) {
2445                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2446                 goto errout;
2447         }
2448         /* allocate CORB/RIRB */
2449         err = azx_alloc_cmd_io(chip);
2450         if (err < 0)
2451                 goto errout;
2452
2453         /* initialize streams */
2454         azx_init_stream(chip);
2455
2456         /* initialize chip */
2457         azx_init_pci(chip);
2458         azx_init_chip(chip);
2459
2460         /* codec detection */
2461         if (!chip->codec_mask) {
2462                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2463                 err = -ENODEV;
2464                 goto errout;
2465         }
2466
2467         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2468         if (err <0) {
2469                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2470                 goto errout;
2471         }
2472
2473         strcpy(card->driver, "HDA-Intel");
2474         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2475                 sizeof(card->shortname));
2476         snprintf(card->longname, sizeof(card->longname),
2477                  "%s at 0x%lx irq %i",
2478                  card->shortname, chip->addr, chip->irq);
2479
2480         *rchip = chip;
2481         return 0;
2482
2483  errout:
2484         azx_free(chip);
2485         return err;
2486 }
2487
2488 static void power_down_all_codecs(struct azx *chip)
2489 {
2490 #ifdef CONFIG_SND_HDA_POWER_SAVE
2491         /* The codecs were powered up in snd_hda_codec_new().
2492          * Now all initialization done, so turn them down if possible
2493          */
2494         struct hda_codec *codec;
2495         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2496                 snd_hda_power_down(codec);
2497         }
2498 #endif
2499 }
2500
2501 static int __devinit azx_probe(struct pci_dev *pci,
2502                                const struct pci_device_id *pci_id)
2503 {
2504         static int dev;
2505         struct snd_card *card;
2506         struct azx *chip;
2507         int err;
2508
2509         if (dev >= SNDRV_CARDS)
2510                 return -ENODEV;
2511         if (!enable[dev]) {
2512                 dev++;
2513                 return -ENOENT;
2514         }
2515
2516         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2517         if (err < 0) {
2518                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2519                 return err;
2520         }
2521
2522         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2523         if (err < 0)
2524                 goto out_free;
2525         card->private_data = chip;
2526
2527         /* create codec instances */
2528         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2529         if (err < 0)
2530                 goto out_free;
2531
2532         /* create PCM streams */
2533         err = snd_hda_build_pcms(chip->bus);
2534         if (err < 0)
2535                 goto out_free;
2536
2537         /* create mixer controls */
2538         err = azx_mixer_create(chip);
2539         if (err < 0)
2540                 goto out_free;
2541
2542         snd_card_set_dev(card, &pci->dev);
2543
2544         err = snd_card_register(card);
2545         if (err < 0)
2546                 goto out_free;
2547
2548         pci_set_drvdata(pci, card);
2549         chip->running = 1;
2550         power_down_all_codecs(chip);
2551         azx_notifier_register(chip);
2552
2553         dev++;
2554         return err;
2555 out_free:
2556         snd_card_free(card);
2557         return err;
2558 }
2559
2560 static void __devexit azx_remove(struct pci_dev *pci)
2561 {
2562         snd_card_free(pci_get_drvdata(pci));
2563         pci_set_drvdata(pci, NULL);
2564 }
2565
2566 /* PCI IDs */
2567 static struct pci_device_id azx_ids[] = {
2568         /* ICH 6..10 */
2569         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2570         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2571         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2572         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2573         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2574         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2575         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2576         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2577         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2578         /* PCH */
2579         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2580         /* SCH */
2581         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2582         /* ATI SB 450/600 */
2583         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2584         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2585         /* ATI HDMI */
2586         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2587         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2588         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2589         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2590         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2591         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2592         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2593         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2594         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2595         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2596         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2597         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2598         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2599         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2600         /* VIA VT8251/VT8237A */
2601         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2602         /* SIS966 */
2603         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2604         /* ULI M5461 */
2605         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2606         /* NVIDIA MCP */
2607         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2608         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2609         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2610         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2611         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2612         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2613         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2614         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2615         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2616         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2617         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2618         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2619         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2620         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2621         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2622         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2623         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2624         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2625         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2626         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2627         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2628         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2629         /* Teradici */
2630         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2631         /* Creative X-Fi (CA0110-IBG) */
2632 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2633         /* the following entry conflicts with snd-ctxfi driver,
2634          * as ctxfi driver mutates from HD-audio to native mode with
2635          * a special command sequence.
2636          */
2637         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2638           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2639           .class_mask = 0xffffff,
2640           .driver_data = AZX_DRIVER_GENERIC },
2641 #else
2642         /* this entry seems still valid -- i.e. without emu20kx chip */
2643         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2644 #endif
2645         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2646         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2647           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2648           .class_mask = 0xffffff,
2649           .driver_data = AZX_DRIVER_GENERIC },
2650         { 0, }
2651 };
2652 MODULE_DEVICE_TABLE(pci, azx_ids);
2653
2654 /* pci_driver definition */
2655 static struct pci_driver driver = {
2656         .name = "HDA Intel",
2657         .id_table = azx_ids,
2658         .probe = azx_probe,
2659         .remove = __devexit_p(azx_remove),
2660 #ifdef CONFIG_PM
2661         .suspend = azx_suspend,
2662         .resume = azx_resume,
2663 #endif
2664 };
2665
2666 static int __init alsa_card_azx_init(void)
2667 {
2668         return pci_register_driver(&driver);
2669 }
2670
2671 static void __exit alsa_card_azx_exit(void)
2672 {
2673         pci_unregister_driver(&driver);
2674 }
2675
2676 module_init(alsa_card_azx_init)
2677 module_exit(alsa_card_azx_exit)