ALSA: HDA: Fix MODPOST errors
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <linux/clk.h>
50 #include <sound/core.h>
51 #include <sound/initval.h>
52 #include "hda_codec.h"
53
54
55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
58 static char *model[SNDRV_CARDS];
59 static int position_fix[SNDRV_CARDS];
60 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
62 static int probe_only[SNDRV_CARDS];
63 static int single_cmd;
64 static int enable_msi = -1;
65 #ifdef CONFIG_SND_HDA_PATCH_LOADER
66 static char *patch[SNDRV_CARDS];
67 #endif
68 #ifdef CONFIG_SND_HDA_INPUT_BEEP
69 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
70                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
71 #endif
72
73 module_param_array(index, int, NULL, 0444);
74 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
75 module_param_array(id, charp, NULL, 0444);
76 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
77 module_param_array(enable, bool, NULL, 0444);
78 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
79 module_param_array(model, charp, NULL, 0444);
80 MODULE_PARM_DESC(model, "Use the given board model.");
81 module_param_array(position_fix, int, NULL, 0444);
82 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
83                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
84 module_param_array(bdl_pos_adj, int, NULL, 0644);
85 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
86 module_param_array(probe_mask, int, NULL, 0444);
87 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
88 module_param_array(probe_only, int, NULL, 0444);
89 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
90 module_param(single_cmd, bool, 0444);
91 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
92                  "(for debugging only).");
93 module_param(enable_msi, int, 0444);
94 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
95 #ifdef CONFIG_SND_HDA_PATCH_LOADER
96 module_param_array(patch, charp, NULL, 0444);
97 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
98 #endif
99 #ifdef CONFIG_SND_HDA_INPUT_BEEP
100 module_param_array(beep_mode, int, NULL, 0444);
101 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
102                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
103 #endif
104
105 #ifdef CONFIG_SND_HDA_POWER_SAVE
106 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
107 module_param(power_save, int, 0644);
108 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
109                  "(in second, 0 = disable).");
110
111 /* reset the HD-audio controller in power save mode.
112  * this may give more power-saving, but will take longer time to
113  * wake up.
114  */
115 static int power_save_controller = 1;
116 module_param(power_save_controller, bool, 0644);
117 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
118 #endif
119
120 MODULE_LICENSE("GPL");
121 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
122                          "{Intel, ICH6M},"
123                          "{Intel, ICH7},"
124                          "{Intel, ESB2},"
125                          "{Intel, ICH8},"
126                          "{Intel, ICH9},"
127                          "{Intel, ICH10},"
128                          "{Intel, PCH},"
129                          "{Intel, CPT},"
130                          "{Intel, PPT},"
131                          "{Intel, PBG},"
132                          "{Intel, SCH},"
133                          "{ATI, SB450},"
134                          "{ATI, SB600},"
135                          "{ATI, RS600},"
136                          "{ATI, RS690},"
137                          "{ATI, RS780},"
138                          "{ATI, R600},"
139                          "{ATI, RV630},"
140                          "{ATI, RV610},"
141                          "{ATI, RV670},"
142                          "{ATI, RV635},"
143                          "{ATI, RV620},"
144                          "{ATI, RV770},"
145                          "{VIA, VT8251},"
146                          "{VIA, VT8237A},"
147                          "{SiS, SIS966},"
148                          "{ULI, M5461}}");
149 MODULE_DESCRIPTION("Intel HDA driver");
150
151 #ifdef CONFIG_SND_VERBOSE_PRINTK
152 #define SFX     /* nop */
153 #else
154 #define SFX     "hda-intel: "
155 #endif
156
157 /*
158  * registers
159  */
160 #define ICH6_REG_GCAP                   0x00
161 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
162 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
163 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
164 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
165 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
166 #define ICH6_REG_VMIN                   0x02
167 #define ICH6_REG_VMAJ                   0x03
168 #define ICH6_REG_OUTPAY                 0x04
169 #define ICH6_REG_INPAY                  0x06
170 #define ICH6_REG_GCTL                   0x08
171 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
172 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
173 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
174 #define ICH6_REG_WAKEEN                 0x0c
175 #define ICH6_REG_STATESTS               0x0e
176 #define ICH6_REG_GSTS                   0x10
177 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
178 #define ICH6_REG_INTCTL                 0x20
179 #define ICH6_REG_INTSTS                 0x24
180 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
181 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
182 #define ICH6_REG_SSYNC                  0x38
183 #define ICH6_REG_CORBLBASE              0x40
184 #define ICH6_REG_CORBUBASE              0x44
185 #define ICH6_REG_CORBWP                 0x48
186 #define ICH6_REG_CORBRP                 0x4a
187 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
188 #define ICH6_REG_CORBCTL                0x4c
189 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
190 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
191 #define ICH6_REG_CORBSTS                0x4d
192 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
193 #define ICH6_REG_CORBSIZE               0x4e
194
195 #define ICH6_REG_RIRBLBASE              0x50
196 #define ICH6_REG_RIRBUBASE              0x54
197 #define ICH6_REG_RIRBWP                 0x58
198 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
199 #define ICH6_REG_RINTCNT                0x5a
200 #define ICH6_REG_RIRBCTL                0x5c
201 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
202 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
203 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
204 #define ICH6_REG_RIRBSTS                0x5d
205 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
206 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
207 #define ICH6_REG_RIRBSIZE               0x5e
208
209 #define ICH6_REG_IC                     0x60
210 #define ICH6_REG_IR                     0x64
211 #define ICH6_REG_IRS                    0x68
212 #define   ICH6_IRS_VALID        (1<<1)
213 #define   ICH6_IRS_BUSY         (1<<0)
214
215 #define ICH6_REG_DPLBASE                0x70
216 #define ICH6_REG_DPUBASE                0x74
217 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
218
219 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
220 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
221
222 /* stream register offsets from stream base */
223 #define ICH6_REG_SD_CTL                 0x00
224 #define ICH6_REG_SD_STS                 0x03
225 #define ICH6_REG_SD_LPIB                0x04
226 #define ICH6_REG_SD_CBL                 0x08
227 #define ICH6_REG_SD_LVI                 0x0c
228 #define ICH6_REG_SD_FIFOW               0x0e
229 #define ICH6_REG_SD_FIFOSIZE            0x10
230 #define ICH6_REG_SD_FORMAT              0x12
231 #define ICH6_REG_SD_BDLPL               0x18
232 #define ICH6_REG_SD_BDLPU               0x1c
233
234 /* PCI space */
235 #define ICH6_PCIREG_TCSEL       0x44
236
237 /*
238  * other constants
239  */
240
241 /* max number of SDs */
242 /* ICH, ATI and VIA have 4 playback and 4 capture */
243 #define ICH6_NUM_CAPTURE        4
244 #define ICH6_NUM_PLAYBACK       4
245
246 /* ULI has 6 playback and 5 capture */
247 #define ULI_NUM_CAPTURE         5
248 #define ULI_NUM_PLAYBACK        6
249
250 /* ATI HDMI has 1 playback and 0 capture */
251 #define ATIHDMI_NUM_CAPTURE     0
252 #define ATIHDMI_NUM_PLAYBACK    1
253
254 /* TERA has 4 playback and 3 capture */
255 #define TERA_NUM_CAPTURE        3
256 #define TERA_NUM_PLAYBACK       4
257
258 /* this number is statically defined for simplicity */
259 #define MAX_AZX_DEV             16
260
261 /* max number of fragments - we may use more if allocating more pages for BDL */
262 #define BDL_SIZE                4096
263 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
264 #define AZX_MAX_FRAG            32
265 /* max buffer size - no h/w limit, you can increase as you like */
266 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
267
268 /* RIRB int mask: overrun[2], response[0] */
269 #define RIRB_INT_RESPONSE       0x01
270 #define RIRB_INT_OVERRUN        0x04
271 #define RIRB_INT_MASK           0x05
272
273 /* STATESTS int mask: S3,SD2,SD1,SD0 */
274 #define AZX_MAX_CODECS          8
275 #define AZX_DEFAULT_CODECS      4
276 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
277
278 /* SD_CTL bits */
279 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
280 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
281 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
282 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
283 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
284 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
285 #define SD_CTL_STREAM_TAG_SHIFT 20
286
287 /* SD_CTL and SD_STS */
288 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
289 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
290 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
291 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
292                                  SD_INT_COMPLETE)
293
294 /* SD_STS */
295 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
296
297 /* INTCTL and INTSTS */
298 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
299 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
300 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
301
302 /* below are so far hardcoded - should read registers in future */
303 #define ICH6_MAX_CORB_ENTRIES   256
304 #define ICH6_MAX_RIRB_ENTRIES   256
305
306 /* position fix mode */
307 enum {
308         POS_FIX_AUTO,
309         POS_FIX_LPIB,
310         POS_FIX_POSBUF,
311         POS_FIX_VIACOMBO,
312 };
313
314 /* Defines for ATI HD Audio support in SB450 south bridge */
315 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
316 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
317
318 /* Defines for Nvidia HDA support */
319 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
320 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
321 #define NVIDIA_HDA_ISTRM_COH          0x4d
322 #define NVIDIA_HDA_OSTRM_COH          0x4c
323 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
324
325 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
326 /* Defines for Nvidia Tegra HDA support */
327 #define NVIDIA_TEGRA_HDA_BAR0_OFFSET           0x8000
328
329 #define NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET        0x1004
330 #define NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET       0x1010
331
332 #define NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE       (1 << 0)
333 #define NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE      (1 << 1)
334 #define NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER     (1 << 2)
335 #define NVIDIA_TEGRA_HDA_ENABLE_SERR           (1 << 8)
336 #define NVIDIA_TEGRA_HDA_DISABLE_INTR          (1 << 10)
337 #define NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
338 #define NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM    (1 << 14)
339
340 /* IPFS */
341 #define NVIDIA_TEGRA_HDA_IPFS_CONFIG           0x180
342 #define NVIDIA_TEGRA_HDA_IPFS_EN_FPCI          0x1
343
344 #define NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0        0x80
345 #define NVIDIA_TEGRA_HDA_FPCI_BAR0_START       0x40
346
347 #define NVIDIA_TEGRA_HDA_IPFS_INTR_MASK        0x188
348 #define NVIDIA_TEGRA_HDA_IPFS_EN_INTR          (1 << 16)
349 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
350
351 /* Defines for Intel SCH HDA snoop control */
352 #define INTEL_SCH_HDA_DEVC      0x78
353 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
354
355 /* Define IN stream 0 FIFO size offset in VIA controller */
356 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
357 /* Define VIA HD Audio Device ID*/
358 #define VIA_HDAC_DEVICE_ID              0x3288
359
360 /* HD Audio class code */
361 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
362
363 /*
364  */
365
366 struct azx_dev {
367         struct snd_dma_buffer bdl; /* BDL buffer */
368         u32 *posbuf;            /* position buffer pointer */
369
370         unsigned int bufsize;   /* size of the play buffer in bytes */
371         unsigned int period_bytes; /* size of the period in bytes */
372         unsigned int frags;     /* number for period in the play buffer */
373         unsigned int fifo_size; /* FIFO size */
374         unsigned long start_wallclk;    /* start + minimum wallclk */
375         unsigned long period_wallclk;   /* wallclk for period */
376
377         void __iomem *sd_addr;  /* stream descriptor pointer */
378
379         u32 sd_int_sta_mask;    /* stream int status mask */
380
381         /* pcm support */
382         struct snd_pcm_substream *substream;    /* assigned substream,
383                                                  * set in PCM open
384                                                  */
385         unsigned int format_val;        /* format value to be set in the
386                                          * controller and the codec
387                                          */
388         unsigned char stream_tag;       /* assigned stream */
389         unsigned char index;            /* stream index */
390         int device;                     /* last device number assigned to */
391
392         unsigned int opened :1;
393         unsigned int running :1;
394         unsigned int irq_pending :1;
395         /*
396          * For VIA:
397          *  A flag to ensure DMA position is 0
398          *  when link position is not greater than FIFO size
399          */
400         unsigned int insufficient :1;
401 };
402
403 /* CORB/RIRB */
404 struct azx_rb {
405         u32 *buf;               /* CORB/RIRB buffer
406                                  * Each CORB entry is 4byte, RIRB is 8byte
407                                  */
408         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
409         /* for RIRB */
410         unsigned short rp, wp;  /* read/write pointers */
411         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
412         u32 res[AZX_MAX_CODECS];        /* last read value */
413 };
414
415 struct azx {
416         struct snd_card *card;
417         struct pci_dev *pci;
418         struct platform_device *pdev;
419         struct device *dev;
420         int irq_id;
421         int dev_index;
422
423         /* chip type specific */
424         int driver_type;
425         unsigned int driver_caps;
426         int playback_streams;
427         int playback_index_offset;
428         int capture_streams;
429         int capture_index_offset;
430         int num_streams;
431
432         /* pci resources */
433         unsigned long addr;
434         void __iomem *remap_addr;
435 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
436         void __iomem *remap_config_addr;
437 #endif
438         int irq;
439
440 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
441         /* platform driver clocks */
442         struct clk **platform_clks;
443         int platform_clk_count;
444         int platform_clk_enable;
445 #endif
446
447         /* locks */
448         spinlock_t reg_lock;
449         struct mutex open_mutex;
450
451         /* streams (x num_streams) */
452         struct azx_dev *azx_dev;
453
454         /* PCM */
455         struct snd_pcm *pcm[HDA_MAX_PCMS];
456
457         /* HD codec */
458         unsigned short codec_mask;
459         int  codec_probe_mask; /* copied from probe_mask option */
460         struct hda_bus *bus;
461         unsigned int beep_mode;
462
463         /* CORB/RIRB */
464         struct azx_rb corb;
465         struct azx_rb rirb;
466
467         /* CORB/RIRB and position buffers */
468         struct snd_dma_buffer rb;
469         struct snd_dma_buffer posbuf;
470
471         /* flags */
472         int position_fix[2]; /* for both playback/capture streams */
473         int poll_count;
474         unsigned int running :1;
475         unsigned int initialized :1;
476         unsigned int single_cmd :1;
477         unsigned int polling_mode :1;
478         unsigned int msi :1;
479         unsigned int irq_pending_warned :1;
480         unsigned int probing :1; /* codec probing phase */
481
482         /* for debugging */
483         unsigned int last_cmd[AZX_MAX_CODECS];
484
485         /* for pending irqs */
486         struct work_struct irq_pending_work;
487
488         /* reboot notifier (for mysterious hangup problem at power-down) */
489         struct notifier_block reboot_notifier;
490 };
491
492 /* driver types */
493 enum {
494         AZX_DRIVER_ICH,
495         AZX_DRIVER_PCH,
496         AZX_DRIVER_SCH,
497         AZX_DRIVER_ATI,
498         AZX_DRIVER_ATIHDMI,
499         AZX_DRIVER_VIA,
500         AZX_DRIVER_SIS,
501         AZX_DRIVER_ULI,
502         AZX_DRIVER_NVIDIA,
503         AZX_DRIVER_NVIDIA_TEGRA,
504         AZX_DRIVER_TERA,
505         AZX_DRIVER_CTX,
506         AZX_DRIVER_GENERIC,
507         AZX_NUM_DRIVERS, /* keep this as last entry */
508 };
509
510 /* driver quirks (capabilities) */
511 /* bits 0-7 are used for indicating driver type */
512 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
513 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
514 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
515 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
516 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
517 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
518 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
519 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
520 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
521 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
522 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
523 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
524 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
525
526 /* quirks for ATI SB / AMD Hudson */
527 #define AZX_DCAPS_PRESET_ATI_SB \
528         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
529          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
530
531 /* quirks for ATI/AMD HDMI */
532 #define AZX_DCAPS_PRESET_ATI_HDMI \
533         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
534
535 /* quirks for Nvidia */
536 #define AZX_DCAPS_PRESET_NVIDIA \
537         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
538
539 static char *driver_short_names[] __devinitdata = {
540         [AZX_DRIVER_ICH] = "HDA Intel",
541         [AZX_DRIVER_PCH] = "HDA Intel PCH",
542         [AZX_DRIVER_SCH] = "HDA Intel MID",
543         [AZX_DRIVER_ATI] = "HDA ATI SB",
544         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
545         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
546         [AZX_DRIVER_SIS] = "HDA SIS966",
547         [AZX_DRIVER_ULI] = "HDA ULI M5461",
548         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
549         [AZX_DRIVER_NVIDIA_TEGRA] = "HDA NVIDIA Tegra",
550         [AZX_DRIVER_TERA] = "HDA Teradici", 
551         [AZX_DRIVER_CTX] = "HDA Creative", 
552         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
553 };
554
555 /*
556  * macros for easy use
557  */
558 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
559 #define MASK_LONG_ALIGN         0x3UL
560 #define SHIFT_BYTE              3
561 #define SHIFT_BITS(reg)         ((reg & MASK_LONG_ALIGN) << SHIFT_BYTE)
562 #define ADDR_ALIGN_L(base, reg) (base + (reg & ~MASK_LONG_ALIGN))
563 #define MASK(bits)              (BIT(bits) - 1)
564 #define MASK_REG(reg, bits)     (MASK(bits) << SHIFT_BITS(reg))
565
566 #define tegra_write(base, reg, val, bits) \
567         writel((readl(ADDR_ALIGN_L(base, reg)) & ~MASK_REG(reg, bits)) | \
568                ((val) << SHIFT_BITS(reg)), ADDR_ALIGN_L(base, reg))
569
570 #define tegra_read(base, reg, bits) \
571         ((readl(ADDR_ALIGN_L(base, reg)) >> SHIFT_BITS(reg)) & MASK(bits))
572
573 #define azx_writel(chip, reg, value) \
574         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
575 #define azx_readl(chip, reg) \
576         readl((chip)->remap_addr + ICH6_REG_##reg)
577 #define azx_writew(chip, reg, value) \
578         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 16)
579 #define azx_readw(chip, reg) \
580         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 16)
581 #define azx_writeb(chip, reg, value) \
582         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 8)
583 #define azx_readb(chip, reg) \
584         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 8)
585
586 #define azx_sd_writel(dev, reg, value) \
587         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
588 #define azx_sd_readl(dev, reg) \
589         readl((dev)->sd_addr + ICH6_REG_##reg)
590 #define azx_sd_writew(dev, reg, value) \
591         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 16)
592 #define azx_sd_readw(dev, reg) \
593         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 16)
594 #define azx_sd_writeb(dev, reg, value) \
595         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 8)
596 #define azx_sd_readb(dev, reg) \
597         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 8)
598
599 #else /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
600 #define azx_writel(chip,reg,value) \
601         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
602 #define azx_readl(chip,reg) \
603         readl((chip)->remap_addr + ICH6_REG_##reg)
604 #define azx_writew(chip,reg,value) \
605         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
606 #define azx_readw(chip,reg) \
607         readw((chip)->remap_addr + ICH6_REG_##reg)
608 #define azx_writeb(chip,reg,value) \
609         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
610 #define azx_readb(chip,reg) \
611         readb((chip)->remap_addr + ICH6_REG_##reg)
612
613 #define azx_sd_writel(dev,reg,value) \
614         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
615 #define azx_sd_readl(dev,reg) \
616         readl((dev)->sd_addr + ICH6_REG_##reg)
617 #define azx_sd_writew(dev,reg,value) \
618         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
619 #define azx_sd_readw(dev,reg) \
620         readw((dev)->sd_addr + ICH6_REG_##reg)
621 #define azx_sd_writeb(dev,reg,value) \
622         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
623 #define azx_sd_readb(dev,reg) \
624         readb((dev)->sd_addr + ICH6_REG_##reg)
625
626 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
627
628 /* for pcm support */
629 #define get_azx_dev(substream) (substream->runtime->private_data)
630
631 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
632 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
633 /*
634  * Interface for HD codec
635  */
636
637 /*
638  * CORB / RIRB interface
639  */
640 static int azx_alloc_cmd_io(struct azx *chip)
641 {
642         int err;
643
644         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
645         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
646                                   chip->dev,
647                                   PAGE_SIZE, &chip->rb);
648         if (err < 0) {
649                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
650                 return err;
651         }
652         return 0;
653 }
654
655 static void azx_init_cmd_io(struct azx *chip)
656 {
657         spin_lock_irq(&chip->reg_lock);
658         /* CORB set up */
659         chip->corb.addr = chip->rb.addr;
660         chip->corb.buf = (u32 *)chip->rb.area;
661         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
662         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
663
664         /* set the corb size to 256 entries (ULI requires explicitly) */
665         azx_writeb(chip, CORBSIZE, 0x02);
666         /* set the corb write pointer to 0 */
667         azx_writew(chip, CORBWP, 0);
668         /* reset the corb hw read pointer */
669         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
670         /* enable corb dma */
671         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
672
673         /* RIRB set up */
674         chip->rirb.addr = chip->rb.addr + 2048;
675         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
676         chip->rirb.wp = chip->rirb.rp = 0;
677         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
678         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
679         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
680
681         /* set the rirb size to 256 entries (ULI requires explicitly) */
682         azx_writeb(chip, RIRBSIZE, 0x02);
683         /* reset the rirb hw write pointer */
684         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
685         /* set N=1, get RIRB response interrupt for new entry */
686         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
687                 azx_writew(chip, RINTCNT, 0xc0);
688         else
689                 azx_writew(chip, RINTCNT, 1);
690         /* enable rirb dma and response irq */
691         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
692         spin_unlock_irq(&chip->reg_lock);
693 }
694
695 static void azx_free_cmd_io(struct azx *chip)
696 {
697         spin_lock_irq(&chip->reg_lock);
698         /* disable ringbuffer DMAs */
699         azx_writeb(chip, RIRBCTL, 0);
700         azx_writeb(chip, CORBCTL, 0);
701         spin_unlock_irq(&chip->reg_lock);
702 }
703
704 static unsigned int azx_command_addr(u32 cmd)
705 {
706         unsigned int addr = cmd >> 28;
707
708         if (addr >= AZX_MAX_CODECS) {
709                 snd_BUG();
710                 addr = 0;
711         }
712
713         return addr;
714 }
715
716 static unsigned int azx_response_addr(u32 res)
717 {
718         unsigned int addr = res & 0xf;
719
720         if (addr >= AZX_MAX_CODECS) {
721                 snd_BUG();
722                 addr = 0;
723         }
724
725         return addr;
726 }
727
728 /* send a command */
729 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
730 {
731         struct azx *chip = bus->private_data;
732         unsigned int addr = azx_command_addr(val);
733         unsigned int wp;
734
735         spin_lock_irq(&chip->reg_lock);
736
737         /* add command to corb */
738         wp = azx_readb(chip, CORBWP);
739         wp++;
740         wp %= ICH6_MAX_CORB_ENTRIES;
741
742         chip->rirb.cmds[addr]++;
743         chip->corb.buf[wp] = cpu_to_le32(val);
744         azx_writel(chip, CORBWP, wp);
745
746         spin_unlock_irq(&chip->reg_lock);
747
748         return 0;
749 }
750
751 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
752
753 /* retrieve RIRB entry - called from interrupt handler */
754 static void azx_update_rirb(struct azx *chip)
755 {
756         unsigned int rp, wp;
757         unsigned int addr;
758         u32 res, res_ex;
759
760         wp = azx_readb(chip, RIRBWP);
761         if (wp == chip->rirb.wp)
762                 return;
763         chip->rirb.wp = wp;
764
765         while (chip->rirb.rp != wp) {
766                 chip->rirb.rp++;
767                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
768
769                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
770                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
771                 res = le32_to_cpu(chip->rirb.buf[rp]);
772                 addr = azx_response_addr(res_ex);
773                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
774                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
775                 else if (chip->rirb.cmds[addr]) {
776                         chip->rirb.res[addr] = res;
777                         smp_wmb();
778                         chip->rirb.cmds[addr]--;
779                 } else
780                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
781                                    "last cmd=%#08x\n",
782                                    res, res_ex,
783                                    chip->last_cmd[addr]);
784         }
785 }
786
787 /* receive a response */
788 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
789                                           unsigned int addr)
790 {
791         struct azx *chip = bus->private_data;
792         unsigned long timeout;
793         int do_poll = 0;
794
795  again:
796         timeout = jiffies + msecs_to_jiffies(1000);
797         for (;;) {
798                 if (chip->polling_mode || do_poll) {
799                         spin_lock_irq(&chip->reg_lock);
800                         azx_update_rirb(chip);
801                         spin_unlock_irq(&chip->reg_lock);
802                 }
803                 if (!chip->rirb.cmds[addr]) {
804                         smp_rmb();
805                         bus->rirb_error = 0;
806
807                         if (!do_poll)
808                                 chip->poll_count = 0;
809                         return chip->rirb.res[addr]; /* the last value */
810                 }
811                 if (time_after(jiffies, timeout))
812                         break;
813                 if (bus->needs_damn_long_delay)
814                         msleep(2); /* temporary workaround */
815                 else {
816                         udelay(10);
817                         cond_resched();
818                 }
819         }
820
821         if (!chip->polling_mode && chip->poll_count < 2) {
822                 snd_printdd(SFX "azx_get_response timeout, "
823                            "polling the codec once: last cmd=0x%08x\n",
824                            chip->last_cmd[addr]);
825                 do_poll = 1;
826                 chip->poll_count++;
827                 goto again;
828         }
829
830
831         if (!chip->polling_mode) {
832                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
833                            "switching to polling mode: last cmd=0x%08x\n",
834                            chip->last_cmd[addr]);
835                 chip->polling_mode = 1;
836                 goto again;
837         }
838
839         if (chip->msi) {
840                 snd_printk(KERN_WARNING SFX "No response from codec, "
841                            "disabling MSI: last cmd=0x%08x\n",
842                            chip->last_cmd[addr]);
843                 free_irq(chip->irq, chip);
844                 chip->irq = -1;
845                 pci_disable_msi(chip->pci);
846                 chip->msi = 0;
847                 if (azx_acquire_irq(chip, 1) < 0) {
848                         bus->rirb_error = 1;
849                         return -1;
850                 }
851                 goto again;
852         }
853
854         if (chip->probing) {
855                 /* If this critical timeout happens during the codec probing
856                  * phase, this is likely an access to a non-existing codec
857                  * slot.  Better to return an error and reset the system.
858                  */
859                 return -1;
860         }
861
862         /* a fatal communication error; need either to reset or to fallback
863          * to the single_cmd mode
864          */
865         bus->rirb_error = 1;
866         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
867                 bus->response_reset = 1;
868                 return -1; /* give a chance to retry */
869         }
870
871         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
872                    "switching to single_cmd mode: last cmd=0x%08x\n",
873                    chip->last_cmd[addr]);
874         chip->single_cmd = 1;
875         bus->response_reset = 0;
876         /* release CORB/RIRB */
877         azx_free_cmd_io(chip);
878         /* disable unsolicited responses */
879         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
880         return -1;
881 }
882
883 /*
884  * Use the single immediate command instead of CORB/RIRB for simplicity
885  *
886  * Note: according to Intel, this is not preferred use.  The command was
887  *       intended for the BIOS only, and may get confused with unsolicited
888  *       responses.  So, we shouldn't use it for normal operation from the
889  *       driver.
890  *       I left the codes, however, for debugging/testing purposes.
891  */
892
893 /* receive a response */
894 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
895 {
896         int timeout = 50;
897
898         while (timeout--) {
899                 /* check IRV busy bit */
900                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
901                         /* reuse rirb.res as the response return value */
902                         chip->rirb.res[addr] = azx_readl(chip, IR);
903                         return 0;
904                 }
905                 udelay(1);
906         }
907         if (printk_ratelimit())
908                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
909                            azx_readw(chip, IRS));
910         chip->rirb.res[addr] = -1;
911         return -EIO;
912 }
913
914 /* send a command */
915 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
916 {
917         struct azx *chip = bus->private_data;
918         unsigned int addr = azx_command_addr(val);
919         int timeout = 50;
920
921         bus->rirb_error = 0;
922         while (timeout--) {
923                 /* check ICB busy bit */
924                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
925                         /* Clear IRV valid bit */
926                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
927                                    ICH6_IRS_VALID);
928                         azx_writel(chip, IC, val);
929                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
930                                    ICH6_IRS_BUSY);
931                         return azx_single_wait_for_response(chip, addr);
932                 }
933                 udelay(1);
934         }
935         if (printk_ratelimit())
936                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
937                            azx_readw(chip, IRS), val);
938         return -EIO;
939 }
940
941 /* receive a response */
942 static unsigned int azx_single_get_response(struct hda_bus *bus,
943                                             unsigned int addr)
944 {
945         struct azx *chip = bus->private_data;
946         return chip->rirb.res[addr];
947 }
948
949 /*
950  * The below are the main callbacks from hda_codec.
951  *
952  * They are just the skeleton to call sub-callbacks according to the
953  * current setting of chip->single_cmd.
954  */
955
956 /* send a command */
957 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
958 {
959         struct azx *chip = bus->private_data;
960
961         chip->last_cmd[azx_command_addr(val)] = val;
962         if (chip->single_cmd)
963                 return azx_single_send_cmd(bus, val);
964         else
965                 return azx_corb_send_cmd(bus, val);
966 }
967
968 /* get a response */
969 static unsigned int azx_get_response(struct hda_bus *bus,
970                                      unsigned int addr)
971 {
972         struct azx *chip = bus->private_data;
973         if (chip->single_cmd)
974                 return azx_single_get_response(bus, addr);
975         else
976                 return azx_rirb_get_response(bus, addr);
977 }
978
979 #ifdef CONFIG_SND_HDA_POWER_SAVE
980 static void azx_power_notify(struct hda_bus *bus);
981 #endif
982
983 /* reset codec link */
984 static int azx_reset(struct azx *chip, int full_reset)
985 {
986         int count;
987
988         if (!full_reset)
989                 goto __skip;
990
991         /* clear STATESTS */
992         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
993
994         /* reset controller */
995         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
996
997         count = 50;
998         while (azx_readb(chip, GCTL) && --count)
999                 msleep(1);
1000
1001         /* delay for >= 100us for codec PLL to settle per spec
1002          * Rev 0.9 section 5.5.1
1003          */
1004         msleep(1);
1005
1006         /* Bring controller out of reset */
1007         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1008
1009         count = 50;
1010         while (!azx_readb(chip, GCTL) && --count)
1011                 msleep(1);
1012
1013         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1014         msleep(1);
1015
1016       __skip:
1017         /* check to see if controller is ready */
1018         if (!azx_readb(chip, GCTL)) {
1019                 snd_printd(SFX "azx_reset: controller not ready!\n");
1020                 return -EBUSY;
1021         }
1022
1023         /* Accept unsolicited responses */
1024         if (!chip->single_cmd)
1025                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1026                            ICH6_GCTL_UNSOL);
1027
1028         /* detect codecs */
1029         if (!chip->codec_mask) {
1030                 chip->codec_mask = azx_readw(chip, STATESTS);
1031                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1032         }
1033
1034         return 0;
1035 }
1036
1037
1038 /*
1039  * Lowlevel interface
1040  */  
1041
1042 /* enable interrupts */
1043 static void azx_int_enable(struct azx *chip)
1044 {
1045         /* enable controller CIE and GIE */
1046         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1047                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1048 }
1049
1050 /* disable interrupts */
1051 static void azx_int_disable(struct azx *chip)
1052 {
1053         int i;
1054
1055         /* disable interrupts in stream descriptor */
1056         for (i = 0; i < chip->num_streams; i++) {
1057                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1058                 azx_sd_writeb(azx_dev, SD_CTL,
1059                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1060         }
1061
1062         /* disable SIE for all streams */
1063         azx_writeb(chip, INTCTL, 0);
1064
1065         /* disable controller CIE and GIE */
1066         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1067                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1068 }
1069
1070 /* clear interrupts */
1071 static void azx_int_clear(struct azx *chip)
1072 {
1073         int i;
1074
1075         /* clear stream status */
1076         for (i = 0; i < chip->num_streams; i++) {
1077                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1078                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1079         }
1080
1081         /* clear STATESTS */
1082         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1083
1084         /* clear rirb status */
1085         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1086
1087         /* clear int status */
1088         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1089 }
1090
1091 /* start a stream */
1092 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1093 {
1094         /*
1095          * Before stream start, initialize parameter
1096          */
1097         azx_dev->insufficient = 1;
1098
1099         /* enable SIE */
1100         azx_writel(chip, INTCTL,
1101                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1102         /* set DMA start and interrupt mask */
1103         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1104                       SD_CTL_DMA_START | SD_INT_MASK);
1105 }
1106
1107 /* stop DMA */
1108 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1109 {
1110         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1111                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1112         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1113 }
1114
1115 /* stop a stream */
1116 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1117 {
1118         azx_stream_clear(chip, azx_dev);
1119         /* disable SIE */
1120         azx_writel(chip, INTCTL,
1121                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1122 }
1123
1124
1125 /*
1126  * reset and start the controller registers
1127  */
1128 static void azx_init_chip(struct azx *chip, int full_reset)
1129 {
1130         if (chip->initialized)
1131                 return;
1132
1133         /* reset controller */
1134         azx_reset(chip, full_reset);
1135
1136         /* initialize interrupts */
1137         azx_int_clear(chip);
1138         azx_int_enable(chip);
1139
1140         /* initialize the codec command I/O */
1141         if (!chip->single_cmd)
1142                 azx_init_cmd_io(chip);
1143
1144         /* program the position buffer */
1145         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1146         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1147
1148         chip->initialized = 1;
1149 }
1150
1151 /*
1152  * initialize the PCI registers
1153  */
1154 /* update bits in a PCI register byte */
1155 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1156                             unsigned char mask, unsigned char val)
1157 {
1158         unsigned char data;
1159
1160         pci_read_config_byte(pci, reg, &data);
1161         data &= ~mask;
1162         data |= (val & mask);
1163         pci_write_config_byte(pci, reg, data);
1164 }
1165
1166 static void azx_init_pci(struct azx *chip)
1167 {
1168         unsigned short snoop;
1169
1170         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1171          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1172          * Ensuring these bits are 0 clears playback static on some HD Audio
1173          * codecs.
1174          * The PCI register TCSEL is defined in the Intel manuals.
1175          */
1176         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1177                 snd_printdd(SFX "Clearing TCSEL\n");
1178                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1179         }
1180
1181         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1182          * we need to enable snoop.
1183          */
1184         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1185                 snd_printdd(SFX "Enabling ATI snoop\n");
1186                 update_pci_byte(chip->pci,
1187                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1188                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1189         }
1190
1191         /* For NVIDIA HDA, enable snoop */
1192         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1193                 snd_printdd(SFX "Enabling Nvidia snoop\n");
1194                 update_pci_byte(chip->pci,
1195                                 NVIDIA_HDA_TRANSREG_ADDR,
1196                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1197                 update_pci_byte(chip->pci,
1198                                 NVIDIA_HDA_ISTRM_COH,
1199                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1200                 update_pci_byte(chip->pci,
1201                                 NVIDIA_HDA_OSTRM_COH,
1202                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1203         }
1204
1205         /* Enable SCH/PCH snoop if needed */
1206         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1207                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1208                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1209                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1210                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1211                         pci_read_config_word(chip->pci,
1212                                 INTEL_SCH_HDA_DEVC, &snoop);
1213                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1214                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1215                                 ? "Failed" : "OK");
1216                 }
1217         }
1218 }
1219
1220 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
1221 /*
1222  * initialize the platform specific registers
1223  */
1224 static void reg_update_bits(void __iomem *base, unsigned int reg,
1225                             unsigned int mask, unsigned int val)
1226 {
1227         unsigned int data;
1228
1229         data = readl(base + reg);
1230         data &= ~mask;
1231         data |= (val & mask);
1232         writel(data, base + reg);
1233 }
1234
1235 static void azx_init_platform(struct azx *chip)
1236 {
1237         switch (chip->driver_type) {
1238 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1239         case AZX_DRIVER_NVIDIA_TEGRA:
1240                 /*Enable the PCI access */
1241                 reg_update_bits(chip->remap_config_addr,
1242                                 NVIDIA_TEGRA_HDA_IPFS_CONFIG,
1243                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI,
1244                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI);
1245                 /* Enable MEM/IO space and bus master */
1246                 reg_update_bits(chip->remap_config_addr,
1247                                 NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET, 0x507,
1248                                 NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE |
1249                                 NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE |
1250                                 NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER |
1251                                 NVIDIA_TEGRA_HDA_ENABLE_SERR);
1252                 reg_update_bits(chip->remap_config_addr,
1253                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1254                                 NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM);
1255                 reg_update_bits(chip->remap_config_addr,
1256                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1257                                 NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM);
1258                 reg_update_bits(chip->remap_config_addr,
1259                                 NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0, 0xFFFFFFFF,
1260                                 NVIDIA_TEGRA_HDA_FPCI_BAR0_START);
1261                 reg_update_bits(chip->remap_config_addr,
1262                                 NVIDIA_TEGRA_HDA_IPFS_INTR_MASK,
1263                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR,
1264                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR);
1265                 break;
1266 #endif
1267         default:
1268                 break;
1269         }
1270
1271         return;
1272 }
1273
1274 static void azx_platform_enable_clocks(struct azx *chip)
1275 {
1276         int i;
1277
1278         for (i = 0; i < chip->platform_clk_count; i++)
1279                 clk_enable(chip->platform_clks[i]);
1280
1281         chip->platform_clk_enable++;
1282 }
1283
1284 static void azx_platform_disable_clocks(struct azx *chip)
1285 {
1286         int i;
1287
1288         if (!chip->platform_clk_enable)
1289                 return;
1290
1291         for (i = 0; i < chip->platform_clk_count; i++)
1292                 clk_disable(chip->platform_clks[i]);
1293
1294         chip->platform_clk_enable--;
1295 }
1296 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
1297
1298 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1299
1300 /*
1301  * interrupt handler
1302  */
1303 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1304 {
1305         struct azx *chip = dev_id;
1306         struct azx_dev *azx_dev;
1307         u32 status;
1308         u8 sd_status;
1309         int i, ok;
1310
1311         spin_lock(&chip->reg_lock);
1312
1313         status = azx_readl(chip, INTSTS);
1314         if (status == 0) {
1315                 spin_unlock(&chip->reg_lock);
1316                 return IRQ_NONE;
1317         }
1318         
1319         for (i = 0; i < chip->num_streams; i++) {
1320                 azx_dev = &chip->azx_dev[i];
1321                 if (status & azx_dev->sd_int_sta_mask) {
1322                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1323                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1324                         if (!azx_dev->substream || !azx_dev->running ||
1325                             !(sd_status & SD_INT_COMPLETE))
1326                                 continue;
1327                         /* check whether this IRQ is really acceptable */
1328                         ok = azx_position_ok(chip, azx_dev);
1329                         if (ok == 1) {
1330                                 azx_dev->irq_pending = 0;
1331                                 spin_unlock(&chip->reg_lock);
1332                                 snd_pcm_period_elapsed(azx_dev->substream);
1333                                 spin_lock(&chip->reg_lock);
1334                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1335                                 /* bogus IRQ, process it later */
1336                                 azx_dev->irq_pending = 1;
1337                                 queue_work(chip->bus->workq,
1338                                            &chip->irq_pending_work);
1339                         }
1340                 }
1341         }
1342
1343         /* clear rirb int */
1344         status = azx_readb(chip, RIRBSTS);
1345         if (status & RIRB_INT_MASK) {
1346                 if (status & RIRB_INT_RESPONSE) {
1347                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1348                                 udelay(80);
1349                         azx_update_rirb(chip);
1350                 }
1351                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1352         }
1353
1354 #if 0
1355         /* clear state status int */
1356         if (azx_readb(chip, STATESTS) & 0x04)
1357                 azx_writeb(chip, STATESTS, 0x04);
1358 #endif
1359         spin_unlock(&chip->reg_lock);
1360         
1361         return IRQ_HANDLED;
1362 }
1363
1364
1365 /*
1366  * set up a BDL entry
1367  */
1368 static int setup_bdle(struct snd_pcm_substream *substream,
1369                       struct azx_dev *azx_dev, u32 **bdlp,
1370                       int ofs, int size, int with_ioc)
1371 {
1372         u32 *bdl = *bdlp;
1373
1374         while (size > 0) {
1375                 dma_addr_t addr;
1376                 int chunk;
1377
1378                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1379                         return -EINVAL;
1380
1381                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1382                 /* program the address field of the BDL entry */
1383                 bdl[0] = cpu_to_le32((u32)addr);
1384                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1385                 /* program the size field of the BDL entry */
1386                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1387                 bdl[2] = cpu_to_le32(chunk);
1388                 /* program the IOC to enable interrupt
1389                  * only when the whole fragment is processed
1390                  */
1391                 size -= chunk;
1392                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1393                 bdl += 4;
1394                 azx_dev->frags++;
1395                 ofs += chunk;
1396         }
1397         *bdlp = bdl;
1398         return ofs;
1399 }
1400
1401 /*
1402  * set up BDL entries
1403  */
1404 static int azx_setup_periods(struct azx *chip,
1405                              struct snd_pcm_substream *substream,
1406                              struct azx_dev *azx_dev)
1407 {
1408         u32 *bdl;
1409         int i, ofs, periods, period_bytes;
1410         int pos_adj;
1411
1412         /* reset BDL address */
1413         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1414         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1415
1416         period_bytes = azx_dev->period_bytes;
1417         periods = azx_dev->bufsize / period_bytes;
1418
1419         /* program the initial BDL entries */
1420         bdl = (u32 *)azx_dev->bdl.area;
1421         ofs = 0;
1422         azx_dev->frags = 0;
1423         pos_adj = bdl_pos_adj[chip->dev_index];
1424         if (pos_adj > 0) {
1425                 struct snd_pcm_runtime *runtime = substream->runtime;
1426                 int pos_align = pos_adj;
1427                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1428                 if (!pos_adj)
1429                         pos_adj = pos_align;
1430                 else
1431                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1432                                 pos_align;
1433                 pos_adj = frames_to_bytes(runtime, pos_adj);
1434                 if (pos_adj >= period_bytes) {
1435                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1436                                    bdl_pos_adj[chip->dev_index]);
1437                         pos_adj = 0;
1438                 } else {
1439                         ofs = setup_bdle(substream, azx_dev,
1440                                          &bdl, ofs, pos_adj,
1441                                          !substream->runtime->no_period_wakeup);
1442                         if (ofs < 0)
1443                                 goto error;
1444                 }
1445         } else
1446                 pos_adj = 0;
1447         for (i = 0; i < periods; i++) {
1448                 if (i == periods - 1 && pos_adj)
1449                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1450                                          period_bytes - pos_adj, 0);
1451                 else
1452                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1453                                          period_bytes,
1454                                          !substream->runtime->no_period_wakeup);
1455                 if (ofs < 0)
1456                         goto error;
1457         }
1458         return 0;
1459
1460  error:
1461         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1462                    azx_dev->bufsize, period_bytes);
1463         return -EINVAL;
1464 }
1465
1466 /* reset stream */
1467 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1468 {
1469         unsigned char val;
1470         int timeout;
1471
1472         azx_stream_clear(chip, azx_dev);
1473
1474         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1475                       SD_CTL_STREAM_RESET);
1476         udelay(3);
1477         timeout = 300;
1478         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1479                --timeout)
1480                 ;
1481         val &= ~SD_CTL_STREAM_RESET;
1482         azx_sd_writeb(azx_dev, SD_CTL, val);
1483         udelay(3);
1484
1485         timeout = 300;
1486         /* waiting for hardware to report that the stream is out of reset */
1487         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1488                --timeout)
1489                 ;
1490
1491         /* reset first position - may not be synced with hw at this time */
1492         *azx_dev->posbuf = 0;
1493 }
1494
1495 /*
1496  * set up the SD for streaming
1497  */
1498 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1499 {
1500         /* make sure the run bit is zero for SD */
1501         azx_stream_clear(chip, azx_dev);
1502         /* program the stream_tag */
1503         azx_sd_writel(azx_dev, SD_CTL,
1504                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1505                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1506
1507         /* program the length of samples in cyclic buffer */
1508         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1509
1510         /* program the stream format */
1511         /* this value needs to be the same as the one programmed */
1512         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1513
1514         /* program the stream LVI (last valid index) of the BDL */
1515         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1516
1517         /* program the BDL address */
1518         /* lower BDL address */
1519         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1520         /* upper BDL address */
1521         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1522
1523         /* enable the position buffer */
1524         if (chip->position_fix[0] != POS_FIX_LPIB ||
1525             chip->position_fix[1] != POS_FIX_LPIB) {
1526                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1527                         azx_writel(chip, DPLBASE,
1528                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1529         }
1530
1531         /* set the interrupt enable bits in the descriptor control register */
1532         azx_sd_writel(azx_dev, SD_CTL,
1533                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1534
1535         return 0;
1536 }
1537
1538 /*
1539  * Probe the given codec address
1540  */
1541 static int probe_codec(struct azx *chip, int addr)
1542 {
1543         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1544                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1545         unsigned int res;
1546
1547         mutex_lock(&chip->bus->cmd_mutex);
1548         chip->probing = 1;
1549         azx_send_cmd(chip->bus, cmd);
1550         res = azx_get_response(chip->bus, addr);
1551         chip->probing = 0;
1552         mutex_unlock(&chip->bus->cmd_mutex);
1553         if (res == -1)
1554                 return -EIO;
1555         snd_printdd(SFX "codec #%d probed OK\n", addr);
1556         return 0;
1557 }
1558
1559 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1560                                  struct hda_pcm *cpcm);
1561 static void azx_stop_chip(struct azx *chip);
1562
1563 static void azx_bus_reset(struct hda_bus *bus)
1564 {
1565         struct azx *chip = bus->private_data;
1566
1567         bus->in_reset = 1;
1568         azx_stop_chip(chip);
1569         azx_init_chip(chip, 1);
1570 #ifdef CONFIG_PM
1571         if (chip->initialized) {
1572                 int i;
1573
1574                 for (i = 0; i < HDA_MAX_PCMS; i++)
1575                         snd_pcm_suspend_all(chip->pcm[i]);
1576                 snd_hda_suspend(chip->bus);
1577                 snd_hda_resume(chip->bus);
1578         }
1579 #endif
1580         bus->in_reset = 0;
1581 }
1582
1583 /*
1584  * Codec initialization
1585  */
1586
1587 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1588 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1589         [AZX_DRIVER_NVIDIA] = 8,
1590         [AZX_DRIVER_TERA] = 1,
1591 };
1592
1593 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1594 {
1595         struct hda_bus_template bus_temp;
1596         int c, codecs, err;
1597         int max_slots;
1598
1599         memset(&bus_temp, 0, sizeof(bus_temp));
1600         bus_temp.private_data = chip;
1601         bus_temp.modelname = model;
1602         bus_temp.pci = chip->pci;
1603         bus_temp.pdev = chip->pdev;
1604         bus_temp.ops.command = azx_send_cmd;
1605         bus_temp.ops.get_response = azx_get_response;
1606         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1607         bus_temp.ops.bus_reset = azx_bus_reset;
1608 #ifdef CONFIG_SND_HDA_POWER_SAVE
1609         bus_temp.power_save = &power_save;
1610         bus_temp.ops.pm_notify = azx_power_notify;
1611 #endif
1612
1613         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1614         if (err < 0)
1615                 return err;
1616
1617         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1618                 snd_printd(SFX "Enable delay in RIRB handling\n");
1619                 chip->bus->needs_damn_long_delay = 1;
1620         }
1621
1622         codecs = 0;
1623         max_slots = azx_max_codecs[chip->driver_type];
1624         if (!max_slots)
1625                 max_slots = AZX_DEFAULT_CODECS;
1626
1627         /* First try to probe all given codec slots */
1628         for (c = 0; c < max_slots; c++) {
1629                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1630                         if (probe_codec(chip, c) < 0) {
1631                                 /* Some BIOSen give you wrong codec addresses
1632                                  * that don't exist
1633                                  */
1634                                 snd_printk(KERN_WARNING SFX
1635                                            "Codec #%d probe error; "
1636                                            "disabling it...\n", c);
1637                                 chip->codec_mask &= ~(1 << c);
1638                                 /* More badly, accessing to a non-existing
1639                                  * codec often screws up the controller chip,
1640                                  * and disturbs the further communications.
1641                                  * Thus if an error occurs during probing,
1642                                  * better to reset the controller chip to
1643                                  * get back to the sanity state.
1644                                  */
1645                                 azx_stop_chip(chip);
1646                                 azx_init_chip(chip, 1);
1647                         }
1648                 }
1649         }
1650
1651         /* AMD chipsets often cause the communication stalls upon certain
1652          * sequence like the pin-detection.  It seems that forcing the synced
1653          * access works around the stall.  Grrr...
1654          */
1655         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1656                 snd_printd(SFX "Enable sync_write for stable communication\n");
1657                 chip->bus->sync_write = 1;
1658                 chip->bus->allow_bus_reset = 1;
1659         }
1660
1661         /* Then create codec instances */
1662         for (c = 0; c < max_slots; c++) {
1663                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1664                         struct hda_codec *codec;
1665                         err = snd_hda_codec_new(chip->bus, c, &codec);
1666                         if (err < 0)
1667                                 continue;
1668                         codec->beep_mode = chip->beep_mode;
1669                         codecs++;
1670                 }
1671         }
1672         if (!codecs) {
1673                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1674                 return -ENXIO;
1675         }
1676         return 0;
1677 }
1678
1679 /* configure each codec instance */
1680 static int __devinit azx_codec_configure(struct azx *chip)
1681 {
1682         struct hda_codec *codec;
1683         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684                 snd_hda_codec_configure(codec);
1685         }
1686         return 0;
1687 }
1688
1689
1690 /*
1691  * PCM support
1692  */
1693
1694 /* assign a stream for the PCM */
1695 static inline struct azx_dev *
1696 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1697 {
1698         int dev, i, nums;
1699         struct azx_dev *res = NULL;
1700
1701         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1702                 dev = chip->playback_index_offset;
1703                 nums = chip->playback_streams;
1704         } else {
1705                 dev = chip->capture_index_offset;
1706                 nums = chip->capture_streams;
1707         }
1708         for (i = 0; i < nums; i++, dev++)
1709                 if (!chip->azx_dev[dev].opened) {
1710                         res = &chip->azx_dev[dev];
1711                         if (res->device == substream->pcm->device)
1712                                 break;
1713                 }
1714         if (res) {
1715                 res->opened = 1;
1716                 res->device = substream->pcm->device;
1717         }
1718         return res;
1719 }
1720
1721 /* release the assigned stream */
1722 static inline void azx_release_device(struct azx_dev *azx_dev)
1723 {
1724         azx_dev->opened = 0;
1725 }
1726
1727 static struct snd_pcm_hardware azx_pcm_hw = {
1728         .info =                 (SNDRV_PCM_INFO_MMAP |
1729                                  SNDRV_PCM_INFO_INTERLEAVED |
1730                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1731                                  SNDRV_PCM_INFO_MMAP_VALID |
1732                                  /* No full-resume yet implemented */
1733                                  /* SNDRV_PCM_INFO_RESUME |*/
1734                                  SNDRV_PCM_INFO_PAUSE |
1735                                  SNDRV_PCM_INFO_SYNC_START |
1736                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1737         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1738         .rates =                SNDRV_PCM_RATE_48000,
1739         .rate_min =             48000,
1740         .rate_max =             48000,
1741         .channels_min =         2,
1742         .channels_max =         2,
1743         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1744         .period_bytes_min =     128,
1745         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1746         .periods_min =          2,
1747         .periods_max =          AZX_MAX_FRAG,
1748         .fifo_size =            0,
1749 };
1750
1751 struct azx_pcm {
1752         struct azx *chip;
1753         struct hda_codec *codec;
1754         struct hda_pcm_stream *hinfo[2];
1755 };
1756
1757 static int azx_pcm_open(struct snd_pcm_substream *substream)
1758 {
1759         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1760         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1761         struct azx *chip = apcm->chip;
1762         struct azx_dev *azx_dev;
1763         struct snd_pcm_runtime *runtime = substream->runtime;
1764         unsigned long flags;
1765         int err;
1766
1767         mutex_lock(&chip->open_mutex);
1768         azx_dev = azx_assign_device(chip, substream);
1769         if (azx_dev == NULL) {
1770                 mutex_unlock(&chip->open_mutex);
1771                 return -EBUSY;
1772         }
1773         runtime->hw = azx_pcm_hw;
1774         runtime->hw.channels_min = hinfo->channels_min;
1775         runtime->hw.channels_max = hinfo->channels_max;
1776         runtime->hw.formats = hinfo->formats;
1777         runtime->hw.rates = hinfo->rates;
1778         snd_pcm_limit_hw_rates(runtime);
1779         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1780         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1781                                    128);
1782         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1783                                    128);
1784         snd_hda_power_up(apcm->codec);
1785         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1786         if (err < 0) {
1787                 azx_release_device(azx_dev);
1788                 snd_hda_power_down(apcm->codec);
1789                 mutex_unlock(&chip->open_mutex);
1790                 return err;
1791         }
1792         snd_pcm_limit_hw_rates(runtime);
1793         /* sanity check */
1794         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1795             snd_BUG_ON(!runtime->hw.channels_max) ||
1796             snd_BUG_ON(!runtime->hw.formats) ||
1797             snd_BUG_ON(!runtime->hw.rates)) {
1798                 azx_release_device(azx_dev);
1799                 hinfo->ops.close(hinfo, apcm->codec, substream);
1800                 snd_hda_power_down(apcm->codec);
1801                 mutex_unlock(&chip->open_mutex);
1802                 return -EINVAL;
1803         }
1804         spin_lock_irqsave(&chip->reg_lock, flags);
1805         azx_dev->substream = substream;
1806         azx_dev->running = 0;
1807         spin_unlock_irqrestore(&chip->reg_lock, flags);
1808
1809         runtime->private_data = azx_dev;
1810         snd_pcm_set_sync(substream);
1811         mutex_unlock(&chip->open_mutex);
1812         return 0;
1813 }
1814
1815 static int azx_pcm_close(struct snd_pcm_substream *substream)
1816 {
1817         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1818         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1819         struct azx *chip = apcm->chip;
1820         struct azx_dev *azx_dev = get_azx_dev(substream);
1821         unsigned long flags;
1822
1823         mutex_lock(&chip->open_mutex);
1824         spin_lock_irqsave(&chip->reg_lock, flags);
1825         azx_dev->substream = NULL;
1826         azx_dev->running = 0;
1827         spin_unlock_irqrestore(&chip->reg_lock, flags);
1828         azx_release_device(azx_dev);
1829         hinfo->ops.close(hinfo, apcm->codec, substream);
1830         snd_hda_power_down(apcm->codec);
1831         mutex_unlock(&chip->open_mutex);
1832         return 0;
1833 }
1834
1835 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1836                              struct snd_pcm_hw_params *hw_params)
1837 {
1838         struct azx_dev *azx_dev = get_azx_dev(substream);
1839
1840         azx_dev->bufsize = 0;
1841         azx_dev->period_bytes = 0;
1842         azx_dev->format_val = 0;
1843         return snd_pcm_lib_malloc_pages(substream,
1844                                         params_buffer_bytes(hw_params));
1845 }
1846
1847 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1848 {
1849         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1850         struct azx_dev *azx_dev = get_azx_dev(substream);
1851         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1852
1853         /* reset BDL address */
1854         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1855         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1856         azx_sd_writel(azx_dev, SD_CTL, 0);
1857         azx_dev->bufsize = 0;
1858         azx_dev->period_bytes = 0;
1859         azx_dev->format_val = 0;
1860
1861         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1862
1863         return snd_pcm_lib_free_pages(substream);
1864 }
1865
1866 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1867 {
1868         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1869         struct azx *chip = apcm->chip;
1870         struct azx_dev *azx_dev = get_azx_dev(substream);
1871         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1872         struct snd_pcm_runtime *runtime = substream->runtime;
1873         unsigned int bufsize, period_bytes, format_val, stream_tag;
1874         int err;
1875         struct hda_spdif_out *spdif =
1876                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1877         unsigned short ctls = spdif ? spdif->ctls : 0;
1878
1879         azx_stream_reset(chip, azx_dev);
1880         format_val = snd_hda_calc_stream_format(runtime->rate,
1881                                                 runtime->channels,
1882                                                 runtime->format,
1883                                                 hinfo->maxbps,
1884                                                 ctls);
1885         if (!format_val) {
1886                 snd_printk(KERN_ERR SFX
1887                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1888                            runtime->rate, runtime->channels, runtime->format);
1889                 return -EINVAL;
1890         }
1891
1892         bufsize = snd_pcm_lib_buffer_bytes(substream);
1893         period_bytes = snd_pcm_lib_period_bytes(substream);
1894
1895         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1896                     bufsize, format_val);
1897
1898         if (bufsize != azx_dev->bufsize ||
1899             period_bytes != azx_dev->period_bytes ||
1900             format_val != azx_dev->format_val) {
1901                 azx_dev->bufsize = bufsize;
1902                 azx_dev->period_bytes = period_bytes;
1903                 azx_dev->format_val = format_val;
1904                 err = azx_setup_periods(chip, substream, azx_dev);
1905                 if (err < 0)
1906                         return err;
1907         }
1908
1909         /* wallclk has 24Mhz clock source */
1910         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1911                                                 runtime->rate) * 1000);
1912         azx_setup_controller(chip, azx_dev);
1913         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1914                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1915         else
1916                 azx_dev->fifo_size = 0;
1917
1918         stream_tag = azx_dev->stream_tag;
1919         /* CA-IBG chips need the playback stream starting from 1 */
1920         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1921             stream_tag > chip->capture_streams)
1922                 stream_tag -= chip->capture_streams;
1923         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1924                                      azx_dev->format_val, substream);
1925 }
1926
1927 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1928 {
1929         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1930         struct azx *chip = apcm->chip;
1931         struct azx_dev *azx_dev;
1932         struct snd_pcm_substream *s;
1933         int rstart = 0, start, nsync = 0, sbits = 0;
1934         int nwait, timeout;
1935
1936         switch (cmd) {
1937         case SNDRV_PCM_TRIGGER_START:
1938                 rstart = 1;
1939         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1940         case SNDRV_PCM_TRIGGER_RESUME:
1941                 start = 1;
1942                 break;
1943         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1944         case SNDRV_PCM_TRIGGER_SUSPEND:
1945         case SNDRV_PCM_TRIGGER_STOP:
1946                 start = 0;
1947                 break;
1948         default:
1949                 return -EINVAL;
1950         }
1951
1952         snd_pcm_group_for_each_entry(s, substream) {
1953                 if (s->pcm->card != substream->pcm->card)
1954                         continue;
1955                 azx_dev = get_azx_dev(s);
1956                 sbits |= 1 << azx_dev->index;
1957                 nsync++;
1958                 snd_pcm_trigger_done(s, substream);
1959         }
1960
1961         spin_lock(&chip->reg_lock);
1962         if (nsync > 1) {
1963                 /* first, set SYNC bits of corresponding streams */
1964                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1965                         azx_writel(chip, OLD_SSYNC,
1966                                    azx_readl(chip, OLD_SSYNC) | sbits);
1967                 else
1968                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1969         }
1970         snd_pcm_group_for_each_entry(s, substream) {
1971                 if (s->pcm->card != substream->pcm->card)
1972                         continue;
1973                 azx_dev = get_azx_dev(s);
1974                 if (start) {
1975                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1976                         if (!rstart)
1977                                 azx_dev->start_wallclk -=
1978                                                 azx_dev->period_wallclk;
1979                         azx_stream_start(chip, azx_dev);
1980                 } else {
1981                         azx_stream_stop(chip, azx_dev);
1982                 }
1983                 azx_dev->running = start;
1984         }
1985         spin_unlock(&chip->reg_lock);
1986         if (start) {
1987                 if (nsync == 1)
1988                         return 0;
1989                 /* wait until all FIFOs get ready */
1990                 for (timeout = 5000; timeout; timeout--) {
1991                         nwait = 0;
1992                         snd_pcm_group_for_each_entry(s, substream) {
1993                                 if (s->pcm->card != substream->pcm->card)
1994                                         continue;
1995                                 azx_dev = get_azx_dev(s);
1996                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1997                                       SD_STS_FIFO_READY))
1998                                         nwait++;
1999                         }
2000                         if (!nwait)
2001                                 break;
2002                         cpu_relax();
2003                 }
2004         } else {
2005                 /* wait until all RUN bits are cleared */
2006                 for (timeout = 5000; timeout; timeout--) {
2007                         nwait = 0;
2008                         snd_pcm_group_for_each_entry(s, substream) {
2009                                 if (s->pcm->card != substream->pcm->card)
2010                                         continue;
2011                                 azx_dev = get_azx_dev(s);
2012                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2013                                     SD_CTL_DMA_START)
2014                                         nwait++;
2015                         }
2016                         if (!nwait)
2017                                 break;
2018                         cpu_relax();
2019                 }
2020         }
2021         if (nsync > 1) {
2022                 spin_lock(&chip->reg_lock);
2023                 /* reset SYNC bits */
2024                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2025                         azx_writel(chip, OLD_SSYNC,
2026                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
2027                 else
2028                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2029                 spin_unlock(&chip->reg_lock);
2030         }
2031         return 0;
2032 }
2033
2034 /* get the current DMA position with correction on VIA chips */
2035 static unsigned int azx_via_get_position(struct azx *chip,
2036                                          struct azx_dev *azx_dev)
2037 {
2038         unsigned int link_pos, mini_pos, bound_pos;
2039         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2040         unsigned int fifo_size;
2041
2042         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2043         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2044                 /* Playback, no problem using link position */
2045                 return link_pos;
2046         }
2047
2048         /* Capture */
2049         /* For new chipset,
2050          * use mod to get the DMA position just like old chipset
2051          */
2052         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2053         mod_dma_pos %= azx_dev->period_bytes;
2054
2055         /* azx_dev->fifo_size can't get FIFO size of in stream.
2056          * Get from base address + offset.
2057          */
2058         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2059
2060         if (azx_dev->insufficient) {
2061                 /* Link position never gather than FIFO size */
2062                 if (link_pos <= fifo_size)
2063                         return 0;
2064
2065                 azx_dev->insufficient = 0;
2066         }
2067
2068         if (link_pos <= fifo_size)
2069                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2070         else
2071                 mini_pos = link_pos - fifo_size;
2072
2073         /* Find nearest previous boudary */
2074         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2075         mod_link_pos = link_pos % azx_dev->period_bytes;
2076         if (mod_link_pos >= fifo_size)
2077                 bound_pos = link_pos - mod_link_pos;
2078         else if (mod_dma_pos >= mod_mini_pos)
2079                 bound_pos = mini_pos - mod_mini_pos;
2080         else {
2081                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2082                 if (bound_pos >= azx_dev->bufsize)
2083                         bound_pos = 0;
2084         }
2085
2086         /* Calculate real DMA position we want */
2087         return bound_pos + mod_dma_pos;
2088 }
2089
2090 static unsigned int azx_get_position(struct azx *chip,
2091                                      struct azx_dev *azx_dev,
2092                                      bool with_check)
2093 {
2094         unsigned int pos;
2095         int stream = azx_dev->substream->stream;
2096
2097         switch (chip->position_fix[stream]) {
2098         case POS_FIX_LPIB:
2099                 /* read LPIB */
2100                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2101                 break;
2102         case POS_FIX_VIACOMBO:
2103                 pos = azx_via_get_position(chip, azx_dev);
2104                 break;
2105         default:
2106                 /* use the position buffer */
2107                 pos = le32_to_cpu(*azx_dev->posbuf);
2108                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2109                         if (!pos || pos == (u32)-1) {
2110                                 printk(KERN_WARNING
2111                                        "hda-intel: Invalid position buffer, "
2112                                        "using LPIB read method instead.\n");
2113                                 chip->position_fix[stream] = POS_FIX_LPIB;
2114                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2115                         } else
2116                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2117                 }
2118                 break;
2119         }
2120
2121         if (pos >= azx_dev->bufsize)
2122                 pos = 0;
2123         return pos;
2124 }
2125
2126 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2127 {
2128         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2129         struct azx *chip = apcm->chip;
2130         struct azx_dev *azx_dev = get_azx_dev(substream);
2131         return bytes_to_frames(substream->runtime,
2132                                azx_get_position(chip, azx_dev, false));
2133 }
2134
2135 /*
2136  * Check whether the current DMA position is acceptable for updating
2137  * periods.  Returns non-zero if it's OK.
2138  *
2139  * Many HD-audio controllers appear pretty inaccurate about
2140  * the update-IRQ timing.  The IRQ is issued before actually the
2141  * data is processed.  So, we need to process it afterwords in a
2142  * workqueue.
2143  */
2144 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2145 {
2146         u32 wallclk;
2147         unsigned int pos;
2148         int stream;
2149
2150         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2151         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2152                 return -1;      /* bogus (too early) interrupt */
2153
2154         stream = azx_dev->substream->stream;
2155         pos = azx_get_position(chip, azx_dev, true);
2156
2157         if (WARN_ONCE(!azx_dev->period_bytes,
2158                       "hda-intel: zero azx_dev->period_bytes"))
2159                 return -1; /* this shouldn't happen! */
2160         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2161             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2162                 /* NG - it's below the first next period boundary */
2163                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2164         azx_dev->start_wallclk += wallclk;
2165         return 1; /* OK, it's fine */
2166 }
2167
2168 /*
2169  * The work for pending PCM period updates.
2170  */
2171 static void azx_irq_pending_work(struct work_struct *work)
2172 {
2173         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2174         int i, pending, ok;
2175
2176         if (!chip->irq_pending_warned) {
2177                 printk(KERN_WARNING
2178                        "hda-intel: IRQ timing workaround is activated "
2179                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2180                        chip->card->number);
2181                 chip->irq_pending_warned = 1;
2182         }
2183
2184         for (;;) {
2185                 pending = 0;
2186                 spin_lock_irq(&chip->reg_lock);
2187                 for (i = 0; i < chip->num_streams; i++) {
2188                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2189                         if (!azx_dev->irq_pending ||
2190                             !azx_dev->substream ||
2191                             !azx_dev->running)
2192                                 continue;
2193                         ok = azx_position_ok(chip, azx_dev);
2194                         if (ok > 0) {
2195                                 azx_dev->irq_pending = 0;
2196                                 spin_unlock(&chip->reg_lock);
2197                                 snd_pcm_period_elapsed(azx_dev->substream);
2198                                 spin_lock(&chip->reg_lock);
2199                         } else if (ok < 0) {
2200                                 pending = 0;    /* too early */
2201                         } else
2202                                 pending++;
2203                 }
2204                 spin_unlock_irq(&chip->reg_lock);
2205                 if (!pending)
2206                         return;
2207                 msleep(1);
2208         }
2209 }
2210
2211 /* clear irq_pending flags and assure no on-going workq */
2212 static void azx_clear_irq_pending(struct azx *chip)
2213 {
2214         int i;
2215
2216         spin_lock_irq(&chip->reg_lock);
2217         for (i = 0; i < chip->num_streams; i++)
2218                 chip->azx_dev[i].irq_pending = 0;
2219         spin_unlock_irq(&chip->reg_lock);
2220 }
2221
2222 static struct snd_pcm_ops azx_pcm_ops = {
2223         .open = azx_pcm_open,
2224         .close = azx_pcm_close,
2225         .ioctl = snd_pcm_lib_ioctl,
2226         .hw_params = azx_pcm_hw_params,
2227         .hw_free = azx_pcm_hw_free,
2228         .prepare = azx_pcm_prepare,
2229         .trigger = azx_pcm_trigger,
2230         .pointer = azx_pcm_pointer,
2231         .page = snd_pcm_sgbuf_ops_page,
2232 };
2233
2234 static void azx_pcm_free(struct snd_pcm *pcm)
2235 {
2236         struct azx_pcm *apcm = pcm->private_data;
2237         if (apcm) {
2238                 apcm->chip->pcm[pcm->device] = NULL;
2239                 kfree(apcm);
2240         }
2241 }
2242
2243 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2244
2245 static int
2246 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2247                       struct hda_pcm *cpcm)
2248 {
2249         struct azx *chip = bus->private_data;
2250         struct snd_pcm *pcm;
2251         struct azx_pcm *apcm;
2252         int pcm_dev = cpcm->device;
2253         unsigned int size;
2254         int s, err;
2255
2256         if (pcm_dev >= HDA_MAX_PCMS) {
2257                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2258                            pcm_dev);
2259                 return -EINVAL;
2260         }
2261         if (chip->pcm[pcm_dev]) {
2262                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2263                 return -EBUSY;
2264         }
2265         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2266                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2267                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2268                           &pcm);
2269         if (err < 0)
2270                 return err;
2271         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2272         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2273         if (apcm == NULL)
2274                 return -ENOMEM;
2275         apcm->chip = chip;
2276         apcm->codec = codec;
2277         pcm->private_data = apcm;
2278         pcm->private_free = azx_pcm_free;
2279         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2280                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2281         chip->pcm[pcm_dev] = pcm;
2282         cpcm->pcm = pcm;
2283         for (s = 0; s < 2; s++) {
2284                 apcm->hinfo[s] = &cpcm->stream[s];
2285                 if (cpcm->stream[s].substreams)
2286                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2287         }
2288         /* buffer pre-allocation */
2289         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2290         if (size > MAX_PREALLOC_SIZE)
2291                 size = MAX_PREALLOC_SIZE;
2292         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2293                                               chip->dev,
2294                                               size, MAX_PREALLOC_SIZE);
2295         return 0;
2296 }
2297
2298 /*
2299  * mixer creation - all stuff is implemented in hda module
2300  */
2301 static int __devinit azx_mixer_create(struct azx *chip)
2302 {
2303         return snd_hda_build_controls(chip->bus);
2304 }
2305
2306
2307 /*
2308  * initialize SD streams
2309  */
2310 static int __devinit azx_init_stream(struct azx *chip)
2311 {
2312         int i;
2313
2314         /* initialize each stream (aka device)
2315          * assign the starting bdl address to each stream (device)
2316          * and initialize
2317          */
2318         for (i = 0; i < chip->num_streams; i++) {
2319                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2320                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2321                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2322                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2323                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2324                 azx_dev->sd_int_sta_mask = 1 << i;
2325                 /* stream tag: must be non-zero and unique */
2326                 azx_dev->index = i;
2327                 azx_dev->stream_tag = i + 1;
2328         }
2329
2330         return 0;
2331 }
2332
2333 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2334 {
2335         if (request_irq(chip->irq_id, azx_interrupt,
2336                         chip->msi ? 0 : IRQF_SHARED,
2337                         KBUILD_MODNAME, chip)) {
2338                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2339                        "disabling device\n", chip->irq_id);
2340                 if (do_disconnect)
2341                         snd_card_disconnect(chip->card);
2342                 return -1;
2343         }
2344         chip->irq = chip->irq_id;
2345         if (chip->pci)
2346                 pci_intx(chip->pci, !chip->msi);
2347
2348         return 0;
2349 }
2350
2351
2352 static void azx_stop_chip(struct azx *chip)
2353 {
2354         if (!chip->initialized)
2355                 return;
2356
2357         /* disable interrupts */
2358         azx_int_disable(chip);
2359         azx_int_clear(chip);
2360
2361         /* disable CORB/RIRB */
2362         azx_free_cmd_io(chip);
2363
2364         /* disable position buffer */
2365         azx_writel(chip, DPLBASE, 0);
2366         azx_writel(chip, DPUBASE, 0);
2367
2368         chip->initialized = 0;
2369 }
2370
2371 #ifdef CONFIG_SND_HDA_POWER_SAVE
2372 /* power-up/down the controller */
2373 static void azx_power_notify(struct hda_bus *bus)
2374 {
2375         struct azx *chip = bus->private_data;
2376         struct hda_codec *c;
2377         int power_on = 0;
2378
2379         list_for_each_entry(c, &bus->codec_list, list) {
2380                 if (c->power_on) {
2381                         power_on = 1;
2382                         break;
2383                 }
2384         }
2385         if (power_on) {
2386 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2387                 azx_platform_enable_clocks(chip);
2388 #endif
2389                 azx_init_chip(chip, 1);
2390         }
2391         else if (chip->running && power_save_controller &&
2392                  !bus->power_keep_link_on) {
2393                 azx_stop_chip(chip);
2394 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2395                 azx_platform_disable_clocks(chip);
2396 #endif
2397         }
2398 }
2399 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2400
2401 #ifdef CONFIG_PM
2402 /*
2403  * power management
2404  */
2405
2406 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2407 {
2408         struct hda_codec *codec;
2409
2410         list_for_each_entry(codec, &bus->codec_list, list) {
2411                 if (snd_hda_codec_needs_resume(codec))
2412                         return 1;
2413         }
2414         return 0;
2415 }
2416
2417 static int azx_suspend(struct azx *chip, pm_message_t state)
2418 {
2419         struct snd_card *card = chip->card;
2420         int i;
2421
2422 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2423         defined(CONFIG_SND_HDA_POWER_SAVE)
2424         if (chip->pdev)
2425                 azx_platform_enable_clocks(chip);
2426 #endif
2427
2428         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2429         azx_clear_irq_pending(chip);
2430         for (i = 0; i < HDA_MAX_PCMS; i++)
2431                 snd_pcm_suspend_all(chip->pcm[i]);
2432         if (chip->initialized)
2433                 snd_hda_suspend(chip->bus);
2434         azx_stop_chip(chip);
2435         if (chip->irq >= 0) {
2436                 free_irq(chip->irq, chip);
2437                 chip->irq = -1;
2438         }
2439
2440         if (chip->pci) {
2441                 if (chip->msi)
2442                         pci_disable_msi(chip->pci);
2443                 pci_disable_device(chip->pci);
2444                 pci_save_state(chip->pci);
2445                 pci_set_power_state(chip->pci,
2446                                     pci_choose_state(chip->pci, state));
2447         }
2448
2449 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2450         if (chip->pdev) {
2451                 /* Disable all clk references */
2452                 while (chip->platform_clk_enable)
2453                         azx_platform_disable_clocks(chip);
2454         }
2455 #endif
2456
2457         return 0;
2458 }
2459
2460 static int azx_resume(struct azx *chip)
2461 {
2462         struct snd_card *card = chip->card;
2463
2464 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2465         if (chip->pdev)
2466                 azx_platform_enable_clocks(chip);
2467 #endif
2468
2469         if (chip->pci) {
2470                 pci_set_power_state(chip->pci, PCI_D0);
2471                 pci_restore_state(chip->pci);
2472                 if (pci_enable_device(chip->pci) < 0) {
2473                         printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2474                                "disabling device\n");
2475                         snd_card_disconnect(card);
2476                         return -EIO;
2477                 }
2478                 pci_set_master(chip->pci);
2479                 if (chip->msi)
2480                         if (pci_enable_msi(chip->pci) < 0)
2481                                 chip->msi = 0;
2482         }
2483
2484         if (azx_acquire_irq(chip, 1) < 0)
2485                 return -EIO;
2486
2487         if (chip->pci)
2488                 azx_init_pci(chip);
2489
2490 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2491         if (chip->pdev)
2492                 azx_init_platform(chip);
2493 #endif
2494
2495         if (snd_hda_codecs_inuse(chip->bus))
2496                 azx_init_chip(chip, 1);
2497 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2498         defined(CONFIG_SND_HDA_POWER_SAVE)
2499         else if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
2500                 struct hda_bus *bus = chip->bus;
2501                 struct hda_codec *c;
2502
2503                 list_for_each_entry(c, &bus->codec_list, list) {
2504                         snd_hda_power_up(c);
2505                         snd_hda_power_down(c);
2506                 }
2507         }
2508 #endif
2509
2510         snd_hda_resume(chip->bus);
2511         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2512
2513 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2514         defined(CONFIG_SND_HDA_POWER_SAVE)
2515         if (chip->pdev)
2516                 azx_platform_disable_clocks(chip);
2517 #endif
2518
2519         return 0;
2520 }
2521
2522 static int azx_suspend_pci(struct pci_dev *pci, pm_message_t state)
2523 {
2524         struct snd_card *card = pci_get_drvdata(pci);
2525         struct azx *chip = card->private_data;
2526
2527         return azx_suspend(chip, state);
2528 }
2529
2530 static int azx_resume_pci(struct pci_dev *pci)
2531 {
2532         struct snd_card *card = pci_get_drvdata(pci);
2533         struct azx *chip = card->private_data;
2534
2535         return azx_resume(chip);
2536 }
2537
2538 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2539 static int azx_suspend_platform(struct platform_device *pdev,
2540                                 pm_message_t state)
2541 {
2542         struct snd_card *card = dev_get_drvdata(&pdev->dev);
2543         struct azx *chip = card->private_data;
2544
2545         return azx_suspend(chip, state);
2546 }
2547
2548 static int azx_resume_platform(struct platform_device *pdev)
2549 {
2550         struct snd_card *card = dev_get_drvdata(&pdev->dev);
2551         struct azx *chip = card->private_data;
2552
2553         return azx_resume(chip);
2554 }
2555 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
2556 #endif /* CONFIG_PM */
2557
2558
2559 /*
2560  * reboot notifier for hang-up problem at power-down
2561  */
2562 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2563 {
2564         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2565
2566 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2567         defined(CONFIG_SND_HDA_POWER_SAVE)
2568         if (chip->pdev)
2569                 azx_platform_enable_clocks(chip);
2570 #endif
2571
2572         snd_hda_bus_reboot_notify(chip->bus);
2573         azx_stop_chip(chip);
2574
2575 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
2576         defined(CONFIG_SND_HDA_POWER_SAVE)
2577         if (chip->pdev)
2578                 azx_platform_disable_clocks(chip);
2579 #endif
2580
2581         return NOTIFY_OK;
2582 }
2583
2584 static void azx_notifier_register(struct azx *chip)
2585 {
2586         chip->reboot_notifier.notifier_call = azx_halt;
2587         register_reboot_notifier(&chip->reboot_notifier);
2588 }
2589
2590 static void azx_notifier_unregister(struct azx *chip)
2591 {
2592         if (chip->reboot_notifier.notifier_call)
2593                 unregister_reboot_notifier(&chip->reboot_notifier);
2594 }
2595
2596 /*
2597  * destructor
2598  */
2599 static int azx_free(struct azx *chip)
2600 {
2601         int i;
2602
2603         azx_notifier_unregister(chip);
2604
2605         if (chip->initialized) {
2606                 azx_clear_irq_pending(chip);
2607                 for (i = 0; i < chip->num_streams; i++)
2608                         azx_stream_stop(chip, &chip->azx_dev[i]);
2609                 azx_stop_chip(chip);
2610         }
2611
2612 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2613         azx_platform_disable_clocks(chip);
2614         for (i = 0; i < chip->platform_clk_count; i++)
2615                 clk_put(chip->platform_clks[i]);
2616 #endif
2617
2618         if (chip->irq >= 0)
2619                 free_irq(chip->irq, (void*)chip);
2620         if (chip->pci && chip->msi)
2621                 pci_disable_msi(chip->pci);
2622         if (chip->remap_addr)
2623                 iounmap(chip->remap_addr);
2624
2625         if (chip->azx_dev) {
2626                 for (i = 0; i < chip->num_streams; i++)
2627                         if (chip->azx_dev[i].bdl.area)
2628                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2629         }
2630         if (chip->rb.area)
2631                 snd_dma_free_pages(&chip->rb);
2632         if (chip->posbuf.area)
2633                 snd_dma_free_pages(&chip->posbuf);
2634         if (chip->pci) {
2635                 pci_release_regions(chip->pci);
2636                 pci_disable_device(chip->pci);
2637         }
2638         kfree(chip->azx_dev);
2639         kfree(chip);
2640
2641         return 0;
2642 }
2643
2644 static int azx_dev_free(struct snd_device *device)
2645 {
2646         return azx_free(device->device_data);
2647 }
2648
2649 /*
2650  * white/black-listing for position_fix
2651  */
2652 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2653         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2654         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2655         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2656         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2657         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2658         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2659         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2660         SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB),
2661         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2662         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2663         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2664         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2665         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2666         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2667         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2668         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2669         {}
2670 };
2671
2672 static int __devinit check_position_fix(struct azx *chip, int fix)
2673 {
2674         const struct snd_pci_quirk *q;
2675
2676         switch (fix) {
2677         case POS_FIX_LPIB:
2678         case POS_FIX_POSBUF:
2679         case POS_FIX_VIACOMBO:
2680                 return fix;
2681         }
2682
2683         if (chip->pci) {
2684                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2685                 if (q) {
2686                         printk(KERN_INFO
2687                                "hda_intel: position_fix set to %d "
2688                                "for device %04x:%04x\n",
2689                                q->value, q->subvendor, q->subdevice);
2690                         return q->value;
2691                 }
2692         }
2693
2694         /* Check VIA/ATI HD Audio Controller exist */
2695         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2696                 snd_printd(SFX "Using VIACOMBO position fix\n");
2697                 return POS_FIX_VIACOMBO;
2698         }
2699         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2700                 snd_printd(SFX "Using LPIB position fix\n");
2701                 return POS_FIX_LPIB;
2702         }
2703         return POS_FIX_AUTO;
2704 }
2705
2706 /*
2707  * black-lists for probe_mask
2708  */
2709 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2710         /* Thinkpad often breaks the controller communication when accessing
2711          * to the non-working (or non-existing) modem codec slot.
2712          */
2713         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2714         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2715         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2716         /* broken BIOS */
2717         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2718         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2719         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2720         /* forced codec slots */
2721         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2722         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2723         {}
2724 };
2725
2726 #define AZX_FORCE_CODEC_MASK    0x100
2727
2728 static void __devinit check_probe_mask(struct azx *chip, int dev)
2729 {
2730         const struct snd_pci_quirk *q;
2731
2732         chip->codec_probe_mask = probe_mask[dev];
2733         if (chip->pci && (chip->codec_probe_mask == -1)) {
2734                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2735                 if (q) {
2736                         printk(KERN_INFO
2737                                "hda_intel: probe_mask set to 0x%x "
2738                                "for device %04x:%04x\n",
2739                                q->value, q->subvendor, q->subdevice);
2740                         chip->codec_probe_mask = q->value;
2741                 }
2742         }
2743
2744         /* check forced option */
2745         if (chip->codec_probe_mask != -1 &&
2746             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2747                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2748                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2749                        chip->codec_mask);
2750         }
2751 }
2752
2753 /*
2754  * white/black-list for enable_msi
2755  */
2756 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2757         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2758         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2759         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2760         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2761         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2762         {}
2763 };
2764
2765 static void __devinit check_msi(struct azx *chip)
2766 {
2767         const struct snd_pci_quirk *q;
2768
2769         /* Disable MSI if chip is not a pci device */
2770         if (!chip->pci) {
2771                 chip->msi = 0;
2772                 return;
2773         }
2774
2775         if (enable_msi >= 0) {
2776                 chip->msi = !!enable_msi;
2777                 return;
2778         }
2779         chip->msi = 1;  /* enable MSI as default */
2780         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2781         if (q) {
2782                 printk(KERN_INFO
2783                        "hda_intel: msi for device %04x:%04x set to %d\n",
2784                        q->subvendor, q->subdevice, q->value);
2785                 chip->msi = q->value;
2786                 return;
2787         }
2788
2789         /* NVidia chipsets seem to cause troubles with MSI */
2790         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2791                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2792                 chip->msi = 0;
2793         }
2794 }
2795
2796 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
2797 static const char *tegra_clk_names[] __devinitdata = {
2798         "hda",
2799         "hda2codec",
2800         "hda2hdmi",
2801 };
2802 static struct clk *tegra_clks[ARRAY_SIZE(tegra_clk_names)];
2803 #endif
2804
2805 /*
2806  * constructor
2807  */
2808 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2809                                 struct platform_device *pdev,
2810                                 int dev, unsigned int driver_caps,
2811                                 struct azx **rchip)
2812 {
2813         struct azx *chip;
2814         int i, err = 0;
2815         unsigned short gcap;
2816         static struct snd_device_ops ops = {
2817                 .dev_free = azx_dev_free,
2818         };
2819
2820         *rchip = NULL;
2821
2822         if (pci) {
2823                 err = pci_enable_device(pci);
2824                 if (err < 0)
2825                         return err;
2826         }
2827
2828         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2829         if (!chip) {
2830                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2831                 if (pci)
2832                         pci_disable_device(pci);
2833                 return -ENOMEM;
2834         }
2835
2836         spin_lock_init(&chip->reg_lock);
2837         mutex_init(&chip->open_mutex);
2838         chip->card = card;
2839         chip->pci = pci;
2840         chip->pdev = pdev;
2841         chip->dev = pci ? snd_dma_pci_data(pci) : &pdev->dev;
2842         chip->irq_id = pci ? pci->irq : platform_get_irq(pdev, 0);
2843         chip->irq = -1;
2844         chip->driver_caps = driver_caps;
2845         chip->driver_type = driver_caps & 0xff;
2846         check_msi(chip);
2847         chip->dev_index = dev;
2848         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2849
2850         chip->position_fix[0] = chip->position_fix[1] =
2851                 check_position_fix(chip, position_fix[dev]);
2852         check_probe_mask(chip, dev);
2853
2854         chip->single_cmd = single_cmd;
2855
2856         if (bdl_pos_adj[dev] < 0) {
2857                 switch (chip->driver_type) {
2858                 case AZX_DRIVER_ICH:
2859                 case AZX_DRIVER_PCH:
2860                         bdl_pos_adj[dev] = 1;
2861                         break;
2862                 default:
2863                         bdl_pos_adj[dev] = 32;
2864                         break;
2865                 }
2866         }
2867
2868 #if BITS_PER_LONG != 64
2869         /* Fix up base address on ULI M5461 */
2870         if (chip->driver_type == AZX_DRIVER_ULI) {
2871                 u16 tmp3;
2872                 pci_read_config_word(pci, 0x40, &tmp3);
2873                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2874                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2875         }
2876 #endif
2877
2878         if (chip->pci) {
2879                 err = pci_request_regions(pci, "ICH HD audio");
2880                 if (err < 0) {
2881                         kfree(chip);
2882                         pci_disable_device(pci);
2883                         return err;
2884                 }
2885
2886                 chip->addr = pci_resource_start(pci, 0);
2887                 chip->remap_addr = pci_ioremap_bar(pci, 0);
2888                 if (chip->remap_addr == NULL) {
2889                         snd_printk(KERN_ERR SFX "ioremap error\n");
2890                         err = -ENXIO;
2891                         goto errout;
2892                 }
2893
2894                 if (chip->msi)
2895                         if (pci_enable_msi(pci) < 0)
2896                                 chip->msi = 0;
2897         }
2898
2899 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
2900         if (chip->pdev) {
2901                 struct resource *res, *region;
2902
2903                 /* Do platform specific initialization */
2904                 switch (chip->driver_type) {
2905 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
2906                 case AZX_DRIVER_NVIDIA_TEGRA:
2907                         chip->platform_clk_count = ARRAY_SIZE(tegra_clk_names);
2908                         for (i = 0; i < chip->platform_clk_count; i++) {
2909                                 tegra_clks[i] = clk_get(&pdev->dev,
2910                                                         tegra_clk_names[i]);
2911                                 if (IS_ERR_OR_NULL(tegra_clks[i])) {
2912                                         err = PTR_ERR(tegra_clks[i]);
2913                                         goto errout;
2914                                 }
2915                         }
2916                         chip->platform_clks = tegra_clks;
2917                         break;
2918 #endif
2919                 default:
2920                         break;
2921                 }
2922
2923                 azx_platform_enable_clocks(chip);
2924
2925                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2926                 if (res == NULL) {
2927                         err = EINVAL;
2928                         goto errout;
2929                 }
2930
2931                 region = devm_request_mem_region(chip->dev, res->start,
2932                                                  resource_size(res),
2933                                                  pdev->name);
2934                 if (!region) {
2935                         snd_printk(KERN_ERR SFX "Mem region already claimed\n");
2936                         err = -EINVAL;
2937                         goto errout;
2938                 }
2939
2940                 chip->addr = res->start;
2941                 chip->remap_addr = devm_ioremap(chip->dev,
2942                                                 res->start,
2943                                                 resource_size(res));
2944                 if (chip->remap_addr == NULL) {
2945                         snd_printk(KERN_ERR SFX "ioremap error\n");
2946                         err = -ENXIO;
2947                         goto errout;
2948                 }
2949
2950 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
2951                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
2952                         chip->remap_config_addr = chip->remap_addr;
2953                         chip->remap_addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
2954                         chip->addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
2955                 }
2956 #endif
2957
2958                 azx_init_platform(chip);
2959         }
2960 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
2961
2962         if (azx_acquire_irq(chip, 0) < 0) {
2963                 err = -EBUSY;
2964                 goto errout;
2965         }
2966
2967         if (chip->pci)
2968                 pci_set_master(pci);
2969
2970         synchronize_irq(chip->irq);
2971
2972         gcap = azx_readw(chip, GCAP);
2973         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2974
2975         /* disable SB600 64bit support for safety */
2976         if (chip->pci && chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2977                 struct pci_dev *p_smbus;
2978                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2979                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2980                                          NULL);
2981                 if (p_smbus) {
2982                         if (p_smbus->revision < 0x30)
2983                                 gcap &= ~ICH6_GCAP_64OK;
2984                         pci_dev_put(p_smbus);
2985                 }
2986         }
2987
2988         /* disable 64bit DMA address on some devices */
2989         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2990                 snd_printd(SFX "Disabling 64bit DMA\n");
2991                 gcap &= ~ICH6_GCAP_64OK;
2992         }
2993
2994         if (chip->pci) {
2995                 /* allow 64bit DMA address if supported by H/W */
2996                 if ((gcap & ICH6_GCAP_64OK) &&
2997                     !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2998                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2999                 else {
3000                         pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3001                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3002                 }
3003         }
3004
3005         /* read number of streams from GCAP register instead of using
3006          * hardcoded value
3007          */
3008         chip->capture_streams = (gcap >> 8) & 0x0f;
3009         chip->playback_streams = (gcap >> 12) & 0x0f;
3010         if (!chip->playback_streams && !chip->capture_streams) {
3011                 /* gcap didn't give any info, switching to old method */
3012
3013                 switch (chip->driver_type) {
3014                 case AZX_DRIVER_ULI:
3015                         chip->playback_streams = ULI_NUM_PLAYBACK;
3016                         chip->capture_streams = ULI_NUM_CAPTURE;
3017                         break;
3018                 case AZX_DRIVER_ATIHDMI:
3019                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3020                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3021                         break;
3022                 case AZX_DRIVER_GENERIC:
3023                 default:
3024                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3025                         chip->capture_streams = ICH6_NUM_CAPTURE;
3026                         break;
3027                 }
3028         }
3029         chip->capture_index_offset = 0;
3030         chip->playback_index_offset = chip->capture_streams;
3031         chip->num_streams = chip->playback_streams + chip->capture_streams;
3032         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3033                                 GFP_KERNEL);
3034         if (!chip->azx_dev) {
3035                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3036                 goto errout;
3037         }
3038
3039         for (i = 0; i < chip->num_streams; i++) {
3040                 /* allocate memory for the BDL for each stream */
3041                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3042                                           chip->dev,
3043                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3044                 if (err < 0) {
3045                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3046                         goto errout;
3047                 }
3048         }
3049         /* allocate memory for the position buffer */
3050         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3051                                   chip->dev,
3052                                   chip->num_streams * 8, &chip->posbuf);
3053         if (err < 0) {
3054                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3055                 goto errout;
3056         }
3057         /* allocate CORB/RIRB */
3058         err = azx_alloc_cmd_io(chip);
3059         if (err < 0)
3060                 goto errout;
3061
3062         /* initialize streams */
3063         azx_init_stream(chip);
3064
3065         /* initialize chip */
3066         if (chip->pci)
3067                 azx_init_pci(chip);
3068         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3069
3070         /* codec detection */
3071         if (!chip->codec_mask) {
3072                 snd_printk(KERN_ERR SFX "no codecs found!\n");
3073                 err = -ENODEV;
3074                 goto errout;
3075         }
3076
3077         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3078         if (err <0) {
3079                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3080                 goto errout;
3081         }
3082
3083         strcpy(card->driver, "HDA-Intel");
3084         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3085                 sizeof(card->shortname));
3086         snprintf(card->longname, sizeof(card->longname),
3087                  "%s at 0x%lx irq %i",
3088                  card->shortname, chip->addr, chip->irq);
3089
3090         *rchip = chip;
3091         return 0;
3092
3093  errout:
3094         azx_free(chip);
3095         return err;
3096 }
3097
3098 static void power_down_all_codecs(struct azx *chip)
3099 {
3100 #ifdef CONFIG_SND_HDA_POWER_SAVE
3101         /* The codecs were powered up in snd_hda_codec_new().
3102          * Now all initialization done, so turn them down if possible
3103          */
3104         struct hda_codec *codec;
3105         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3106                 snd_hda_power_down(codec);
3107         }
3108 #endif
3109 }
3110
3111 static int __devinit azx_probe(struct pci_dev *pci,
3112                                struct platform_device *pdev,
3113                                int driver_data)
3114 {
3115         static int dev;
3116         struct snd_card *card;
3117         struct azx *chip;
3118         struct device *azx_dev = pci ? &pci->dev : &pdev->dev;
3119         int err;
3120
3121         if (dev >= SNDRV_CARDS)
3122                 return -ENODEV;
3123         if (!enable[dev]) {
3124                 dev++;
3125                 return -ENOENT;
3126         }
3127
3128         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3129         if (err < 0) {
3130                 snd_printk(KERN_ERR SFX "Error creating card!\n");
3131                 return err;
3132         }
3133
3134         /* set this here since it's referred in snd_hda_load_patch() */
3135         snd_card_set_dev(card, azx_dev);
3136
3137         err = azx_create(card, pci, pdev, dev, driver_data, &chip);
3138         if (err < 0)
3139                 goto out_free;
3140         card->private_data = chip;
3141
3142 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3143         chip->beep_mode = beep_mode[dev];
3144 #endif
3145
3146         /* create codec instances */
3147         err = azx_codec_create(chip, model[dev]);
3148         if (err < 0)
3149                 goto out_free;
3150 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3151         if (patch[dev] && *patch[dev]) {
3152                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3153                            patch[dev]);
3154                 err = snd_hda_load_patch(chip->bus, patch[dev]);
3155                 if (err < 0)
3156                         goto out_free;
3157         }
3158 #endif
3159         if ((probe_only[dev] & 1) == 0) {
3160                 err = azx_codec_configure(chip);
3161                 if (err < 0)
3162                         goto out_free;
3163         }
3164
3165         /* create PCM streams */
3166         err = snd_hda_build_pcms(chip->bus);
3167         if (err < 0)
3168                 goto out_free;
3169
3170         /* create mixer controls */
3171         err = azx_mixer_create(chip);
3172         if (err < 0)
3173                 goto out_free;
3174
3175         err = snd_card_register(card);
3176         if (err < 0)
3177                 goto out_free;
3178
3179         if (pci)
3180                 pci_set_drvdata(pci, card);
3181         else
3182                 dev_set_drvdata(&pdev->dev, card);
3183
3184         chip->running = 1;
3185         power_down_all_codecs(chip);
3186         azx_notifier_register(chip);
3187
3188         dev++;
3189         return err;
3190 out_free:
3191         snd_card_free(card);
3192         return err;
3193 }
3194
3195 static int __devinit azx_probe_pci(struct pci_dev *pci,
3196                                    const struct pci_device_id *pci_id)
3197 {
3198         return azx_probe(pci, NULL, pci_id->driver_data);
3199 }
3200
3201 static void __devexit azx_remove_pci(struct pci_dev *pci)
3202 {
3203         snd_card_free(pci_get_drvdata(pci));
3204         pci_set_drvdata(pci, NULL);
3205 }
3206
3207 /* PCI IDs */
3208 static DEFINE_PCI_DEVICE_TABLE(azx_pci_ids) = {
3209         /* CPT */
3210         { PCI_DEVICE(0x8086, 0x1c20),
3211           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
3212         /* PBG */
3213         { PCI_DEVICE(0x8086, 0x1d20),
3214           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
3215         /* Panther Point */
3216         { PCI_DEVICE(0x8086, 0x1e20),
3217           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP },
3218         /* SCH */
3219         { PCI_DEVICE(0x8086, 0x811b),
3220           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
3221         { PCI_DEVICE(0x8086, 0x2668),
3222           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH6 */
3223         { PCI_DEVICE(0x8086, 0x27d8),
3224           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH7 */
3225         { PCI_DEVICE(0x8086, 0x269a),
3226           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ESB2 */
3227         { PCI_DEVICE(0x8086, 0x284b),
3228           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH8 */
3229         { PCI_DEVICE(0x8086, 0x293e),
3230           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH9 */
3231         { PCI_DEVICE(0x8086, 0x293f),
3232           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH9 */
3233         { PCI_DEVICE(0x8086, 0x3a3e),
3234           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH10 */
3235         { PCI_DEVICE(0x8086, 0x3a6e),
3236           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC },  /* ICH10 */
3237         /* Generic Intel */
3238         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3239           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3240           .class_mask = 0xffffff,
3241           .driver_data = AZX_DRIVER_ICH },
3242         /* ATI SB 450/600/700/800/900 */
3243         { PCI_DEVICE(0x1002, 0x437b),
3244           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3245         { PCI_DEVICE(0x1002, 0x4383),
3246           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3247         /* AMD Hudson */
3248         { PCI_DEVICE(0x1022, 0x780d),
3249           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3250         /* ATI HDMI */
3251         { PCI_DEVICE(0x1002, 0x793b),
3252           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3253         { PCI_DEVICE(0x1002, 0x7919),
3254           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3255         { PCI_DEVICE(0x1002, 0x960f),
3256           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3257         { PCI_DEVICE(0x1002, 0x970f),
3258           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3259         { PCI_DEVICE(0x1002, 0xaa00),
3260           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3261         { PCI_DEVICE(0x1002, 0xaa08),
3262           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3263         { PCI_DEVICE(0x1002, 0xaa10),
3264           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3265         { PCI_DEVICE(0x1002, 0xaa18),
3266           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3267         { PCI_DEVICE(0x1002, 0xaa20),
3268           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3269         { PCI_DEVICE(0x1002, 0xaa28),
3270           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3271         { PCI_DEVICE(0x1002, 0xaa30),
3272           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3273         { PCI_DEVICE(0x1002, 0xaa38),
3274           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3275         { PCI_DEVICE(0x1002, 0xaa40),
3276           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3277         { PCI_DEVICE(0x1002, 0xaa48),
3278           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3279         /* VIA VT8251/VT8237A */
3280         { PCI_DEVICE(0x1106, 0x3288),
3281           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3282         /* SIS966 */
3283         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3284         /* ULI M5461 */
3285         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3286         /* NVIDIA MCP */
3287         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3288           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3289           .class_mask = 0xffffff,
3290           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3291         /* Teradici */
3292         { PCI_DEVICE(0x6549, 0x1200),
3293           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3294         /* Creative X-Fi (CA0110-IBG) */
3295 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3296         /* the following entry conflicts with snd-ctxfi driver,
3297          * as ctxfi driver mutates from HD-audio to native mode with
3298          * a special command sequence.
3299          */
3300         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3301           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3302           .class_mask = 0xffffff,
3303           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3304           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3305 #else
3306         /* this entry seems still valid -- i.e. without emu20kx chip */
3307         { PCI_DEVICE(0x1102, 0x0009),
3308           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3309           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3310 #endif
3311         /* Vortex86MX */
3312         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3313         /* VMware HDAudio */
3314         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3315         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3316         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3317           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3318           .class_mask = 0xffffff,
3319           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3320         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3321           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3322           .class_mask = 0xffffff,
3323           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3324         { 0, }
3325 };
3326 MODULE_DEVICE_TABLE(pci, azx_pci_ids);
3327
3328 /* pci_driver definition */
3329 static struct pci_driver driver = {
3330         .name = KBUILD_MODNAME,
3331         .id_table = azx_pci_ids,
3332         .probe = azx_probe_pci,
3333         .remove = __devexit_p(azx_remove_pci),
3334 #ifdef CONFIG_PM
3335         .suspend = azx_suspend_pci,
3336         .resume = azx_resume_pci,
3337 #endif
3338 };
3339
3340 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3341 static int __devinit azx_probe_platform(struct platform_device *pdev)
3342 {
3343         const struct platform_device_id *pdev_id = platform_get_device_id(pdev);
3344
3345         return azx_probe(NULL, pdev, pdev_id->driver_data);
3346 }
3347
3348 static int __devexit azx_remove_platform(struct platform_device *pdev)
3349 {
3350         return snd_card_free(dev_get_drvdata(&pdev->dev));
3351 }
3352
3353 static const struct platform_device_id azx_platform_ids[] = {
3354 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3355         { "tegra30-hda",
3356           .driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_RIRB_DELAY },
3357 #endif
3358         { },
3359 };
3360 MODULE_DEVICE_TABLE(platform, azx_platform_ids);
3361
3362 /* platform_driver definition */
3363 static struct platform_driver hda_platform_driver = {
3364         .driver = {
3365                 .name = "hda-platform"
3366         },
3367         .probe = azx_probe_platform,
3368         .remove = __devexit_p(azx_remove_platform),
3369         .id_table = azx_platform_ids,
3370 #ifdef CONFIG_PM
3371         .suspend = azx_suspend_platform,
3372         .resume = azx_resume_platform,
3373 #endif
3374 };
3375 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3376
3377 static int __init alsa_card_azx_init(void)
3378 {
3379         int err = 0;
3380
3381         err = pci_register_driver(&driver);
3382         if (err < 0) {
3383                 snd_printk(KERN_ERR SFX "Failed to register pci driver\n");
3384                 return err;
3385         }
3386
3387 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3388         err = platform_driver_register(&hda_platform_driver);
3389         if (err < 0) {
3390                 snd_printk(KERN_ERR SFX "Failed to register platform driver\n");
3391                 pci_unregister_driver(&driver);
3392                 return err;
3393         }
3394 #endif
3395
3396         return 0;
3397 }
3398
3399 static void __exit alsa_card_azx_exit(void)
3400 {
3401 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3402         platform_driver_unregister(&hda_platform_driver);
3403 #endif
3404
3405         pci_unregister_driver(&driver);
3406 }
3407
3408 module_init(alsa_card_azx_init)
3409 module_exit(alsa_card_azx_exit)