ALSA: hda - Don't initialize CORB/RIRB for single_cmd mode
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67
68 module_param_array(index, int, NULL, 0444);
69 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
70 module_param_array(id, charp, NULL, 0444);
71 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
74 module_param_array(model, charp, NULL, 0444);
75 MODULE_PARM_DESC(model, "Use the given board model.");
76 module_param_array(position_fix, int, NULL, 0444);
77 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
78                  "(0 = auto, 1 = none, 2 = POSBUF).");
79 module_param_array(bdl_pos_adj, int, NULL, 0644);
80 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
81 module_param_array(probe_mask, int, NULL, 0444);
82 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
83 module_param_array(probe_only, bool, NULL, 0444);
84 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
85 module_param(single_cmd, bool, 0444);
86 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
87                  "(for debugging only).");
88 module_param(enable_msi, int, 0444);
89 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
90 #ifdef CONFIG_SND_HDA_PATCH_LOADER
91 module_param_array(patch, charp, NULL, 0444);
92 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
93 #endif
94
95 #ifdef CONFIG_SND_HDA_POWER_SAVE
96 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
97 module_param(power_save, int, 0644);
98 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
99                  "(in second, 0 = disable).");
100
101 /* reset the HD-audio controller in power save mode.
102  * this may give more power-saving, but will take longer time to
103  * wake up.
104  */
105 static int power_save_controller = 1;
106 module_param(power_save_controller, bool, 0644);
107 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
108 #endif
109
110 MODULE_LICENSE("GPL");
111 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
112                          "{Intel, ICH6M},"
113                          "{Intel, ICH7},"
114                          "{Intel, ESB2},"
115                          "{Intel, ICH8},"
116                          "{Intel, ICH9},"
117                          "{Intel, ICH10},"
118                          "{Intel, PCH},"
119                          "{Intel, SCH},"
120                          "{ATI, SB450},"
121                          "{ATI, SB600},"
122                          "{ATI, RS600},"
123                          "{ATI, RS690},"
124                          "{ATI, RS780},"
125                          "{ATI, R600},"
126                          "{ATI, RV630},"
127                          "{ATI, RV610},"
128                          "{ATI, RV670},"
129                          "{ATI, RV635},"
130                          "{ATI, RV620},"
131                          "{ATI, RV770},"
132                          "{VIA, VT8251},"
133                          "{VIA, VT8237A},"
134                          "{SiS, SIS966},"
135                          "{ULI, M5461}}");
136 MODULE_DESCRIPTION("Intel HDA driver");
137
138 #ifdef CONFIG_SND_VERBOSE_PRINTK
139 #define SFX     /* nop */
140 #else
141 #define SFX     "hda-intel: "
142 #endif
143
144 /*
145  * registers
146  */
147 #define ICH6_REG_GCAP                   0x00
148 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
149 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
150 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
151 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
152 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
153 #define ICH6_REG_VMIN                   0x02
154 #define ICH6_REG_VMAJ                   0x03
155 #define ICH6_REG_OUTPAY                 0x04
156 #define ICH6_REG_INPAY                  0x06
157 #define ICH6_REG_GCTL                   0x08
158 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
159 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
160 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
161 #define ICH6_REG_WAKEEN                 0x0c
162 #define ICH6_REG_STATESTS               0x0e
163 #define ICH6_REG_GSTS                   0x10
164 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
165 #define ICH6_REG_INTCTL                 0x20
166 #define ICH6_REG_INTSTS                 0x24
167 #define ICH6_REG_WALCLK                 0x30
168 #define ICH6_REG_SYNC                   0x34    
169 #define ICH6_REG_CORBLBASE              0x40
170 #define ICH6_REG_CORBUBASE              0x44
171 #define ICH6_REG_CORBWP                 0x48
172 #define ICH6_REG_CORBRP                 0x4a
173 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
174 #define ICH6_REG_CORBCTL                0x4c
175 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
176 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
177 #define ICH6_REG_CORBSTS                0x4d
178 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
179 #define ICH6_REG_CORBSIZE               0x4e
180
181 #define ICH6_REG_RIRBLBASE              0x50
182 #define ICH6_REG_RIRBUBASE              0x54
183 #define ICH6_REG_RIRBWP                 0x58
184 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
185 #define ICH6_REG_RINTCNT                0x5a
186 #define ICH6_REG_RIRBCTL                0x5c
187 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
188 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
189 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
190 #define ICH6_REG_RIRBSTS                0x5d
191 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
192 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
193 #define ICH6_REG_RIRBSIZE               0x5e
194
195 #define ICH6_REG_IC                     0x60
196 #define ICH6_REG_IR                     0x64
197 #define ICH6_REG_IRS                    0x68
198 #define   ICH6_IRS_VALID        (1<<1)
199 #define   ICH6_IRS_BUSY         (1<<0)
200
201 #define ICH6_REG_DPLBASE                0x70
202 #define ICH6_REG_DPUBASE                0x74
203 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
204
205 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
206 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
207
208 /* stream register offsets from stream base */
209 #define ICH6_REG_SD_CTL                 0x00
210 #define ICH6_REG_SD_STS                 0x03
211 #define ICH6_REG_SD_LPIB                0x04
212 #define ICH6_REG_SD_CBL                 0x08
213 #define ICH6_REG_SD_LVI                 0x0c
214 #define ICH6_REG_SD_FIFOW               0x0e
215 #define ICH6_REG_SD_FIFOSIZE            0x10
216 #define ICH6_REG_SD_FORMAT              0x12
217 #define ICH6_REG_SD_BDLPL               0x18
218 #define ICH6_REG_SD_BDLPU               0x1c
219
220 /* PCI space */
221 #define ICH6_PCIREG_TCSEL       0x44
222
223 /*
224  * other constants
225  */
226
227 /* max number of SDs */
228 /* ICH, ATI and VIA have 4 playback and 4 capture */
229 #define ICH6_NUM_CAPTURE        4
230 #define ICH6_NUM_PLAYBACK       4
231
232 /* ULI has 6 playback and 5 capture */
233 #define ULI_NUM_CAPTURE         5
234 #define ULI_NUM_PLAYBACK        6
235
236 /* ATI HDMI has 1 playback and 0 capture */
237 #define ATIHDMI_NUM_CAPTURE     0
238 #define ATIHDMI_NUM_PLAYBACK    1
239
240 /* TERA has 4 playback and 3 capture */
241 #define TERA_NUM_CAPTURE        3
242 #define TERA_NUM_PLAYBACK       4
243
244 /* this number is statically defined for simplicity */
245 #define MAX_AZX_DEV             16
246
247 /* max number of fragments - we may use more if allocating more pages for BDL */
248 #define BDL_SIZE                4096
249 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
250 #define AZX_MAX_FRAG            32
251 /* max buffer size - no h/w limit, you can increase as you like */
252 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
253 /* max number of PCM devics per card */
254 #define AZX_MAX_PCMS            8
255
256 /* RIRB int mask: overrun[2], response[0] */
257 #define RIRB_INT_RESPONSE       0x01
258 #define RIRB_INT_OVERRUN        0x04
259 #define RIRB_INT_MASK           0x05
260
261 /* STATESTS int mask: S3,SD2,SD1,SD0 */
262 #define AZX_MAX_CODECS          4
263 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
264
265 /* SD_CTL bits */
266 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
267 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
268 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
269 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
270 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
271 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
272 #define SD_CTL_STREAM_TAG_SHIFT 20
273
274 /* SD_CTL and SD_STS */
275 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
276 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
277 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
278 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
279                                  SD_INT_COMPLETE)
280
281 /* SD_STS */
282 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
283
284 /* INTCTL and INTSTS */
285 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
286 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
287 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
288
289 /* below are so far hardcoded - should read registers in future */
290 #define ICH6_MAX_CORB_ENTRIES   256
291 #define ICH6_MAX_RIRB_ENTRIES   256
292
293 /* position fix mode */
294 enum {
295         POS_FIX_AUTO,
296         POS_FIX_LPIB,
297         POS_FIX_POSBUF,
298 };
299
300 /* Defines for ATI HD Audio support in SB450 south bridge */
301 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
302 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
303
304 /* Defines for Nvidia HDA support */
305 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
306 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
307 #define NVIDIA_HDA_ISTRM_COH          0x4d
308 #define NVIDIA_HDA_OSTRM_COH          0x4c
309 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
310
311 /* Defines for Intel SCH HDA snoop control */
312 #define INTEL_SCH_HDA_DEVC      0x78
313 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
314
315 /* Define IN stream 0 FIFO size offset in VIA controller */
316 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
317 /* Define VIA HD Audio Device ID*/
318 #define VIA_HDAC_DEVICE_ID              0x3288
319
320 /* HD Audio class code */
321 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
322
323 /*
324  */
325
326 struct azx_dev {
327         struct snd_dma_buffer bdl; /* BDL buffer */
328         u32 *posbuf;            /* position buffer pointer */
329
330         unsigned int bufsize;   /* size of the play buffer in bytes */
331         unsigned int period_bytes; /* size of the period in bytes */
332         unsigned int frags;     /* number for period in the play buffer */
333         unsigned int fifo_size; /* FIFO size */
334         unsigned long start_jiffies;    /* start + minimum jiffies */
335         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
336
337         void __iomem *sd_addr;  /* stream descriptor pointer */
338
339         u32 sd_int_sta_mask;    /* stream int status mask */
340
341         /* pcm support */
342         struct snd_pcm_substream *substream;    /* assigned substream,
343                                                  * set in PCM open
344                                                  */
345         unsigned int format_val;        /* format value to be set in the
346                                          * controller and the codec
347                                          */
348         unsigned char stream_tag;       /* assigned stream */
349         unsigned char index;            /* stream index */
350
351         unsigned int opened :1;
352         unsigned int running :1;
353         unsigned int irq_pending :1;
354         unsigned int start_flag: 1;     /* stream full start flag */
355         /*
356          * For VIA:
357          *  A flag to ensure DMA position is 0
358          *  when link position is not greater than FIFO size
359          */
360         unsigned int insufficient :1;
361 };
362
363 /* CORB/RIRB */
364 struct azx_rb {
365         u32 *buf;               /* CORB/RIRB buffer
366                                  * Each CORB entry is 4byte, RIRB is 8byte
367                                  */
368         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
369         /* for RIRB */
370         unsigned short rp, wp;  /* read/write pointers */
371         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
372         u32 res[AZX_MAX_CODECS];        /* last read value */
373 };
374
375 struct azx {
376         struct snd_card *card;
377         struct pci_dev *pci;
378         int dev_index;
379
380         /* chip type specific */
381         int driver_type;
382         int playback_streams;
383         int playback_index_offset;
384         int capture_streams;
385         int capture_index_offset;
386         int num_streams;
387
388         /* pci resources */
389         unsigned long addr;
390         void __iomem *remap_addr;
391         int irq;
392
393         /* locks */
394         spinlock_t reg_lock;
395         struct mutex open_mutex;
396
397         /* streams (x num_streams) */
398         struct azx_dev *azx_dev;
399
400         /* PCM */
401         struct snd_pcm *pcm[AZX_MAX_PCMS];
402
403         /* HD codec */
404         unsigned short codec_mask;
405         int  codec_probe_mask; /* copied from probe_mask option */
406         struct hda_bus *bus;
407
408         /* CORB/RIRB */
409         struct azx_rb corb;
410         struct azx_rb rirb;
411
412         /* CORB/RIRB and position buffers */
413         struct snd_dma_buffer rb;
414         struct snd_dma_buffer posbuf;
415
416         /* flags */
417         int position_fix;
418         unsigned int running :1;
419         unsigned int initialized :1;
420         unsigned int single_cmd :1;
421         unsigned int polling_mode :1;
422         unsigned int msi :1;
423         unsigned int irq_pending_warned :1;
424         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
425         unsigned int probing :1; /* codec probing phase */
426
427         /* for debugging */
428         unsigned int last_cmd[AZX_MAX_CODECS];
429
430         /* for pending irqs */
431         struct work_struct irq_pending_work;
432
433         /* reboot notifier (for mysterious hangup problem at power-down) */
434         struct notifier_block reboot_notifier;
435 };
436
437 /* driver types */
438 enum {
439         AZX_DRIVER_ICH,
440         AZX_DRIVER_SCH,
441         AZX_DRIVER_ATI,
442         AZX_DRIVER_ATIHDMI,
443         AZX_DRIVER_VIA,
444         AZX_DRIVER_SIS,
445         AZX_DRIVER_ULI,
446         AZX_DRIVER_NVIDIA,
447         AZX_DRIVER_TERA,
448         AZX_DRIVER_GENERIC,
449         AZX_NUM_DRIVERS, /* keep this as last entry */
450 };
451
452 static char *driver_short_names[] __devinitdata = {
453         [AZX_DRIVER_ICH] = "HDA Intel",
454         [AZX_DRIVER_SCH] = "HDA Intel MID",
455         [AZX_DRIVER_ATI] = "HDA ATI SB",
456         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
457         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
458         [AZX_DRIVER_SIS] = "HDA SIS966",
459         [AZX_DRIVER_ULI] = "HDA ULI M5461",
460         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
461         [AZX_DRIVER_TERA] = "HDA Teradici", 
462         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
463 };
464
465 /*
466  * macros for easy use
467  */
468 #define azx_writel(chip,reg,value) \
469         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
470 #define azx_readl(chip,reg) \
471         readl((chip)->remap_addr + ICH6_REG_##reg)
472 #define azx_writew(chip,reg,value) \
473         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_readw(chip,reg) \
475         readw((chip)->remap_addr + ICH6_REG_##reg)
476 #define azx_writeb(chip,reg,value) \
477         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
478 #define azx_readb(chip,reg) \
479         readb((chip)->remap_addr + ICH6_REG_##reg)
480
481 #define azx_sd_writel(dev,reg,value) \
482         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
483 #define azx_sd_readl(dev,reg) \
484         readl((dev)->sd_addr + ICH6_REG_##reg)
485 #define azx_sd_writew(dev,reg,value) \
486         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
487 #define azx_sd_readw(dev,reg) \
488         readw((dev)->sd_addr + ICH6_REG_##reg)
489 #define azx_sd_writeb(dev,reg,value) \
490         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
491 #define azx_sd_readb(dev,reg) \
492         readb((dev)->sd_addr + ICH6_REG_##reg)
493
494 /* for pcm support */
495 #define get_azx_dev(substream) (substream->runtime->private_data)
496
497 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
498
499 /*
500  * Interface for HD codec
501  */
502
503 /*
504  * CORB / RIRB interface
505  */
506 static int azx_alloc_cmd_io(struct azx *chip)
507 {
508         int err;
509
510         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
511         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
512                                   snd_dma_pci_data(chip->pci),
513                                   PAGE_SIZE, &chip->rb);
514         if (err < 0) {
515                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
516                 return err;
517         }
518         return 0;
519 }
520
521 static void azx_init_cmd_io(struct azx *chip)
522 {
523         spin_lock_irq(&chip->reg_lock);
524         /* CORB set up */
525         chip->corb.addr = chip->rb.addr;
526         chip->corb.buf = (u32 *)chip->rb.area;
527         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
528         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
529
530         /* set the corb size to 256 entries (ULI requires explicitly) */
531         azx_writeb(chip, CORBSIZE, 0x02);
532         /* set the corb write pointer to 0 */
533         azx_writew(chip, CORBWP, 0);
534         /* reset the corb hw read pointer */
535         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
536         /* enable corb dma */
537         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
538
539         /* RIRB set up */
540         chip->rirb.addr = chip->rb.addr + 2048;
541         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
542         chip->rirb.wp = chip->rirb.rp = 0;
543         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
544         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
545         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
546
547         /* set the rirb size to 256 entries (ULI requires explicitly) */
548         azx_writeb(chip, RIRBSIZE, 0x02);
549         /* reset the rirb hw write pointer */
550         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
551         /* set N=1, get RIRB response interrupt for new entry */
552         azx_writew(chip, RINTCNT, 1);
553         /* enable rirb dma and response irq */
554         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
555         spin_unlock_irq(&chip->reg_lock);
556 }
557
558 static void azx_free_cmd_io(struct azx *chip)
559 {
560         spin_lock_irq(&chip->reg_lock);
561         /* disable ringbuffer DMAs */
562         azx_writeb(chip, RIRBCTL, 0);
563         azx_writeb(chip, CORBCTL, 0);
564         spin_unlock_irq(&chip->reg_lock);
565 }
566
567 static unsigned int azx_command_addr(u32 cmd)
568 {
569         unsigned int addr = cmd >> 28;
570
571         if (addr >= AZX_MAX_CODECS) {
572                 snd_BUG();
573                 addr = 0;
574         }
575
576         return addr;
577 }
578
579 static unsigned int azx_response_addr(u32 res)
580 {
581         unsigned int addr = res & 0xf;
582
583         if (addr >= AZX_MAX_CODECS) {
584                 snd_BUG();
585                 addr = 0;
586         }
587
588         return addr;
589 }
590
591 /* send a command */
592 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
593 {
594         struct azx *chip = bus->private_data;
595         unsigned int addr = azx_command_addr(val);
596         unsigned int wp;
597
598         spin_lock_irq(&chip->reg_lock);
599
600         /* add command to corb */
601         wp = azx_readb(chip, CORBWP);
602         wp++;
603         wp %= ICH6_MAX_CORB_ENTRIES;
604
605         chip->rirb.cmds[addr]++;
606         chip->corb.buf[wp] = cpu_to_le32(val);
607         azx_writel(chip, CORBWP, wp);
608
609         spin_unlock_irq(&chip->reg_lock);
610
611         return 0;
612 }
613
614 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
615
616 /* retrieve RIRB entry - called from interrupt handler */
617 static void azx_update_rirb(struct azx *chip)
618 {
619         unsigned int rp, wp;
620         unsigned int addr;
621         u32 res, res_ex;
622
623         wp = azx_readb(chip, RIRBWP);
624         if (wp == chip->rirb.wp)
625                 return;
626         chip->rirb.wp = wp;
627
628         while (chip->rirb.rp != wp) {
629                 chip->rirb.rp++;
630                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
631
632                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
633                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
634                 res = le32_to_cpu(chip->rirb.buf[rp]);
635                 addr = azx_response_addr(res_ex);
636                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
637                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
638                 else if (chip->rirb.cmds[addr]) {
639                         chip->rirb.res[addr] = res;
640                         smp_wmb();
641                         chip->rirb.cmds[addr]--;
642                 } else
643                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
644                                    "last cmd=%#08x\n",
645                                    res, res_ex,
646                                    chip->last_cmd[addr]);
647         }
648 }
649
650 /* receive a response */
651 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
652                                           unsigned int addr)
653 {
654         struct azx *chip = bus->private_data;
655         unsigned long timeout;
656
657  again:
658         timeout = jiffies + msecs_to_jiffies(1000);
659         for (;;) {
660                 if (chip->polling_mode) {
661                         spin_lock_irq(&chip->reg_lock);
662                         azx_update_rirb(chip);
663                         spin_unlock_irq(&chip->reg_lock);
664                 }
665                 if (!chip->rirb.cmds[addr]) {
666                         smp_rmb();
667                         bus->rirb_error = 0;
668                         return chip->rirb.res[addr]; /* the last value */
669                 }
670                 if (time_after(jiffies, timeout))
671                         break;
672                 if (bus->needs_damn_long_delay)
673                         msleep(2); /* temporary workaround */
674                 else {
675                         udelay(10);
676                         cond_resched();
677                 }
678         }
679
680         if (chip->msi) {
681                 snd_printk(KERN_WARNING SFX "No response from codec, "
682                            "disabling MSI: last cmd=0x%08x\n",
683                            chip->last_cmd[addr]);
684                 free_irq(chip->irq, chip);
685                 chip->irq = -1;
686                 pci_disable_msi(chip->pci);
687                 chip->msi = 0;
688                 if (azx_acquire_irq(chip, 1) < 0) {
689                         bus->rirb_error = 1;
690                         return -1;
691                 }
692                 goto again;
693         }
694
695         if (!chip->polling_mode) {
696                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
697                            "switching to polling mode: last cmd=0x%08x\n",
698                            chip->last_cmd[addr]);
699                 chip->polling_mode = 1;
700                 goto again;
701         }
702
703         if (chip->probing) {
704                 /* If this critical timeout happens during the codec probing
705                  * phase, this is likely an access to a non-existing codec
706                  * slot.  Better to return an error and reset the system.
707                  */
708                 return -1;
709         }
710
711         /* a fatal communication error; need either to reset or to fallback
712          * to the single_cmd mode
713          */
714         bus->rirb_error = 1;
715         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
716                 bus->response_reset = 1;
717                 return -1; /* give a chance to retry */
718         }
719
720         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
721                    "switching to single_cmd mode: last cmd=0x%08x\n",
722                    chip->last_cmd[addr]);
723         chip->single_cmd = 1;
724         bus->response_reset = 0;
725         /* release CORB/RIRB */
726         azx_free_cmd_io(chip);
727         /* disable unsolicited responses */
728         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
729         return -1;
730 }
731
732 /*
733  * Use the single immediate command instead of CORB/RIRB for simplicity
734  *
735  * Note: according to Intel, this is not preferred use.  The command was
736  *       intended for the BIOS only, and may get confused with unsolicited
737  *       responses.  So, we shouldn't use it for normal operation from the
738  *       driver.
739  *       I left the codes, however, for debugging/testing purposes.
740  */
741
742 /* receive a response */
743 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
744 {
745         int timeout = 50;
746
747         while (timeout--) {
748                 /* check IRV busy bit */
749                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
750                         /* reuse rirb.res as the response return value */
751                         chip->rirb.res[addr] = azx_readl(chip, IR);
752                         return 0;
753                 }
754                 udelay(1);
755         }
756         if (printk_ratelimit())
757                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
758                            azx_readw(chip, IRS));
759         chip->rirb.res[addr] = -1;
760         return -EIO;
761 }
762
763 /* send a command */
764 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
765 {
766         struct azx *chip = bus->private_data;
767         unsigned int addr = azx_command_addr(val);
768         int timeout = 50;
769
770         bus->rirb_error = 0;
771         while (timeout--) {
772                 /* check ICB busy bit */
773                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
774                         /* Clear IRV valid bit */
775                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
776                                    ICH6_IRS_VALID);
777                         azx_writel(chip, IC, val);
778                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
779                                    ICH6_IRS_BUSY);
780                         return azx_single_wait_for_response(chip, addr);
781                 }
782                 udelay(1);
783         }
784         if (printk_ratelimit())
785                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
786                            azx_readw(chip, IRS), val);
787         return -EIO;
788 }
789
790 /* receive a response */
791 static unsigned int azx_single_get_response(struct hda_bus *bus,
792                                             unsigned int addr)
793 {
794         struct azx *chip = bus->private_data;
795         return chip->rirb.res[addr];
796 }
797
798 /*
799  * The below are the main callbacks from hda_codec.
800  *
801  * They are just the skeleton to call sub-callbacks according to the
802  * current setting of chip->single_cmd.
803  */
804
805 /* send a command */
806 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
807 {
808         struct azx *chip = bus->private_data;
809
810         chip->last_cmd[azx_command_addr(val)] = val;
811         if (chip->single_cmd)
812                 return azx_single_send_cmd(bus, val);
813         else
814                 return azx_corb_send_cmd(bus, val);
815 }
816
817 /* get a response */
818 static unsigned int azx_get_response(struct hda_bus *bus,
819                                      unsigned int addr)
820 {
821         struct azx *chip = bus->private_data;
822         if (chip->single_cmd)
823                 return azx_single_get_response(bus, addr);
824         else
825                 return azx_rirb_get_response(bus, addr);
826 }
827
828 #ifdef CONFIG_SND_HDA_POWER_SAVE
829 static void azx_power_notify(struct hda_bus *bus);
830 #endif
831
832 /* reset codec link */
833 static int azx_reset(struct azx *chip)
834 {
835         int count;
836
837         /* clear STATESTS */
838         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
839
840         /* reset controller */
841         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
842
843         count = 50;
844         while (azx_readb(chip, GCTL) && --count)
845                 msleep(1);
846
847         /* delay for >= 100us for codec PLL to settle per spec
848          * Rev 0.9 section 5.5.1
849          */
850         msleep(1);
851
852         /* Bring controller out of reset */
853         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
854
855         count = 50;
856         while (!azx_readb(chip, GCTL) && --count)
857                 msleep(1);
858
859         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
860         msleep(1);
861
862         /* check to see if controller is ready */
863         if (!azx_readb(chip, GCTL)) {
864                 snd_printd(SFX "azx_reset: controller not ready!\n");
865                 return -EBUSY;
866         }
867
868         /* Accept unsolicited responses */
869         if (!chip->single_cmd)
870                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
871                            ICH6_GCTL_UNSOL);
872
873         /* detect codecs */
874         if (!chip->codec_mask) {
875                 chip->codec_mask = azx_readw(chip, STATESTS);
876                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
877         }
878
879         return 0;
880 }
881
882
883 /*
884  * Lowlevel interface
885  */  
886
887 /* enable interrupts */
888 static void azx_int_enable(struct azx *chip)
889 {
890         /* enable controller CIE and GIE */
891         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
892                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
893 }
894
895 /* disable interrupts */
896 static void azx_int_disable(struct azx *chip)
897 {
898         int i;
899
900         /* disable interrupts in stream descriptor */
901         for (i = 0; i < chip->num_streams; i++) {
902                 struct azx_dev *azx_dev = &chip->azx_dev[i];
903                 azx_sd_writeb(azx_dev, SD_CTL,
904                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
905         }
906
907         /* disable SIE for all streams */
908         azx_writeb(chip, INTCTL, 0);
909
910         /* disable controller CIE and GIE */
911         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
912                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
913 }
914
915 /* clear interrupts */
916 static void azx_int_clear(struct azx *chip)
917 {
918         int i;
919
920         /* clear stream status */
921         for (i = 0; i < chip->num_streams; i++) {
922                 struct azx_dev *azx_dev = &chip->azx_dev[i];
923                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
924         }
925
926         /* clear STATESTS */
927         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
928
929         /* clear rirb status */
930         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
931
932         /* clear int status */
933         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
934 }
935
936 /* start a stream */
937 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
938 {
939         /*
940          * Before stream start, initialize parameter
941          */
942         azx_dev->insufficient = 1;
943
944         /* enable SIE */
945         azx_writeb(chip, INTCTL,
946                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
947         /* set DMA start and interrupt mask */
948         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
949                       SD_CTL_DMA_START | SD_INT_MASK);
950 }
951
952 /* stop DMA */
953 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
954 {
955         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
956                       ~(SD_CTL_DMA_START | SD_INT_MASK));
957         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
958 }
959
960 /* stop a stream */
961 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
962 {
963         azx_stream_clear(chip, azx_dev);
964         /* disable SIE */
965         azx_writeb(chip, INTCTL,
966                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
967 }
968
969
970 /*
971  * reset and start the controller registers
972  */
973 static void azx_init_chip(struct azx *chip)
974 {
975         if (chip->initialized)
976                 return;
977
978         /* reset controller */
979         azx_reset(chip);
980
981         /* initialize interrupts */
982         azx_int_clear(chip);
983         azx_int_enable(chip);
984
985         /* initialize the codec command I/O */
986         if (!chip->single_cmd)
987                 azx_init_cmd_io(chip);
988
989         /* program the position buffer */
990         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
991         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
992
993         chip->initialized = 1;
994 }
995
996 /*
997  * initialize the PCI registers
998  */
999 /* update bits in a PCI register byte */
1000 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1001                             unsigned char mask, unsigned char val)
1002 {
1003         unsigned char data;
1004
1005         pci_read_config_byte(pci, reg, &data);
1006         data &= ~mask;
1007         data |= (val & mask);
1008         pci_write_config_byte(pci, reg, data);
1009 }
1010
1011 static void azx_init_pci(struct azx *chip)
1012 {
1013         unsigned short snoop;
1014
1015         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1016          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1017          * Ensuring these bits are 0 clears playback static on some HD Audio
1018          * codecs
1019          */
1020         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1021
1022         switch (chip->driver_type) {
1023         case AZX_DRIVER_ATI:
1024                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1025                 update_pci_byte(chip->pci,
1026                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1027                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1028                 break;
1029         case AZX_DRIVER_NVIDIA:
1030                 /* For NVIDIA HDA, enable snoop */
1031                 update_pci_byte(chip->pci,
1032                                 NVIDIA_HDA_TRANSREG_ADDR,
1033                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1034                 update_pci_byte(chip->pci,
1035                                 NVIDIA_HDA_ISTRM_COH,
1036                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1037                 update_pci_byte(chip->pci,
1038                                 NVIDIA_HDA_OSTRM_COH,
1039                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1040                 break;
1041         case AZX_DRIVER_SCH:
1042                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1043                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1044                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1045                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1046                         pci_read_config_word(chip->pci,
1047                                 INTEL_SCH_HDA_DEVC, &snoop);
1048                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1049                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1050                                 ? "Failed" : "OK");
1051                 }
1052                 break;
1053
1054         }
1055 }
1056
1057
1058 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1059
1060 /*
1061  * interrupt handler
1062  */
1063 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1064 {
1065         struct azx *chip = dev_id;
1066         struct azx_dev *azx_dev;
1067         u32 status;
1068         int i, ok;
1069
1070         spin_lock(&chip->reg_lock);
1071
1072         status = azx_readl(chip, INTSTS);
1073         if (status == 0) {
1074                 spin_unlock(&chip->reg_lock);
1075                 return IRQ_NONE;
1076         }
1077         
1078         for (i = 0; i < chip->num_streams; i++) {
1079                 azx_dev = &chip->azx_dev[i];
1080                 if (status & azx_dev->sd_int_sta_mask) {
1081                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1082                         if (!azx_dev->substream || !azx_dev->running)
1083                                 continue;
1084                         /* check whether this IRQ is really acceptable */
1085                         ok = azx_position_ok(chip, azx_dev);
1086                         if (ok == 1) {
1087                                 azx_dev->irq_pending = 0;
1088                                 spin_unlock(&chip->reg_lock);
1089                                 snd_pcm_period_elapsed(azx_dev->substream);
1090                                 spin_lock(&chip->reg_lock);
1091                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1092                                 /* bogus IRQ, process it later */
1093                                 azx_dev->irq_pending = 1;
1094                                 queue_work(chip->bus->workq,
1095                                            &chip->irq_pending_work);
1096                         }
1097                 }
1098         }
1099
1100         /* clear rirb int */
1101         status = azx_readb(chip, RIRBSTS);
1102         if (status & RIRB_INT_MASK) {
1103                 if (status & RIRB_INT_RESPONSE)
1104                         azx_update_rirb(chip);
1105                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1106         }
1107
1108 #if 0
1109         /* clear state status int */
1110         if (azx_readb(chip, STATESTS) & 0x04)
1111                 azx_writeb(chip, STATESTS, 0x04);
1112 #endif
1113         spin_unlock(&chip->reg_lock);
1114         
1115         return IRQ_HANDLED;
1116 }
1117
1118
1119 /*
1120  * set up a BDL entry
1121  */
1122 static int setup_bdle(struct snd_pcm_substream *substream,
1123                       struct azx_dev *azx_dev, u32 **bdlp,
1124                       int ofs, int size, int with_ioc)
1125 {
1126         u32 *bdl = *bdlp;
1127
1128         while (size > 0) {
1129                 dma_addr_t addr;
1130                 int chunk;
1131
1132                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1133                         return -EINVAL;
1134
1135                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1136                 /* program the address field of the BDL entry */
1137                 bdl[0] = cpu_to_le32((u32)addr);
1138                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1139                 /* program the size field of the BDL entry */
1140                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1141                 bdl[2] = cpu_to_le32(chunk);
1142                 /* program the IOC to enable interrupt
1143                  * only when the whole fragment is processed
1144                  */
1145                 size -= chunk;
1146                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1147                 bdl += 4;
1148                 azx_dev->frags++;
1149                 ofs += chunk;
1150         }
1151         *bdlp = bdl;
1152         return ofs;
1153 }
1154
1155 /*
1156  * set up BDL entries
1157  */
1158 static int azx_setup_periods(struct azx *chip,
1159                              struct snd_pcm_substream *substream,
1160                              struct azx_dev *azx_dev)
1161 {
1162         u32 *bdl;
1163         int i, ofs, periods, period_bytes;
1164         int pos_adj;
1165
1166         /* reset BDL address */
1167         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1168         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1169
1170         period_bytes = azx_dev->period_bytes;
1171         periods = azx_dev->bufsize / period_bytes;
1172
1173         /* program the initial BDL entries */
1174         bdl = (u32 *)azx_dev->bdl.area;
1175         ofs = 0;
1176         azx_dev->frags = 0;
1177         pos_adj = bdl_pos_adj[chip->dev_index];
1178         if (pos_adj > 0) {
1179                 struct snd_pcm_runtime *runtime = substream->runtime;
1180                 int pos_align = pos_adj;
1181                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1182                 if (!pos_adj)
1183                         pos_adj = pos_align;
1184                 else
1185                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1186                                 pos_align;
1187                 pos_adj = frames_to_bytes(runtime, pos_adj);
1188                 if (pos_adj >= period_bytes) {
1189                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1190                                    bdl_pos_adj[chip->dev_index]);
1191                         pos_adj = 0;
1192                 } else {
1193                         ofs = setup_bdle(substream, azx_dev,
1194                                          &bdl, ofs, pos_adj, 1);
1195                         if (ofs < 0)
1196                                 goto error;
1197                 }
1198         } else
1199                 pos_adj = 0;
1200         for (i = 0; i < periods; i++) {
1201                 if (i == periods - 1 && pos_adj)
1202                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1203                                          period_bytes - pos_adj, 0);
1204                 else
1205                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1206                                          period_bytes, 1);
1207                 if (ofs < 0)
1208                         goto error;
1209         }
1210         return 0;
1211
1212  error:
1213         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1214                    azx_dev->bufsize, period_bytes);
1215         return -EINVAL;
1216 }
1217
1218 /* reset stream */
1219 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1220 {
1221         unsigned char val;
1222         int timeout;
1223
1224         azx_stream_clear(chip, azx_dev);
1225
1226         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1227                       SD_CTL_STREAM_RESET);
1228         udelay(3);
1229         timeout = 300;
1230         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1231                --timeout)
1232                 ;
1233         val &= ~SD_CTL_STREAM_RESET;
1234         azx_sd_writeb(azx_dev, SD_CTL, val);
1235         udelay(3);
1236
1237         timeout = 300;
1238         /* waiting for hardware to report that the stream is out of reset */
1239         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1240                --timeout)
1241                 ;
1242
1243         /* reset first position - may not be synced with hw at this time */
1244         *azx_dev->posbuf = 0;
1245 }
1246
1247 /*
1248  * set up the SD for streaming
1249  */
1250 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1251 {
1252         /* make sure the run bit is zero for SD */
1253         azx_stream_clear(chip, azx_dev);
1254         /* program the stream_tag */
1255         azx_sd_writel(azx_dev, SD_CTL,
1256                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1257                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1258
1259         /* program the length of samples in cyclic buffer */
1260         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1261
1262         /* program the stream format */
1263         /* this value needs to be the same as the one programmed */
1264         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1265
1266         /* program the stream LVI (last valid index) of the BDL */
1267         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1268
1269         /* program the BDL address */
1270         /* lower BDL address */
1271         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1272         /* upper BDL address */
1273         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1274
1275         /* enable the position buffer */
1276         if (chip->position_fix == POS_FIX_POSBUF ||
1277             chip->position_fix == POS_FIX_AUTO ||
1278             chip->via_dmapos_patch) {
1279                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1280                         azx_writel(chip, DPLBASE,
1281                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1282         }
1283
1284         /* set the interrupt enable bits in the descriptor control register */
1285         azx_sd_writel(azx_dev, SD_CTL,
1286                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1287
1288         return 0;
1289 }
1290
1291 /*
1292  * Probe the given codec address
1293  */
1294 static int probe_codec(struct azx *chip, int addr)
1295 {
1296         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1297                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1298         unsigned int res;
1299
1300         mutex_lock(&chip->bus->cmd_mutex);
1301         chip->probing = 1;
1302         azx_send_cmd(chip->bus, cmd);
1303         res = azx_get_response(chip->bus, addr);
1304         chip->probing = 0;
1305         mutex_unlock(&chip->bus->cmd_mutex);
1306         if (res == -1)
1307                 return -EIO;
1308         snd_printdd(SFX "codec #%d probed OK\n", addr);
1309         return 0;
1310 }
1311
1312 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1313                                  struct hda_pcm *cpcm);
1314 static void azx_stop_chip(struct azx *chip);
1315
1316 static void azx_bus_reset(struct hda_bus *bus)
1317 {
1318         struct azx *chip = bus->private_data;
1319
1320         bus->in_reset = 1;
1321         azx_stop_chip(chip);
1322         azx_init_chip(chip);
1323 #ifdef CONFIG_PM
1324         if (chip->initialized) {
1325                 int i;
1326
1327                 for (i = 0; i < AZX_MAX_PCMS; i++)
1328                         snd_pcm_suspend_all(chip->pcm[i]);
1329                 snd_hda_suspend(chip->bus);
1330                 snd_hda_resume(chip->bus);
1331         }
1332 #endif
1333         bus->in_reset = 0;
1334 }
1335
1336 /*
1337  * Codec initialization
1338  */
1339
1340 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1341 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1342         [AZX_DRIVER_TERA] = 1,
1343 };
1344
1345 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1346 {
1347         struct hda_bus_template bus_temp;
1348         int c, codecs, err;
1349         int max_slots;
1350
1351         memset(&bus_temp, 0, sizeof(bus_temp));
1352         bus_temp.private_data = chip;
1353         bus_temp.modelname = model;
1354         bus_temp.pci = chip->pci;
1355         bus_temp.ops.command = azx_send_cmd;
1356         bus_temp.ops.get_response = azx_get_response;
1357         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1358         bus_temp.ops.bus_reset = azx_bus_reset;
1359 #ifdef CONFIG_SND_HDA_POWER_SAVE
1360         bus_temp.power_save = &power_save;
1361         bus_temp.ops.pm_notify = azx_power_notify;
1362 #endif
1363
1364         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1365         if (err < 0)
1366                 return err;
1367
1368         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1369                 chip->bus->needs_damn_long_delay = 1;
1370
1371         codecs = 0;
1372         max_slots = azx_max_codecs[chip->driver_type];
1373         if (!max_slots)
1374                 max_slots = AZX_MAX_CODECS;
1375
1376         /* First try to probe all given codec slots */
1377         for (c = 0; c < max_slots; c++) {
1378                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1379                         if (probe_codec(chip, c) < 0) {
1380                                 /* Some BIOSen give you wrong codec addresses
1381                                  * that don't exist
1382                                  */
1383                                 snd_printk(KERN_WARNING SFX
1384                                            "Codec #%d probe error; "
1385                                            "disabling it...\n", c);
1386                                 chip->codec_mask &= ~(1 << c);
1387                                 /* More badly, accessing to a non-existing
1388                                  * codec often screws up the controller chip,
1389                                  * and distrubs the further communications.
1390                                  * Thus if an error occurs during probing,
1391                                  * better to reset the controller chip to
1392                                  * get back to the sanity state.
1393                                  */
1394                                 azx_stop_chip(chip);
1395                                 azx_init_chip(chip);
1396                         }
1397                 }
1398         }
1399
1400         /* Then create codec instances */
1401         for (c = 0; c < max_slots; c++) {
1402                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1403                         struct hda_codec *codec;
1404                         err = snd_hda_codec_new(chip->bus, c, &codec);
1405                         if (err < 0)
1406                                 continue;
1407                         codecs++;
1408                 }
1409         }
1410         if (!codecs) {
1411                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1412                 return -ENXIO;
1413         }
1414         return 0;
1415 }
1416
1417 /* configure each codec instance */
1418 static int __devinit azx_codec_configure(struct azx *chip)
1419 {
1420         struct hda_codec *codec;
1421         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1422                 snd_hda_codec_configure(codec);
1423         }
1424         return 0;
1425 }
1426
1427
1428 /*
1429  * PCM support
1430  */
1431
1432 /* assign a stream for the PCM */
1433 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1434 {
1435         int dev, i, nums;
1436         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1437                 dev = chip->playback_index_offset;
1438                 nums = chip->playback_streams;
1439         } else {
1440                 dev = chip->capture_index_offset;
1441                 nums = chip->capture_streams;
1442         }
1443         for (i = 0; i < nums; i++, dev++)
1444                 if (!chip->azx_dev[dev].opened) {
1445                         chip->azx_dev[dev].opened = 1;
1446                         return &chip->azx_dev[dev];
1447                 }
1448         return NULL;
1449 }
1450
1451 /* release the assigned stream */
1452 static inline void azx_release_device(struct azx_dev *azx_dev)
1453 {
1454         azx_dev->opened = 0;
1455 }
1456
1457 static struct snd_pcm_hardware azx_pcm_hw = {
1458         .info =                 (SNDRV_PCM_INFO_MMAP |
1459                                  SNDRV_PCM_INFO_INTERLEAVED |
1460                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1461                                  SNDRV_PCM_INFO_MMAP_VALID |
1462                                  /* No full-resume yet implemented */
1463                                  /* SNDRV_PCM_INFO_RESUME |*/
1464                                  SNDRV_PCM_INFO_PAUSE |
1465                                  SNDRV_PCM_INFO_SYNC_START),
1466         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1467         .rates =                SNDRV_PCM_RATE_48000,
1468         .rate_min =             48000,
1469         .rate_max =             48000,
1470         .channels_min =         2,
1471         .channels_max =         2,
1472         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1473         .period_bytes_min =     128,
1474         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1475         .periods_min =          2,
1476         .periods_max =          AZX_MAX_FRAG,
1477         .fifo_size =            0,
1478 };
1479
1480 struct azx_pcm {
1481         struct azx *chip;
1482         struct hda_codec *codec;
1483         struct hda_pcm_stream *hinfo[2];
1484 };
1485
1486 static int azx_pcm_open(struct snd_pcm_substream *substream)
1487 {
1488         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1489         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1490         struct azx *chip = apcm->chip;
1491         struct azx_dev *azx_dev;
1492         struct snd_pcm_runtime *runtime = substream->runtime;
1493         unsigned long flags;
1494         int err;
1495
1496         mutex_lock(&chip->open_mutex);
1497         azx_dev = azx_assign_device(chip, substream->stream);
1498         if (azx_dev == NULL) {
1499                 mutex_unlock(&chip->open_mutex);
1500                 return -EBUSY;
1501         }
1502         runtime->hw = azx_pcm_hw;
1503         runtime->hw.channels_min = hinfo->channels_min;
1504         runtime->hw.channels_max = hinfo->channels_max;
1505         runtime->hw.formats = hinfo->formats;
1506         runtime->hw.rates = hinfo->rates;
1507         snd_pcm_limit_hw_rates(runtime);
1508         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1509         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1510                                    128);
1511         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1512                                    128);
1513         snd_hda_power_up(apcm->codec);
1514         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1515         if (err < 0) {
1516                 azx_release_device(azx_dev);
1517                 snd_hda_power_down(apcm->codec);
1518                 mutex_unlock(&chip->open_mutex);
1519                 return err;
1520         }
1521         snd_pcm_limit_hw_rates(runtime);
1522         /* sanity check */
1523         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1524             snd_BUG_ON(!runtime->hw.channels_max) ||
1525             snd_BUG_ON(!runtime->hw.formats) ||
1526             snd_BUG_ON(!runtime->hw.rates)) {
1527                 azx_release_device(azx_dev);
1528                 hinfo->ops.close(hinfo, apcm->codec, substream);
1529                 snd_hda_power_down(apcm->codec);
1530                 mutex_unlock(&chip->open_mutex);
1531                 return -EINVAL;
1532         }
1533         spin_lock_irqsave(&chip->reg_lock, flags);
1534         azx_dev->substream = substream;
1535         azx_dev->running = 0;
1536         spin_unlock_irqrestore(&chip->reg_lock, flags);
1537
1538         runtime->private_data = azx_dev;
1539         snd_pcm_set_sync(substream);
1540         mutex_unlock(&chip->open_mutex);
1541         return 0;
1542 }
1543
1544 static int azx_pcm_close(struct snd_pcm_substream *substream)
1545 {
1546         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1547         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1548         struct azx *chip = apcm->chip;
1549         struct azx_dev *azx_dev = get_azx_dev(substream);
1550         unsigned long flags;
1551
1552         mutex_lock(&chip->open_mutex);
1553         spin_lock_irqsave(&chip->reg_lock, flags);
1554         azx_dev->substream = NULL;
1555         azx_dev->running = 0;
1556         spin_unlock_irqrestore(&chip->reg_lock, flags);
1557         azx_release_device(azx_dev);
1558         hinfo->ops.close(hinfo, apcm->codec, substream);
1559         snd_hda_power_down(apcm->codec);
1560         mutex_unlock(&chip->open_mutex);
1561         return 0;
1562 }
1563
1564 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1565                              struct snd_pcm_hw_params *hw_params)
1566 {
1567         struct azx_dev *azx_dev = get_azx_dev(substream);
1568
1569         azx_dev->bufsize = 0;
1570         azx_dev->period_bytes = 0;
1571         azx_dev->format_val = 0;
1572         return snd_pcm_lib_malloc_pages(substream,
1573                                         params_buffer_bytes(hw_params));
1574 }
1575
1576 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1577 {
1578         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1579         struct azx_dev *azx_dev = get_azx_dev(substream);
1580         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1581
1582         /* reset BDL address */
1583         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1584         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1585         azx_sd_writel(azx_dev, SD_CTL, 0);
1586         azx_dev->bufsize = 0;
1587         azx_dev->period_bytes = 0;
1588         azx_dev->format_val = 0;
1589
1590         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1591
1592         return snd_pcm_lib_free_pages(substream);
1593 }
1594
1595 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1596 {
1597         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1598         struct azx *chip = apcm->chip;
1599         struct azx_dev *azx_dev = get_azx_dev(substream);
1600         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1601         struct snd_pcm_runtime *runtime = substream->runtime;
1602         unsigned int bufsize, period_bytes, format_val;
1603         int err;
1604
1605         azx_stream_reset(chip, azx_dev);
1606         format_val = snd_hda_calc_stream_format(runtime->rate,
1607                                                 runtime->channels,
1608                                                 runtime->format,
1609                                                 hinfo->maxbps);
1610         if (!format_val) {
1611                 snd_printk(KERN_ERR SFX
1612                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1613                            runtime->rate, runtime->channels, runtime->format);
1614                 return -EINVAL;
1615         }
1616
1617         bufsize = snd_pcm_lib_buffer_bytes(substream);
1618         period_bytes = snd_pcm_lib_period_bytes(substream);
1619
1620         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1621                     bufsize, format_val);
1622
1623         if (bufsize != azx_dev->bufsize ||
1624             period_bytes != azx_dev->period_bytes ||
1625             format_val != azx_dev->format_val) {
1626                 azx_dev->bufsize = bufsize;
1627                 azx_dev->period_bytes = period_bytes;
1628                 azx_dev->format_val = format_val;
1629                 err = azx_setup_periods(chip, substream, azx_dev);
1630                 if (err < 0)
1631                         return err;
1632         }
1633
1634         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1635                                                 (runtime->rate * 2);
1636         azx_setup_controller(chip, azx_dev);
1637         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1638                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1639         else
1640                 azx_dev->fifo_size = 0;
1641
1642         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1643                                   azx_dev->format_val, substream);
1644 }
1645
1646 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1647 {
1648         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1649         struct azx *chip = apcm->chip;
1650         struct azx_dev *azx_dev;
1651         struct snd_pcm_substream *s;
1652         int rstart = 0, start, nsync = 0, sbits = 0;
1653         int nwait, timeout;
1654
1655         switch (cmd) {
1656         case SNDRV_PCM_TRIGGER_START:
1657                 rstart = 1;
1658         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1659         case SNDRV_PCM_TRIGGER_RESUME:
1660                 start = 1;
1661                 break;
1662         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1663         case SNDRV_PCM_TRIGGER_SUSPEND:
1664         case SNDRV_PCM_TRIGGER_STOP:
1665                 start = 0;
1666                 break;
1667         default:
1668                 return -EINVAL;
1669         }
1670
1671         snd_pcm_group_for_each_entry(s, substream) {
1672                 if (s->pcm->card != substream->pcm->card)
1673                         continue;
1674                 azx_dev = get_azx_dev(s);
1675                 sbits |= 1 << azx_dev->index;
1676                 nsync++;
1677                 snd_pcm_trigger_done(s, substream);
1678         }
1679
1680         spin_lock(&chip->reg_lock);
1681         if (nsync > 1) {
1682                 /* first, set SYNC bits of corresponding streams */
1683                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1684         }
1685         snd_pcm_group_for_each_entry(s, substream) {
1686                 if (s->pcm->card != substream->pcm->card)
1687                         continue;
1688                 azx_dev = get_azx_dev(s);
1689                 if (rstart) {
1690                         azx_dev->start_flag = 1;
1691                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1692                 }
1693                 if (start)
1694                         azx_stream_start(chip, azx_dev);
1695                 else
1696                         azx_stream_stop(chip, azx_dev);
1697                 azx_dev->running = start;
1698         }
1699         spin_unlock(&chip->reg_lock);
1700         if (start) {
1701                 if (nsync == 1)
1702                         return 0;
1703                 /* wait until all FIFOs get ready */
1704                 for (timeout = 5000; timeout; timeout--) {
1705                         nwait = 0;
1706                         snd_pcm_group_for_each_entry(s, substream) {
1707                                 if (s->pcm->card != substream->pcm->card)
1708                                         continue;
1709                                 azx_dev = get_azx_dev(s);
1710                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1711                                       SD_STS_FIFO_READY))
1712                                         nwait++;
1713                         }
1714                         if (!nwait)
1715                                 break;
1716                         cpu_relax();
1717                 }
1718         } else {
1719                 /* wait until all RUN bits are cleared */
1720                 for (timeout = 5000; timeout; timeout--) {
1721                         nwait = 0;
1722                         snd_pcm_group_for_each_entry(s, substream) {
1723                                 if (s->pcm->card != substream->pcm->card)
1724                                         continue;
1725                                 azx_dev = get_azx_dev(s);
1726                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1727                                     SD_CTL_DMA_START)
1728                                         nwait++;
1729                         }
1730                         if (!nwait)
1731                                 break;
1732                         cpu_relax();
1733                 }
1734         }
1735         if (nsync > 1) {
1736                 spin_lock(&chip->reg_lock);
1737                 /* reset SYNC bits */
1738                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1739                 spin_unlock(&chip->reg_lock);
1740         }
1741         return 0;
1742 }
1743
1744 /* get the current DMA position with correction on VIA chips */
1745 static unsigned int azx_via_get_position(struct azx *chip,
1746                                          struct azx_dev *azx_dev)
1747 {
1748         unsigned int link_pos, mini_pos, bound_pos;
1749         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1750         unsigned int fifo_size;
1751
1752         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1753         if (azx_dev->index >= 4) {
1754                 /* Playback, no problem using link position */
1755                 return link_pos;
1756         }
1757
1758         /* Capture */
1759         /* For new chipset,
1760          * use mod to get the DMA position just like old chipset
1761          */
1762         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1763         mod_dma_pos %= azx_dev->period_bytes;
1764
1765         /* azx_dev->fifo_size can't get FIFO size of in stream.
1766          * Get from base address + offset.
1767          */
1768         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1769
1770         if (azx_dev->insufficient) {
1771                 /* Link position never gather than FIFO size */
1772                 if (link_pos <= fifo_size)
1773                         return 0;
1774
1775                 azx_dev->insufficient = 0;
1776         }
1777
1778         if (link_pos <= fifo_size)
1779                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1780         else
1781                 mini_pos = link_pos - fifo_size;
1782
1783         /* Find nearest previous boudary */
1784         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1785         mod_link_pos = link_pos % azx_dev->period_bytes;
1786         if (mod_link_pos >= fifo_size)
1787                 bound_pos = link_pos - mod_link_pos;
1788         else if (mod_dma_pos >= mod_mini_pos)
1789                 bound_pos = mini_pos - mod_mini_pos;
1790         else {
1791                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1792                 if (bound_pos >= azx_dev->bufsize)
1793                         bound_pos = 0;
1794         }
1795
1796         /* Calculate real DMA position we want */
1797         return bound_pos + mod_dma_pos;
1798 }
1799
1800 static unsigned int azx_get_position(struct azx *chip,
1801                                      struct azx_dev *azx_dev)
1802 {
1803         unsigned int pos;
1804
1805         if (chip->via_dmapos_patch)
1806                 pos = azx_via_get_position(chip, azx_dev);
1807         else if (chip->position_fix == POS_FIX_POSBUF ||
1808                  chip->position_fix == POS_FIX_AUTO) {
1809                 /* use the position buffer */
1810                 pos = le32_to_cpu(*azx_dev->posbuf);
1811         } else {
1812                 /* read LPIB */
1813                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1814         }
1815         if (pos >= azx_dev->bufsize)
1816                 pos = 0;
1817         return pos;
1818 }
1819
1820 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1821 {
1822         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1823         struct azx *chip = apcm->chip;
1824         struct azx_dev *azx_dev = get_azx_dev(substream);
1825         return bytes_to_frames(substream->runtime,
1826                                azx_get_position(chip, azx_dev));
1827 }
1828
1829 /*
1830  * Check whether the current DMA position is acceptable for updating
1831  * periods.  Returns non-zero if it's OK.
1832  *
1833  * Many HD-audio controllers appear pretty inaccurate about
1834  * the update-IRQ timing.  The IRQ is issued before actually the
1835  * data is processed.  So, we need to process it afterwords in a
1836  * workqueue.
1837  */
1838 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1839 {
1840         unsigned int pos;
1841
1842         if (azx_dev->start_flag &&
1843             time_before_eq(jiffies, azx_dev->start_jiffies))
1844                 return -1;      /* bogus (too early) interrupt */
1845         azx_dev->start_flag = 0;
1846
1847         pos = azx_get_position(chip, azx_dev);
1848         if (chip->position_fix == POS_FIX_AUTO) {
1849                 if (!pos) {
1850                         printk(KERN_WARNING
1851                                "hda-intel: Invalid position buffer, "
1852                                "using LPIB read method instead.\n");
1853                         chip->position_fix = POS_FIX_LPIB;
1854                         pos = azx_get_position(chip, azx_dev);
1855                 } else
1856                         chip->position_fix = POS_FIX_POSBUF;
1857         }
1858
1859         if (!bdl_pos_adj[chip->dev_index])
1860                 return 1; /* no delayed ack */
1861         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1862                 return 0; /* NG - it's below the period boundary */
1863         return 1; /* OK, it's fine */
1864 }
1865
1866 /*
1867  * The work for pending PCM period updates.
1868  */
1869 static void azx_irq_pending_work(struct work_struct *work)
1870 {
1871         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1872         int i, pending;
1873
1874         if (!chip->irq_pending_warned) {
1875                 printk(KERN_WARNING
1876                        "hda-intel: IRQ timing workaround is activated "
1877                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1878                        chip->card->number);
1879                 chip->irq_pending_warned = 1;
1880         }
1881
1882         for (;;) {
1883                 pending = 0;
1884                 spin_lock_irq(&chip->reg_lock);
1885                 for (i = 0; i < chip->num_streams; i++) {
1886                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1887                         if (!azx_dev->irq_pending ||
1888                             !azx_dev->substream ||
1889                             !azx_dev->running)
1890                                 continue;
1891                         if (azx_position_ok(chip, azx_dev)) {
1892                                 azx_dev->irq_pending = 0;
1893                                 spin_unlock(&chip->reg_lock);
1894                                 snd_pcm_period_elapsed(azx_dev->substream);
1895                                 spin_lock(&chip->reg_lock);
1896                         } else
1897                                 pending++;
1898                 }
1899                 spin_unlock_irq(&chip->reg_lock);
1900                 if (!pending)
1901                         return;
1902                 cond_resched();
1903         }
1904 }
1905
1906 /* clear irq_pending flags and assure no on-going workq */
1907 static void azx_clear_irq_pending(struct azx *chip)
1908 {
1909         int i;
1910
1911         spin_lock_irq(&chip->reg_lock);
1912         for (i = 0; i < chip->num_streams; i++)
1913                 chip->azx_dev[i].irq_pending = 0;
1914         spin_unlock_irq(&chip->reg_lock);
1915 }
1916
1917 static struct snd_pcm_ops azx_pcm_ops = {
1918         .open = azx_pcm_open,
1919         .close = azx_pcm_close,
1920         .ioctl = snd_pcm_lib_ioctl,
1921         .hw_params = azx_pcm_hw_params,
1922         .hw_free = azx_pcm_hw_free,
1923         .prepare = azx_pcm_prepare,
1924         .trigger = azx_pcm_trigger,
1925         .pointer = azx_pcm_pointer,
1926         .page = snd_pcm_sgbuf_ops_page,
1927 };
1928
1929 static void azx_pcm_free(struct snd_pcm *pcm)
1930 {
1931         struct azx_pcm *apcm = pcm->private_data;
1932         if (apcm) {
1933                 apcm->chip->pcm[pcm->device] = NULL;
1934                 kfree(apcm);
1935         }
1936 }
1937
1938 static int
1939 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1940                       struct hda_pcm *cpcm)
1941 {
1942         struct azx *chip = bus->private_data;
1943         struct snd_pcm *pcm;
1944         struct azx_pcm *apcm;
1945         int pcm_dev = cpcm->device;
1946         int s, err;
1947
1948         if (pcm_dev >= AZX_MAX_PCMS) {
1949                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1950                            pcm_dev);
1951                 return -EINVAL;
1952         }
1953         if (chip->pcm[pcm_dev]) {
1954                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1955                 return -EBUSY;
1956         }
1957         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1958                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1959                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1960                           &pcm);
1961         if (err < 0)
1962                 return err;
1963         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1964         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1965         if (apcm == NULL)
1966                 return -ENOMEM;
1967         apcm->chip = chip;
1968         apcm->codec = codec;
1969         pcm->private_data = apcm;
1970         pcm->private_free = azx_pcm_free;
1971         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1972                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1973         chip->pcm[pcm_dev] = pcm;
1974         cpcm->pcm = pcm;
1975         for (s = 0; s < 2; s++) {
1976                 apcm->hinfo[s] = &cpcm->stream[s];
1977                 if (cpcm->stream[s].substreams)
1978                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1979         }
1980         /* buffer pre-allocation */
1981         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1982                                               snd_dma_pci_data(chip->pci),
1983                                               1024 * 64, 32 * 1024 * 1024);
1984         return 0;
1985 }
1986
1987 /*
1988  * mixer creation - all stuff is implemented in hda module
1989  */
1990 static int __devinit azx_mixer_create(struct azx *chip)
1991 {
1992         return snd_hda_build_controls(chip->bus);
1993 }
1994
1995
1996 /*
1997  * initialize SD streams
1998  */
1999 static int __devinit azx_init_stream(struct azx *chip)
2000 {
2001         int i;
2002
2003         /* initialize each stream (aka device)
2004          * assign the starting bdl address to each stream (device)
2005          * and initialize
2006          */
2007         for (i = 0; i < chip->num_streams; i++) {
2008                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2009                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2010                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2011                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2012                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2013                 azx_dev->sd_int_sta_mask = 1 << i;
2014                 /* stream tag: must be non-zero and unique */
2015                 azx_dev->index = i;
2016                 azx_dev->stream_tag = i + 1;
2017         }
2018
2019         return 0;
2020 }
2021
2022 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2023 {
2024         if (request_irq(chip->pci->irq, azx_interrupt,
2025                         chip->msi ? 0 : IRQF_SHARED,
2026                         "HDA Intel", chip)) {
2027                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2028                        "disabling device\n", chip->pci->irq);
2029                 if (do_disconnect)
2030                         snd_card_disconnect(chip->card);
2031                 return -1;
2032         }
2033         chip->irq = chip->pci->irq;
2034         pci_intx(chip->pci, !chip->msi);
2035         return 0;
2036 }
2037
2038
2039 static void azx_stop_chip(struct azx *chip)
2040 {
2041         if (!chip->initialized)
2042                 return;
2043
2044         /* disable interrupts */
2045         azx_int_disable(chip);
2046         azx_int_clear(chip);
2047
2048         /* disable CORB/RIRB */
2049         azx_free_cmd_io(chip);
2050
2051         /* disable position buffer */
2052         azx_writel(chip, DPLBASE, 0);
2053         azx_writel(chip, DPUBASE, 0);
2054
2055         chip->initialized = 0;
2056 }
2057
2058 #ifdef CONFIG_SND_HDA_POWER_SAVE
2059 /* power-up/down the controller */
2060 static void azx_power_notify(struct hda_bus *bus)
2061 {
2062         struct azx *chip = bus->private_data;
2063         struct hda_codec *c;
2064         int power_on = 0;
2065
2066         list_for_each_entry(c, &bus->codec_list, list) {
2067                 if (c->power_on) {
2068                         power_on = 1;
2069                         break;
2070                 }
2071         }
2072         if (power_on)
2073                 azx_init_chip(chip);
2074         else if (chip->running && power_save_controller)
2075                 azx_stop_chip(chip);
2076 }
2077 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2078
2079 #ifdef CONFIG_PM
2080 /*
2081  * power management
2082  */
2083
2084 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2085 {
2086         struct hda_codec *codec;
2087
2088         list_for_each_entry(codec, &bus->codec_list, list) {
2089                 if (snd_hda_codec_needs_resume(codec))
2090                         return 1;
2091         }
2092         return 0;
2093 }
2094
2095 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2096 {
2097         struct snd_card *card = pci_get_drvdata(pci);
2098         struct azx *chip = card->private_data;
2099         int i;
2100
2101         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2102         azx_clear_irq_pending(chip);
2103         for (i = 0; i < AZX_MAX_PCMS; i++)
2104                 snd_pcm_suspend_all(chip->pcm[i]);
2105         if (chip->initialized)
2106                 snd_hda_suspend(chip->bus);
2107         azx_stop_chip(chip);
2108         if (chip->irq >= 0) {
2109                 free_irq(chip->irq, chip);
2110                 chip->irq = -1;
2111         }
2112         if (chip->msi)
2113                 pci_disable_msi(chip->pci);
2114         pci_disable_device(pci);
2115         pci_save_state(pci);
2116         pci_set_power_state(pci, pci_choose_state(pci, state));
2117         return 0;
2118 }
2119
2120 static int azx_resume(struct pci_dev *pci)
2121 {
2122         struct snd_card *card = pci_get_drvdata(pci);
2123         struct azx *chip = card->private_data;
2124
2125         pci_set_power_state(pci, PCI_D0);
2126         pci_restore_state(pci);
2127         if (pci_enable_device(pci) < 0) {
2128                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2129                        "disabling device\n");
2130                 snd_card_disconnect(card);
2131                 return -EIO;
2132         }
2133         pci_set_master(pci);
2134         if (chip->msi)
2135                 if (pci_enable_msi(pci) < 0)
2136                         chip->msi = 0;
2137         if (azx_acquire_irq(chip, 1) < 0)
2138                 return -EIO;
2139         azx_init_pci(chip);
2140
2141         if (snd_hda_codecs_inuse(chip->bus))
2142                 azx_init_chip(chip);
2143
2144         snd_hda_resume(chip->bus);
2145         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2146         return 0;
2147 }
2148 #endif /* CONFIG_PM */
2149
2150
2151 /*
2152  * reboot notifier for hang-up problem at power-down
2153  */
2154 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2155 {
2156         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2157         azx_stop_chip(chip);
2158         return NOTIFY_OK;
2159 }
2160
2161 static void azx_notifier_register(struct azx *chip)
2162 {
2163         chip->reboot_notifier.notifier_call = azx_halt;
2164         register_reboot_notifier(&chip->reboot_notifier);
2165 }
2166
2167 static void azx_notifier_unregister(struct azx *chip)
2168 {
2169         if (chip->reboot_notifier.notifier_call)
2170                 unregister_reboot_notifier(&chip->reboot_notifier);
2171 }
2172
2173 /*
2174  * destructor
2175  */
2176 static int azx_free(struct azx *chip)
2177 {
2178         int i;
2179
2180         azx_notifier_unregister(chip);
2181
2182         if (chip->initialized) {
2183                 azx_clear_irq_pending(chip);
2184                 for (i = 0; i < chip->num_streams; i++)
2185                         azx_stream_stop(chip, &chip->azx_dev[i]);
2186                 azx_stop_chip(chip);
2187         }
2188
2189         if (chip->irq >= 0)
2190                 free_irq(chip->irq, (void*)chip);
2191         if (chip->msi)
2192                 pci_disable_msi(chip->pci);
2193         if (chip->remap_addr)
2194                 iounmap(chip->remap_addr);
2195
2196         if (chip->azx_dev) {
2197                 for (i = 0; i < chip->num_streams; i++)
2198                         if (chip->azx_dev[i].bdl.area)
2199                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2200         }
2201         if (chip->rb.area)
2202                 snd_dma_free_pages(&chip->rb);
2203         if (chip->posbuf.area)
2204                 snd_dma_free_pages(&chip->posbuf);
2205         pci_release_regions(chip->pci);
2206         pci_disable_device(chip->pci);
2207         kfree(chip->azx_dev);
2208         kfree(chip);
2209
2210         return 0;
2211 }
2212
2213 static int azx_dev_free(struct snd_device *device)
2214 {
2215         return azx_free(device->device_data);
2216 }
2217
2218 /*
2219  * white/black-listing for position_fix
2220  */
2221 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2222         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2223         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2224         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2225         {}
2226 };
2227
2228 static int __devinit check_position_fix(struct azx *chip, int fix)
2229 {
2230         const struct snd_pci_quirk *q;
2231
2232         switch (fix) {
2233         case POS_FIX_LPIB:
2234         case POS_FIX_POSBUF:
2235                 return fix;
2236         }
2237
2238         /* Check VIA/ATI HD Audio Controller exist */
2239         switch (chip->driver_type) {
2240         case AZX_DRIVER_VIA:
2241         case AZX_DRIVER_ATI:
2242                 chip->via_dmapos_patch = 1;
2243                 /* Use link position directly, avoid any transfer problem. */
2244                 return POS_FIX_LPIB;
2245         }
2246         chip->via_dmapos_patch = 0;
2247
2248         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2249         if (q) {
2250                 printk(KERN_INFO
2251                        "hda_intel: position_fix set to %d "
2252                        "for device %04x:%04x\n",
2253                        q->value, q->subvendor, q->subdevice);
2254                 return q->value;
2255         }
2256         return POS_FIX_AUTO;
2257 }
2258
2259 /*
2260  * black-lists for probe_mask
2261  */
2262 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2263         /* Thinkpad often breaks the controller communication when accessing
2264          * to the non-working (or non-existing) modem codec slot.
2265          */
2266         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2267         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2268         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2269         /* broken BIOS */
2270         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2271         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2272         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2273         /* forced codec slots */
2274         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2275         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2276         {}
2277 };
2278
2279 #define AZX_FORCE_CODEC_MASK    0x100
2280
2281 static void __devinit check_probe_mask(struct azx *chip, int dev)
2282 {
2283         const struct snd_pci_quirk *q;
2284
2285         chip->codec_probe_mask = probe_mask[dev];
2286         if (chip->codec_probe_mask == -1) {
2287                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2288                 if (q) {
2289                         printk(KERN_INFO
2290                                "hda_intel: probe_mask set to 0x%x "
2291                                "for device %04x:%04x\n",
2292                                q->value, q->subvendor, q->subdevice);
2293                         chip->codec_probe_mask = q->value;
2294                 }
2295         }
2296
2297         /* check forced option */
2298         if (chip->codec_probe_mask != -1 &&
2299             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2300                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2301                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2302                        chip->codec_mask);
2303         }
2304 }
2305
2306 /*
2307  * white-list for enable_msi
2308  */
2309 static struct snd_pci_quirk msi_white_list[] __devinitdata = {
2310         SND_PCI_QUIRK(0x103c, 0x30f7, "HP Pavilion dv4t-1300", 1),
2311         SND_PCI_QUIRK(0x103c, 0x3607, "HP Compa CQ40", 1),
2312         {}
2313 };
2314
2315 static void __devinit check_msi(struct azx *chip)
2316 {
2317         const struct snd_pci_quirk *q;
2318
2319         chip->msi = enable_msi;
2320         if (chip->msi)
2321                 return;
2322         q = snd_pci_quirk_lookup(chip->pci, msi_white_list);
2323         if (q) {
2324                 printk(KERN_INFO
2325                        "hda_intel: msi for device %04x:%04x set to %d\n",
2326                        q->subvendor, q->subdevice, q->value);
2327                 chip->msi = q->value;
2328         }
2329 }
2330
2331
2332 /*
2333  * constructor
2334  */
2335 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2336                                 int dev, int driver_type,
2337                                 struct azx **rchip)
2338 {
2339         struct azx *chip;
2340         int i, err;
2341         unsigned short gcap;
2342         static struct snd_device_ops ops = {
2343                 .dev_free = azx_dev_free,
2344         };
2345
2346         *rchip = NULL;
2347
2348         err = pci_enable_device(pci);
2349         if (err < 0)
2350                 return err;
2351
2352         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2353         if (!chip) {
2354                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2355                 pci_disable_device(pci);
2356                 return -ENOMEM;
2357         }
2358
2359         spin_lock_init(&chip->reg_lock);
2360         mutex_init(&chip->open_mutex);
2361         chip->card = card;
2362         chip->pci = pci;
2363         chip->irq = -1;
2364         chip->driver_type = driver_type;
2365         check_msi(chip);
2366         chip->dev_index = dev;
2367         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2368
2369         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2370         check_probe_mask(chip, dev);
2371
2372         chip->single_cmd = single_cmd;
2373
2374         if (bdl_pos_adj[dev] < 0) {
2375                 switch (chip->driver_type) {
2376                 case AZX_DRIVER_ICH:
2377                         bdl_pos_adj[dev] = 1;
2378                         break;
2379                 default:
2380                         bdl_pos_adj[dev] = 32;
2381                         break;
2382                 }
2383         }
2384
2385 #if BITS_PER_LONG != 64
2386         /* Fix up base address on ULI M5461 */
2387         if (chip->driver_type == AZX_DRIVER_ULI) {
2388                 u16 tmp3;
2389                 pci_read_config_word(pci, 0x40, &tmp3);
2390                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2391                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2392         }
2393 #endif
2394
2395         err = pci_request_regions(pci, "ICH HD audio");
2396         if (err < 0) {
2397                 kfree(chip);
2398                 pci_disable_device(pci);
2399                 return err;
2400         }
2401
2402         chip->addr = pci_resource_start(pci, 0);
2403         chip->remap_addr = pci_ioremap_bar(pci, 0);
2404         if (chip->remap_addr == NULL) {
2405                 snd_printk(KERN_ERR SFX "ioremap error\n");
2406                 err = -ENXIO;
2407                 goto errout;
2408         }
2409
2410         if (chip->msi)
2411                 if (pci_enable_msi(pci) < 0)
2412                         chip->msi = 0;
2413
2414         if (azx_acquire_irq(chip, 0) < 0) {
2415                 err = -EBUSY;
2416                 goto errout;
2417         }
2418
2419         pci_set_master(pci);
2420         synchronize_irq(chip->irq);
2421
2422         gcap = azx_readw(chip, GCAP);
2423         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2424
2425         /* disable SB600 64bit support for safety */
2426         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2427             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2428                 struct pci_dev *p_smbus;
2429                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2430                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2431                                          NULL);
2432                 if (p_smbus) {
2433                         if (p_smbus->revision < 0x30)
2434                                 gcap &= ~ICH6_GCAP_64OK;
2435                         pci_dev_put(p_smbus);
2436                 }
2437         }
2438
2439         /* allow 64bit DMA address if supported by H/W */
2440         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2441                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2442         else {
2443                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2444                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2445         }
2446
2447         /* read number of streams from GCAP register instead of using
2448          * hardcoded value
2449          */
2450         chip->capture_streams = (gcap >> 8) & 0x0f;
2451         chip->playback_streams = (gcap >> 12) & 0x0f;
2452         if (!chip->playback_streams && !chip->capture_streams) {
2453                 /* gcap didn't give any info, switching to old method */
2454
2455                 switch (chip->driver_type) {
2456                 case AZX_DRIVER_ULI:
2457                         chip->playback_streams = ULI_NUM_PLAYBACK;
2458                         chip->capture_streams = ULI_NUM_CAPTURE;
2459                         break;
2460                 case AZX_DRIVER_ATIHDMI:
2461                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2462                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2463                         break;
2464                 case AZX_DRIVER_GENERIC:
2465                 default:
2466                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2467                         chip->capture_streams = ICH6_NUM_CAPTURE;
2468                         break;
2469                 }
2470         }
2471         chip->capture_index_offset = 0;
2472         chip->playback_index_offset = chip->capture_streams;
2473         chip->num_streams = chip->playback_streams + chip->capture_streams;
2474         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2475                                 GFP_KERNEL);
2476         if (!chip->azx_dev) {
2477                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2478                 goto errout;
2479         }
2480
2481         for (i = 0; i < chip->num_streams; i++) {
2482                 /* allocate memory for the BDL for each stream */
2483                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2484                                           snd_dma_pci_data(chip->pci),
2485                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2486                 if (err < 0) {
2487                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2488                         goto errout;
2489                 }
2490         }
2491         /* allocate memory for the position buffer */
2492         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2493                                   snd_dma_pci_data(chip->pci),
2494                                   chip->num_streams * 8, &chip->posbuf);
2495         if (err < 0) {
2496                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2497                 goto errout;
2498         }
2499         /* allocate CORB/RIRB */
2500         err = azx_alloc_cmd_io(chip);
2501         if (err < 0)
2502                 goto errout;
2503
2504         /* initialize streams */
2505         azx_init_stream(chip);
2506
2507         /* initialize chip */
2508         azx_init_pci(chip);
2509         azx_init_chip(chip);
2510
2511         /* codec detection */
2512         if (!chip->codec_mask) {
2513                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2514                 err = -ENODEV;
2515                 goto errout;
2516         }
2517
2518         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2519         if (err <0) {
2520                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2521                 goto errout;
2522         }
2523
2524         strcpy(card->driver, "HDA-Intel");
2525         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2526                 sizeof(card->shortname));
2527         snprintf(card->longname, sizeof(card->longname),
2528                  "%s at 0x%lx irq %i",
2529                  card->shortname, chip->addr, chip->irq);
2530
2531         *rchip = chip;
2532         return 0;
2533
2534  errout:
2535         azx_free(chip);
2536         return err;
2537 }
2538
2539 static void power_down_all_codecs(struct azx *chip)
2540 {
2541 #ifdef CONFIG_SND_HDA_POWER_SAVE
2542         /* The codecs were powered up in snd_hda_codec_new().
2543          * Now all initialization done, so turn them down if possible
2544          */
2545         struct hda_codec *codec;
2546         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2547                 snd_hda_power_down(codec);
2548         }
2549 #endif
2550 }
2551
2552 static int __devinit azx_probe(struct pci_dev *pci,
2553                                const struct pci_device_id *pci_id)
2554 {
2555         static int dev;
2556         struct snd_card *card;
2557         struct azx *chip;
2558         int err;
2559
2560         if (dev >= SNDRV_CARDS)
2561                 return -ENODEV;
2562         if (!enable[dev]) {
2563                 dev++;
2564                 return -ENOENT;
2565         }
2566
2567         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2568         if (err < 0) {
2569                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2570                 return err;
2571         }
2572
2573         /* set this here since it's referred in snd_hda_load_patch() */
2574         snd_card_set_dev(card, &pci->dev);
2575
2576         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2577         if (err < 0)
2578                 goto out_free;
2579         card->private_data = chip;
2580
2581         /* create codec instances */
2582         err = azx_codec_create(chip, model[dev]);
2583         if (err < 0)
2584                 goto out_free;
2585 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2586         if (patch[dev]) {
2587                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2588                            patch[dev]);
2589                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2590                 if (err < 0)
2591                         goto out_free;
2592         }
2593 #endif
2594         if (!probe_only[dev]) {
2595                 err = azx_codec_configure(chip);
2596                 if (err < 0)
2597                         goto out_free;
2598         }
2599
2600         /* create PCM streams */
2601         err = snd_hda_build_pcms(chip->bus);
2602         if (err < 0)
2603                 goto out_free;
2604
2605         /* create mixer controls */
2606         err = azx_mixer_create(chip);
2607         if (err < 0)
2608                 goto out_free;
2609
2610         err = snd_card_register(card);
2611         if (err < 0)
2612                 goto out_free;
2613
2614         pci_set_drvdata(pci, card);
2615         chip->running = 1;
2616         power_down_all_codecs(chip);
2617         azx_notifier_register(chip);
2618
2619         dev++;
2620         return err;
2621 out_free:
2622         snd_card_free(card);
2623         return err;
2624 }
2625
2626 static void __devexit azx_remove(struct pci_dev *pci)
2627 {
2628         snd_card_free(pci_get_drvdata(pci));
2629         pci_set_drvdata(pci, NULL);
2630 }
2631
2632 /* PCI IDs */
2633 static struct pci_device_id azx_ids[] = {
2634         /* ICH 6..10 */
2635         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2636         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2637         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2638         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2639         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2640         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2641         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2642         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2643         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2644         /* PCH */
2645         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2646         /* SCH */
2647         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2648         /* ATI SB 450/600 */
2649         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2650         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2651         /* ATI HDMI */
2652         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2653         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2654         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2655         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2656         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2657         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2658         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2659         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2660         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2661         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2662         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2663         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2664         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2665         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2666         /* VIA VT8251/VT8237A */
2667         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2668         /* SIS966 */
2669         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2670         /* ULI M5461 */
2671         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2672         /* NVIDIA MCP */
2673         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2674         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2675         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2676         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2677         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2678         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2679         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2680         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2681         { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA },
2682         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2683         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2684         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2685         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2686         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2687         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2688         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2689         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2690         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2691         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2692         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2693         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2694         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2695         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2696         /* Teradici */
2697         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2698         /* Creative X-Fi (CA0110-IBG) */
2699 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2700         /* the following entry conflicts with snd-ctxfi driver,
2701          * as ctxfi driver mutates from HD-audio to native mode with
2702          * a special command sequence.
2703          */
2704         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2705           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2706           .class_mask = 0xffffff,
2707           .driver_data = AZX_DRIVER_GENERIC },
2708 #else
2709         /* this entry seems still valid -- i.e. without emu20kx chip */
2710         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2711 #endif
2712         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2713         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2714           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2715           .class_mask = 0xffffff,
2716           .driver_data = AZX_DRIVER_GENERIC },
2717         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2718           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2719           .class_mask = 0xffffff,
2720           .driver_data = AZX_DRIVER_GENERIC },
2721         { 0, }
2722 };
2723 MODULE_DEVICE_TABLE(pci, azx_ids);
2724
2725 /* pci_driver definition */
2726 static struct pci_driver driver = {
2727         .name = "HDA Intel",
2728         .id_table = azx_ids,
2729         .probe = azx_probe,
2730         .remove = __devexit_p(azx_remove),
2731 #ifdef CONFIG_PM
2732         .suspend = azx_suspend,
2733         .resume = azx_resume,
2734 #endif
2735 };
2736
2737 static int __init alsa_card_azx_init(void)
2738 {
2739         return pci_register_driver(&driver);
2740 }
2741
2742 static void __exit alsa_card_azx_exit(void)
2743 {
2744         pci_unregister_driver(&driver);
2745 }
2746
2747 module_init(alsa_card_azx_init)
2748 module_exit(alsa_card_azx_exit)