ALSA: hda-intel: Add position_fix quirk for ASUS M2V-MX SE.
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82                  "(0 = auto, 1 = none, 2 = POSBUF).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, bool, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91                  "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108                  "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111  * this may give more power-saving, but will take longer time to
112  * wake up.
113  */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121                          "{Intel, ICH6M},"
122                          "{Intel, ICH7},"
123                          "{Intel, ESB2},"
124                          "{Intel, ICH8},"
125                          "{Intel, ICH9},"
126                          "{Intel, ICH10},"
127                          "{Intel, PCH},"
128                          "{Intel, CPT},"
129                          "{Intel, SCH},"
130                          "{ATI, SB450},"
131                          "{ATI, SB600},"
132                          "{ATI, RS600},"
133                          "{ATI, RS690},"
134                          "{ATI, RS780},"
135                          "{ATI, R600},"
136                          "{ATI, RV630},"
137                          "{ATI, RV610},"
138                          "{ATI, RV670},"
139                          "{ATI, RV635},"
140                          "{ATI, RV620},"
141                          "{ATI, RV770},"
142                          "{VIA, VT8251},"
143                          "{VIA, VT8237A},"
144                          "{SiS, SIS966},"
145                          "{ULI, M5461}}");
146 MODULE_DESCRIPTION("Intel HDA driver");
147
148 #ifdef CONFIG_SND_VERBOSE_PRINTK
149 #define SFX     /* nop */
150 #else
151 #define SFX     "hda-intel: "
152 #endif
153
154 /*
155  * registers
156  */
157 #define ICH6_REG_GCAP                   0x00
158 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
159 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
160 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
161 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
162 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
163 #define ICH6_REG_VMIN                   0x02
164 #define ICH6_REG_VMAJ                   0x03
165 #define ICH6_REG_OUTPAY                 0x04
166 #define ICH6_REG_INPAY                  0x06
167 #define ICH6_REG_GCTL                   0x08
168 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
169 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
170 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
171 #define ICH6_REG_WAKEEN                 0x0c
172 #define ICH6_REG_STATESTS               0x0e
173 #define ICH6_REG_GSTS                   0x10
174 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
175 #define ICH6_REG_INTCTL                 0x20
176 #define ICH6_REG_INTSTS                 0x24
177 #define ICH6_REG_WALCLK                 0x30
178 #define ICH6_REG_SYNC                   0x34    
179 #define ICH6_REG_CORBLBASE              0x40
180 #define ICH6_REG_CORBUBASE              0x44
181 #define ICH6_REG_CORBWP                 0x48
182 #define ICH6_REG_CORBRP                 0x4a
183 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
184 #define ICH6_REG_CORBCTL                0x4c
185 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
186 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
187 #define ICH6_REG_CORBSTS                0x4d
188 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
189 #define ICH6_REG_CORBSIZE               0x4e
190
191 #define ICH6_REG_RIRBLBASE              0x50
192 #define ICH6_REG_RIRBUBASE              0x54
193 #define ICH6_REG_RIRBWP                 0x58
194 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
195 #define ICH6_REG_RINTCNT                0x5a
196 #define ICH6_REG_RIRBCTL                0x5c
197 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
198 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
199 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
200 #define ICH6_REG_RIRBSTS                0x5d
201 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
202 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
203 #define ICH6_REG_RIRBSIZE               0x5e
204
205 #define ICH6_REG_IC                     0x60
206 #define ICH6_REG_IR                     0x64
207 #define ICH6_REG_IRS                    0x68
208 #define   ICH6_IRS_VALID        (1<<1)
209 #define   ICH6_IRS_BUSY         (1<<0)
210
211 #define ICH6_REG_DPLBASE                0x70
212 #define ICH6_REG_DPUBASE                0x74
213 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
214
215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218 /* stream register offsets from stream base */
219 #define ICH6_REG_SD_CTL                 0x00
220 #define ICH6_REG_SD_STS                 0x03
221 #define ICH6_REG_SD_LPIB                0x04
222 #define ICH6_REG_SD_CBL                 0x08
223 #define ICH6_REG_SD_LVI                 0x0c
224 #define ICH6_REG_SD_FIFOW               0x0e
225 #define ICH6_REG_SD_FIFOSIZE            0x10
226 #define ICH6_REG_SD_FORMAT              0x12
227 #define ICH6_REG_SD_BDLPL               0x18
228 #define ICH6_REG_SD_BDLPU               0x1c
229
230 /* PCI space */
231 #define ICH6_PCIREG_TCSEL       0x44
232
233 /*
234  * other constants
235  */
236
237 /* max number of SDs */
238 /* ICH, ATI and VIA have 4 playback and 4 capture */
239 #define ICH6_NUM_CAPTURE        4
240 #define ICH6_NUM_PLAYBACK       4
241
242 /* ULI has 6 playback and 5 capture */
243 #define ULI_NUM_CAPTURE         5
244 #define ULI_NUM_PLAYBACK        6
245
246 /* ATI HDMI has 1 playback and 0 capture */
247 #define ATIHDMI_NUM_CAPTURE     0
248 #define ATIHDMI_NUM_PLAYBACK    1
249
250 /* TERA has 4 playback and 3 capture */
251 #define TERA_NUM_CAPTURE        3
252 #define TERA_NUM_PLAYBACK       4
253
254 /* this number is statically defined for simplicity */
255 #define MAX_AZX_DEV             16
256
257 /* max number of fragments - we may use more if allocating more pages for BDL */
258 #define BDL_SIZE                4096
259 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
260 #define AZX_MAX_FRAG            32
261 /* max buffer size - no h/w limit, you can increase as you like */
262 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
263
264 /* RIRB int mask: overrun[2], response[0] */
265 #define RIRB_INT_RESPONSE       0x01
266 #define RIRB_INT_OVERRUN        0x04
267 #define RIRB_INT_MASK           0x05
268
269 /* STATESTS int mask: S3,SD2,SD1,SD0 */
270 #define AZX_MAX_CODECS          4
271 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
272
273 /* SD_CTL bits */
274 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
275 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
276 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
277 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
278 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
279 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
280 #define SD_CTL_STREAM_TAG_SHIFT 20
281
282 /* SD_CTL and SD_STS */
283 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
284 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
285 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
286 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
287                                  SD_INT_COMPLETE)
288
289 /* SD_STS */
290 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
291
292 /* INTCTL and INTSTS */
293 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
294 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
295 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
296
297 /* below are so far hardcoded - should read registers in future */
298 #define ICH6_MAX_CORB_ENTRIES   256
299 #define ICH6_MAX_RIRB_ENTRIES   256
300
301 /* position fix mode */
302 enum {
303         POS_FIX_AUTO,
304         POS_FIX_LPIB,
305         POS_FIX_POSBUF,
306 };
307
308 /* Defines for ATI HD Audio support in SB450 south bridge */
309 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
310 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
311
312 /* Defines for Nvidia HDA support */
313 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
314 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
315 #define NVIDIA_HDA_ISTRM_COH          0x4d
316 #define NVIDIA_HDA_OSTRM_COH          0x4c
317 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
318
319 /* Defines for Intel SCH HDA snoop control */
320 #define INTEL_SCH_HDA_DEVC      0x78
321 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
322
323 /* Define IN stream 0 FIFO size offset in VIA controller */
324 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
325 /* Define VIA HD Audio Device ID*/
326 #define VIA_HDAC_DEVICE_ID              0x3288
327
328 /* HD Audio class code */
329 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
330
331 /*
332  */
333
334 struct azx_dev {
335         struct snd_dma_buffer bdl; /* BDL buffer */
336         u32 *posbuf;            /* position buffer pointer */
337
338         unsigned int bufsize;   /* size of the play buffer in bytes */
339         unsigned int period_bytes; /* size of the period in bytes */
340         unsigned int frags;     /* number for period in the play buffer */
341         unsigned int fifo_size; /* FIFO size */
342         unsigned long start_jiffies;    /* start + minimum jiffies */
343         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
344
345         void __iomem *sd_addr;  /* stream descriptor pointer */
346
347         u32 sd_int_sta_mask;    /* stream int status mask */
348
349         /* pcm support */
350         struct snd_pcm_substream *substream;    /* assigned substream,
351                                                  * set in PCM open
352                                                  */
353         unsigned int format_val;        /* format value to be set in the
354                                          * controller and the codec
355                                          */
356         unsigned char stream_tag;       /* assigned stream */
357         unsigned char index;            /* stream index */
358         int device;                     /* last device number assigned to */
359
360         unsigned int opened :1;
361         unsigned int running :1;
362         unsigned int irq_pending :1;
363         unsigned int start_flag: 1;     /* stream full start flag */
364         /*
365          * For VIA:
366          *  A flag to ensure DMA position is 0
367          *  when link position is not greater than FIFO size
368          */
369         unsigned int insufficient :1;
370 };
371
372 /* CORB/RIRB */
373 struct azx_rb {
374         u32 *buf;               /* CORB/RIRB buffer
375                                  * Each CORB entry is 4byte, RIRB is 8byte
376                                  */
377         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
378         /* for RIRB */
379         unsigned short rp, wp;  /* read/write pointers */
380         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
381         u32 res[AZX_MAX_CODECS];        /* last read value */
382 };
383
384 struct azx {
385         struct snd_card *card;
386         struct pci_dev *pci;
387         int dev_index;
388
389         /* chip type specific */
390         int driver_type;
391         int playback_streams;
392         int playback_index_offset;
393         int capture_streams;
394         int capture_index_offset;
395         int num_streams;
396
397         /* pci resources */
398         unsigned long addr;
399         void __iomem *remap_addr;
400         int irq;
401
402         /* locks */
403         spinlock_t reg_lock;
404         struct mutex open_mutex;
405
406         /* streams (x num_streams) */
407         struct azx_dev *azx_dev;
408
409         /* PCM */
410         struct snd_pcm *pcm[HDA_MAX_PCMS];
411
412         /* HD codec */
413         unsigned short codec_mask;
414         int  codec_probe_mask; /* copied from probe_mask option */
415         struct hda_bus *bus;
416         unsigned int beep_mode;
417
418         /* CORB/RIRB */
419         struct azx_rb corb;
420         struct azx_rb rirb;
421
422         /* CORB/RIRB and position buffers */
423         struct snd_dma_buffer rb;
424         struct snd_dma_buffer posbuf;
425
426         /* flags */
427         int position_fix;
428         int poll_count;
429         unsigned int running :1;
430         unsigned int initialized :1;
431         unsigned int single_cmd :1;
432         unsigned int polling_mode :1;
433         unsigned int msi :1;
434         unsigned int irq_pending_warned :1;
435         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
436         unsigned int probing :1; /* codec probing phase */
437
438         /* for debugging */
439         unsigned int last_cmd[AZX_MAX_CODECS];
440
441         /* for pending irqs */
442         struct work_struct irq_pending_work;
443
444         /* reboot notifier (for mysterious hangup problem at power-down) */
445         struct notifier_block reboot_notifier;
446 };
447
448 /* driver types */
449 enum {
450         AZX_DRIVER_ICH,
451         AZX_DRIVER_SCH,
452         AZX_DRIVER_ATI,
453         AZX_DRIVER_ATIHDMI,
454         AZX_DRIVER_VIA,
455         AZX_DRIVER_SIS,
456         AZX_DRIVER_ULI,
457         AZX_DRIVER_NVIDIA,
458         AZX_DRIVER_TERA,
459         AZX_DRIVER_GENERIC,
460         AZX_NUM_DRIVERS, /* keep this as last entry */
461 };
462
463 static char *driver_short_names[] __devinitdata = {
464         [AZX_DRIVER_ICH] = "HDA Intel",
465         [AZX_DRIVER_SCH] = "HDA Intel MID",
466         [AZX_DRIVER_ATI] = "HDA ATI SB",
467         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
468         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
469         [AZX_DRIVER_SIS] = "HDA SIS966",
470         [AZX_DRIVER_ULI] = "HDA ULI M5461",
471         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
472         [AZX_DRIVER_TERA] = "HDA Teradici", 
473         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
474 };
475
476 /*
477  * macros for easy use
478  */
479 #define azx_writel(chip,reg,value) \
480         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
481 #define azx_readl(chip,reg) \
482         readl((chip)->remap_addr + ICH6_REG_##reg)
483 #define azx_writew(chip,reg,value) \
484         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
485 #define azx_readw(chip,reg) \
486         readw((chip)->remap_addr + ICH6_REG_##reg)
487 #define azx_writeb(chip,reg,value) \
488         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
489 #define azx_readb(chip,reg) \
490         readb((chip)->remap_addr + ICH6_REG_##reg)
491
492 #define azx_sd_writel(dev,reg,value) \
493         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
494 #define azx_sd_readl(dev,reg) \
495         readl((dev)->sd_addr + ICH6_REG_##reg)
496 #define azx_sd_writew(dev,reg,value) \
497         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
498 #define azx_sd_readw(dev,reg) \
499         readw((dev)->sd_addr + ICH6_REG_##reg)
500 #define azx_sd_writeb(dev,reg,value) \
501         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
502 #define azx_sd_readb(dev,reg) \
503         readb((dev)->sd_addr + ICH6_REG_##reg)
504
505 /* for pcm support */
506 #define get_azx_dev(substream) (substream->runtime->private_data)
507
508 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
509 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
510 /*
511  * Interface for HD codec
512  */
513
514 /*
515  * CORB / RIRB interface
516  */
517 static int azx_alloc_cmd_io(struct azx *chip)
518 {
519         int err;
520
521         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
522         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
523                                   snd_dma_pci_data(chip->pci),
524                                   PAGE_SIZE, &chip->rb);
525         if (err < 0) {
526                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
527                 return err;
528         }
529         return 0;
530 }
531
532 static void azx_init_cmd_io(struct azx *chip)
533 {
534         spin_lock_irq(&chip->reg_lock);
535         /* CORB set up */
536         chip->corb.addr = chip->rb.addr;
537         chip->corb.buf = (u32 *)chip->rb.area;
538         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
539         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
540
541         /* set the corb size to 256 entries (ULI requires explicitly) */
542         azx_writeb(chip, CORBSIZE, 0x02);
543         /* set the corb write pointer to 0 */
544         azx_writew(chip, CORBWP, 0);
545         /* reset the corb hw read pointer */
546         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
547         /* enable corb dma */
548         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
549
550         /* RIRB set up */
551         chip->rirb.addr = chip->rb.addr + 2048;
552         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
553         chip->rirb.wp = chip->rirb.rp = 0;
554         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
555         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
556         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
557
558         /* set the rirb size to 256 entries (ULI requires explicitly) */
559         azx_writeb(chip, RIRBSIZE, 0x02);
560         /* reset the rirb hw write pointer */
561         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
562         /* set N=1, get RIRB response interrupt for new entry */
563         azx_writew(chip, RINTCNT, 1);
564         /* enable rirb dma and response irq */
565         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
566         spin_unlock_irq(&chip->reg_lock);
567 }
568
569 static void azx_free_cmd_io(struct azx *chip)
570 {
571         spin_lock_irq(&chip->reg_lock);
572         /* disable ringbuffer DMAs */
573         azx_writeb(chip, RIRBCTL, 0);
574         azx_writeb(chip, CORBCTL, 0);
575         spin_unlock_irq(&chip->reg_lock);
576 }
577
578 static unsigned int azx_command_addr(u32 cmd)
579 {
580         unsigned int addr = cmd >> 28;
581
582         if (addr >= AZX_MAX_CODECS) {
583                 snd_BUG();
584                 addr = 0;
585         }
586
587         return addr;
588 }
589
590 static unsigned int azx_response_addr(u32 res)
591 {
592         unsigned int addr = res & 0xf;
593
594         if (addr >= AZX_MAX_CODECS) {
595                 snd_BUG();
596                 addr = 0;
597         }
598
599         return addr;
600 }
601
602 /* send a command */
603 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
604 {
605         struct azx *chip = bus->private_data;
606         unsigned int addr = azx_command_addr(val);
607         unsigned int wp;
608
609         spin_lock_irq(&chip->reg_lock);
610
611         /* add command to corb */
612         wp = azx_readb(chip, CORBWP);
613         wp++;
614         wp %= ICH6_MAX_CORB_ENTRIES;
615
616         chip->rirb.cmds[addr]++;
617         chip->corb.buf[wp] = cpu_to_le32(val);
618         azx_writel(chip, CORBWP, wp);
619
620         spin_unlock_irq(&chip->reg_lock);
621
622         return 0;
623 }
624
625 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
626
627 /* retrieve RIRB entry - called from interrupt handler */
628 static void azx_update_rirb(struct azx *chip)
629 {
630         unsigned int rp, wp;
631         unsigned int addr;
632         u32 res, res_ex;
633
634         wp = azx_readb(chip, RIRBWP);
635         if (wp == chip->rirb.wp)
636                 return;
637         chip->rirb.wp = wp;
638
639         while (chip->rirb.rp != wp) {
640                 chip->rirb.rp++;
641                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
642
643                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
644                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
645                 res = le32_to_cpu(chip->rirb.buf[rp]);
646                 addr = azx_response_addr(res_ex);
647                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
648                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
649                 else if (chip->rirb.cmds[addr]) {
650                         chip->rirb.res[addr] = res;
651                         smp_wmb();
652                         chip->rirb.cmds[addr]--;
653                 } else
654                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
655                                    "last cmd=%#08x\n",
656                                    res, res_ex,
657                                    chip->last_cmd[addr]);
658         }
659 }
660
661 /* receive a response */
662 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
663                                           unsigned int addr)
664 {
665         struct azx *chip = bus->private_data;
666         unsigned long timeout;
667         int do_poll = 0;
668
669  again:
670         timeout = jiffies + msecs_to_jiffies(1000);
671         for (;;) {
672                 if (chip->polling_mode || do_poll) {
673                         spin_lock_irq(&chip->reg_lock);
674                         azx_update_rirb(chip);
675                         spin_unlock_irq(&chip->reg_lock);
676                 }
677                 if (!chip->rirb.cmds[addr]) {
678                         smp_rmb();
679                         bus->rirb_error = 0;
680
681                         if (!do_poll)
682                                 chip->poll_count = 0;
683                         return chip->rirb.res[addr]; /* the last value */
684                 }
685                 if (time_after(jiffies, timeout))
686                         break;
687                 if (bus->needs_damn_long_delay)
688                         msleep(2); /* temporary workaround */
689                 else {
690                         udelay(10);
691                         cond_resched();
692                 }
693         }
694
695         if (!chip->polling_mode && chip->poll_count < 2) {
696                 snd_printdd(SFX "azx_get_response timeout, "
697                            "polling the codec once: last cmd=0x%08x\n",
698                            chip->last_cmd[addr]);
699                 do_poll = 1;
700                 chip->poll_count++;
701                 goto again;
702         }
703
704
705         if (!chip->polling_mode) {
706                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
707                            "switching to polling mode: last cmd=0x%08x\n",
708                            chip->last_cmd[addr]);
709                 chip->polling_mode = 1;
710                 goto again;
711         }
712
713         if (chip->msi) {
714                 snd_printk(KERN_WARNING SFX "No response from codec, "
715                            "disabling MSI: last cmd=0x%08x\n",
716                            chip->last_cmd[addr]);
717                 free_irq(chip->irq, chip);
718                 chip->irq = -1;
719                 pci_disable_msi(chip->pci);
720                 chip->msi = 0;
721                 if (azx_acquire_irq(chip, 1) < 0) {
722                         bus->rirb_error = 1;
723                         return -1;
724                 }
725                 goto again;
726         }
727
728         if (chip->probing) {
729                 /* If this critical timeout happens during the codec probing
730                  * phase, this is likely an access to a non-existing codec
731                  * slot.  Better to return an error and reset the system.
732                  */
733                 return -1;
734         }
735
736         /* a fatal communication error; need either to reset or to fallback
737          * to the single_cmd mode
738          */
739         bus->rirb_error = 1;
740         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
741                 bus->response_reset = 1;
742                 return -1; /* give a chance to retry */
743         }
744
745         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
746                    "switching to single_cmd mode: last cmd=0x%08x\n",
747                    chip->last_cmd[addr]);
748         chip->single_cmd = 1;
749         bus->response_reset = 0;
750         /* release CORB/RIRB */
751         azx_free_cmd_io(chip);
752         /* disable unsolicited responses */
753         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
754         return -1;
755 }
756
757 /*
758  * Use the single immediate command instead of CORB/RIRB for simplicity
759  *
760  * Note: according to Intel, this is not preferred use.  The command was
761  *       intended for the BIOS only, and may get confused with unsolicited
762  *       responses.  So, we shouldn't use it for normal operation from the
763  *       driver.
764  *       I left the codes, however, for debugging/testing purposes.
765  */
766
767 /* receive a response */
768 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
769 {
770         int timeout = 50;
771
772         while (timeout--) {
773                 /* check IRV busy bit */
774                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
775                         /* reuse rirb.res as the response return value */
776                         chip->rirb.res[addr] = azx_readl(chip, IR);
777                         return 0;
778                 }
779                 udelay(1);
780         }
781         if (printk_ratelimit())
782                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
783                            azx_readw(chip, IRS));
784         chip->rirb.res[addr] = -1;
785         return -EIO;
786 }
787
788 /* send a command */
789 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
790 {
791         struct azx *chip = bus->private_data;
792         unsigned int addr = azx_command_addr(val);
793         int timeout = 50;
794
795         bus->rirb_error = 0;
796         while (timeout--) {
797                 /* check ICB busy bit */
798                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
799                         /* Clear IRV valid bit */
800                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
801                                    ICH6_IRS_VALID);
802                         azx_writel(chip, IC, val);
803                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
804                                    ICH6_IRS_BUSY);
805                         return azx_single_wait_for_response(chip, addr);
806                 }
807                 udelay(1);
808         }
809         if (printk_ratelimit())
810                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
811                            azx_readw(chip, IRS), val);
812         return -EIO;
813 }
814
815 /* receive a response */
816 static unsigned int azx_single_get_response(struct hda_bus *bus,
817                                             unsigned int addr)
818 {
819         struct azx *chip = bus->private_data;
820         return chip->rirb.res[addr];
821 }
822
823 /*
824  * The below are the main callbacks from hda_codec.
825  *
826  * They are just the skeleton to call sub-callbacks according to the
827  * current setting of chip->single_cmd.
828  */
829
830 /* send a command */
831 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
832 {
833         struct azx *chip = bus->private_data;
834
835         chip->last_cmd[azx_command_addr(val)] = val;
836         if (chip->single_cmd)
837                 return azx_single_send_cmd(bus, val);
838         else
839                 return azx_corb_send_cmd(bus, val);
840 }
841
842 /* get a response */
843 static unsigned int azx_get_response(struct hda_bus *bus,
844                                      unsigned int addr)
845 {
846         struct azx *chip = bus->private_data;
847         if (chip->single_cmd)
848                 return azx_single_get_response(bus, addr);
849         else
850                 return azx_rirb_get_response(bus, addr);
851 }
852
853 #ifdef CONFIG_SND_HDA_POWER_SAVE
854 static void azx_power_notify(struct hda_bus *bus);
855 #endif
856
857 /* reset codec link */
858 static int azx_reset(struct azx *chip)
859 {
860         int count;
861
862         /* clear STATESTS */
863         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
864
865         /* reset controller */
866         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
867
868         count = 50;
869         while (azx_readb(chip, GCTL) && --count)
870                 msleep(1);
871
872         /* delay for >= 100us for codec PLL to settle per spec
873          * Rev 0.9 section 5.5.1
874          */
875         msleep(1);
876
877         /* Bring controller out of reset */
878         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
879
880         count = 50;
881         while (!azx_readb(chip, GCTL) && --count)
882                 msleep(1);
883
884         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
885         msleep(1);
886
887         /* check to see if controller is ready */
888         if (!azx_readb(chip, GCTL)) {
889                 snd_printd(SFX "azx_reset: controller not ready!\n");
890                 return -EBUSY;
891         }
892
893         /* Accept unsolicited responses */
894         if (!chip->single_cmd)
895                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
896                            ICH6_GCTL_UNSOL);
897
898         /* detect codecs */
899         if (!chip->codec_mask) {
900                 chip->codec_mask = azx_readw(chip, STATESTS);
901                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
902         }
903
904         return 0;
905 }
906
907
908 /*
909  * Lowlevel interface
910  */  
911
912 /* enable interrupts */
913 static void azx_int_enable(struct azx *chip)
914 {
915         /* enable controller CIE and GIE */
916         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
917                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
918 }
919
920 /* disable interrupts */
921 static void azx_int_disable(struct azx *chip)
922 {
923         int i;
924
925         /* disable interrupts in stream descriptor */
926         for (i = 0; i < chip->num_streams; i++) {
927                 struct azx_dev *azx_dev = &chip->azx_dev[i];
928                 azx_sd_writeb(azx_dev, SD_CTL,
929                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
930         }
931
932         /* disable SIE for all streams */
933         azx_writeb(chip, INTCTL, 0);
934
935         /* disable controller CIE and GIE */
936         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
937                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
938 }
939
940 /* clear interrupts */
941 static void azx_int_clear(struct azx *chip)
942 {
943         int i;
944
945         /* clear stream status */
946         for (i = 0; i < chip->num_streams; i++) {
947                 struct azx_dev *azx_dev = &chip->azx_dev[i];
948                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
949         }
950
951         /* clear STATESTS */
952         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
953
954         /* clear rirb status */
955         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
956
957         /* clear int status */
958         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
959 }
960
961 /* start a stream */
962 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
963 {
964         /*
965          * Before stream start, initialize parameter
966          */
967         azx_dev->insufficient = 1;
968
969         /* enable SIE */
970         azx_writel(chip, INTCTL,
971                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
972         /* set DMA start and interrupt mask */
973         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
974                       SD_CTL_DMA_START | SD_INT_MASK);
975 }
976
977 /* stop DMA */
978 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
979 {
980         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
981                       ~(SD_CTL_DMA_START | SD_INT_MASK));
982         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
983 }
984
985 /* stop a stream */
986 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
987 {
988         azx_stream_clear(chip, azx_dev);
989         /* disable SIE */
990         azx_writel(chip, INTCTL,
991                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
992 }
993
994
995 /*
996  * reset and start the controller registers
997  */
998 static void azx_init_chip(struct azx *chip)
999 {
1000         if (chip->initialized)
1001                 return;
1002
1003         /* reset controller */
1004         azx_reset(chip);
1005
1006         /* initialize interrupts */
1007         azx_int_clear(chip);
1008         azx_int_enable(chip);
1009
1010         /* initialize the codec command I/O */
1011         if (!chip->single_cmd)
1012                 azx_init_cmd_io(chip);
1013
1014         /* program the position buffer */
1015         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1016         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1017
1018         chip->initialized = 1;
1019 }
1020
1021 /*
1022  * initialize the PCI registers
1023  */
1024 /* update bits in a PCI register byte */
1025 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1026                             unsigned char mask, unsigned char val)
1027 {
1028         unsigned char data;
1029
1030         pci_read_config_byte(pci, reg, &data);
1031         data &= ~mask;
1032         data |= (val & mask);
1033         pci_write_config_byte(pci, reg, data);
1034 }
1035
1036 static void azx_init_pci(struct azx *chip)
1037 {
1038         unsigned short snoop;
1039
1040         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1041          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1042          * Ensuring these bits are 0 clears playback static on some HD Audio
1043          * codecs
1044          */
1045         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1046
1047         switch (chip->driver_type) {
1048         case AZX_DRIVER_ATI:
1049                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1050                 update_pci_byte(chip->pci,
1051                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
1052                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1053                 break;
1054         case AZX_DRIVER_NVIDIA:
1055                 /* For NVIDIA HDA, enable snoop */
1056                 update_pci_byte(chip->pci,
1057                                 NVIDIA_HDA_TRANSREG_ADDR,
1058                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1059                 update_pci_byte(chip->pci,
1060                                 NVIDIA_HDA_ISTRM_COH,
1061                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1062                 update_pci_byte(chip->pci,
1063                                 NVIDIA_HDA_OSTRM_COH,
1064                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1065                 break;
1066         case AZX_DRIVER_SCH:
1067                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1068                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1069                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1070                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1071                         pci_read_config_word(chip->pci,
1072                                 INTEL_SCH_HDA_DEVC, &snoop);
1073                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1074                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1075                                 ? "Failed" : "OK");
1076                 }
1077                 break;
1078
1079         }
1080 }
1081
1082
1083 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1084
1085 /*
1086  * interrupt handler
1087  */
1088 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1089 {
1090         struct azx *chip = dev_id;
1091         struct azx_dev *azx_dev;
1092         u32 status;
1093         int i, ok;
1094
1095         spin_lock(&chip->reg_lock);
1096
1097         status = azx_readl(chip, INTSTS);
1098         if (status == 0) {
1099                 spin_unlock(&chip->reg_lock);
1100                 return IRQ_NONE;
1101         }
1102         
1103         for (i = 0; i < chip->num_streams; i++) {
1104                 azx_dev = &chip->azx_dev[i];
1105                 if (status & azx_dev->sd_int_sta_mask) {
1106                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1107                         if (!azx_dev->substream || !azx_dev->running)
1108                                 continue;
1109                         /* check whether this IRQ is really acceptable */
1110                         ok = azx_position_ok(chip, azx_dev);
1111                         if (ok == 1) {
1112                                 azx_dev->irq_pending = 0;
1113                                 spin_unlock(&chip->reg_lock);
1114                                 snd_pcm_period_elapsed(azx_dev->substream);
1115                                 spin_lock(&chip->reg_lock);
1116                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1117                                 /* bogus IRQ, process it later */
1118                                 azx_dev->irq_pending = 1;
1119                                 queue_work(chip->bus->workq,
1120                                            &chip->irq_pending_work);
1121                         }
1122                 }
1123         }
1124
1125         /* clear rirb int */
1126         status = azx_readb(chip, RIRBSTS);
1127         if (status & RIRB_INT_MASK) {
1128                 if (status & RIRB_INT_RESPONSE)
1129                         azx_update_rirb(chip);
1130                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1131         }
1132
1133 #if 0
1134         /* clear state status int */
1135         if (azx_readb(chip, STATESTS) & 0x04)
1136                 azx_writeb(chip, STATESTS, 0x04);
1137 #endif
1138         spin_unlock(&chip->reg_lock);
1139         
1140         return IRQ_HANDLED;
1141 }
1142
1143
1144 /*
1145  * set up a BDL entry
1146  */
1147 static int setup_bdle(struct snd_pcm_substream *substream,
1148                       struct azx_dev *azx_dev, u32 **bdlp,
1149                       int ofs, int size, int with_ioc)
1150 {
1151         u32 *bdl = *bdlp;
1152
1153         while (size > 0) {
1154                 dma_addr_t addr;
1155                 int chunk;
1156
1157                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1158                         return -EINVAL;
1159
1160                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1161                 /* program the address field of the BDL entry */
1162                 bdl[0] = cpu_to_le32((u32)addr);
1163                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1164                 /* program the size field of the BDL entry */
1165                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1166                 bdl[2] = cpu_to_le32(chunk);
1167                 /* program the IOC to enable interrupt
1168                  * only when the whole fragment is processed
1169                  */
1170                 size -= chunk;
1171                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1172                 bdl += 4;
1173                 azx_dev->frags++;
1174                 ofs += chunk;
1175         }
1176         *bdlp = bdl;
1177         return ofs;
1178 }
1179
1180 /*
1181  * set up BDL entries
1182  */
1183 static int azx_setup_periods(struct azx *chip,
1184                              struct snd_pcm_substream *substream,
1185                              struct azx_dev *azx_dev)
1186 {
1187         u32 *bdl;
1188         int i, ofs, periods, period_bytes;
1189         int pos_adj;
1190
1191         /* reset BDL address */
1192         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1193         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1194
1195         period_bytes = azx_dev->period_bytes;
1196         periods = azx_dev->bufsize / period_bytes;
1197
1198         /* program the initial BDL entries */
1199         bdl = (u32 *)azx_dev->bdl.area;
1200         ofs = 0;
1201         azx_dev->frags = 0;
1202         pos_adj = bdl_pos_adj[chip->dev_index];
1203         if (pos_adj > 0) {
1204                 struct snd_pcm_runtime *runtime = substream->runtime;
1205                 int pos_align = pos_adj;
1206                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1207                 if (!pos_adj)
1208                         pos_adj = pos_align;
1209                 else
1210                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1211                                 pos_align;
1212                 pos_adj = frames_to_bytes(runtime, pos_adj);
1213                 if (pos_adj >= period_bytes) {
1214                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1215                                    bdl_pos_adj[chip->dev_index]);
1216                         pos_adj = 0;
1217                 } else {
1218                         ofs = setup_bdle(substream, azx_dev,
1219                                          &bdl, ofs, pos_adj, 1);
1220                         if (ofs < 0)
1221                                 goto error;
1222                 }
1223         } else
1224                 pos_adj = 0;
1225         for (i = 0; i < periods; i++) {
1226                 if (i == periods - 1 && pos_adj)
1227                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1228                                          period_bytes - pos_adj, 0);
1229                 else
1230                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1231                                          period_bytes, 1);
1232                 if (ofs < 0)
1233                         goto error;
1234         }
1235         return 0;
1236
1237  error:
1238         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1239                    azx_dev->bufsize, period_bytes);
1240         return -EINVAL;
1241 }
1242
1243 /* reset stream */
1244 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1245 {
1246         unsigned char val;
1247         int timeout;
1248
1249         azx_stream_clear(chip, azx_dev);
1250
1251         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1252                       SD_CTL_STREAM_RESET);
1253         udelay(3);
1254         timeout = 300;
1255         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1256                --timeout)
1257                 ;
1258         val &= ~SD_CTL_STREAM_RESET;
1259         azx_sd_writeb(azx_dev, SD_CTL, val);
1260         udelay(3);
1261
1262         timeout = 300;
1263         /* waiting for hardware to report that the stream is out of reset */
1264         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1265                --timeout)
1266                 ;
1267
1268         /* reset first position - may not be synced with hw at this time */
1269         *azx_dev->posbuf = 0;
1270 }
1271
1272 /*
1273  * set up the SD for streaming
1274  */
1275 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1276 {
1277         /* make sure the run bit is zero for SD */
1278         azx_stream_clear(chip, azx_dev);
1279         /* program the stream_tag */
1280         azx_sd_writel(azx_dev, SD_CTL,
1281                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1282                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1283
1284         /* program the length of samples in cyclic buffer */
1285         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1286
1287         /* program the stream format */
1288         /* this value needs to be the same as the one programmed */
1289         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1290
1291         /* program the stream LVI (last valid index) of the BDL */
1292         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1293
1294         /* program the BDL address */
1295         /* lower BDL address */
1296         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1297         /* upper BDL address */
1298         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1299
1300         /* enable the position buffer */
1301         if (chip->position_fix == POS_FIX_POSBUF ||
1302             chip->position_fix == POS_FIX_AUTO ||
1303             chip->via_dmapos_patch) {
1304                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1305                         azx_writel(chip, DPLBASE,
1306                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1307         }
1308
1309         /* set the interrupt enable bits in the descriptor control register */
1310         azx_sd_writel(azx_dev, SD_CTL,
1311                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1312
1313         return 0;
1314 }
1315
1316 /*
1317  * Probe the given codec address
1318  */
1319 static int probe_codec(struct azx *chip, int addr)
1320 {
1321         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1322                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1323         unsigned int res;
1324
1325         mutex_lock(&chip->bus->cmd_mutex);
1326         chip->probing = 1;
1327         azx_send_cmd(chip->bus, cmd);
1328         res = azx_get_response(chip->bus, addr);
1329         chip->probing = 0;
1330         mutex_unlock(&chip->bus->cmd_mutex);
1331         if (res == -1)
1332                 return -EIO;
1333         snd_printdd(SFX "codec #%d probed OK\n", addr);
1334         return 0;
1335 }
1336
1337 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1338                                  struct hda_pcm *cpcm);
1339 static void azx_stop_chip(struct azx *chip);
1340
1341 static void azx_bus_reset(struct hda_bus *bus)
1342 {
1343         struct azx *chip = bus->private_data;
1344
1345         bus->in_reset = 1;
1346         azx_stop_chip(chip);
1347         azx_init_chip(chip);
1348 #ifdef CONFIG_PM
1349         if (chip->initialized) {
1350                 int i;
1351
1352                 for (i = 0; i < HDA_MAX_PCMS; i++)
1353                         snd_pcm_suspend_all(chip->pcm[i]);
1354                 snd_hda_suspend(chip->bus);
1355                 snd_hda_resume(chip->bus);
1356         }
1357 #endif
1358         bus->in_reset = 0;
1359 }
1360
1361 /*
1362  * Codec initialization
1363  */
1364
1365 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1366 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1367         [AZX_DRIVER_TERA] = 1,
1368 };
1369
1370 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1371 {
1372         struct hda_bus_template bus_temp;
1373         int c, codecs, err;
1374         int max_slots;
1375
1376         memset(&bus_temp, 0, sizeof(bus_temp));
1377         bus_temp.private_data = chip;
1378         bus_temp.modelname = model;
1379         bus_temp.pci = chip->pci;
1380         bus_temp.ops.command = azx_send_cmd;
1381         bus_temp.ops.get_response = azx_get_response;
1382         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1383         bus_temp.ops.bus_reset = azx_bus_reset;
1384 #ifdef CONFIG_SND_HDA_POWER_SAVE
1385         bus_temp.power_save = &power_save;
1386         bus_temp.ops.pm_notify = azx_power_notify;
1387 #endif
1388
1389         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1390         if (err < 0)
1391                 return err;
1392
1393         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1394                 chip->bus->needs_damn_long_delay = 1;
1395
1396         codecs = 0;
1397         max_slots = azx_max_codecs[chip->driver_type];
1398         if (!max_slots)
1399                 max_slots = AZX_MAX_CODECS;
1400
1401         /* First try to probe all given codec slots */
1402         for (c = 0; c < max_slots; c++) {
1403                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1404                         if (probe_codec(chip, c) < 0) {
1405                                 /* Some BIOSen give you wrong codec addresses
1406                                  * that don't exist
1407                                  */
1408                                 snd_printk(KERN_WARNING SFX
1409                                            "Codec #%d probe error; "
1410                                            "disabling it...\n", c);
1411                                 chip->codec_mask &= ~(1 << c);
1412                                 /* More badly, accessing to a non-existing
1413                                  * codec often screws up the controller chip,
1414                                  * and disturbs the further communications.
1415                                  * Thus if an error occurs during probing,
1416                                  * better to reset the controller chip to
1417                                  * get back to the sanity state.
1418                                  */
1419                                 azx_stop_chip(chip);
1420                                 azx_init_chip(chip);
1421                         }
1422                 }
1423         }
1424
1425         /* Then create codec instances */
1426         for (c = 0; c < max_slots; c++) {
1427                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1428                         struct hda_codec *codec;
1429                         err = snd_hda_codec_new(chip->bus, c, &codec);
1430                         if (err < 0)
1431                                 continue;
1432                         codec->beep_mode = chip->beep_mode;
1433                         codecs++;
1434                 }
1435         }
1436         if (!codecs) {
1437                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1438                 return -ENXIO;
1439         }
1440         return 0;
1441 }
1442
1443 /* configure each codec instance */
1444 static int __devinit azx_codec_configure(struct azx *chip)
1445 {
1446         struct hda_codec *codec;
1447         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1448                 snd_hda_codec_configure(codec);
1449         }
1450         return 0;
1451 }
1452
1453
1454 /*
1455  * PCM support
1456  */
1457
1458 /* assign a stream for the PCM */
1459 static inline struct azx_dev *
1460 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1461 {
1462         int dev, i, nums;
1463         struct azx_dev *res = NULL;
1464
1465         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1466                 dev = chip->playback_index_offset;
1467                 nums = chip->playback_streams;
1468         } else {
1469                 dev = chip->capture_index_offset;
1470                 nums = chip->capture_streams;
1471         }
1472         for (i = 0; i < nums; i++, dev++)
1473                 if (!chip->azx_dev[dev].opened) {
1474                         res = &chip->azx_dev[dev];
1475                         if (res->device == substream->pcm->device)
1476                                 break;
1477                 }
1478         if (res) {
1479                 res->opened = 1;
1480                 res->device = substream->pcm->device;
1481         }
1482         return res;
1483 }
1484
1485 /* release the assigned stream */
1486 static inline void azx_release_device(struct azx_dev *azx_dev)
1487 {
1488         azx_dev->opened = 0;
1489 }
1490
1491 static struct snd_pcm_hardware azx_pcm_hw = {
1492         .info =                 (SNDRV_PCM_INFO_MMAP |
1493                                  SNDRV_PCM_INFO_INTERLEAVED |
1494                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1495                                  SNDRV_PCM_INFO_MMAP_VALID |
1496                                  /* No full-resume yet implemented */
1497                                  /* SNDRV_PCM_INFO_RESUME |*/
1498                                  SNDRV_PCM_INFO_PAUSE |
1499                                  SNDRV_PCM_INFO_SYNC_START),
1500         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1501         .rates =                SNDRV_PCM_RATE_48000,
1502         .rate_min =             48000,
1503         .rate_max =             48000,
1504         .channels_min =         2,
1505         .channels_max =         2,
1506         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1507         .period_bytes_min =     128,
1508         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1509         .periods_min =          2,
1510         .periods_max =          AZX_MAX_FRAG,
1511         .fifo_size =            0,
1512 };
1513
1514 struct azx_pcm {
1515         struct azx *chip;
1516         struct hda_codec *codec;
1517         struct hda_pcm_stream *hinfo[2];
1518 };
1519
1520 static int azx_pcm_open(struct snd_pcm_substream *substream)
1521 {
1522         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1523         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1524         struct azx *chip = apcm->chip;
1525         struct azx_dev *azx_dev;
1526         struct snd_pcm_runtime *runtime = substream->runtime;
1527         unsigned long flags;
1528         int err;
1529
1530         mutex_lock(&chip->open_mutex);
1531         azx_dev = azx_assign_device(chip, substream);
1532         if (azx_dev == NULL) {
1533                 mutex_unlock(&chip->open_mutex);
1534                 return -EBUSY;
1535         }
1536         runtime->hw = azx_pcm_hw;
1537         runtime->hw.channels_min = hinfo->channels_min;
1538         runtime->hw.channels_max = hinfo->channels_max;
1539         runtime->hw.formats = hinfo->formats;
1540         runtime->hw.rates = hinfo->rates;
1541         snd_pcm_limit_hw_rates(runtime);
1542         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1543         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1544                                    128);
1545         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1546                                    128);
1547         snd_hda_power_up(apcm->codec);
1548         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1549         if (err < 0) {
1550                 azx_release_device(azx_dev);
1551                 snd_hda_power_down(apcm->codec);
1552                 mutex_unlock(&chip->open_mutex);
1553                 return err;
1554         }
1555         snd_pcm_limit_hw_rates(runtime);
1556         /* sanity check */
1557         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1558             snd_BUG_ON(!runtime->hw.channels_max) ||
1559             snd_BUG_ON(!runtime->hw.formats) ||
1560             snd_BUG_ON(!runtime->hw.rates)) {
1561                 azx_release_device(azx_dev);
1562                 hinfo->ops.close(hinfo, apcm->codec, substream);
1563                 snd_hda_power_down(apcm->codec);
1564                 mutex_unlock(&chip->open_mutex);
1565                 return -EINVAL;
1566         }
1567         spin_lock_irqsave(&chip->reg_lock, flags);
1568         azx_dev->substream = substream;
1569         azx_dev->running = 0;
1570         spin_unlock_irqrestore(&chip->reg_lock, flags);
1571
1572         runtime->private_data = azx_dev;
1573         snd_pcm_set_sync(substream);
1574         mutex_unlock(&chip->open_mutex);
1575         return 0;
1576 }
1577
1578 static int azx_pcm_close(struct snd_pcm_substream *substream)
1579 {
1580         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1581         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1582         struct azx *chip = apcm->chip;
1583         struct azx_dev *azx_dev = get_azx_dev(substream);
1584         unsigned long flags;
1585
1586         mutex_lock(&chip->open_mutex);
1587         spin_lock_irqsave(&chip->reg_lock, flags);
1588         azx_dev->substream = NULL;
1589         azx_dev->running = 0;
1590         spin_unlock_irqrestore(&chip->reg_lock, flags);
1591         azx_release_device(azx_dev);
1592         hinfo->ops.close(hinfo, apcm->codec, substream);
1593         snd_hda_power_down(apcm->codec);
1594         mutex_unlock(&chip->open_mutex);
1595         return 0;
1596 }
1597
1598 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1599                              struct snd_pcm_hw_params *hw_params)
1600 {
1601         struct azx_dev *azx_dev = get_azx_dev(substream);
1602
1603         azx_dev->bufsize = 0;
1604         azx_dev->period_bytes = 0;
1605         azx_dev->format_val = 0;
1606         return snd_pcm_lib_malloc_pages(substream,
1607                                         params_buffer_bytes(hw_params));
1608 }
1609
1610 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1611 {
1612         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1613         struct azx_dev *azx_dev = get_azx_dev(substream);
1614         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1615
1616         /* reset BDL address */
1617         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1618         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1619         azx_sd_writel(azx_dev, SD_CTL, 0);
1620         azx_dev->bufsize = 0;
1621         azx_dev->period_bytes = 0;
1622         azx_dev->format_val = 0;
1623
1624         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1625
1626         return snd_pcm_lib_free_pages(substream);
1627 }
1628
1629 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1630 {
1631         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1632         struct azx *chip = apcm->chip;
1633         struct azx_dev *azx_dev = get_azx_dev(substream);
1634         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1635         struct snd_pcm_runtime *runtime = substream->runtime;
1636         unsigned int bufsize, period_bytes, format_val;
1637         int err;
1638
1639         azx_stream_reset(chip, azx_dev);
1640         format_val = snd_hda_calc_stream_format(runtime->rate,
1641                                                 runtime->channels,
1642                                                 runtime->format,
1643                                                 hinfo->maxbps);
1644         if (!format_val) {
1645                 snd_printk(KERN_ERR SFX
1646                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1647                            runtime->rate, runtime->channels, runtime->format);
1648                 return -EINVAL;
1649         }
1650
1651         bufsize = snd_pcm_lib_buffer_bytes(substream);
1652         period_bytes = snd_pcm_lib_period_bytes(substream);
1653
1654         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1655                     bufsize, format_val);
1656
1657         if (bufsize != azx_dev->bufsize ||
1658             period_bytes != azx_dev->period_bytes ||
1659             format_val != azx_dev->format_val) {
1660                 azx_dev->bufsize = bufsize;
1661                 azx_dev->period_bytes = period_bytes;
1662                 azx_dev->format_val = format_val;
1663                 err = azx_setup_periods(chip, substream, azx_dev);
1664                 if (err < 0)
1665                         return err;
1666         }
1667
1668         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1669                                                 (runtime->rate * 2);
1670         azx_setup_controller(chip, azx_dev);
1671         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1672                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1673         else
1674                 azx_dev->fifo_size = 0;
1675
1676         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1677                                   azx_dev->format_val, substream);
1678 }
1679
1680 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1681 {
1682         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1683         struct azx *chip = apcm->chip;
1684         struct azx_dev *azx_dev;
1685         struct snd_pcm_substream *s;
1686         int rstart = 0, start, nsync = 0, sbits = 0;
1687         int nwait, timeout;
1688
1689         switch (cmd) {
1690         case SNDRV_PCM_TRIGGER_START:
1691                 rstart = 1;
1692         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1693         case SNDRV_PCM_TRIGGER_RESUME:
1694                 start = 1;
1695                 break;
1696         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1697         case SNDRV_PCM_TRIGGER_SUSPEND:
1698         case SNDRV_PCM_TRIGGER_STOP:
1699                 start = 0;
1700                 break;
1701         default:
1702                 return -EINVAL;
1703         }
1704
1705         snd_pcm_group_for_each_entry(s, substream) {
1706                 if (s->pcm->card != substream->pcm->card)
1707                         continue;
1708                 azx_dev = get_azx_dev(s);
1709                 sbits |= 1 << azx_dev->index;
1710                 nsync++;
1711                 snd_pcm_trigger_done(s, substream);
1712         }
1713
1714         spin_lock(&chip->reg_lock);
1715         if (nsync > 1) {
1716                 /* first, set SYNC bits of corresponding streams */
1717                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1718         }
1719         snd_pcm_group_for_each_entry(s, substream) {
1720                 if (s->pcm->card != substream->pcm->card)
1721                         continue;
1722                 azx_dev = get_azx_dev(s);
1723                 if (rstart) {
1724                         azx_dev->start_flag = 1;
1725                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1726                 }
1727                 if (start)
1728                         azx_stream_start(chip, azx_dev);
1729                 else
1730                         azx_stream_stop(chip, azx_dev);
1731                 azx_dev->running = start;
1732         }
1733         spin_unlock(&chip->reg_lock);
1734         if (start) {
1735                 if (nsync == 1)
1736                         return 0;
1737                 /* wait until all FIFOs get ready */
1738                 for (timeout = 5000; timeout; timeout--) {
1739                         nwait = 0;
1740                         snd_pcm_group_for_each_entry(s, substream) {
1741                                 if (s->pcm->card != substream->pcm->card)
1742                                         continue;
1743                                 azx_dev = get_azx_dev(s);
1744                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1745                                       SD_STS_FIFO_READY))
1746                                         nwait++;
1747                         }
1748                         if (!nwait)
1749                                 break;
1750                         cpu_relax();
1751                 }
1752         } else {
1753                 /* wait until all RUN bits are cleared */
1754                 for (timeout = 5000; timeout; timeout--) {
1755                         nwait = 0;
1756                         snd_pcm_group_for_each_entry(s, substream) {
1757                                 if (s->pcm->card != substream->pcm->card)
1758                                         continue;
1759                                 azx_dev = get_azx_dev(s);
1760                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1761                                     SD_CTL_DMA_START)
1762                                         nwait++;
1763                         }
1764                         if (!nwait)
1765                                 break;
1766                         cpu_relax();
1767                 }
1768         }
1769         if (nsync > 1) {
1770                 spin_lock(&chip->reg_lock);
1771                 /* reset SYNC bits */
1772                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1773                 spin_unlock(&chip->reg_lock);
1774         }
1775         return 0;
1776 }
1777
1778 /* get the current DMA position with correction on VIA chips */
1779 static unsigned int azx_via_get_position(struct azx *chip,
1780                                          struct azx_dev *azx_dev)
1781 {
1782         unsigned int link_pos, mini_pos, bound_pos;
1783         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1784         unsigned int fifo_size;
1785
1786         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1787         if (azx_dev->index >= 4) {
1788                 /* Playback, no problem using link position */
1789                 return link_pos;
1790         }
1791
1792         /* Capture */
1793         /* For new chipset,
1794          * use mod to get the DMA position just like old chipset
1795          */
1796         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1797         mod_dma_pos %= azx_dev->period_bytes;
1798
1799         /* azx_dev->fifo_size can't get FIFO size of in stream.
1800          * Get from base address + offset.
1801          */
1802         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1803
1804         if (azx_dev->insufficient) {
1805                 /* Link position never gather than FIFO size */
1806                 if (link_pos <= fifo_size)
1807                         return 0;
1808
1809                 azx_dev->insufficient = 0;
1810         }
1811
1812         if (link_pos <= fifo_size)
1813                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1814         else
1815                 mini_pos = link_pos - fifo_size;
1816
1817         /* Find nearest previous boudary */
1818         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1819         mod_link_pos = link_pos % azx_dev->period_bytes;
1820         if (mod_link_pos >= fifo_size)
1821                 bound_pos = link_pos - mod_link_pos;
1822         else if (mod_dma_pos >= mod_mini_pos)
1823                 bound_pos = mini_pos - mod_mini_pos;
1824         else {
1825                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1826                 if (bound_pos >= azx_dev->bufsize)
1827                         bound_pos = 0;
1828         }
1829
1830         /* Calculate real DMA position we want */
1831         return bound_pos + mod_dma_pos;
1832 }
1833
1834 static unsigned int azx_get_position(struct azx *chip,
1835                                      struct azx_dev *azx_dev)
1836 {
1837         unsigned int pos;
1838
1839         if (chip->via_dmapos_patch)
1840                 pos = azx_via_get_position(chip, azx_dev);
1841         else if (chip->position_fix == POS_FIX_POSBUF ||
1842                  chip->position_fix == POS_FIX_AUTO) {
1843                 /* use the position buffer */
1844                 pos = le32_to_cpu(*azx_dev->posbuf);
1845         } else {
1846                 /* read LPIB */
1847                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1848         }
1849         if (pos >= azx_dev->bufsize)
1850                 pos = 0;
1851         return pos;
1852 }
1853
1854 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1855 {
1856         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1857         struct azx *chip = apcm->chip;
1858         struct azx_dev *azx_dev = get_azx_dev(substream);
1859         return bytes_to_frames(substream->runtime,
1860                                azx_get_position(chip, azx_dev));
1861 }
1862
1863 /*
1864  * Check whether the current DMA position is acceptable for updating
1865  * periods.  Returns non-zero if it's OK.
1866  *
1867  * Many HD-audio controllers appear pretty inaccurate about
1868  * the update-IRQ timing.  The IRQ is issued before actually the
1869  * data is processed.  So, we need to process it afterwords in a
1870  * workqueue.
1871  */
1872 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1873 {
1874         unsigned int pos;
1875
1876         if (azx_dev->start_flag &&
1877             time_before_eq(jiffies, azx_dev->start_jiffies))
1878                 return -1;      /* bogus (too early) interrupt */
1879         azx_dev->start_flag = 0;
1880
1881         pos = azx_get_position(chip, azx_dev);
1882         if (chip->position_fix == POS_FIX_AUTO) {
1883                 if (!pos) {
1884                         printk(KERN_WARNING
1885                                "hda-intel: Invalid position buffer, "
1886                                "using LPIB read method instead.\n");
1887                         chip->position_fix = POS_FIX_LPIB;
1888                         pos = azx_get_position(chip, azx_dev);
1889                 } else
1890                         chip->position_fix = POS_FIX_POSBUF;
1891         }
1892
1893         if (!bdl_pos_adj[chip->dev_index])
1894                 return 1; /* no delayed ack */
1895         if (azx_dev->period_bytes == 0) {
1896                 printk(KERN_WARNING
1897                        "hda-intel: Divide by zero was avoided "
1898                        "in azx_dev->period_bytes.\n");
1899                 return 0;
1900         }
1901         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1902                 return 0; /* NG - it's below the period boundary */
1903         return 1; /* OK, it's fine */
1904 }
1905
1906 /*
1907  * The work for pending PCM period updates.
1908  */
1909 static void azx_irq_pending_work(struct work_struct *work)
1910 {
1911         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1912         int i, pending;
1913
1914         if (!chip->irq_pending_warned) {
1915                 printk(KERN_WARNING
1916                        "hda-intel: IRQ timing workaround is activated "
1917                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1918                        chip->card->number);
1919                 chip->irq_pending_warned = 1;
1920         }
1921
1922         for (;;) {
1923                 pending = 0;
1924                 spin_lock_irq(&chip->reg_lock);
1925                 for (i = 0; i < chip->num_streams; i++) {
1926                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1927                         if (!azx_dev->irq_pending ||
1928                             !azx_dev->substream ||
1929                             !azx_dev->running)
1930                                 continue;
1931                         if (azx_position_ok(chip, azx_dev)) {
1932                                 azx_dev->irq_pending = 0;
1933                                 spin_unlock(&chip->reg_lock);
1934                                 snd_pcm_period_elapsed(azx_dev->substream);
1935                                 spin_lock(&chip->reg_lock);
1936                         } else
1937                                 pending++;
1938                 }
1939                 spin_unlock_irq(&chip->reg_lock);
1940                 if (!pending)
1941                         return;
1942                 cond_resched();
1943         }
1944 }
1945
1946 /* clear irq_pending flags and assure no on-going workq */
1947 static void azx_clear_irq_pending(struct azx *chip)
1948 {
1949         int i;
1950
1951         spin_lock_irq(&chip->reg_lock);
1952         for (i = 0; i < chip->num_streams; i++)
1953                 chip->azx_dev[i].irq_pending = 0;
1954         spin_unlock_irq(&chip->reg_lock);
1955 }
1956
1957 static struct snd_pcm_ops azx_pcm_ops = {
1958         .open = azx_pcm_open,
1959         .close = azx_pcm_close,
1960         .ioctl = snd_pcm_lib_ioctl,
1961         .hw_params = azx_pcm_hw_params,
1962         .hw_free = azx_pcm_hw_free,
1963         .prepare = azx_pcm_prepare,
1964         .trigger = azx_pcm_trigger,
1965         .pointer = azx_pcm_pointer,
1966         .page = snd_pcm_sgbuf_ops_page,
1967 };
1968
1969 static void azx_pcm_free(struct snd_pcm *pcm)
1970 {
1971         struct azx_pcm *apcm = pcm->private_data;
1972         if (apcm) {
1973                 apcm->chip->pcm[pcm->device] = NULL;
1974                 kfree(apcm);
1975         }
1976 }
1977
1978 static int
1979 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1980                       struct hda_pcm *cpcm)
1981 {
1982         struct azx *chip = bus->private_data;
1983         struct snd_pcm *pcm;
1984         struct azx_pcm *apcm;
1985         int pcm_dev = cpcm->device;
1986         int s, err;
1987
1988         if (pcm_dev >= HDA_MAX_PCMS) {
1989                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1990                            pcm_dev);
1991                 return -EINVAL;
1992         }
1993         if (chip->pcm[pcm_dev]) {
1994                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1995                 return -EBUSY;
1996         }
1997         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1998                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1999                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2000                           &pcm);
2001         if (err < 0)
2002                 return err;
2003         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2004         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2005         if (apcm == NULL)
2006                 return -ENOMEM;
2007         apcm->chip = chip;
2008         apcm->codec = codec;
2009         pcm->private_data = apcm;
2010         pcm->private_free = azx_pcm_free;
2011         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2012                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2013         chip->pcm[pcm_dev] = pcm;
2014         cpcm->pcm = pcm;
2015         for (s = 0; s < 2; s++) {
2016                 apcm->hinfo[s] = &cpcm->stream[s];
2017                 if (cpcm->stream[s].substreams)
2018                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2019         }
2020         /* buffer pre-allocation */
2021         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2022                                               snd_dma_pci_data(chip->pci),
2023                                               1024 * 64, 32 * 1024 * 1024);
2024         return 0;
2025 }
2026
2027 /*
2028  * mixer creation - all stuff is implemented in hda module
2029  */
2030 static int __devinit azx_mixer_create(struct azx *chip)
2031 {
2032         return snd_hda_build_controls(chip->bus);
2033 }
2034
2035
2036 /*
2037  * initialize SD streams
2038  */
2039 static int __devinit azx_init_stream(struct azx *chip)
2040 {
2041         int i;
2042
2043         /* initialize each stream (aka device)
2044          * assign the starting bdl address to each stream (device)
2045          * and initialize
2046          */
2047         for (i = 0; i < chip->num_streams; i++) {
2048                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2049                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2050                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2051                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2052                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2053                 azx_dev->sd_int_sta_mask = 1 << i;
2054                 /* stream tag: must be non-zero and unique */
2055                 azx_dev->index = i;
2056                 azx_dev->stream_tag = i + 1;
2057         }
2058
2059         return 0;
2060 }
2061
2062 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2063 {
2064         if (request_irq(chip->pci->irq, azx_interrupt,
2065                         chip->msi ? 0 : IRQF_SHARED,
2066                         "hda_intel", chip)) {
2067                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2068                        "disabling device\n", chip->pci->irq);
2069                 if (do_disconnect)
2070                         snd_card_disconnect(chip->card);
2071                 return -1;
2072         }
2073         chip->irq = chip->pci->irq;
2074         pci_intx(chip->pci, !chip->msi);
2075         return 0;
2076 }
2077
2078
2079 static void azx_stop_chip(struct azx *chip)
2080 {
2081         if (!chip->initialized)
2082                 return;
2083
2084         /* disable interrupts */
2085         azx_int_disable(chip);
2086         azx_int_clear(chip);
2087
2088         /* disable CORB/RIRB */
2089         azx_free_cmd_io(chip);
2090
2091         /* disable position buffer */
2092         azx_writel(chip, DPLBASE, 0);
2093         azx_writel(chip, DPUBASE, 0);
2094
2095         chip->initialized = 0;
2096 }
2097
2098 #ifdef CONFIG_SND_HDA_POWER_SAVE
2099 /* power-up/down the controller */
2100 static void azx_power_notify(struct hda_bus *bus)
2101 {
2102         struct azx *chip = bus->private_data;
2103         struct hda_codec *c;
2104         int power_on = 0;
2105
2106         list_for_each_entry(c, &bus->codec_list, list) {
2107                 if (c->power_on) {
2108                         power_on = 1;
2109                         break;
2110                 }
2111         }
2112         if (power_on)
2113                 azx_init_chip(chip);
2114         else if (chip->running && power_save_controller &&
2115                  !bus->power_keep_link_on)
2116                 azx_stop_chip(chip);
2117 }
2118 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2119
2120 #ifdef CONFIG_PM
2121 /*
2122  * power management
2123  */
2124
2125 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2126 {
2127         struct hda_codec *codec;
2128
2129         list_for_each_entry(codec, &bus->codec_list, list) {
2130                 if (snd_hda_codec_needs_resume(codec))
2131                         return 1;
2132         }
2133         return 0;
2134 }
2135
2136 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2137 {
2138         struct snd_card *card = pci_get_drvdata(pci);
2139         struct azx *chip = card->private_data;
2140         int i;
2141
2142         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2143         azx_clear_irq_pending(chip);
2144         for (i = 0; i < HDA_MAX_PCMS; i++)
2145                 snd_pcm_suspend_all(chip->pcm[i]);
2146         if (chip->initialized)
2147                 snd_hda_suspend(chip->bus);
2148         azx_stop_chip(chip);
2149         if (chip->irq >= 0) {
2150                 free_irq(chip->irq, chip);
2151                 chip->irq = -1;
2152         }
2153         if (chip->msi)
2154                 pci_disable_msi(chip->pci);
2155         pci_disable_device(pci);
2156         pci_save_state(pci);
2157         pci_set_power_state(pci, pci_choose_state(pci, state));
2158         return 0;
2159 }
2160
2161 static int azx_resume(struct pci_dev *pci)
2162 {
2163         struct snd_card *card = pci_get_drvdata(pci);
2164         struct azx *chip = card->private_data;
2165
2166         pci_set_power_state(pci, PCI_D0);
2167         pci_restore_state(pci);
2168         if (pci_enable_device(pci) < 0) {
2169                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2170                        "disabling device\n");
2171                 snd_card_disconnect(card);
2172                 return -EIO;
2173         }
2174         pci_set_master(pci);
2175         if (chip->msi)
2176                 if (pci_enable_msi(pci) < 0)
2177                         chip->msi = 0;
2178         if (azx_acquire_irq(chip, 1) < 0)
2179                 return -EIO;
2180         azx_init_pci(chip);
2181
2182         if (snd_hda_codecs_inuse(chip->bus))
2183                 azx_init_chip(chip);
2184
2185         snd_hda_resume(chip->bus);
2186         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2187         return 0;
2188 }
2189 #endif /* CONFIG_PM */
2190
2191
2192 /*
2193  * reboot notifier for hang-up problem at power-down
2194  */
2195 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2196 {
2197         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2198         snd_hda_bus_reboot_notify(chip->bus);
2199         azx_stop_chip(chip);
2200         return NOTIFY_OK;
2201 }
2202
2203 static void azx_notifier_register(struct azx *chip)
2204 {
2205         chip->reboot_notifier.notifier_call = azx_halt;
2206         register_reboot_notifier(&chip->reboot_notifier);
2207 }
2208
2209 static void azx_notifier_unregister(struct azx *chip)
2210 {
2211         if (chip->reboot_notifier.notifier_call)
2212                 unregister_reboot_notifier(&chip->reboot_notifier);
2213 }
2214
2215 /*
2216  * destructor
2217  */
2218 static int azx_free(struct azx *chip)
2219 {
2220         int i;
2221
2222         azx_notifier_unregister(chip);
2223
2224         if (chip->initialized) {
2225                 azx_clear_irq_pending(chip);
2226                 for (i = 0; i < chip->num_streams; i++)
2227                         azx_stream_stop(chip, &chip->azx_dev[i]);
2228                 azx_stop_chip(chip);
2229         }
2230
2231         if (chip->irq >= 0)
2232                 free_irq(chip->irq, (void*)chip);
2233         if (chip->msi)
2234                 pci_disable_msi(chip->pci);
2235         if (chip->remap_addr)
2236                 iounmap(chip->remap_addr);
2237
2238         if (chip->azx_dev) {
2239                 for (i = 0; i < chip->num_streams; i++)
2240                         if (chip->azx_dev[i].bdl.area)
2241                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2242         }
2243         if (chip->rb.area)
2244                 snd_dma_free_pages(&chip->rb);
2245         if (chip->posbuf.area)
2246                 snd_dma_free_pages(&chip->posbuf);
2247         pci_release_regions(chip->pci);
2248         pci_disable_device(chip->pci);
2249         kfree(chip->azx_dev);
2250         kfree(chip);
2251
2252         return 0;
2253 }
2254
2255 static int azx_dev_free(struct snd_device *device)
2256 {
2257         return azx_free(device->device_data);
2258 }
2259
2260 /*
2261  * white/black-listing for position_fix
2262  */
2263 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2264         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2265         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2266         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2267         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2268         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2269         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2270         {}
2271 };
2272
2273 static int __devinit check_position_fix(struct azx *chip, int fix)
2274 {
2275         const struct snd_pci_quirk *q;
2276
2277         switch (fix) {
2278         case POS_FIX_LPIB:
2279         case POS_FIX_POSBUF:
2280                 return fix;
2281         }
2282
2283         /* Check VIA/ATI HD Audio Controller exist */
2284         switch (chip->driver_type) {
2285         case AZX_DRIVER_VIA:
2286         case AZX_DRIVER_ATI:
2287                 chip->via_dmapos_patch = 1;
2288                 /* Use link position directly, avoid any transfer problem. */
2289                 return POS_FIX_LPIB;
2290         }
2291         chip->via_dmapos_patch = 0;
2292
2293         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2294         if (q) {
2295                 printk(KERN_INFO
2296                        "hda_intel: position_fix set to %d "
2297                        "for device %04x:%04x\n",
2298                        q->value, q->subvendor, q->subdevice);
2299                 return q->value;
2300         }
2301         return POS_FIX_AUTO;
2302 }
2303
2304 /*
2305  * black-lists for probe_mask
2306  */
2307 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2308         /* Thinkpad often breaks the controller communication when accessing
2309          * to the non-working (or non-existing) modem codec slot.
2310          */
2311         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2312         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2313         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2314         /* broken BIOS */
2315         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2316         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2317         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2318         /* forced codec slots */
2319         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2320         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2321         {}
2322 };
2323
2324 #define AZX_FORCE_CODEC_MASK    0x100
2325
2326 static void __devinit check_probe_mask(struct azx *chip, int dev)
2327 {
2328         const struct snd_pci_quirk *q;
2329
2330         chip->codec_probe_mask = probe_mask[dev];
2331         if (chip->codec_probe_mask == -1) {
2332                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2333                 if (q) {
2334                         printk(KERN_INFO
2335                                "hda_intel: probe_mask set to 0x%x "
2336                                "for device %04x:%04x\n",
2337                                q->value, q->subvendor, q->subdevice);
2338                         chip->codec_probe_mask = q->value;
2339                 }
2340         }
2341
2342         /* check forced option */
2343         if (chip->codec_probe_mask != -1 &&
2344             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2345                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2346                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2347                        chip->codec_mask);
2348         }
2349 }
2350
2351 /*
2352  * white/black-list for enable_msi
2353  */
2354 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2355         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2356         SND_PCI_QUIRK(0x1043, 0x829c, "ASUS", 0), /* nvidia */
2357         {}
2358 };
2359
2360 static void __devinit check_msi(struct azx *chip)
2361 {
2362         const struct snd_pci_quirk *q;
2363
2364         if (enable_msi >= 0) {
2365                 chip->msi = !!enable_msi;
2366                 return;
2367         }
2368         chip->msi = 1;  /* enable MSI as default */
2369         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2370         if (q) {
2371                 printk(KERN_INFO
2372                        "hda_intel: msi for device %04x:%04x set to %d\n",
2373                        q->subvendor, q->subdevice, q->value);
2374                 chip->msi = q->value;
2375         }
2376 }
2377
2378
2379 /*
2380  * constructor
2381  */
2382 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2383                                 int dev, int driver_type,
2384                                 struct azx **rchip)
2385 {
2386         struct azx *chip;
2387         int i, err;
2388         unsigned short gcap;
2389         static struct snd_device_ops ops = {
2390                 .dev_free = azx_dev_free,
2391         };
2392
2393         *rchip = NULL;
2394
2395         err = pci_enable_device(pci);
2396         if (err < 0)
2397                 return err;
2398
2399         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2400         if (!chip) {
2401                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2402                 pci_disable_device(pci);
2403                 return -ENOMEM;
2404         }
2405
2406         spin_lock_init(&chip->reg_lock);
2407         mutex_init(&chip->open_mutex);
2408         chip->card = card;
2409         chip->pci = pci;
2410         chip->irq = -1;
2411         chip->driver_type = driver_type;
2412         check_msi(chip);
2413         chip->dev_index = dev;
2414         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2415
2416         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2417         check_probe_mask(chip, dev);
2418
2419         chip->single_cmd = single_cmd;
2420
2421         if (bdl_pos_adj[dev] < 0) {
2422                 switch (chip->driver_type) {
2423                 case AZX_DRIVER_ICH:
2424                         bdl_pos_adj[dev] = 1;
2425                         break;
2426                 default:
2427                         bdl_pos_adj[dev] = 32;
2428                         break;
2429                 }
2430         }
2431
2432 #if BITS_PER_LONG != 64
2433         /* Fix up base address on ULI M5461 */
2434         if (chip->driver_type == AZX_DRIVER_ULI) {
2435                 u16 tmp3;
2436                 pci_read_config_word(pci, 0x40, &tmp3);
2437                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2438                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2439         }
2440 #endif
2441
2442         err = pci_request_regions(pci, "ICH HD audio");
2443         if (err < 0) {
2444                 kfree(chip);
2445                 pci_disable_device(pci);
2446                 return err;
2447         }
2448
2449         chip->addr = pci_resource_start(pci, 0);
2450         chip->remap_addr = pci_ioremap_bar(pci, 0);
2451         if (chip->remap_addr == NULL) {
2452                 snd_printk(KERN_ERR SFX "ioremap error\n");
2453                 err = -ENXIO;
2454                 goto errout;
2455         }
2456
2457         if (chip->msi)
2458                 if (pci_enable_msi(pci) < 0)
2459                         chip->msi = 0;
2460
2461         if (azx_acquire_irq(chip, 0) < 0) {
2462                 err = -EBUSY;
2463                 goto errout;
2464         }
2465
2466         pci_set_master(pci);
2467         synchronize_irq(chip->irq);
2468
2469         gcap = azx_readw(chip, GCAP);
2470         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2471
2472         /* disable SB600 64bit support for safety */
2473         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2474             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2475                 struct pci_dev *p_smbus;
2476                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2477                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2478                                          NULL);
2479                 if (p_smbus) {
2480                         if (p_smbus->revision < 0x30)
2481                                 gcap &= ~ICH6_GCAP_64OK;
2482                         pci_dev_put(p_smbus);
2483                 }
2484         }
2485
2486         /* disable 64bit DMA address for Teradici */
2487         /* it does not work with device 6549:1200 subsys e4a2:040b */
2488         if (chip->driver_type == AZX_DRIVER_TERA)
2489                 gcap &= ~ICH6_GCAP_64OK;
2490
2491         /* allow 64bit DMA address if supported by H/W */
2492         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2493                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2494         else {
2495                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2496                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2497         }
2498
2499         /* read number of streams from GCAP register instead of using
2500          * hardcoded value
2501          */
2502         chip->capture_streams = (gcap >> 8) & 0x0f;
2503         chip->playback_streams = (gcap >> 12) & 0x0f;
2504         if (!chip->playback_streams && !chip->capture_streams) {
2505                 /* gcap didn't give any info, switching to old method */
2506
2507                 switch (chip->driver_type) {
2508                 case AZX_DRIVER_ULI:
2509                         chip->playback_streams = ULI_NUM_PLAYBACK;
2510                         chip->capture_streams = ULI_NUM_CAPTURE;
2511                         break;
2512                 case AZX_DRIVER_ATIHDMI:
2513                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2514                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2515                         break;
2516                 case AZX_DRIVER_GENERIC:
2517                 default:
2518                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2519                         chip->capture_streams = ICH6_NUM_CAPTURE;
2520                         break;
2521                 }
2522         }
2523         chip->capture_index_offset = 0;
2524         chip->playback_index_offset = chip->capture_streams;
2525         chip->num_streams = chip->playback_streams + chip->capture_streams;
2526         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2527                                 GFP_KERNEL);
2528         if (!chip->azx_dev) {
2529                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2530                 goto errout;
2531         }
2532
2533         for (i = 0; i < chip->num_streams; i++) {
2534                 /* allocate memory for the BDL for each stream */
2535                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2536                                           snd_dma_pci_data(chip->pci),
2537                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2538                 if (err < 0) {
2539                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2540                         goto errout;
2541                 }
2542         }
2543         /* allocate memory for the position buffer */
2544         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2545                                   snd_dma_pci_data(chip->pci),
2546                                   chip->num_streams * 8, &chip->posbuf);
2547         if (err < 0) {
2548                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2549                 goto errout;
2550         }
2551         /* allocate CORB/RIRB */
2552         err = azx_alloc_cmd_io(chip);
2553         if (err < 0)
2554                 goto errout;
2555
2556         /* initialize streams */
2557         azx_init_stream(chip);
2558
2559         /* initialize chip */
2560         azx_init_pci(chip);
2561         azx_init_chip(chip);
2562
2563         /* codec detection */
2564         if (!chip->codec_mask) {
2565                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2566                 err = -ENODEV;
2567                 goto errout;
2568         }
2569
2570         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2571         if (err <0) {
2572                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2573                 goto errout;
2574         }
2575
2576         strcpy(card->driver, "HDA-Intel");
2577         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2578                 sizeof(card->shortname));
2579         snprintf(card->longname, sizeof(card->longname),
2580                  "%s at 0x%lx irq %i",
2581                  card->shortname, chip->addr, chip->irq);
2582
2583         *rchip = chip;
2584         return 0;
2585
2586  errout:
2587         azx_free(chip);
2588         return err;
2589 }
2590
2591 static void power_down_all_codecs(struct azx *chip)
2592 {
2593 #ifdef CONFIG_SND_HDA_POWER_SAVE
2594         /* The codecs were powered up in snd_hda_codec_new().
2595          * Now all initialization done, so turn them down if possible
2596          */
2597         struct hda_codec *codec;
2598         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2599                 snd_hda_power_down(codec);
2600         }
2601 #endif
2602 }
2603
2604 static int __devinit azx_probe(struct pci_dev *pci,
2605                                const struct pci_device_id *pci_id)
2606 {
2607         static int dev;
2608         struct snd_card *card;
2609         struct azx *chip;
2610         int err;
2611
2612         if (dev >= SNDRV_CARDS)
2613                 return -ENODEV;
2614         if (!enable[dev]) {
2615                 dev++;
2616                 return -ENOENT;
2617         }
2618
2619         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2620         if (err < 0) {
2621                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2622                 return err;
2623         }
2624
2625         /* set this here since it's referred in snd_hda_load_patch() */
2626         snd_card_set_dev(card, &pci->dev);
2627
2628         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2629         if (err < 0)
2630                 goto out_free;
2631         card->private_data = chip;
2632
2633 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2634         chip->beep_mode = beep_mode[dev];
2635 #endif
2636
2637         /* create codec instances */
2638         err = azx_codec_create(chip, model[dev]);
2639         if (err < 0)
2640                 goto out_free;
2641 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2642         if (patch[dev]) {
2643                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2644                            patch[dev]);
2645                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2646                 if (err < 0)
2647                         goto out_free;
2648         }
2649 #endif
2650         if (!probe_only[dev]) {
2651                 err = azx_codec_configure(chip);
2652                 if (err < 0)
2653                         goto out_free;
2654         }
2655
2656         /* create PCM streams */
2657         err = snd_hda_build_pcms(chip->bus);
2658         if (err < 0)
2659                 goto out_free;
2660
2661         /* create mixer controls */
2662         err = azx_mixer_create(chip);
2663         if (err < 0)
2664                 goto out_free;
2665
2666         err = snd_card_register(card);
2667         if (err < 0)
2668                 goto out_free;
2669
2670         pci_set_drvdata(pci, card);
2671         chip->running = 1;
2672         power_down_all_codecs(chip);
2673         azx_notifier_register(chip);
2674
2675         dev++;
2676         return err;
2677 out_free:
2678         snd_card_free(card);
2679         return err;
2680 }
2681
2682 static void __devexit azx_remove(struct pci_dev *pci)
2683 {
2684         snd_card_free(pci_get_drvdata(pci));
2685         pci_set_drvdata(pci, NULL);
2686 }
2687
2688 /* PCI IDs */
2689 static struct pci_device_id azx_ids[] = {
2690         /* ICH 6..10 */
2691         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2692         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2693         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2694         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2695         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2696         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2697         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2698         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2699         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2700         /* PCH */
2701         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2702         /* CPT */
2703         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_ICH },
2704         /* SCH */
2705         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2706         /* ATI SB 450/600 */
2707         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2708         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2709         /* ATI HDMI */
2710         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2711         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2712         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2713         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2714         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2715         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2716         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2717         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2718         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2719         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2720         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2721         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2722         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2723         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2724         /* VIA VT8251/VT8237A */
2725         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2726         /* SIS966 */
2727         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2728         /* ULI M5461 */
2729         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2730         /* NVIDIA MCP */
2731         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2732           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2733           .class_mask = 0xffffff,
2734           .driver_data = AZX_DRIVER_NVIDIA },
2735         /* Teradici */
2736         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2737         /* Creative X-Fi (CA0110-IBG) */
2738 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2739         /* the following entry conflicts with snd-ctxfi driver,
2740          * as ctxfi driver mutates from HD-audio to native mode with
2741          * a special command sequence.
2742          */
2743         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2744           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2745           .class_mask = 0xffffff,
2746           .driver_data = AZX_DRIVER_GENERIC },
2747 #else
2748         /* this entry seems still valid -- i.e. without emu20kx chip */
2749         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2750 #endif
2751         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2752         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2753           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2754           .class_mask = 0xffffff,
2755           .driver_data = AZX_DRIVER_GENERIC },
2756         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2757           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2758           .class_mask = 0xffffff,
2759           .driver_data = AZX_DRIVER_GENERIC },
2760         { 0, }
2761 };
2762 MODULE_DEVICE_TABLE(pci, azx_ids);
2763
2764 /* pci_driver definition */
2765 static struct pci_driver driver = {
2766         .name = "HDA Intel",
2767         .id_table = azx_ids,
2768         .probe = azx_probe,
2769         .remove = __devexit_p(azx_remove),
2770 #ifdef CONFIG_PM
2771         .suspend = azx_suspend,
2772         .resume = azx_resume,
2773 #endif
2774 };
2775
2776 static int __init alsa_card_azx_init(void)
2777 {
2778         return pci_register_driver(&driver);
2779 }
2780
2781 static void __exit alsa_card_azx_exit(void)
2782 {
2783         pci_unregister_driver(&driver);
2784 }
2785
2786 module_init(alsa_card_azx_init)
2787 module_exit(alsa_card_azx_exit)